URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk/rtl
- from Rev 62 to Rev 63
- ↔ Reverse comparison
Rev 62 → Rev 63
/verilog/sdr_16.v
1052,7 → 1052,7
rfr: |
if (shreg[0]) begin |
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch}; |
open_ba[ba_reg] <= 1'b0; |
open_ba <= 4'b0000; |
end else if (shreg[2]) |
{ba,a,cmd,cmd_aref} <= {2'b00, 13'd0, cmd_rfr,1'b1}; |
adr: |
1061,7 → 1061,8
pch: |
if (shreg[0]) begin |
{ba,a,cmd} <= {ba_reg,13'd0,cmd_pch}; |
open_ba <= 4'b0000; |
//open_ba <= 4'b0000; |
open_ba[ba_reg] <= 1'b0; |
end |
act: |
if (shreg[0]) begin |
1115,7 → 1116,7
|
|
endmodule |
`line 277 "fsm_sdr_16.v" 2 |
`line 278 "fsm_sdr_16.v" 2 |
`line 1 "versatile_mem_ctrl_wb.v" 1 |
`timescale 1ns/1ns |
module versatile_mem_ctrl_wb ( |
/verilog/fsm_sdr_16.v
211,7 → 211,7
rfr: |
if (shreg[0]) begin |
{ba,a,cmd} <= {2'b00, 13'b0010000000000, cmd_pch}; |
open_ba[ba_reg] <= 1'b0; |
open_ba <= 4'b0000; |
end else if (shreg[2]) |
{ba,a,cmd,cmd_aref} <= {2'b00, 13'd0, cmd_rfr,1'b1}; |
adr: |
220,7 → 220,8
pch: |
if (shreg[0]) begin |
{ba,a,cmd} <= {ba_reg,13'd0,cmd_pch}; |
open_ba <= 4'b0000; |
//open_ba <= 4'b0000; |
open_ba[ba_reg] <= 1'b0; |
end |
act: |
if (shreg[0]) begin |