URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk/rtl
- from Rev 85 to Rev 86
- ↔ Reverse comparison
Rev 85 → Rev 86
/verilog/versatile_mem_ctrl_ip.v
2713,6 → 2713,7
wire [0:0] sub_wire1 = sub_wire0[0:0]; |
wire sub_wire6 = clk_in; |
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; |
wire clk_fb; |
|
assign clk0_out = sub_wire1; |
assign clk90_out = sub_wire2; |
2744,7 → 2745,6
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
.operation_mode("NORMAL"), |
// .operation_mode("SOURCE_SYNCHRONOUS"), |
.pll_type("AUTO"), |
.port_activeclock("PORT_UNUSED"), |
.port_areset("PORT_USED"), |
2791,11 → 2791,11
.using_fbmimicbidir_port("OFF"), |
.width_clock(10)) |
altpll_internal ( |
.fbin (),//(clkfb_in), |
.fbin (clkfb), |
.inclk (sub_wire7), |
.areset (rst), |
.clk (sub_wire0), |
.fbout (),//(clkfb_out), |
.fbout (clkfb), |
.activeclock (), |
.clkbad (), |
.clkena ({6{1'b1}}), |
/verilog/dcm_pll.v
124,6 → 124,7
wire [0:0] sub_wire1 = sub_wire0[0:0]; |
wire sub_wire6 = clk_in; |
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; |
wire clk_fb; |
|
assign clk0_out = sub_wire1; |
assign clk90_out = sub_wire2; |
155,7 → 156,6
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
.operation_mode("NORMAL"), |
// .operation_mode("SOURCE_SYNCHRONOUS"), |
.pll_type("AUTO"), |
.port_activeclock("PORT_UNUSED"), |
.port_areset("PORT_USED"), |
202,11 → 202,11
.using_fbmimicbidir_port("OFF"), |
.width_clock(10)) |
altpll_internal ( |
.fbin (),//(clkfb_in), |
.fbin (clkfb), |
.inclk (sub_wire7), |
.areset (rst), |
.clk (sub_wire0), |
.fbout (),//(clkfb_out), |
.fbout (clkfb), |
.activeclock (), |
.clkbad (), |
.clkena ({6{1'b1}}), |