URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk/syn/altera
- from Rev 15 to Rev 20
- ↔ Reverse comparison
Rev 15 → Rev 20
/bin/versatile_memory_controller.sdc
1,9 → 1,26
#************************************************************** |
# Time Information |
#************************************************************** |
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16 -5E) |
|
# Clock cycle time: min=5.00ns, max=8.00ns |
set tCK 5.000 |
|
# Input setup time: tISb=350ps, tISa=600ps |
set tSU 0.600 |
|
# Input hold time: tIHb=470ps, tIHa=600ps |
set tH 0.600 |
|
# DQS output access time from CK/CK# |
set tDQSCKmin -0.500 |
set tDQSCKmax 0.500 |
|
# DQ output access time from CK/CK# |
set tACmin -0.600 |
set tACmax 0.600 |
|
|
#************************************************************** |
# Create Clock |
#************************************************************** |
10,11 → 27,11
|
# Clock frequency |
set wb_clk_period 20.000 |
set sdram_clk_period 8.000 |
set sdram_clk_period $tCK |
|
# Clocks |
create_clock -name {wb_clk} -period $wb_clk_period |
create_clock -name {sdram_clk} -period $sdram_clk_period |
create_clock -name {wb_clk} -period $wb_clk_period [get_ports {wb_clk}] |
create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}] |
|
# Virtual clocks |
create_clock -name {v_wb_clk_in} -period $wb_clk_period |
22,23 → 39,15
create_clock -name {v_sdram_clk_in} -period $sdram_clk_period |
create_clock -name {v_sdram_clk_out} -period $sdram_clk_period |
|
# Base clock for the PLL input clock port |
create_clock -name pll_base_clock -period $sdram_clk_period [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] |
|
|
#************************************************************** |
# Create Generated Clock |
#************************************************************** |
|
create_generated_clock -name {sdram_clk_0} -phase 0 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}] |
create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}] |
create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}] |
create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}] |
create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*] |
|
create_generated_clock -name {sdram_clk_180} -phase 180 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}] |
|
create_generated_clock -name {sdram_clk_270} -phase 270 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}] |
|
#derive_pll_clocks |
|
|
#************************************************************** |
# Set Clock Latency |
#************************************************************** |
56,66 → 65,32
# Set Input Delay |
#************************************************************** |
|
set ddr2_input_delay_min 0 |
set ddr2_input_delay_max 0 |
set_input_delay -clock {v_sdram_clk_in} -max $tACmax [get_ports {dq_pad_io[*]}] |
set_input_delay -clock {v_sdram_clk_in} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
|
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {ck_fb_pad_i}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dm_rdqs_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dq_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dqs_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dqs_n_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {rdqs_n_pad_i[*]}] |
set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] |
set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
|
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {ck_fb_pad_i}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dm_rdqs_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dq_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dqs_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dqs_n_pad_io[*]}] |
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {rdqs_n_pad_i[*]}] |
|
|
#************************************************************** |
# Set Output Delay |
#************************************************************** |
|
set ddr2_output_delay_min 0 |
set ddr2_output_delay_max 0 |
set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dq_pad_io[*]}] |
set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
|
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_n_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cke_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_fb_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cs_n_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ras_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cas_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {we_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dm_rdqs_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ba_pad_o[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {addr_pad_o[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dq_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_oe}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_n_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {odt_pad_o}] |
set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dqs_pad_io[*]}] |
set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dqs_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
|
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_n_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cke_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_fb_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cs_n_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ras_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cas_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {we_pad_o}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dm_rdqs_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ba_pad_o[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {addr_pad_o[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dq_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_oe}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_n_pad_io[*]}] |
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {odt_pad_o}] |
|
|
#************************************************************** |
# Set Clock Groups |
#************************************************************** |
126,7 → 101,15
# Set False Path |
#************************************************************** |
|
# Reset |
set_false_path -from [get_ports {wb_rst}] |
# Input Timing Exceptions |
# |
# Output timing Exceptions |
set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out] |
set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out] |
set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out] |
set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out] |
|
|
#************************************************************** |
/bin/versatile_memory_controller.tcl
1,23 → 1,7
# Copyright (C) 1991-2009 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# Usage: |
# cd /versatile_mem_ctrl/trunk/syn/altera/run/ |
# quartus_sh -t ../bin/versatile_memory_controller.tcl |
|
# Quartus II: Generate Tcl File for Project |
# File: versatile_memory_controller.tcl |
# Generated on: Mon Feb 1 15:14:07 2010 |
|
# Usage: quartus_sh -t versatile_memory_controller.tcl |
|
# Load Quartus II Tcl Project package |
package require ::quartus::project |
|