OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /versatile_mem_ctrl/trunk/syn/xilinx
    from Rev 13 to Rev 15
    ↔ Reverse comparison
  •

Rev 13 → Rev 15

/bin/versatile_mem_ctrl.ucf File deleted
/bin/versatile_memory_controller.ucf
0,0 → 1,122
#**************************************************************
# System Level Constraints
#**************************************************************
NET sdram_clk LOC = "F13" | IOSTANDARD = LVCMOS33;
NET wb_clk LOC = "K14" | IOSTANDARD = LVCMOS33;
NET wb_rst LOC = "Y16" | IOSTANDARD = LVTTL;
NET wb_rst TIG;
 
#**************************************************************
# Timing Constraints
#**************************************************************
 
#**************************************************************
# Clocks
#**************************************************************
NET "sdram_clk" TNM_NET = sdram_clk;
TIMESPEC TS_sdram_clk = PERIOD "sdram_clk" 8 ns HIGH 50%; # 125 MHz
NET "wb_clk" TNM_NET = wb_clk;
TIMESPEC TS_wb_clk = PERIOD "wb_clk" 40 ns HIGH 50%; # 25 MHz
 
# External feedback to DCM
NET "ck_fb_pad_i" FEEDBACK = 2 ns NET "ck_fb_pad_o";
 
#
NET "sdram_clk" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "dcm_pll_o/DCM_external/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
NET "wb_clk" CLOCK_DEDICATED_ROUTE = FALSE;
 
#**************************************************************
# DDR2 IF
#**************************************************************
# Data
#NET dq_pad_io<31> LOC="U9" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<30> LOC="V8" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<29> LOC="AB1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<28> LOC="AC1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<27> LOC="Y5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<26> LOC="Y6" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<25> LOC="U7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<24> LOC="U8" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<23> LOC="AA2" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<22> LOC="AA3" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<21> LOC="Y1" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<20> LOC="Y2" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<19> LOC="T7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<18> LOC="U6" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<17> LOC="U5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dq_pad_io<16> LOC="V5" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
NET dq_pad_io<15> LOC="R8" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<14> LOC="R7" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<13> LOC="U1" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<12> LOC="U2" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<11> LOC="P8" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<10> LOC="P9" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<9> LOC="R5" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<8> LOC="R6" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<7> LOC="P7" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<6> LOC="P6" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<5> LOC="T3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<4> LOC="T4" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<3> LOC="N9" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<2> LOC="P10" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<1> LOC="P4" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dq_pad_io<0> LOC="P3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
# Address
NET addr_pad_o<0> LOC="M4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<1> LOC="M3" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<2> LOC="M8" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<3> LOC="M7" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<4> LOC="L4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<5> LOC="L3" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<6> LOC="K3" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<7> LOC="K2" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<8> LOC="K5" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<9> LOC="K4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<10> LOC="M10" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<11> LOC="M9" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET addr_pad_o<12> LOC="J5" |IOSTANDARD = SSTL18_I |IOB = TRUE;
# Bank address
NET ba_pad_o<0> LOC="J4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET ba_pad_o<1> LOC="K6" |IOSTANDARD = SSTL18_I |IOB = TRUE;
# Control
NET cas_pad_o LOC="L10" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET cke_pad_o LOC="L7" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET cs_n_pad_o LOC="H2" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET ras_pad_o LOC="H1" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET we_pad_o LOC="L9" |IOSTANDARD = SSTL18_I |IOB = TRUE;
# Data mask
NET dm_rdqs_pad_io<0> LOC="M6" |IOSTANDARD = SSTL18_II |IOB = TRUE;
NET dm_rdqs_pad_io<1> LOC="R2" |IOSTANDARD = SSTL18_II |IOB = TRUE;
#NET dm_rdqs_pad_io<2> LOC="V1" | IOSTANDARD = SSTL18_II | IOB = TRUE;
#NET dm_rdqs_pad_io<3> LOC="V2" | IOSTANDARD = SSTL18_II | IOB = TRUE;
# Strobe
NET dqs_pad_io<0> LOC="R3" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
NET dqs_pad_io<1> LOC="T5" |IOSTANDARD = SSTL18_II |IOB = TRUE |FAST;
#NET dqs_pad_io<2> LOC="W3" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
#NET dqs_pad_io<3> LOC="V7" | IOSTANDARD = SSTL18_II | IOB = TRUE | FAST;
# Clocks
NET ck_pad_o LOC="N5" |IOSTANDARD = SSTL18_I |IOB = TRUE;
NET ck_n_pad_o LOC="N4" |IOSTANDARD = SSTL18_I |IOB = TRUE;
#NET ck_pad_o<1> LOC="N1" | IOSTANDARD = SSTL18_I | IOB = TRUE;
#NET ck_n_pad_o<1> LOC="N2" | IOSTANDARD = SSTL18_I | IOB = TRUE;
NET ck_fb_pad_o LOC="M2" |IOSTANDARD = LVCMOS18 |IOB = TRUE;
NET ck_fb_pad_i LOC="N7" |IOSTANDARD = LVCMOS18 |IOB = TRUE;
#
INST "dq_pad_io<0>" TNM = TNM_dq_in;
INST "dq_pad_io<1>" TNM = TNM_dq_in;
INST "dq_pad_io<2>" TNM = TNM_dq_in;
INST "dq_pad_io<3>" TNM = TNM_dq_in;
INST "dq_pad_io<4>" TNM = TNM_dq_in;
INST "dq_pad_io<5>" TNM = TNM_dq_in;
INST "dq_pad_io<6>" TNM = TNM_dq_in;
INST "dq_pad_io<7>" TNM = TNM_dq_in;
INST "dq_pad_io<8>" TNM = TNM_dq_in;
INST "dq_pad_io<9>" TNM = TNM_dq_in;
INST "dq_pad_io<10>" TNM = TNM_dq_in;
INST "dq_pad_io<11>" TNM = TNM_dq_in;
INST "dq_pad_io<12>" TNM = TNM_dq_in;
INST "dq_pad_io<13>" TNM = TNM_dq_in;
INST "dq_pad_io<14>" TNM = TNM_dq_in;
INST "dq_pad_io<15>" TNM = TNM_dq_in;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.