URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
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/versatile_mem_ctrl/trunk/syn
- from Rev 22 to Rev 30
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Rev 22 → Rev 30
/altera/bin/versatile_memory_controller.sdc
83,9 → 83,8
create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}] |
create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}] |
create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}] |
create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*] |
create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {versatile_mem_ctrl_ddr_0|ddr_ff_out_ck|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports {ck_pad_o}] |
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#************************************************************** |
# Set Clock Latency |
#************************************************************** |