URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
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- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk/syn
- from Rev 75 to Rev 81
- ↔ Reverse comparison
Rev 75 → Rev 81
/altera/bin/versatile_memory_controller.sdc
4,7 → 4,7
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E) |
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# Clock cycle time: min=5.00ns, max=8.00ns |
set tCK 5.000 |
set tCK 8.000 |
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# Data Strobe Out |
# DQS output access time from CK/CK# |
66,7 → 66,7
set sdram_clk_period $tCK |
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# Clocks |
create_clock -name {wb_clk} -period $wb_clk_period [get_ports {wb_clk}] |
create_clock -name {wb_clk[*]} -period $wb_clk_period [get_ports {wb_clk[*]}] |
create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}] |
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# Virtual clocks |
194,7 → 194,7
#************************************************************** |
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# Reset |
set_false_path -from [get_ports {wb_rst}] |
set_false_path -from [get_ports {wb_rst[*]}] |
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# Input Timing Exceptions |
# False path exceptions for opposite-edge transfer |