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Rev 19 → Rev 20

/rtl/verilog/ddr_16_defines.v
125,94 → 125,5
`define CMD_WRITE 3'b100
`define CMD_BT 3'b110
 
// AC Operating Specifications and Conditions
//`define TWR 4'd2 // Write recovery time, tWR/tCLK=15/8=2 (tCLK)
//`define TRFC 5'd10 // REFRESH-to-ACTIVATE/REFRESH interval (256Mb), tRFC/tCLK=75/8=10 (tCLK)
//`define TRFC 5'd14 // REFRESH-to-ACTIVATE/REFRESH interval (512Mb), tRFC/tCLK=105/8=14 (tCLK)
//`define TRFC 5'd16 // REFRESH-to-ACTIVATE/REFRESH interval (1Gb), tRFC/tCLK=127,5/8=16 (tCLK)
//`define TRFC 5'd25 // REFRESH-to-ACTIVATE/REFRESH interval (2Gb), tRFC/tCLK=197,5/8=25 (tCLK)
//`define TRCD 2'd2 // ACTIVATE-to-READ/WRITE delay, 12-15ns, tRCD/tCLK=15/8=2 (tCLK)
 
`endif // `ifdef MT47H32M16
 
 
/*
//`define MT48LC16M16
`ifdef MT48LC16M16
// using 1 of MT48LC16M16
// SDRAM data width is 16
 
`define BURST_SIZE 2
`define SDRAM_DATA_WIDTH 16
`define COL_SIZE 9
`define ROW_SIZE 13
`define BA_SIZE 2
 
`define SDRAM16
`define BA tx_fifo_dat_o[28:27]
`define ROW tx_fifo_dat_o[26:14]
`define COL {4'b0000,tx_fifo_dat_o[13:10],burst_adr,1'b0}
`define WORD_SIZE 1
`define WB_ADR_HI 24
`define WB_ADR_LO 2
`endif // `ifdef MT48LC16M16
 
//`define DEVICE MT48LC4M16
`ifdef MT48LC4M16
// using 1 of MT48LC4M16
// SDRAM data width is 16
 
`define BURST_SIZE 2
`define SDRAM_DATA_WIDTH 16
`define COL_SIZE 8
`define ROW_SIZE 12
`define BA_SIZE 2
 
`define SDRAM16
`define COL {5'b0000,wb_adr_i[8:1]}
`define ROW wb_adr_i[20:9]
`define BA wb_adr_i[22:21]
`define WORD_SIZE 1
`define END_OF_BURST burst_counter[0]
`define WB_ADR_HI 22
`define WB_ADR_LO 1
`endif // `ifdef MT48LC4M16
 
 
// FIFO
`define DLY_INIT 4095
`define AREF_INIT 390
 
 
// LMR
// [12:10] reserved
// [9] WB, write burst; 0 - programmed burst length, 1 - single location
// [8:7] OP Mode, 2'b00
// [6:4] CAS Latency; 3'b010 - 2, 3'b011 - 3
// [3] BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
// [2:0] Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
`define WB 1'b0
`define CL 2
`define BT 1'b0
`define BL 3'b001
 
// Adr to SDRAM {ba[1:0],a[12:0]}
`define A_LMR {2'b00,3'b000,`WB,2'b00,3'd`CL,`BT,`BL}
`define A_PRE {2'b00,13'b0010000000000}
`define A_ACT {`BA,`ROW}
`define A_READ {`BA,`COL}
`define A_WRITE {`BA,`COL}
`define A_DEFAULT {2'b00,13'b0000000000000}
 
// command
`define CMD {ras, cas, we}
`define CMD_NOP 3'b111
`define CMD_AREF 3'b001
`define CMD_LMR 3'b000
`define CMD_PRE 3'b010
`define CMD_ACT 3'b011
`define CMD_READ 3'b101
`define CMD_WRITE 3'b100
`define CMD_BT 3'b110
 
*/
/rtl/verilog/ddr_ff.v
34,7 → 34,7
altddio_in #(
.WIDTH(1),
.POWER_UP_HIGH("OFF"),
.INTENDED_DEVICE_FAMILY())
.INTENDED_DEVICE_FAMILY("Stratix III"))
altddio_in_inst (
.aset(),
.datain(D),
101,7 → 101,7
altddio_out #(
.WIDTH(1),
.POWER_UP_HIGH("OFF"),
.INTENDED_DEVICE_FAMILY(),
.INTENDED_DEVICE_FAMILY("Stratix III"),
.OE_REG("UNUSED"))
altddio_out_inst (
.aset(),
/rtl/verilog/inc_adr.v
1,5 → 1,3
`include "versatile_mem_ctrl_defines.v"
 
module inc_adr
(
input [3:0] adr_i,
48,7 → 46,6
default: adr_o <= adr_o + 4'd1;
endcase // case (bte)
`ifdef SDR_16
// done
always @ (posedge clk or posedge rst)
if (rst)
67,31 → 64,7
else
if (inc)
{done,cnt} <= cnt + 4'd1;
`endif
 
`ifdef DDR_16
// done
always @ (posedge clk or posedge rst)
if (rst)
{done,cnt} <= {1'b0,4'd0};
else
if (init_i)
begin
done <= ({bte_i,cti_i} == {2'b00,3'b000});
case (bte_i)
2'b01: cnt <= 4'd12;
2'b10: cnt <= 4'd8;
2'b11: cnt <= 4'd0;
default: cnt <= adr_i;
endcase
end
else
if (inc)
{done,cnt} <= cnt + 4'd1;
`endif
 
 
 
endmodule // inc_adr
 
/rtl/verilog/versatile_mem_ctrl_top.v
827,18 → 827,28
// write latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay1.depth=`CL+`AL-1;
defparam delay1.width=4;
defparam delay1.width=3;
delay delay1 (
.d({write, write, write, dqm_en_i}),
.q({dq_en, dq_oe, dqs_en, dqm_en}),
.d({write, write, dqm_en_i}),
.q({dq_en, dq_oe, dqm_en}),
.clk(sdram_clk_270),
.rst(wb_rst)
);
 
// write latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay2.depth=`CL+`AL-1;
defparam delay2.width=1;
delay delay2 (
.d(write),
.q(dqs_en),
.clk(sdram_clk_0),
.rst(wb_rst)
);
 
// if CL>4 delay read from Tx FIFO
defparam delay2.depth=`CL+`AL-3;
defparam delay2.width=2;
delay delay2 (
defparam delay3.depth=`CL+`AL-3;
defparam delay3.width=2;
delay delay3 (
.d({tx_fifo_re_i && !wr_burst_mask, tx_fifo_re_i && !wr_burst_mask}),
.q({tx_fifo_re, adr_init_delay}),
.clk(sdram_clk_0),
856,9 → 866,9
// CL=3, not supported
 
// Increment address
defparam delay3.depth=`CL+`AL-1;
defparam delay3.width=1;
delay delay3 (
defparam delay4.depth=`CL+`AL-1;
defparam delay4.width=1;
delay delay4 (
.d({write|read}),
.q({adr_inc}),
.clk(sdram_clk_0),
/rtl/verilog/versatile_mem_ctrl_ip.v
1038,8 → 1038,6
endmodule
 
`include "versatile_mem_ctrl_defines.v"
 
module inc_adr
(
input [3:0] adr_i,
1088,7 → 1086,6
default: adr_o <= adr_o + 4'd1;
endcase // case (bte)
`ifdef SDR_16
// done
always @ (posedge clk or posedge rst)
if (rst)
1107,31 → 1104,7
else
if (inc)
{done,cnt} <= cnt + 4'd1;
`endif
 
`ifdef DDR_16
// done
always @ (posedge clk or posedge rst)
if (rst)
{done,cnt} <= {1'b0,4'd0};
else
if (init_i)
begin
done <= ({bte_i,cti_i} == {2'b00,3'b000});
case (bte_i)
2'b01: cnt <= 4'd12;
2'b10: cnt <= 4'd8;
2'b11: cnt <= 4'd0;
default: cnt <= adr_i;
endcase
end
else
if (inc)
{done,cnt} <= cnt + 4'd1;
`endif
 
 
 
endmodule // inc_adr
 
2476,7 → 2449,7
altddio_in #(
.WIDTH(1),
.POWER_UP_HIGH("OFF"),
.INTENDED_DEVICE_FAMILY())
.INTENDED_DEVICE_FAMILY("Stratix III"))
altddio_in_inst (
.aset(),
.datain(D),
2543,7 → 2516,7
altddio_out #(
.WIDTH(1),
.POWER_UP_HIGH("OFF"),
.INTENDED_DEVICE_FAMILY(),
.INTENDED_DEVICE_FAMILY("Stratix III"),
.OE_REG("UNUSED"))
altddio_out_inst (
.aset(),
2717,20 → 2690,20
.clk1_divide_by(1),
.clk1_duty_cycle(50),
.clk1_multiply_by(1),
.clk1_phase_shift("2000"),
.clk1_phase_shift("1250"),
.clk2_divide_by(1),
.clk2_duty_cycle(50),
.clk2_multiply_by(1),
.clk2_phase_shift("4000"),
.clk2_phase_shift("2500"),
.clk3_divide_by(1),
.clk3_duty_cycle(50),
.clk3_multiply_by(1),
.clk3_phase_shift("6000"),
.inclk0_input_frequency(8000),
.clk3_phase_shift("3750"),
.inclk0_input_frequency(5000),
.intended_device_family("Stratix III"),
.lpm_hint("CBX_MODULE_PREFIX=tmp_pll"),
.lpm_type("altpll"),
.operation_mode("EXTERNAL_FEEDBACK"),
.operation_mode("NORMAL"),
.pll_type("AUTO"),
.port_activeclock("PORT_UNUSED"),
.port_areset("PORT_USED"),
2777,11 → 2750,11
.using_fbmimicbidir_port("OFF"),
.width_clock(10))
altpll_internal (
.fbin (clkfb_in),
.fbin (),//(clkfb_in),
.inclk (sub_wire7),
.areset (rst),
.clk (sub_wire0),
.fbout (clkfb_out),
.fbout (),//(clkfb_out),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
3651,18 → 3624,28
// write latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay1.depth=`CL+`AL-1;
defparam delay1.width=4;
defparam delay1.width=3;
delay delay1 (
.d({write, write, write, dqm_en_i}),
.q({dq_en, dq_oe, dqs_en, dqm_en}),
.d({write, write, dqm_en_i}),
.q({dq_en, dq_oe, dqm_en}),
.clk(sdram_clk_270),
.rst(wb_rst)
);
 
// write latency, delay the control signals to fit latency of the DDR2 SDRAM
defparam delay2.depth=`CL+`AL-1;
defparam delay2.width=1;
delay delay2 (
.d(write),
.q(dqs_en),
.clk(sdram_clk_0),
.rst(wb_rst)
);
 
// if CL>4 delay read from Tx FIFO
defparam delay2.depth=`CL+`AL-3;
defparam delay2.width=2;
delay delay2 (
defparam delay3.depth=`CL+`AL-3;
defparam delay3.width=2;
delay delay3 (
.d({tx_fifo_re_i && !wr_burst_mask, tx_fifo_re_i && !wr_burst_mask}),
.q({tx_fifo_re, adr_init_delay}),
.clk(sdram_clk_0),
3680,9 → 3663,9
// CL=3, not supported
 
// Increment address
defparam delay3.depth=`CL+`AL-1;
defparam delay3.width=1;
delay delay3 (
defparam delay4.depth=`CL+`AL-1;
defparam delay4.width=1;
delay delay4 (
.d({write|read}),
.q({adr_inc}),
.clk(sdram_clk_0),
/rtl/verilog/dcm_pll.v
140,20 → 140,20
.clk1_divide_by(1),
.clk1_duty_cycle(50),
.clk1_multiply_by(1),
.clk1_phase_shift("2000"),
.clk1_phase_shift("1250"),
.clk2_divide_by(1),
.clk2_duty_cycle(50),
.clk2_multiply_by(1),
.clk2_phase_shift("4000"),
.clk2_phase_shift("2500"),
.clk3_divide_by(1),
.clk3_duty_cycle(50),
.clk3_multiply_by(1),
.clk3_phase_shift("6000"),
.inclk0_input_frequency(8000),
.clk3_phase_shift("3750"),
.inclk0_input_frequency(5000),
.intended_device_family("Stratix III"),
.lpm_hint("CBX_MODULE_PREFIX=tmp_pll"),
.lpm_type("altpll"),
.operation_mode("EXTERNAL_FEEDBACK"),
.operation_mode("NORMAL"),
.pll_type("AUTO"),
.port_activeclock("PORT_UNUSED"),
.port_areset("PORT_USED"),
200,11 → 200,11
.using_fbmimicbidir_port("OFF"),
.width_clock(10))
altpll_internal (
.fbin (clkfb_in),
.fbin (),//(clkfb_in),
.inclk (sub_wire7),
.areset (rst),
.clk (sub_wire0),
.fbout (clkfb_out),
.fbout (),//(clkfb_out),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
/syn/altera/bin/versatile_memory_controller.sdc
1,9 → 1,26
#**************************************************************
# Time Information
#**************************************************************
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16 -5E)
 
# Clock cycle time: min=5.00ns, max=8.00ns
set tCK 5.000
 
# Input setup time: tISb=350ps, tISa=600ps
set tSU 0.600
 
# Input hold time: tIHb=470ps, tIHa=600ps
set tH 0.600
 
# DQS output access time from CK/CK#
set tDQSCKmin -0.500
set tDQSCKmax 0.500
 
# DQ output access time from CK/CK#
set tACmin -0.600
set tACmax 0.600
 
 
#**************************************************************
# Create Clock
#**************************************************************
10,11 → 27,11
 
# Clock frequency
set wb_clk_period 20.000
set sdram_clk_period 8.000
set sdram_clk_period $tCK
 
# Clocks
create_clock -name {wb_clk} -period $wb_clk_period
create_clock -name {sdram_clk} -period $sdram_clk_period
create_clock -name {wb_clk} -period $wb_clk_period [get_ports {wb_clk}]
create_clock -name {sdram_clk} -period $sdram_clk_period [get_ports {sdram_clk}]
 
# Virtual clocks
create_clock -name {v_wb_clk_in} -period $wb_clk_period
22,23 → 39,15
create_clock -name {v_sdram_clk_in} -period $sdram_clk_period
create_clock -name {v_sdram_clk_out} -period $sdram_clk_period
 
# Base clock for the PLL input clock port
create_clock -name pll_base_clock -period $sdram_clk_period [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}]
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
create_generated_clock -name {sdram_clk_0} -phase 0 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}]
create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*]
 
create_generated_clock -name {sdram_clk_180} -phase 180 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}]
 
create_generated_clock -name {sdram_clk_270} -phase 270 -source [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|inclk[0]}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}]
 
#derive_pll_clocks
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
56,66 → 65,32
# Set Input Delay
#**************************************************************
 
set ddr2_input_delay_min 0
set ddr2_input_delay_max 0
set_input_delay -clock {v_sdram_clk_in} -max $tACmax [get_ports {dq_pad_io[*]}]
set_input_delay -clock {v_sdram_clk_in} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
set_input_delay -clock {v_sdram_clk_in} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay
set_input_delay -clock {v_sdram_clk_in} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
 
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {ck_fb_pad_i}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dm_rdqs_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dq_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dqs_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {dqs_n_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_min [get_ports {rdqs_n_pad_i[*]}]
set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}]
set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay
set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
 
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {ck_fb_pad_i}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dm_rdqs_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dq_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dqs_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {dqs_n_pad_io[*]}]
set_input_delay -add_delay -clock { v_sdram_clk_in } $ddr2_input_delay_max [get_ports {rdqs_n_pad_i[*]}]
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
set ddr2_output_delay_min 0
set ddr2_output_delay_max 0
set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dq_pad_io[*]}]
set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dq_pad_io[*]}] -add_delay
set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay
 
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_n_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cke_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ck_fb_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cs_n_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ras_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {cas_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {we_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dm_rdqs_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {ba_pad_o[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {addr_pad_o[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dq_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_oe}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {dqs_n_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_min [get_ports {odt_pad_o}]
set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dqs_pad_io[*]}]
set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dqs_pad_io[*]}] -add_delay
set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay
 
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_n_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cke_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ck_fb_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cs_n_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ras_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {cas_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {we_pad_o}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dm_rdqs_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {ba_pad_o[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {addr_pad_o[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dq_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_oe}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {dqs_n_pad_io[*]}]
set_output_delay -add_delay -clock { v_sdram_clk_out } $ddr2_output_delay_max [get_ports {odt_pad_o}]
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
126,7 → 101,15
# Set False Path
#**************************************************************
 
# Reset
set_false_path -from [get_ports {wb_rst}]
# Input Timing Exceptions
#
# Output timing Exceptions
set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out]
set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out]
set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out]
set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out]
 
 
#**************************************************************
/syn/altera/bin/versatile_memory_controller.tcl
1,23 → 1,7
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Usage:
# cd /versatile_mem_ctrl/trunk/syn/altera/run/
# quartus_sh -t ../bin/versatile_memory_controller.tcl
 
# Quartus II: Generate Tcl File for Project
# File: versatile_memory_controller.tcl
# Generated on: Mon Feb 1 15:14:07 2010
 
# Usage: quartus_sh -t versatile_memory_controller.tcl
 
# Load Quartus II Tcl Project package
package require ::quartus::project
 

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