URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
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- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk
- from Rev 20 to Rev 21
- ↔ Reverse comparison
Rev 20 → Rev 21
/rtl/verilog/versatile_mem_ctrl_ip.v
2699,11 → 2699,13
.clk3_duty_cycle(50), |
.clk3_multiply_by(1), |
.clk3_phase_shift("3750"), |
.compensate_clock("CLK0"), |
.inclk0_input_frequency(5000), |
.intended_device_family("Stratix III"), |
.lpm_hint("CBX_MODULE_PREFIX=tmp_pll"), |
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
.operation_mode("NORMAL"), |
// .operation_mode("SOURCE_SYNCHRONOUS"), |
.pll_type("AUTO"), |
.port_activeclock("PORT_UNUSED"), |
.port_areset("PORT_USED"), |
/rtl/verilog/dcm_pll.v
149,11 → 149,13
.clk3_duty_cycle(50), |
.clk3_multiply_by(1), |
.clk3_phase_shift("3750"), |
.compensate_clock("CLK0"), |
.inclk0_input_frequency(5000), |
.intended_device_family("Stratix III"), |
.lpm_hint("CBX_MODULE_PREFIX=tmp_pll"), |
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
.operation_mode("NORMAL"), |
// .operation_mode("SOURCE_SYNCHRONOUS"), |
.pll_type("AUTO"), |
.port_activeclock("PORT_UNUSED"), |
.port_areset("PORT_USED"), |
/syn/altera/bin/versatile_memory_controller.sdc
1,7 → 1,7
#************************************************************** |
# Time Information |
#************************************************************** |
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16 -5E) |
# Timing specifications from Micron Data Sheet (DDR2 SDRAM MT47H32M16-5E) |
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# Clock cycle time: min=5.00ns, max=8.00ns |
set tCK 5.000 |
39,15 → 39,20
create_clock -name {v_sdram_clk_in} -period $sdram_clk_period |
create_clock -name {v_sdram_clk_out} -period $sdram_clk_period |
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#************************************************************** |
# Create Generated Clock |
#************************************************************** |
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create_generated_clock -name sdram_clk_0 -phase 0 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[0]}] |
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create_generated_clock -name sdram_clk_180 -phase 180 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[2]}] |
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create_generated_clock -name sdram_clk_270 -phase 270 -source [get_ports {sdram_clk}] [get_pins {dcm_pll_0|altpll_internal|auto_generated|pll1|clk[3]}] |
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create_generated_clock -name ck_pad_o -phase 0 -source [get_pins {ddr_ff_out_inst_2|altddio_out_inst|auto_generated|ddio_outa[0]|clkhi}] [get_ports ck_pad*] |
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#************************************************************** |
# Set Clock Latency |
#************************************************************** |
65,32 → 70,43
# Set Input Delay |
#************************************************************** |
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set_input_delay -clock {v_sdram_clk_in} -max $tACmax [get_ports {dq_pad_io[*]}] |
set_input_delay -clock {v_sdram_clk_in} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {ck_pad_o} -max $tACmax [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {ck_pad_o} -max $tACmax -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {ck_pad_o} -min $tACmin [get_ports {dq_pad_io[*]}] -add_delay |
set_input_delay -clock {ck_pad_o} -min $tACmin -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
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set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] |
set_input_delay -clock {v_sdram_clk_in} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay |
set_input_delay -clock {v_sdram_clk_in} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_pad_io[*]}] -add_delay |
#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_pad_io[*]}] -add_delay |
#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
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#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax [get_ports {dqs_n_pad_io[*]}] -add_delay |
#set_input_delay -clock {ck_pad_o} -max $tDQSCKmax -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay |
#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin [get_ports {dqs_n_pad_io[*]}] -add_delay |
#set_input_delay -clock {ck_pad_o} -min $tDQSCKmin -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay |
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#************************************************************** |
# Set Output Delay |
#************************************************************** |
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set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dq_pad_io[*]}] |
set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dq_pad_io[*]}] -add_delay |
set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dq_pad_io[*]}] -add_delay |
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set_output_delay -clock {v_sdram_clk_out} -max $tSU [get_ports {dqs_pad_io[*]}] |
set_output_delay -clock {v_sdram_clk_out} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH [get_ports {dqs_pad_io[*]}] -add_delay |
set_output_delay -clock {v_sdram_clk_out} -min $tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
#set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dqs_pad_io[*]}] -add_delay |
#set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
#set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dqs_pad_io[*]}] -add_delay |
#set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dqs_pad_io[*]}] -add_delay |
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#set_output_delay -clock {ck_pad_o} -max $tSU [get_ports {dqs_n_pad_io[*]}] -add_delay |
#set_output_delay -clock {ck_pad_o} -max $tSU -clock_fall [get_ports {dqs_pad_n_io[*]}] -add_delay |
#set_output_delay -clock {ck_pad_o} -min -$tH [get_ports {dqs_n_pad_io[*]}] -add_delay |
#set_output_delay -clock {ck_pad_o} -min -$tH -clock_fall [get_ports {dqs_n_pad_io[*]}] -add_delay |
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#************************************************************** |
# Set Clock Groups |
#************************************************************** |
103,15 → 119,20
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# Reset |
set_false_path -from [get_ports {wb_rst}] |
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# Input Timing Exceptions |
# |
# Output timing Exceptions |
set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out] |
set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out] |
set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks v_sdram_clk_out] |
set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks v_sdram_clk_out] |
set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] |
set_false_path -setup -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] |
set_false_path -hold -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] |
set_false_path -hold -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] |
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# Output Timing Exceptions |
set_false_path -setup -rise_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o] |
set_false_path -setup -fall_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o] |
set_false_path -hold -rise_from [get_clocks sdram_clk_270] -rise_to [get_clocks ck_pad_o] |
set_false_path -hold -fall_from [get_clocks sdram_clk_270] -fall_to [get_clocks ck_pad_o] |
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#************************************************************** |
# Set Multicycle Path |
#************************************************************** |
134,3 → 155,10
# Set Input Transition |
#************************************************************** |
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#************************************************************** |
# Set Input Transition |
#************************************************************** |
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