URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl/trunk
- from Rev 28 to Rev 29
- ↔ Reverse comparison
Rev 28 → Rev 29
/bench/tb.v
5,6 → 5,14
output OK |
); |
|
// number of wb clock domains |
parameter nr_of_wb_clk_domains = 1; |
// number of wb ports in each wb clock domain |
parameter nr_of_wb_ports_clk0 = 3; |
parameter nr_of_wb_ports_clk1 = 0; |
parameter nr_of_wb_ports_clk2 = 0; |
parameter nr_of_wb_ports_clk3 = 0; |
|
reg sdram_clk, wb_clk, wb_rst; |
|
wire [31:0] wb0_dat_i; |
48,6 → 56,20
wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked; |
wire ck_fb_i, ck_fb_o; |
|
// |
wire [36*nr_of_wb_ports_clk0-1:0] wb_dat_i_v; |
wire [36*nr_of_wb_ports_clk0-1:0] wb_adr_i_v; |
wire [31:0] wb_dat_o_v; |
wire [0:nr_of_wb_ports_clk0-1] wb_cyc_i_v; |
wire [0:nr_of_wb_ports_clk0-1] wb_stb_i_v; |
wire [0:nr_of_wb_ports_clk0-1] wb_ack_o_v; |
// |
assign wb_dat_i_v = {4'h0,wb4_dat_i,4'h0,wb1_dat_i,3'h0,wb0_dat_i}; |
assign wb_adr_i_v = {4'h0,wb4_adr_i,4'h0,wb1_adr_i,3'h0,wb0_adr_i}; |
assign wb_cyc_i_v = {wb4_cyc_i,wb1_cyc_i,wb0_cyc_i}; |
assign wb_stb_i_v = {wb4_stb_i,wb1_stb_i,wb0_stb_i}; |
assign wb_ack_o_v = {}; |
|
`ifdef SDR_16 // SDR SDRAM |
wb0 wb0i |
( |
144,78 → 166,91
); |
`endif |
|
versatile_mem_ctrl_top dut |
( |
.wbs0_dat_i(wb0_dat_i), |
.wbs0_dat_o(wb0_dat_o), |
.wbs0_adr_i(wb0_adr_i[31:2]), |
.wbs0_sel_i(wb0_sel_i), |
.wbs0_cti_i(wb0_cti_i), |
.wbs0_bte_i(wb0_bte_i), |
.wbs0_we_i (wb0_we_i), |
.wbs0_cyc_i(wb0_cyc_i), |
.wbs0_stb_i(wb0_stb_i), |
.wbs0_ack_o(wb0_ack_o), |
.wbs1_dat_i(wb1_dat_i), |
.wbs1_dat_o(wb1_dat_o), |
.wbs1_adr_i(wb1_adr_i[31:2]), |
.wbs1_sel_i(wb1_sel_i), |
.wbs1_cti_i(wb1_cti_i), |
.wbs1_bte_i(wb1_bte_i), |
.wbs1_we_i (wb1_we_i), |
.wbs1_cyc_i(wb1_cyc_i), |
.wbs1_stb_i(wb1_stb_i), |
.wbs1_ack_o(wb1_ack_o), |
.wbs4_dat_i(wb4_dat_i), |
.wbs4_dat_o(wb4_dat_o), |
.wbs4_adr_i(wb4_adr_i[31:2]), |
.wbs4_sel_i(wb4_sel_i), |
.wbs4_cti_i(wb4_cti_i), |
.wbs4_bte_i(wb4_bte_i), |
.wbs4_we_i (wb4_we_i), |
.wbs4_cyc_i(wb4_cyc_i), |
.wbs4_stb_i(wb4_stb_i), |
.wbs4_ack_o(wb4_ack_o), |
// SDR SDRAM 16 |
`ifdef SDR_16 |
.ba_pad_o(ba), |
.a_pad_o(a), |
.cs_n_pad_o(cs_n), |
.ras_pad_o(ras), |
.cas_pad_o(cas), |
.we_pad_o(we), |
.dq_o(dq_o), |
.dqm_pad_o(dqm), |
.dq_i(dq_i), |
.dq_oe(dq_oe), |
.cke_pad_o(cke), |
`endif |
`ifdef DDR_16 |
// DDR2 SDRAM 16 |
.ck_pad_o(ck), |
.ck_n_pad_o(ck_n), |
.cke_pad_o(cke), |
.ck_fb_pad_o(ck_fb_o), |
.ck_fb_pad_i(ck_fb_i), |
.cs_n_pad_o(cs_n), |
.ras_pad_o(ras), |
.cas_pad_o(cas), |
.we_pad_o(we), |
.dm_rdqs_pad_io(dm_rdqs), |
.ba_pad_o(ba), |
.addr_pad_o(a), |
.dq_pad_io(dq_io), |
.dqs_pad_io(dqs_io), |
.dqs_oe(dqs_oe), |
.dqs_n_pad_io(dqs_n_io), |
.rdqs_n_pad_i(), |
.odt_pad_o(), |
`endif |
// misc |
.wb_clk(wb_clk), |
.wb_rst(wb_rst), |
.sdram_clk(sdram_clk) |
); |
versatile_mem_ctrl_top dut ( |
// wb clk0 |
.wb_dat_i_0(wb_dat_i_v), |
.wb_dat_o_0(wb_dat_o_v), |
.wb_adr_i_0(wb_adr_i_v), |
//.wb_sel_i_0(), |
//.wb_cti_i_0(), |
//.wb_bte_i_0(), |
//.wb_we_i_0(), |
.wb_cyc_i_0(wb_cyc_i_v), |
.wb_stb_i_0(wb_stb_i_v), |
.wb_ack_o_0(wb_ack_o_v), |
// wb clk1 |
/* .wb_dat_i_1(), |
.wb_dat_o_1(), |
.wb_adr_i_1(), |
.wb_sel_i_1(), |
.wb_cti_i_1(), |
.wb_bte_i_1(), |
.wb_we_i_1(), |
.wb_cyc_i_1(), |
.wb_stb_i_1(), |
.wb_ack_o_1(), */ |
// wb clk2 |
/* .wb_dat_i_2(), |
.wb_dat_o_2(), |
.wb_adr_i_2(), |
.wb_sel_i_2(), |
.wb_cti_i_2(), |
.wb_bte_i_2(), |
.wb_we_i_2(), |
.wb_cyc_i_2(), |
.wb_stb_i_2(), |
.wb_ack_o_2(), */ |
// wb clk3 |
/* .wb_dat_i_3(), |
.wb_dat_o_3(), |
.wb_adr_i_3(), |
.wb_sel_i_3(), |
.wb_cti_i_3(), |
.wb_bte_i_3(), |
.wb_we_i_3(), |
.wb_cyc_i_3(), |
.wb_stb_i_3(), |
.wb_ack_o_3(), */ |
// SDR SDRAM 16 |
`ifdef SDR_16 |
.ba_pad_o(ba), |
.a_pad_o(a), |
.cs_n_pad_o(cs_n), |
.ras_pad_o(ras), |
.cas_pad_o(cas), |
.we_pad_o(we), |
.dq_o(dq_o), |
.dqm_pad_o(dqm), |
.dq_i(dq_i), |
.dq_oe(dq_oe), |
.cke_pad_o(cke), |
`endif |
`ifdef DDR_16 |
// DDR2 SDRAM 16 |
.ck_pad_o(ck), |
.ck_n_pad_o(ck_n), |
.cke_pad_o(cke), |
.ck_fb_pad_o(ck_fb_o), |
.ck_fb_pad_i(ck_fb_i), |
.cs_n_pad_o(cs_n), |
.ras_pad_o(ras), |
.cas_pad_o(cas), |
.we_pad_o(we), |
.dm_rdqs_pad_io(dm_rdqs), |
.ba_pad_o(ba), |
.addr_pad_o(a), |
.dq_pad_io(dq_io), |
.dqs_pad_io(dqs_io), |
.dqs_oe(dqs_oe), |
.dqs_n_pad_io(dqs_n_io), |
.rdqs_n_pad_i(), |
.odt_pad_o(), |
`endif |
// misc |
.wb_clk(wb_clk), |
.wb_rst(wb_rst), |
.sdram_clk(sdram_clk) |
); |
|
`ifdef SDR_16 |
assign #1 dq_io = dq_oe ? dq_o : {16{1'bz}}; |