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    /versatile_mem_ctrl/trunk
    from Rev 75 to Rev 76
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Rev 75 → Rev 76

/rtl/verilog/versatile_mem_ctrl_top.v
76,7 → 76,7
output we_pad_o;
output reg [(`SDRAM_DATA_WIDTH)-1:0] dq_o /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output [1:0] dqm_pad_o;
input [(`SDRAM_DATA_WIDTH)-1:0] dq_i /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
input [(`SDRAM_DATA_WIDTH)-1:0] dq_i ;
output dq_oe;
output cke_pad_o;
`endif
290,7 → 290,8
`ifdef SDR_16
 
wire ref_cnt_zero;
reg [(`SDRAM_DATA_WIDTH)-1:0] dq_i_reg, dq_i_tmp_reg;
reg [(`SDRAM_DATA_WIDTH)-1:0] dq_i_reg /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
reg [(`SDRAM_DATA_WIDTH)-1:0] dq_i_tmp_reg;
reg [17:0] dq_o_tmp_reg;
wire cmd_aref, cmd_read;
368,13 → 369,13
// output registers
assign cs_n_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
always @ (posedge sdram_clk)
dq_i_reg <= dq_i;
 
always @(posedge sdram_clk)
dq_i_tmp_reg <= dq_i_reg;
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{dq_i_reg, dq_i_tmp_reg} <= {16'h0000,16'h0000};
else
{dq_i_reg, dq_i_tmp_reg} <= {dq_i, dq_i_reg};
 
assign fifo_dat_i = {dq_i_tmp_reg, dq_i_reg};
always @ (posedge sdram_clk or posedge sdram_rst)
/rtl/verilog/fsm_wb.v
1,89 → 1,93
module fsm_wb (
stall_i, stall_o,
we_i, cti_i, bte_i, stb_i, cyc_i, ack_o,
egress_fifo_we, egress_fifo_full,
ingress_fifo_re, ingress_fifo_empty,
state_idle,
wb_clk, wb_rst
);
stall_i, stall_o,
we_i, cti_i, bte_i, stb_i, cyc_i, ack_o,
egress_fifo_we, egress_fifo_full,
ingress_fifo_re, ingress_fifo_empty,
state_idle,
wb_clk, wb_rst
);
 
input stall_i;
output stall_o;
input stall_i;
output stall_o;
 
input [2:0] cti_i;
input [1:0] bte_i;
input we_i, stb_i, cyc_i;
output ack_o;
output egress_fifo_we, ingress_fifo_re;
input egress_fifo_full, ingress_fifo_empty;
output state_idle;
input wb_clk, wb_rst;
input [2:0] cti_i;
input [1:0] bte_i;
input we_i, stb_i, cyc_i;
output ack_o;
output egress_fifo_we, ingress_fifo_re;
input egress_fifo_full, ingress_fifo_empty;
output state_idle;
input wb_clk, wb_rst;
 
reg ingress_fifo_read_reg;
reg ingress_fifo_read_reg;
 
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter endofburst = 3'b111;
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter endofburst = 3'b111;
 
parameter idle = 2'b00;
parameter rd = 2'b01;
parameter wr = 2'b10;
parameter fe = 2'b11;
reg [1:0] state;
parameter idle = 2'b00;
parameter rd = 2'b01;
parameter wr = 2'b10;
parameter fe = 2'b11;
reg [1:0] state;
 
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
state <= idle;
else
case (state)
idle:
if (we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= wr;
else if (!we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= rd;
wr:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= idle;
rd:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) & stb_i & cyc_i & ack_o)
state <= fe;
fe:
if (ingress_fifo_empty)
state <= idle;
default: ;
endcase
assign state_idle = (state==idle);
assign stall_o = (stall_i) ? 1'b1 :
(state==idle & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==rd & stb_i & cyc_i & !ingress_fifo_empty) ? 1'b1 :
(state==fe & !ingress_fifo_empty) ? 1'b1 :
1'b0;
assign egress_fifo_we = (state==idle & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
state <= idle;
else
case (state)
idle:
if (we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= wr;
else if (!we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= rd;
wr:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) &
stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= idle;
rd:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) &
stb_i & cyc_i & ack_o)
state <= fe;
fe:
if (ingress_fifo_empty)
state <= idle;
default: ;
endcase
assign state_idle = (state==idle);
assign stall_o = (stall_i) ? 1'b1 :
(state==idle & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==rd & stb_i & cyc_i & !ingress_fifo_empty) ? 1'b1 :
(state==fe & !ingress_fifo_empty) ? 1'b1 :
1'b0;
assign egress_fifo_we = (state==idle & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;
assign ingress_fifo_re = (state==rd & stb_i & cyc_i & !ingress_fifo_empty & !stall_i) ? 1'b1 :
(state==fe & !ingress_fifo_empty & !stall_i) ? 1'b1:
1'b0;
assign ingress_fifo_re = (state==rd & stb_i & cyc_i & !ingress_fifo_empty & !stall_i) ? 1'b1 :
(state==fe & !ingress_fifo_empty & !stall_i) ? 1'b1:
1'b0;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
ingress_fifo_read_reg <= 1'b0;
else
ingress_fifo_read_reg <= ingress_fifo_re;
assign ack_o = (ingress_fifo_read_reg) ? 1'b1 :
(state==fe) ? 1'b0 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
ingress_fifo_read_reg <= 1'b0;
else
ingress_fifo_read_reg <= ingress_fifo_re;
/*assign ack_o = (ingress_fifo_read_reg & stb_i) ? 1'b1 :
(state==fe) ? 1'b0 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;*/
 
assign ack_o = !(state==fe) & ((ingress_fifo_read_reg & stb_i) | (state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i));
endmodule
/rtl/verilog/sdr_16_defines.v
8,8 → 8,8
 
// Most of these defines have an effect on things in fsm_sdr_16.v
 
//`define MT48LC16M16 // 32MB part
`define MT48LC4M16 // 8MB part
`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part
 
 
`ifdef MT48LC16M16

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