OpenCores
URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

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  • This comparison shows the changes necessary to convert path 
    /versatile_mem_ctrl/trunk
    from Rev 79 to Rev 80
    ↔ Reverse comparison
  •

Rev 79 → Rev 80

/bench/tb.v
5,7 → 5,9
output OK
);
 
reg sdram_clk, wb_clk, wb_rst;
reg wb_clk, wb_rst;
reg sdram_clk, sdram_rst;
reg tb_rst;
 
wire [31:0] wb0_dat_i;
wire [3:0] wb0_sel_i;
110,7 → 112,7
.ack(wb0_ack_o),
.clk(wb_clk),
.dat_i(wb0_dat_o),
.reset(wb_rst)
.reset(tb_rst)
);
wb1_ddr wb1i
(
125,7 → 127,7
.ack(wb1_ack_o),
.clk(wb_clk),
.dat_i(wb1_dat_o),
.reset(wb_rst)
.reset(tb_rst)
);
wb4_ddr wb4i
(
140,13 → 142,13
.ack(wb4_ack_o),
.clk(wb_clk),
.dat_i(wb4_dat_o),
.reset(wb_rst)
.reset(tb_rst)
);
`endif
 
versatile_mem_ctrl_top # (
.nr_of_wb_clk_domains(2),
.nr_of_wb_ports_clk0(2),
.nr_of_wb_ports_clk0(1),
.nr_of_wb_ports_clk1(1),
.nr_of_wb_ports_clk2(0),
.nr_of_wb_ports_clk3(0))
279,26 → 281,48
.odt()
);
`endif
 
// Wishbone reset
initial
begin
#0 wb_rst = 1'b1;
#200 wb_rst = 1'b1;
#0 wb_rst = 1'b1;
#200 wb_rst = 1'b1;
#200000 wb_rst = 1'b0;
end
 
// SDRAM reset
initial
begin
#0 sdram_rst = 1'b1;
#200 sdram_rst = 1'b1;
#200000 sdram_rst = 1'b0;
end
// Test bench reset
initial
begin
#0 tb_rst = 1'b1;
#200 tb_rst = 1'b1;
//#200000 tb_rst = 1'b0;
#300000 tb_rst = 1'b0; // hold reset to let initialization complete
end
 
// Wishbone clock
initial
begin
#0 wb_clk = 1'b0;
forever
#200 wb_clk = !wb_clk; // 25MHz
//#200 wb_clk = !wb_clk; // 2.5 MHz
#20 wb_clk = !wb_clk; // 25 MHz
end
 
// SDRAM clock
initial
begin
#0 sdram_clk = 1'b0;
forever
#4 sdram_clk = !sdram_clk; // 125MHz
//#4 sdram_clk = !sdram_clk; // 125 MHz
#5 sdram_clk = !sdram_clk; // 100 MHz
end
endmodule // versatile_mem_ctrl_tb
/bench/wb1_ddr.fzm
1,4 → 1,4
## File last modified by Fizzim: 1:27:11 PM on 4/13/10
## File last modified by Fizzim: 1:20:37 PM on 6/7/10
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1251,10 → 1251,10
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def_type
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output
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<type>
output
<status>
GLOBAL_VAR
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LOCAL
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</value>
<vis>
1
<status>
GLOBAL_VAR
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</vis>
<type>
output
<status>
GLOBAL_VAR
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<comment>
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GLOBAL_VAR
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<color>
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<status>
GLOBAL_VAR
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<vis>
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<status>
GLOBAL_VAR
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</vis>
<type>
output
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GLOBAL_VAR
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</type>
<comment>
<status>
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<color>
-16777216
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<reset>
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<color>
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<state>
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<status>
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state10
<status>
LOCAL
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</value>
<vis>
1
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GLOBAL_VAR
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</vis>
<type>
def_type
<status>
GLOBAL_VAR
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</type>
<comment>
<status>
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<color>
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</color>
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<value>
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1
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GLOBAL_VAR
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<type>
output
<status>
GLOBAL_VAR
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<value>
32'h0
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GLOBAL_VAR
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GLOBAL_VAR
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</vis>
<type>
output
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GLOBAL_VAR
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</type>
<comment>
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<color>
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<status>
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</color>
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4'b1111
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output
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GLOBAL_VAR
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<status>
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3287,16 → 5305,16
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525
25
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680
755
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<reset>
false
3317,7 → 5335,7
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trans3
trans6
<status>
LOCAL
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3361,9 → 5379,9
ABS
</status>
<value>
ack
1
<status>
LOCAL
GLOBAL_VAR
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</value>
<vis>
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14
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<page>
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3402,34 → 5420,34
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state10
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3480,7 → 5498,7
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state8
state13
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3873,16 → 5891,16
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550
800
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775
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680
930
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155
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3903,7 → 5921,7
ABS
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trans5
trans9
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3977,10 → 5995,10
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44
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<page>
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3988,34 → 6006,34
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state11_1
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trans10
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def_type
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def_type
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4066,7 → 6247,7
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state14_0
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4110,7 → 6291,7
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32'h2014
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<type>
output
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32'h2014
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32'h0
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</endState>
<startPtX>
1040.0
</startPtX>
<startPtY>
905.0
</startPtY>
<endPtX>
1040.0
</endPtX>
<endPtY>
1025.0
</endPtY>
<startCtrlPtX>
1040.0
</startCtrlPtX>
<startCtrlPtY>
930.0
</startCtrlPtY>
<endCtrlPtY>
1040.0
</endCtrlPtY>
<endCtrlPtY>
999.0
</endCtrlPtY>
<startStateIndex>
9
</startStateIndex>
<endStateIndex>
27
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<page>
1
</page>
</textObj>
<textObj>
(NOP)
<x>
531
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<y>
797
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<color>
-16777216
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0.0
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0.0
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0.0
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<pageECY>
0.0
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<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
ABS
</status>
<value>
trans32
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
1
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
1
<status>
GLOBAL_VAR
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
2
</x2Obj>
<y2Obj>
-50
</y2Obj>
<page>
1
</page>
</equation>
</attributes>
<startState>
state17_3
</startState>
<endState>
state19
</endState>
<startPtX>
1081.0
</startPtX>
<startPtY>
1040.0
</startPtY>
<endPtX>
1153.0
</endPtX>
<endPtY>
112.0
</endPtY>
<startCtrlPtX>
1144.0
</startCtrlPtX>
<startCtrlPtY>
828.0
</startCtrlPtY>
<endCtrlPtY>
1111.0
</endCtrlPtY>
<endCtrlPtY>
268.0
</endCtrlPtY>
<startStateIndex>
31
</startStateIndex>
<endStateIndex>
16
</endStateIndex>
<page>
1
</page>
</textObj>
<textObj>
(NOP)
<x>
781
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<y>
279
</y>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
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<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
ABS
</status>
<value>
trans33
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
1
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
ack
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
13
</x2Obj>
<y2Obj>
44
</y2Obj>
<page>
1
</page>
</equation>
</attributes>
<startState>
state14_0
</startState>
<endState>
state14_1
</endState>
<startPtX>
865.0
</startPtX>
<startPtY>
405.0
</startPtY>
<endPtX>
865.0
</endPtX>
<endPtY>
525.0
</endPtY>
<startCtrlPtX>
865.0
</startCtrlPtX>
<startCtrlPtY>
430.0
</startCtrlPtY>
<endCtrlPtY>
865.0
</endCtrlPtY>
<endCtrlPtY>
499.0
</endCtrlPtY>
<startStateIndex>
9
</startStateIndex>
<endStateIndex>
27
</endStateIndex>
<page>
1
</page>
</textObj>
<textObj>
(NOP)
<x>
311
</x>
<y>
33
</y>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
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0.0
</PageSCX>
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0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
ABS
</status>
<value>
trans34
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
1
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
ack
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
15
</x2Obj>
<y2Obj>
44
</y2Obj>
<page>
1
</page>
</equation>
</attributes>
<startState>
state17_0
</startState>
<endState>
state17_1
</endState>
<startPtX>
1040.0
</startPtX>
<startPtY>
405.0
</startPtY>
<endPtX>
1040.0
</endPtX>
<endPtY>
525.0
</endPtY>
<startCtrlPtX>
1040.0
</startCtrlPtX>
<startCtrlPtY>
430.0
</startCtrlPtY>
<endCtrlPtY>
1040.0
</endCtrlPtY>
<endCtrlPtY>
499.0
</endCtrlPtY>
<startStateIndex>
9
</startStateIndex>
<endStateIndex>
27
</endStateIndex>
<page>
1
</page>
</textObj>
<textObj>
(Burst write)
<x>
288
</x>
<y>
280
</y>
<page>
1
</page>
</textObj>
<textObj>
(Read burst)
<x>
542
</x>
<y>
274
</y>
<page>
1
</page>
</textObj>
<textObj>
(NOP)
<x>
541
</x>
<y>
531
</y>
<page>
1
</page>
</textObj>
<textObj>
(Read burst)
<x>
508
</x>
<y>
1035
</y>
<page>
1
</page>
</textObj>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## END OBJECTS
/rtl/verilog/egress_fifo.v
2,7 → 2,7
 
module egress_fifo (
d, fifo_full, write, write_enable, clk1, rst1,
q, fifo_empty, read_adr, read_data, read_enable, clk2, rst2
q, fifo_empty, fifo_flag, read_adr, read_data, read_enable, clk2, rst2
);
 
parameter a_hi_size = 4;
18,7 → 18,9
input rst1;
 
output reg [data_width-1:0] q;
output [0:nr_of_queues-1] fifo_empty;
output [0:nr_of_queues-1] fifo_empty;
output [0:nr_of_queues-1] fifo_flag;
input read_adr, read_data;
input [0:nr_of_queues-1] read_enable;
input clk2;
35,6 → 37,8
reg [data_width-1:0] wdata;
wire [data_width-1:0] wdataa[0:nr_of_queues-1];
 
wire [a_hi_size-1:0] fifo_fill_i[0:nr_of_queues-1];
 
reg read_adr_reg;
reg [0:nr_of_queues-1] read_enable_reg;
 
91,7 → 95,8
.wptr(fifo_wadr_gray[i]),
.rptr(fifo_radr_gray[i]),
.fifo_empty(fifo_empty[i]),
.fifo_full(fifo_full[i]),
.fifo_full(fifo_full[i]),
.fifo_flag(fifo_flag[i]),
.wclk(clk1),
.rclk(clk2),
.rst(rst1));
110,6 → 115,19
 
// and-or mux read address
always @*
begin
if (nr_of_queues > 1) begin
radr = {a_lo_size{1'b0}};
for (k=0;k<nr_of_queues;k=k+1) begin
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable_reg[k]}}) | radr;
end
end
else
radr = fifo_radr_bin[0];
end
/*
always @*
begin
radr = {a_lo_size{1'b0}};
for (k=0;k<nr_of_queues;k=k+1) begin
116,6 → 134,7
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable_reg[k]}}) | radr;
end
end
*/
 
// and-or mux write data
generate
147,6 → 166,6
// Added registering of FIFO output to break a timing path
always@(posedge clk2)
q <= fifo_q;
 
 
endmodule
/rtl/verilog/versatile_mem_ctrl_top.v
103,6 → 103,7
input sdram_clk, sdram_rst;
 
wire [0:15] fifo_empty[0:3];
wire [0:15] fifo_flag[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
wire [35:0] fifo_dat_o[0:3];
142,6 → 143,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[0]),
.sdram_fifo_empty(fifo_empty[0][0:nr_of_wb_ports_clk0-1]),
.sdram_fifo_flag(fifo_flag[0][0:nr_of_wb_ports_clk0-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[0][0:nr_of_wb_ports_clk0-1]),
154,6 → 156,7
end
if (nr_of_wb_ports_clk0 < 16) begin
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}};
assign fifo_flag[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b0}};
end
endgenerate
 
175,6 → 178,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[1]),
.sdram_fifo_empty(fifo_empty[1][0:nr_of_wb_ports_clk1-1]),
.sdram_fifo_flag(fifo_flag[1][0:nr_of_wb_ports_clk1-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[1][0:nr_of_wb_ports_clk1-1]),
186,9 → 190,11
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk1 < 16) begin
assign fifo_empty[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b1}};
assign fifo_flag[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b0}};
end
end else begin
assign fifo_empty[1] = {16{1'b1}};
assign fifo_flag[1] = {16{1'b0}};
assign fifo_dat_o[1] = {36{1'b0}};
end
endgenerate
211,6 → 217,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[2]),
.sdram_fifo_empty(fifo_empty[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_flag(fifo_flag[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[2][0:nr_of_wb_ports_clk2-1]),
222,9 → 229,11
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk2 < 16) begin
assign fifo_empty[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b1}};
assign fifo_flag[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b0}};
end
end else begin
assign fifo_empty[2] = {16{1'b1}};
assign fifo_flag[2] = {16{1'b0}};
assign fifo_dat_o[2] = {36{1'b0}};
end
endgenerate
247,6 → 256,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[3]),
.sdram_fifo_empty(fifo_empty[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_flag(fifo_flag[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[3][0:nr_of_wb_ports_clk3-1]),
258,9 → 268,11
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk3 < 16) begin
assign fifo_empty[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b1}};
assign fifo_flag[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b0}};
end
end else begin
assign fifo_empty[3] = {16{1'b1}};
assign fifo_flag[3 ] = {16{1'b0}};
assign fifo_dat_o[3] = {36{1'b0}};
end
endgenerate
457,53 → 469,62
reg cke, ras, cas, we, cs_n;
wire cke_d, ras_d, cas_d, we_d, cs_n_d;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire [1:0] ba_o;
wire [12:0] addr_o;
reg [1:0] ba;
wire [1:0] ba_d;
reg [12:0] addr;
reg [1:0] ba;
wire [1:0] ba_d;
reg [12:0] addr;
wire [12:0] addr_d;
wire dq_en, dqm_en;
reg [15:0] dq_tx_reg;
reg [15:0] dq_tx_reg;
wire [15:0] dq_tx;
reg [31:0] dq_rx_reg;
reg [31:0] dq_rx_reg;
wire [31:0] dq_rx;
wire [15:0] dq_o;
reg [3:0] dqm_tx_reg;
wire [3:0] dqm_tx;
wire [1:0] dqm_o, dqs_o, dqs_n_o;
reg [3:0] dqm_tx_reg;
wire [3:0] dqm_tx;
wire [1:0] dqm_o, dqs_o, dqs_n_o;
wire ref_delay, ref_delay_ack;
wire bl_en, bl_ack;
wire tx_fifo_re, tx_fifo_re_i;
//wire adr_init_delay;
//reg adr_init_delay_i;
reg [3:0] burst_cnt;
wire [3:0] burst_next_cnt, burst_length;
//wire burst_mask;
reg [3:0] burst_cnt;
wire [3:0] burst_next_cnt, burst_length;
reg burst_mask;
wire [12:0] cur_row;
wire [3:0] burst_adr;
//wire [2:0] tx_fifo_b_sel_i_cur;
wire [2:0] rx_fifo_a_sel_i;
//wire [7:0] tx_fifo_empty;
wire rx_fifo_we;
 
wire ref_cnt_zero;
wire cmd_aref;
wire ref_cnt_zero;
wire cmd_aref;
reg [4:0] fill_0;
wire [1:0] bte_i;
reg stall;
wire [0:63] fifo_re_vec, fifo_flag_vec, stall_vec;
wire write_i, burst_avail, burst;
wire open_cur_row, close_cur_row;
wire [12:0] open_row_i, next_row;
wire [1:0] open_bank_i, next_bank;
reg [12:0] open_row[0:3];
reg [3:0] open_ba;
wire next_row_open, current_bank_closed, current_row_open;
reg current_bank_closed_reg, current_row_open_reg;
// refresh counter
ref_counter ref_counter0(
.zq(ref_cnt_zero),
.rst(sdram_rst),
.clk(sdram_clk));
ref_counter ref_counter0
(
.zq(ref_cnt_zero),
.rst(sdram_rst),
.clk(sdram_clk)
);
 
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
 
// DDR SDRAM 16 FSM
ddr_16 ddr_16_0
514,7 → 535,7
.tx_fifo_dat_o(fifo_dat_o[fifo_sel_domain_reg]),
.burst_adr(burst_adr),
.fifo_empty(current_fifo_empty),
.fifo_sel(),
.stall(stall),
.read(read),
.write(write),
.ref_req(refresh_req),
527,11 → 548,66
.a({ba_o,addr_o}),
.cmd({ras_o,cas_o,we_o}),
.cs_n(cs_n_o),
.cur_row(cur_row),
.open_ba(open_bank_i),
.open_row(open_row_i),
.open_cur_row(open_cur_row),
.close_cur_row(close_cur_row),
.next_row_open(next_row_open),
.clk(sdram_clk_0),
.rst(sdram_rst)
);
 
// Check if a burst is available in FIFO
genvar j;
generate
for (j=0;j<4;j=j+1) begin : array_to_vector
assign fifo_flag_vec[(j*16):(j*16+15)] = fifo_flag[j];
assign fifo_re_vec[(j*16):(j*16+15)] = fifo_re[j];
end
endgenerate
assign write_i = fifo_dat_o[fifo_sel_domain_reg][5];
assign bte_i = fifo_dat_o[fifo_sel_domain_reg][4:3];
assign burst = (bte_i == 2'b01) ? 1'b1 : 1'b0;
assign burst_avail = |(fifo_flag_vec & fifo_re_vec);
 
always @ (write_i or burst or burst_avail)
if (write_i)
if (burst)
if (burst_avail)
stall <= 1'b0; // burst write, with burst in FIFO
else
stall <= 1'b1; // burst write, no burst in FIFO
else
stall <= 1'b0; // single wite
else
stall <= 1'b0; // read (single or burst)
 
// sdram_clock is faster than wb_clk
assign burst_reading = 1'b0;
 
// Keep track of open row in banks
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst) begin
open_row[0] <= 13'b0;
open_row[1] <= 13'b0;
open_row[2] <= 13'b0;
open_row[3] <= 13'b0;
end else begin
if (open_cur_row)
open_row[open_bank_i] <= open_row_i;
else if (close_cur_row)
open_row[open_bank_i] <= 13'b0;
end
// Bank and row of next read/write operation
assign next_bank = fifo_dat_o[fifo_sel_domain_reg][28:27];
assign next_row = fifo_dat_o[fifo_sel_domain_reg][26:14];
// Check if next row is open
assign next_row_open = (next_row == open_row[next_bank]);
// Calculate the address
inc_adr inc_adr0
(
.adr_i(fifo_dat_o[fifo_sel_domain_reg][9:6]),
577,8 → 653,6
else
if (bl_en)
burst_cnt <= burst_next_cnt;
// Burst Mask
//assign burst_mask = (burst_cnt >= burst_length) ? 1'b1 : 1'b0;
 
// Burst Mask
always @ (posedge sdram_clk_0 or posedge sdram_rst)
587,14 → 661,16
else
burst_mask <= (burst_cnt >= burst_length) ? 1'b1 : 1'b0;
 
// Delay address and control to compensate for delay in Tx FIOFs
// Delay address and control to compensate for delay in TxFIOFs
defparam delay0.depth=3;
defparam delay0.width=20;
delay delay0 (
delay delay0
(
.d({cs_n_o,1'b1,ras_o,cas_o,we_o,ba_o,addr_o}),
.q({cs_n_d,cke_d,ras_d,cas_d,we_d,ba_d,addr_d}),
.clk(sdram_clk_180),
.rst(sdram_rst));
.rst(sdram_rst)
);
 
// Assing outputs
// Non-DDR outputs
661,26 → 737,27
genvar i;
generate
for (i=0; i < 16; i=i+1) begin : dly
 
defparam delay4.depth=`CL+2;
defparam delay4.width=1;
delay delay4 (
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
delay delay4
(
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
end
defparam delay5.depth=`CL+2;
defparam delay5.width=2;
delay delay5 (
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
delay delay5
(
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
 
 
// Increment address
728,7 → 805,8
.clk_0(sdram_clk_0),
.clk_90(sdram_clk_90),
.clk_180(sdram_clk_180),
.clk_270(sdram_clk_270));
.clk_270(sdram_clk_270)
);
 
`endif // `ifdef DDR_16
/rtl/verilog/ddr_16.fzm
1,4 → 1,4
## File last modified by Fizzim: 1:56:06 PM on 4/16/10
## File last modified by Fizzim: 12:16:57 PM on 6/8/10
<version>
8.04.05
</version>
446,7 → 446,7
-1
</page>
</fifo_empty>
<fifo_sel[2:0]>
<tx_fifo_dat_o[35:0]>
<status>
GLOBAL_FIXED
</status>
489,8 → 489,8
<page>
-1
</page>
</fifo_sel[2:0]>
<tx_fifo_dat_o[35:0]>
</tx_fifo_dat_o[35:0]>
<burst_adr[3:0]>
<status>
GLOBAL_FIXED
</status>
533,8 → 533,8
<page>
-1
</page>
</tx_fifo_dat_o[35:0]>
<burst_adr[3:0]>
</burst_adr[3:0]>
<ref_delay_ack>
<status>
GLOBAL_FIXED
</status>
577,8 → 577,8
<page>
-1
</page>
</burst_adr[3:0]>
<ref_delay_ack>
</ref_delay_ack>
<bl_ack>
<status>
GLOBAL_FIXED
</status>
621,8 → 621,8
<page>
-1
</page>
</ref_delay_ack>
<bl_ack>
</bl_ack>
<fifo_re_d>
<status>
GLOBAL_FIXED
</status>
665,8 → 665,8
<page>
-1
</page>
</bl_ack>
<fifo_re_d>
</fifo_re_d>
<stall>
<status>
GLOBAL_FIXED
</status>
709,7 → 709,51
<page>
-1
</page>
</fifo_re_d>
</stall>
<next_row_open>
<status>
GLOBAL_FIXED
</status>
<value>
<status>
GLOBAL_VAR
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</next_row_open>
</inputs>
<outputs>
<cs_n>
1152,12 → 1196,12
-1
</page>
</bl_en>
<cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
cur_row
1'b0
<status>
GLOBAL_VAR
</status>
1169,6 → 1213,50
</status>
</vis>
<type>
comb
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</state_idle>
<open_ba[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
reg
<status>
GLOBAL_VAR
1195,12 → 1283,56
<page>
-1
</page>
</cur_row[12:0]>
<state_idle>
</open_ba[1:0]>
<open_row[12:0]>
<status>
GLOBAL_FIXED
</status>
<value>
13'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
reg
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</open_row[12:0]>
<open_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
1213,7 → 1345,7
</status>
</vis>
<type>
comb
reg
<status>
GLOBAL_VAR
</status>
1239,7 → 1371,51
<page>
-1
</page>
</state_idle>
</open_cur_row>
<close_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
reg
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</close_cur_row>
</outputs>
<state>
<name>
1726,12 → 1902,12
-1
</page>
</bl_en>
<cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
cur_row
1'b0
<status>
GLOBAL_VAR
</status>
1769,12 → 1945,100
<page>
-1
</page>
</cur_row[12:0]>
<state_idle>
</state_idle>
<open_ba[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</open_ba[1:0]>
<open_row[12:0]>
<status>
GLOBAL_FIXED
</status>
<value>
13'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</open_row[12:0]>
<open_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
1813,7 → 2077,51
<page>
-1
</page>
</state_idle>
</open_cur_row>
<close_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
-1
</page>
</close_cur_row>
</state>
<trans>
<name>
1957,10 → 2265,10
</tabs>
## START PREFERENCES
<SCounter>
115
116
</SCounter>
<TCounter>
174
177
</TCounter>
<TableVis>
true
2484,12 → 2792,12
2
</page>
</bl_en>
<cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
cur_row
1'b0
<status>
GLOBAL_VAR
</status>
2527,12 → 2835,100
<page>
2
</page>
</cur_row[12:0]>
<state_idle>
</state_idle>
<open_ba[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</open_ba[1:0]>
<open_row[12:0]>
<status>
GLOBAL_FIXED
</status>
<value>
13'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</open_row[12:0]>
<open_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
2571,7 → 2967,51
<page>
2
</page>
</state_idle>
</open_cur_row>
<close_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</close_cur_row>
</attributes>
<x0>
75
3083,12 → 3523,12
2
</page>
</bl_en>
<cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
cur_row
1'b0
<status>
GLOBAL_VAR
</status>
3126,12 → 3566,100
<page>
2
</page>
</cur_row[12:0]>
<state_idle>
</state_idle>
<open_ba[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</open_ba[1:0]>
<open_row[12:0]>
<status>
GLOBAL_FIXED
</status>
<value>
13'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</open_row[12:0]>
<open_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
3170,7 → 3698,51
<page>
2
</page>
</state_idle>
</open_cur_row>
<close_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</close_cur_row>
</attributes>
<x0>
75
3901,12 → 4473,12
2
</page>
</bl_en>
<cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
cur_row
1'b0
<status>
GLOBAL_VAR
</status>
3944,12 → 4516,100
<page>
2
</page>
</cur_row[12:0]>
<state_idle>
</state_idle>
<open_ba[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</open_ba[1:0]>
<open_row[12:0]>
<status>
GLOBAL_FIXED
</status>
<value>
13'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</open_row[12:0]>
<open_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
3988,7 → 4648,51
<page>
2
</page>
</state_idle>
</open_cur_row>
<close_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
2
</page>
</close_cur_row>
</attributes>
<x0>
75
4500,15 → 5204,59
3
</page>
</bl_en>
<cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
cur_row
1'b1
<status>
LOCAL
</status>
</value>
<vis>
2
<status>
LOCAL
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
-1
</x2Obj>
<y2Obj>
-25
</y2Obj>
<page>
3
</page>
</state_idle>
<open_ba[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
4543,21 → 5291,21
<page>
3
</page>
</cur_row[12:0]>
<state_idle>
</open_ba[1:0]>
<open_row[12:0]>
<status>
GLOBAL_FIXED
</status>
<value>
1'b1
13'b0
<status>
LOCAL
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
LOCAL
GLOBAL_VAR
</status>
</vis>
<type>
4579,15 → 5327,103
</status>
</color>
<x2Obj>
-1
0
</x2Obj>
<y2Obj>
-25
0
</y2Obj>
<page>
3
</page>
</state_idle>
</open_row[12:0]>
<open_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</open_cur_row>
<close_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</close_cur_row>
</attributes>
<x0>
275
5099,12 → 5935,12
3
</page>
</bl_en>
<cur_row[12:0]>
<state_idle>
<status>
GLOBAL_FIXED
</status>
<value>
cur_row
1'b0
<status>
GLOBAL_VAR
</status>
5142,12 → 5978,100
<page>
3
</page>
</cur_row[12:0]>
<state_idle>
</state_idle>
<open_ba[1:0]>
<status>
GLOBAL_FIXED
</status>
<value>
2'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</open_ba[1:0]>
<open_row[12:0]>
<status>
GLOBAL_FIXED
</status>
<value>
13'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</open_row[12:0]>
<open_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
5186,7 → 6110,51
<page>
3
</page>
</state_idle>
</open_cur_row>
<close_cur_row>
<status>
GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
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33661,7 → 39073,51
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34587,12 → 40043,12
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## START STATE OBJECT
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GLOBAL_FIXED
</status>
<value>
1'b0
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
output
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</close_cur_row>
</attributes>
<x0>
475
</x0>
<y0>
1175
</y0>
<x1>
575
</x1>
<y1>
1275
</y1>
<reset>
false
</reset>
<page>
3
</page>
<color>
-16777216
</color>
</state>
## END STATE OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
ABS
</status>
<value>
trans174
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
1
<status>
GLOBAL_VAR
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
1000
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</priority>
</attributes>
<startState>
NOP40
</startState>
<endState>
PRECHARGE
</endState>
<startPtX>
575.0
</startPtX>
<startPtY>
1225.0
</startPtY>
<endPtX>
675.0
</endPtX>
<endPtY>
1225.0
</endPtY>
<startCtrlPtX>
596.0
</startCtrlPtX>
<startCtrlPtY>
1225.0
</startCtrlPtY>
<endCtrlPtY>
653.0
</endCtrlPtY>
<endCtrlPtY>
1225.0
</endCtrlPtY>
<startStateIndex>
0
</startStateIndex>
<endStateIndex>
18
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
ABS
</status>
<value>
trans175
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
tx_fifo_dat_o[5] && next_row_open && !stall
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
-8
</x2Obj>
<y2Obj>
-65
</y2Obj>
<page>
3
</page>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
100
<status>
LOCAL
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
-16
</x2Obj>
<y2Obj>
-71
</y2Obj>
<page>
3
</page>
</priority>
</attributes>
<startState>
NOP40
</startState>
<endState>
NOP14
</endState>
<startPtX>
500.0
</startPtX>
<startPtY>
1181.0
</startPtY>
<endPtX>
150.0
</endPtX>
<endPtY>
518.0
</endPtY>
<startCtrlPtX>
441.0
</startCtrlPtX>
<startCtrlPtY>
978.0
</startCtrlPtY>
<endCtrlPtY>
300.0
</endCtrlPtY>
<endCtrlPtY>
638.0
</endCtrlPtY>
<startStateIndex>
24
</startStateIndex>
<endStateIndex>
6
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## START STATE TRANSITION OBJECT
<transition>
<attributes>
<name>
<status>
ABS
</status>
<value>
trans176
<status>
LOCAL
</status>
</value>
<vis>
0
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</name>
<equation>
<status>
ABS
</status>
<value>
!tx_fifo_dat_o[5] && next_row_open && !stall
<status>
LOCAL
</status>
</value>
<vis>
1
<status>
GLOBAL_VAR
</status>
</vis>
<type>
def_type
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
201
</x2Obj>
<y2Obj>
-69
</y2Obj>
<page>
3
</page>
</equation>
<priority>
<status>
GLOBAL_FIXED
</status>
<value>
1000
<status>
GLOBAL_VAR
</status>
</value>
<vis>
2
<status>
GLOBAL_VAR
</status>
</vis>
<type>
<status>
GLOBAL_VAR
</status>
</type>
<comment>
<status>
GLOBAL_VAR
</status>
</comment>
<color>
-16777216
<status>
GLOBAL_VAR
</status>
</color>
<x2Obj>
0
</x2Obj>
<y2Obj>
0
</y2Obj>
<page>
3
</page>
</priority>
</attributes>
<startState>
NOP40
</startState>
<endState>
NOP15
</endState>
<startPtX>
563.0
</startPtX>
<startPtY>
1192.0
</startPtY>
<endPtX>
571.0
</endPtX>
<endPtY>
492.0
</endPtY>
<startCtrlPtX>
713.0
</startCtrlPtX>
<startCtrlPtY>
1009.0
</startCtrlPtY>
<endCtrlPtY>
709.0
</endCtrlPtY>
<endCtrlPtY>
614.0
</endCtrlPtY>
<startStateIndex>
32
</startStateIndex>
<endStateIndex>
2
</endStateIndex>
<page>
3
</page>
<color>
-16777216
</color>
<pageSX>
0.0
</PageSX>
<pageSY>
0.0
</pageSY>
<pageSCX>
0.0
</PageSCX>
<pageSCY>
0.0
</pageSCY>
<pageEX>
0.0
</PageEX>
<pageEY>
0.0
</pageEY>
<pageECX>
0.0
</PageECX>
<pageECY>
0.0
</pageECY>
<stub>
false
</stub>
</transition>
## END STATE TRANSITION OBJECT
## END OBJECTS
/rtl/verilog/versatile_mem_ctrl_wb.v
5,7 → 5,8
wb_stb_i, wb_cyc_i, wb_ack_o,
wb_clk, wb_rst,
// SDRAM controller interface
sdram_dat_o, sdram_fifo_empty, sdram_fifo_rd_adr, sdram_fifo_rd_data, sdram_fifo_re,
sdram_dat_o, sdram_fifo_empty, sdram_fifo_flag, sdram_fifo_rd_adr,
sdram_fifo_rd_data, sdram_fifo_re,
sdram_dat_i, sdram_fifo_wr, sdram_fifo_we, sdram_burst_reading,
sdram_clk, sdram_rst
 
12,6 → 13,7
);
 
parameter nr_of_wb_ports = 3;
parameter nr_of_queues = 16;
input [36*nr_of_wb_ports-1:0] wb_adr_i_v;
input [36*nr_of_wb_ports-1:0] wb_dat_i_v;
24,6 → 26,7
 
output [35:0] sdram_dat_o;
output [0:nr_of_wb_ports-1] sdram_fifo_empty;
output [0:nr_of_wb_ports-1] sdram_fifo_flag;
input sdram_fifo_rd_adr, sdram_fifo_rd_data;
input [0:nr_of_wb_ports-1] sdram_fifo_re;
input [31:0] sdram_dat_i;
61,6 → 64,8
wire [0:nr_of_wb_ports-1] egress_fifo_we, egress_fifo_full;
wire [0:nr_of_wb_ports-1] ingress_fifo_re, ingress_fifo_empty;
 
//wire [4*nr_of_queues-1:0] sdram_fifo_fill;
 
genvar i;
 
assign stall[0] = 1'b0;
106,7 → 111,8
.write(|(egress_fifo_we)),
.write_enable(egress_fifo_we),
.q(sdram_dat_o),
.fifo_empty(sdram_fifo_empty),
.fifo_empty(sdram_fifo_empty),
.fifo_flag(sdram_fifo_flag),
.read_adr(sdram_fifo_rd_adr),
.read_data(sdram_fifo_rd_data),
.read_enable(sdram_fifo_re),
/rtl/verilog/versatile_mem_ctrl_ip.v
81,7 → 81,7
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, fifo_flag, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
93,10 → 93,13
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
 
parameter fifo_flag_value = 4'd4;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
output fifo_flag;
input wclk, rclk, rst;
wire direction;
104,8 → 107,13
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
reg fifo_empty2;
reg [N:0] wptr1, wptr2, wptr_bin, rptr_bin;
reg [N:0] ptr_diff;
 
integer i;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
162,6 → 170,36
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
 
// Write-domain to read-domain synchronizer
always @ (posedge wclk or posedge rst)
if (rst)
{wptr2,wptr1} <= {4'b0000,4'b0000};
else
{wptr2,wptr1} <= {wptr1,wptr};
 
// Gray-to-bin conversion
always @(wptr2)
for (i=0;i<4; i=i+1)
wptr_bin[i] = ^(wptr2>>i);
 
always @(rptr)
for (i=0;i<4; i=i+1)
rptr_bin[i] = ^(rptr>>i);
 
// Pointer difference
always @ (wptr_bin or rptr_bin)
if (wptr_bin > rptr_bin)
ptr_diff <= wptr_bin - rptr_bin;
else if (wptr_bin < rptr_bin)
ptr_diff <= ((4'd16 - rptr_bin) + wptr_bin);
else
ptr_diff <= 4'd0;
 
 
assign fifo_flag = (ptr_diff >= fifo_flag_value);
endmodule // async_comp
// async FIFO with multiple queues
 
236,7 → 274,8
.wptr(fifo_wadr_gray[i]),
.rptr(fifo_radr_gray[i]),
.fifo_empty(fifo_empty[i]),
.fifo_full(fifo_full[i]),
.fifo_full(fifo_full[i]),
.fifo_flag(),
.wclk(clk1),
.rclk(clk2),
.rst(rst1));
1607,10 → 1646,13
output reg [14:0] a,
output reg adr_init,
output reg bl_en,
output reg close_cur_row,
output reg [2:0] cmd,
output reg cs_n,
output reg [12:0] cur_row,
output reg fifo_re,
output reg [1:0] open_ba,
output reg open_cur_row,
output reg [12:0] open_row,
output reg read,
output reg ref_ack,
output reg ref_delay,
1621,10 → 1663,11
input wire clk,
input wire fifo_empty,
input wire fifo_re_d,
input wire [2:0] fifo_sel,
input wire next_row_open,
input wire ref_delay_ack,
input wire ref_req,
input wire rst,
input wire stall,
input wire [35:0] tx_fifo_dat_o
);
parameter
1657,24 → 1700,25
NOP31 = 26,
NOP32 = 27,
NOP4 = 28,
NOP5 = 29,
NOP6 = 30,
NOP7 = 31,
NOP8 = 32,
NOP9 = 33,
NOP_tRFC = 34,
NOP_tWR = 35,
PRECHARGE = 36,
PRE_0 = 37,
PRE_1 = 38,
READ_ADDR = 39,
READ_BURST = 40,
WRITE_ADDR = 41,
WRITE_BURST = 42;
reg [42:0] state;
reg [42:0] nextstate;
NOP40 = 29,
NOP5 = 30,
NOP6 = 31,
NOP7 = 32,
NOP8 = 33,
NOP9 = 34,
NOP_tRFC = 35,
NOP_tWR = 36,
PRECHARGE = 37,
PRE_0 = 38,
PRE_1 = 39,
READ_ADDR = 40,
READ_BURST = 41,
WRITE_ADDR = 42,
WRITE_BURST = 43;
reg [43:0] state;
reg [43:0] nextstate;
always @* begin
nextstate = 43'b0000000000000000000000000000000000000000000;
nextstate = 44'b00000000000000000000000000000000000000000000;
adr_init = 1'b0;
bl_en = 1'b0;
fifo_re = 1'b0;
1801,9 → 1845,12
end
end
state[NOP12] : begin
begin
if (!stall) begin
nextstate[ACT_ROW] = 1'b1;
end
else begin
nextstate[NOP12] = 1'b1;
end
end
state[NOP14] : begin
begin
1824,13 → 1871,12
end
end
state[NOP20] : begin
fifo_re = 1'b1;
begin
nextstate[NOP21] = 1'b1;
end
end
state[NOP21] : begin
adr_init = 1'b1;
fifo_re = 1'b1;
begin
nextstate[NOP22] = 1'b1;
end
1849,13 → 1895,12
end
end
state[NOP30] : begin
fifo_re = 1'b1;
begin
nextstate[NOP31] = 1'b1;
end
end
state[NOP31] : begin
adr_init = 1'b1;
fifo_re = 1'b1;
begin
nextstate[NOP32] = 1'b1;
end
1873,6 → 1918,17
nextstate[NOP4] = 1'b1;
end
end
state[NOP40] : begin
if (tx_fifo_dat_o[5] && next_row_open && !stall) begin
nextstate[NOP14] = 1'b1;
end
else if (!tx_fifo_dat_o[5] && next_row_open && !stall) begin
nextstate[NOP15] = 1'b1;
end
else begin
nextstate[PRECHARGE] = 1'b1;
end
end
state[NOP5] : begin
if (ref_req) begin
nextstate[PRE_1] = 1'b1;
1923,8 → 1979,9
end
end
state[NOP_tWR] : begin
adr_init = 1'b1;
begin
nextstate[PRECHARGE] = 1'b1;
nextstate[NOP40] = 1'b1;
end
end
state[PRECHARGE] : begin
1983,7 → 2040,7
end
always @(posedge clk or posedge rst) begin
if (rst)
state <= 43'b0000000000000000000000000000000000000000001 << IDLE;
state <= 44'b00000000000000000000000000000000000000000001 << IDLE;
else
state <= nextstate;
end
1990,15 → 2047,21
always @(posedge clk or posedge rst) begin
if (rst) begin
a[14:0] <= 15'd0;
close_cur_row <= 1'b0;
cmd[2:0] <= 3'b111;
cs_n <= 1'b1;
cur_row[12:0] <= cur_row;
open_ba[1:0] <= 2'b0;
open_cur_row <= 1'b0;
open_row[12:0] <= 13'b0;
end
else begin
a[14:0] <= 15'd0;
close_cur_row <= 1'b0;
cmd[2:0] <= 3'b111;
cs_n <= 1'b0;
cur_row[12:0] <= cur_row;
open_ba[1:0] <= 2'b0;
open_cur_row <= 1'b0;
open_row[12:0] <= 13'b0;
case (1'b1)
nextstate[IDLE] : begin
cs_n <= 1'b1;
2006,7 → 2069,7
nextstate[ACT_ROW] : begin
a[14:0] <= {tx_fifo_dat_o[28:27],tx_fifo_dat_o[26:14]};
cmd[2:0] <= 3'b011;
cur_row[12:0] <= tx_fifo_dat_o[26:14];
open_ba[1:0] <= tx_fifo_dat_o[28:27];
end
nextstate[AREF] : begin
a[14:0] <= a;
2066,6 → 2129,7
end
nextstate[NOP14] : begin
a[14:0] <= a;
open_ba[1:0] <= open_ba;
end
nextstate[NOP15] : begin
a[14:0] <= a;
2133,6 → 2197,9
nextstate[READ_ADDR] : begin
a[14:0] <= {tx_fifo_dat_o[28:27],{4'b0000,tx_fifo_dat_o[13:10],burst_adr,1'b0}};
cmd[2:0] <= 3'b101;
open_ba[1:0] <= open_ba;
open_cur_row <= 1'b1;
open_row[12:0] <= tx_fifo_dat_o[26:14];
end
nextstate[READ_BURST] : begin
a[14:0] <= a;
2140,6 → 2207,9
nextstate[WRITE_ADDR] : begin
a[14:0] <= {tx_fifo_dat_o[28:27],{4'b0000,tx_fifo_dat_o[13:10],burst_adr,1'b0}};
cmd[2:0] <= 3'b100;
open_ba[1:0] <= open_ba;
open_cur_row <= 1'b1;
open_row[12:0] <= tx_fifo_dat_o[26:14];
end
nextstate[WRITE_BURST]: begin
a[14:0] <= a;
2208,6 → 2278,8
statename = "NOP32";
state[NOP4] :
statename = "NOP4";
state[NOP40] :
statename = "NOP40";
state[NOP5] :
statename = "NOP5";
state[NOP6] :
2242,93 → 2314,114
end
endmodule
module fsm_wb (
stall_i, stall_o,
we_i, cti_i, bte_i, stb_i, cyc_i, ack_o,
egress_fifo_we, egress_fifo_full,
ingress_fifo_re, ingress_fifo_empty,
state_idle,
wb_clk, wb_rst
);
stall_i, stall_o,
we_i, cti_i, bte_i, stb_i, cyc_i, ack_o,
egress_fifo_we, egress_fifo_full,
ingress_fifo_re, ingress_fifo_empty,
state_idle,
sdram_burst_reading,
wb_clk, wb_rst
);
 
input stall_i;
output stall_o;
input stall_i;
output stall_o;
 
input [2:0] cti_i;
input [1:0] bte_i;
input we_i, stb_i, cyc_i;
output ack_o;
output egress_fifo_we, ingress_fifo_re;
input egress_fifo_full, ingress_fifo_empty;
output state_idle;
input wb_clk, wb_rst;
input [2:0] cti_i;
input [1:0] bte_i;
input we_i, stb_i, cyc_i;
output ack_o;
output egress_fifo_we, ingress_fifo_re;
input egress_fifo_full, ingress_fifo_empty;
input sdram_burst_reading;
output state_idle;
input wb_clk, wb_rst;
 
reg ingress_fifo_read_reg;
reg ingress_fifo_read_reg;
 
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter endofburst = 3'b111;
// bte
parameter linear = 2'b00;
parameter wrap4 = 2'b01;
parameter wrap8 = 2'b10;
parameter wrap16 = 2'b11;
// cti
parameter classic = 3'b000;
parameter endofburst = 3'b111;
 
parameter idle = 2'b00;
parameter rd = 2'b01;
parameter wr = 2'b10;
parameter fe = 2'b11;
reg [1:0] state;
parameter idle = 2'b00;
parameter rd = 2'b01;
parameter wr = 2'b10;
parameter fe = 2'b11;
reg [1:0] state;
 
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
state <= idle;
else
case (state)
idle:
if (we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= wr;
else if (!we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= rd;
wr:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= idle;
rd:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) & stb_i & cyc_i & ack_o)
state <= fe;
fe:
if (ingress_fifo_empty)
state <= idle;
default: ;
endcase
assign state_idle = (state==idle);
assign stall_o = (stall_i) ? 1'b1 :
(state==idle & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==rd & stb_i & cyc_i & !ingress_fifo_empty) ? 1'b1 :
(state==fe & !ingress_fifo_empty) ? 1'b1 :
1'b0;
assign egress_fifo_we = (state==idle & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
reg sdram_burst_reading_1, sdram_burst_reading_2;
wire sdram_burst_reading_wb_clk;
 
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
state <= idle;
else
case (state)
idle:
if (we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= wr;
else if (!we_i & stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= rd;
wr:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) &
stb_i & cyc_i & !egress_fifo_full & !stall_i)
state <= idle;
rd:
if ((cti_i==classic | cti_i==endofburst | bte_i==linear) &
stb_i & cyc_i & ack_o)
state <= fe;
fe:
if (ingress_fifo_empty & !sdram_burst_reading_wb_clk)
state <= idle;
default: ;
endcase
assign state_idle = (state==idle);
assign stall_o = (stall_i) ? 1'b1 :
(state==idle & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full) ? 1'b1 :
(state==rd & stb_i & cyc_i & !ingress_fifo_empty) ? 1'b1 :
(state==fe & !ingress_fifo_empty) ? 1'b1 :
1'b0;
assign egress_fifo_we = (state==idle & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;
assign ingress_fifo_re = (state==rd & stb_i & cyc_i & !ingress_fifo_empty & !stall_i) ? 1'b1 :
(state==fe & !ingress_fifo_empty & !stall_i) ? 1'b1:
1'b0;
assign ingress_fifo_re = (state==rd & stb_i & cyc_i & !ingress_fifo_empty & !stall_i) ? 1'b1 :
(state==fe & !ingress_fifo_empty & !stall_i) ? 1'b1:
1'b0;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
ingress_fifo_read_reg <= 1'b0;
else
ingress_fifo_read_reg <= ingress_fifo_re;
assign ack_o = (ingress_fifo_read_reg) ? 1'b1 :
(state==fe) ? 1'b0 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
ingress_fifo_read_reg <= 1'b0;
else
ingress_fifo_read_reg <= ingress_fifo_re;
/*assign ack_o = (ingress_fifo_read_reg & stb_i) ? 1'b1 :
(state==fe) ? 1'b0 :
(state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i) ? 1'b1 :
1'b0;*/
 
assign ack_o = !(state==fe) & ((ingress_fifo_read_reg & stb_i) | (state==wr & stb_i & cyc_i & !egress_fifo_full & !stall_i));
 
 
// Sample the SDRAM burst reading signal in WB domain
always @(posedge wb_clk)
sdram_burst_reading_1 <= sdram_burst_reading;
always @(posedge wb_clk)
sdram_burst_reading_2 <= sdram_burst_reading_1;
 
assign sdram_burst_reading_wb_clk = sdram_burst_reading_2;
endmodule`timescale 1ns/1ns
module delay (d, q, clk, rst);
 
3237,6 → 3330,11
// Assign outport
assign dq_io = dq_en ? dq_o : {16{1'bz}};
 
// DQS strobe
assign dqs_io = dq_en ? dqs_o : {2{1'bz}};
assign dqs_n_io = dq_en ? dqs_n_o : {2{1'bz}};
 
// Data mask
// Data mask from Tx FIFO
assign dqm_tx = dqm_en ? {4{1'b0}} : tx_dat_i[3:0];
3447,10 → 3545,22
 
// Most of these defines have an effect on things in fsm_sdr_16.v
 
//`define MT48LC16M16 // 32MB part
`define MT48LC4M16 // 8MB part
`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part
 
// Define this to allow indication that a burst read is still going
// to the wishbone state machine, so it doesn't start emptying the
// ingress fifo after a aborted burst before the burst read is
// actually finished.
//`define SDRAM_WB_SAME_CLOCKS
 
// If intending to burst write, and the wishbone clock is about 1/4 the speed
// of the SDRAM clock, then the data may come late, and this triggers a bug
// during write. To avoid this we can just wait a little longer for data when
// burst reading (there's no almost_empty signal from the FIFO)
//`define SLOW_WB_CLOCK
 
 
`ifdef MT48LC16M16
// using 1 of MT48LC16M16
// SDRAM data width is 16
3687,7 → 3797,7
 
module egress_fifo (
d, fifo_full, write, write_enable, clk1, rst1,
q, fifo_empty, read_adr, read_data, read_enable, clk2, rst2
q, fifo_empty, fifo_flag, read_adr, read_data, read_enable, clk2, rst2
);
 
parameter a_hi_size = 4;
3703,7 → 3813,9
input rst1;
 
output reg [data_width-1:0] q;
output [0:nr_of_queues-1] fifo_empty;
output [0:nr_of_queues-1] fifo_empty;
output [0:nr_of_queues-1] fifo_flag;
input read_adr, read_data;
input [0:nr_of_queues-1] read_enable;
input clk2;
3720,6 → 3832,8
reg [data_width-1:0] wdata;
wire [data_width-1:0] wdataa[0:nr_of_queues-1];
 
wire [a_hi_size-1:0] fifo_fill_i[0:nr_of_queues-1];
 
reg read_adr_reg;
reg [0:nr_of_queues-1] read_enable_reg;
 
3776,7 → 3890,8
.wptr(fifo_wadr_gray[i]),
.rptr(fifo_radr_gray[i]),
.fifo_empty(fifo_empty[i]),
.fifo_full(fifo_full[i]),
.fifo_full(fifo_full[i]),
.fifo_flag(fifo_flag[i]),
.wclk(clk1),
.rclk(clk2),
.rst(rst1));
3795,6 → 3910,19
 
// and-or mux read address
always @*
begin
if (nr_of_queues > 1) begin
radr = {a_lo_size{1'b0}};
for (k=0;k<nr_of_queues;k=k+1) begin
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable_reg[k]}}) | radr;
end
end
else
radr = fifo_radr_bin[0];
end
/* -----\/----- EXCLUDED -----\/-----
always @*
begin
radr = {a_lo_size{1'b0}};
for (k=0;k<nr_of_queues;k=k+1) begin
3801,6 → 3929,7
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable_reg[k]}}) | radr;
end
end
-----/\----- EXCLUDED -----/\----- */
 
// and-or mux write data
generate
3832,8 → 3961,8
// Added registering of FIFO output to break a timing path
always@(posedge clk2)
q <= fifo_q;
 
 
endmodule
module vfifo_dual_port_ram_dc_sw
(
3869,7 → 3998,8
fifo_empty, fifo_rd_adr, fifo_rd_data, count0,
refresh_req, cmd_aref, cmd_read, state_idle,
ba, a, cmd, dqm, dq_oe,
sdram_clk, sdram_rst
sdram_burst_reading,
sdram_clk, sdram_fifo_wr, sdram_rst
);
 
/* Now these are defined
3898,7 → 4028,8
output reg [1:0] dqm /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output reg dq_oe;
 
input sdram_clk, sdram_rst;
output sdram_burst_reading;
input sdram_clk, sdram_fifo_wr, sdram_rst;
 
wire [`BA_SIZE-1:0] bank;
wire [`ROW_SIZE-1:0] row;
3993,33 → 4124,60
begin
next = 3'bx;
case (state)
`FSM_INIT: if (shreg[31]) next = `FSM_IDLE;
else next = `FSM_INIT;
`FSM_IDLE: if (refresh_req) next = `FSM_RFR;
else if (!fifo_empty) next = `FSM_ADR;
else next = `FSM_IDLE;
`FSM_RFR: if (shreg[5]) next = `FSM_IDLE;
else next = `FSM_RFR;
`FSM_ADR: if (current_row_open_reg & (shreg[4]) & we_reg) next = `FSM_W4D;
else if (current_row_open_reg & shreg[4]) next = `FSM_RW;
else if (current_bank_closed_reg & shreg[4]) next = `FSM_ACT;
else if (shreg[4]) next = `FSM_PCH;
else next = `FSM_ADR;
`FSM_INIT:
if (shreg[31]) next = `FSM_IDLE;
else next = `FSM_INIT;
`FSM_IDLE:
if (refresh_req) next = `FSM_RFR;
else if (!shreg[0] & !fifo_empty) next = `FSM_ADR;
else next = `FSM_IDLE;
`FSM_RFR:
if (shreg[5]) next = `FSM_IDLE;
else next = `FSM_RFR;
`FSM_ADR:
if (shreg[5])
begin
if (current_bank_closed_reg) next = `FSM_ACT;
else if (current_row_open_reg)
next = (we_reg) ? `FSM_W4D : `FSM_RW;
else next = `FSM_PCH;
end
else next = `FSM_ADR;
`FSM_PCH: if (shreg[1]) next = `FSM_ACT;
else next = `FSM_PCH;
`FSM_ACT: if (shreg[2] & (!fifo_empty | !we_reg)) next = `FSM_RW;
else if (shreg[2] & fifo_empty) next = `FSM_W4D;
else next = `FSM_ACT;
`FSM_ACT:
if (shreg[2])
begin
`ifdef SLOW_WB_CLOCK
// Automatiacally go to wait for data if burst writing
if ((|bte_reg) & we_reg) next = `FSM_W4D;
else if ((!fifo_empty | !we_reg)) next = `FSM_RW;
`else
if ((!fifo_empty | !we_reg)) next = `FSM_RW;
`endif
else if (fifo_empty) next = `FSM_W4D;
end
else next = `FSM_ACT;
`ifdef SLOW_WB_CLOCK
// Add some wait here if bursting and the wishbone clock is slow
`FSM_W4D: if (!fifo_empty & ((bte_reg==linear)|((|bte_reg) & shreg[9])))
next = `FSM_RW;
`else
`FSM_W4D: if (!fifo_empty) next = `FSM_RW;
`endif
else next = `FSM_W4D;
`FSM_RW: if (bte_reg==linear & shreg[1])
next = `FSM_IDLE;
else if (bte_reg==beat4 & shreg[7])
next = `FSM_IDLE;
`ifdef BEAT8
else if (bte_reg==beat8 & shreg[15])
next = `FSM_IDLE;
`endif
`ifdef BEAT16
else if (bte_reg==beat16 & shreg[31])
next = `FSM_IDLE;
`endif
else
next = `FSM_RW;
endcase
4085,7 → 4243,7
end else if (shreg[2])
{ba,a,cmd,cmd_aref} <= {2'b00, 13'd0, cmd_rfr,1'b1};
`FSM_ADR:
if (shreg[3])
if (shreg[4])
{ba_reg,row_reg,col_reg,we_reg,bte_reg} <=
{bank,row,col,we_i,bte_i};
`FSM_PCH:
4120,10 → 4278,14
linear: {ba,a} <= {ba_reg,col_reg_a10_fix};
beat4: {ba,a,col_reg[2:0]} <=
{ba_reg,col_reg_a10_fix, col_reg[2:0] + 3'd1};
`ifdef BEAT8
beat8: {ba,a,col_reg[3:0]} <=
{ba_reg,col_reg_a10_fix, col_reg[3:0] + 4'd1};
`endif
`ifdef BEAT16
beat16: {ba,a,col_reg[4:0]} <=
{ba_reg,col_reg_a10_fix, col_reg[4:0] + 5'd1};
`endif
endcase
end
endcase
4130,16 → 4292,42
end
end
 
reg fifo_read_data_en;
always @(posedge sdram_clk)
if (sdram_rst)
fifo_read_data_en <= 1;
else if (next==`FSM_RW)
fifo_read_data_en <= ~fifo_read_data_en;
else
fifo_read_data_en <= 1;
 
reg [3:0] beat4_data_read_limiter; // Use this to record how many times we've pulsed fifo_rd_data
// Only 3 bits, becuase we're looking at when fifo_read_data_en goes low - should only happen 3
// times for a 4-beat burst
always @(posedge sdram_clk)
if (sdram_rst)
beat4_data_read_limiter <= 0;
else if(state==`FSM_ADR)
beat4_data_read_limiter <= 0;
else if (!fifo_read_data_en)
beat4_data_read_limiter <= {beat4_data_read_limiter[2:0],1'b1};
 
// rd_adr goes high when next adr is fetched from sync RAM and during write burst
assign fifo_rd_adr = state==`FSM_ADR & shreg[0];
assign fifo_rd_adr = state==`FSM_ADR & shreg[1];
 
assign fifo_rd_data = (((state!=`FSM_RW & next==`FSM_RW)|(state==`FSM_RW & (bte_reg==beat4 & fifo_read_data_en & !(&beat4_data_read_limiter)))) & we_reg & !fifo_empty);
/*
assign fifo_rd_data = ((state==`FSM_RW & next==`FSM_RW) &
we_reg & !count0 & !fifo_empty);
 
*/
assign state_idle = (state==`FSM_IDLE);
 
// bank and row open ?
assign current_bank_closed = !(open_ba[bank]);
assign current_row_open = open_ba[bank] & (open_row[bank]==row);
assign current_row_open = open_row[bank]==row;
 
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
4148,6 → 4336,25
//if (state==adr & counter[1:0]==2'b10)
{current_bank_closed_reg, current_row_open_reg} <=
{current_bank_closed, current_row_open};
 
// Record the number of write enables going to INGRESS fifo (ie. that we
// generate when we're reading) - this makes sure we keep track of when a
// burst read is in progress, and we can signal the wishbone bus to wait
// for this data to be put into the FIFO before it'll empty it when it's
// had a terminated burst transfer.
reg [3:0] fifo_we_record;
always @(posedge sdram_clk)
if (sdram_rst)
fifo_we_record <= 0;
else if (next==`FSM_RW & ((state==`FSM_ADR)|(state==`FSM_ACT)) & (bte_reg==beat4) & !we_reg)
fifo_we_record <= 4'b0001;
else if (sdram_fifo_wr)
fifo_we_record <= {fifo_we_record[2:0],1'b0};
`ifdef SDRAM_WB_SAME_CLOCKS
assign sdram_burst_reading = |fifo_we_record;
`else
assign sdram_burst_reading = 0;
`endif
 
endmodule
4158,13 → 4365,15
wb_stb_i, wb_cyc_i, wb_ack_o,
wb_clk, wb_rst,
// SDRAM controller interface
sdram_dat_o, sdram_fifo_empty, sdram_fifo_rd_adr, sdram_fifo_rd_data, sdram_fifo_re,
sdram_dat_i, sdram_fifo_wr, sdram_fifo_we,
sdram_dat_o, sdram_fifo_empty, sdram_fifo_flag, sdram_fifo_rd_adr,
sdram_fifo_rd_data, sdram_fifo_re,
sdram_dat_i, sdram_fifo_wr, sdram_fifo_we, sdram_burst_reading,
sdram_clk, sdram_rst
 
);
 
parameter nr_of_wb_ports = 3;
parameter nr_of_queues = 16;
input [36*nr_of_wb_ports-1:0] wb_adr_i_v;
input [36*nr_of_wb_ports-1:0] wb_dat_i_v;
4177,11 → 4386,13
 
output [35:0] sdram_dat_o;
output [0:nr_of_wb_ports-1] sdram_fifo_empty;
output [0:nr_of_wb_ports-1] sdram_fifo_flag;
input sdram_fifo_rd_adr, sdram_fifo_rd_data;
input [0:nr_of_wb_ports-1] sdram_fifo_re;
input [31:0] sdram_dat_i;
input sdram_fifo_wr;
input [0:nr_of_wb_ports-1] sdram_fifo_we;
input sdram_burst_reading;
input sdram_clk;
input sdram_rst;
 
4213,6 → 4424,8
wire [0:nr_of_wb_ports-1] egress_fifo_we, egress_fifo_full;
wire [0:nr_of_wb_ports-1] ingress_fifo_re, ingress_fifo_empty;
 
//wire [4*nr_of_queues-1:0] sdram_fifo_fill;
 
genvar i;
 
assign stall[0] = 1'b0;
4242,6 → 4455,7
.ingress_fifo_re(ingress_fifo_re[i]),
.ingress_fifo_empty(ingress_fifo_empty[i]),
.state_idle(state_idle[i]),
.sdram_burst_reading(sdram_burst_reading),
.wb_clk(wb_clk),
.wb_rst(wb_rst)
);
4248,20 → 4462,37
end
endgenerate
 
egress_fifo # (.a_hi_size(4),.a_lo_size(4),.nr_of_queues(nr_of_wb_ports),.data_width(36))
egress_FIFO(
.d(egress_fifo_di), .fifo_full(egress_fifo_full), .write(|(egress_fifo_we)), .write_enable(egress_fifo_we),
.q(sdram_dat_o), .fifo_empty(sdram_fifo_empty), .read_adr(sdram_fifo_rd_adr), .read_data(sdram_fifo_rd_data), .read_enable(sdram_fifo_re),
.clk1(wb_clk), .rst1(wb_rst), .clk2(sdram_clk), .rst2(sdram_rst)
);
egress_fifo # (
.a_hi_size(4),.a_lo_size(4),.nr_of_queues(nr_of_wb_ports),
.data_width(36))
egress_FIFO(
.d(egress_fifo_di),
.fifo_full(egress_fifo_full),
.write(|(egress_fifo_we)),
.write_enable(egress_fifo_we),
.q(sdram_dat_o),
.fifo_empty(sdram_fifo_empty),
.fifo_flag(sdram_fifo_flag),
.read_adr(sdram_fifo_rd_adr),
.read_data(sdram_fifo_rd_data),
.read_enable(sdram_fifo_re),
.clk1(wb_clk),
.rst1(wb_rst),
.clk2(sdram_clk),
.rst2(sdram_rst)
);
async_fifo_mq # (
.a_hi_size(4),.a_lo_size(4),.nr_of_queues(nr_of_wb_ports),
.data_width(32))
ingress_FIFO(
.d(sdram_dat_i), .fifo_full(), .write(sdram_fifo_wr),
.write_enable(sdram_fifo_we), .q(wb_dat_o),
.fifo_empty(ingress_fifo_empty), .read(|(ingress_fifo_re)),
.read_enable(ingress_fifo_re), .clk1(sdram_clk),
.rst1(sdram_rst), .clk2(wb_clk), .rst2(wb_rst)
);
 
async_fifo_mq # (.a_hi_size(4),.a_lo_size(4),.nr_of_queues(nr_of_wb_ports),.data_width(32))
ingress_FIFO(
.d(sdram_dat_i), .fifo_full(), .write(sdram_fifo_wr), .write_enable(sdram_fifo_we),
.q(wb_dat_o), .fifo_empty(ingress_fifo_empty), .read(|(ingress_fifo_re)), .read_enable(ingress_fifo_re),
.clk1(sdram_clk), .rst1(sdram_rst), .clk2(wb_clk), .rst2(wb_rst)
);
 
assign wb_dat_o_v = {nr_of_wb_ports{wb_dat_o}};
 
endmodule`timescale 1ns/1ns
4340,9 → 4571,9
output ras_pad_o;
output cas_pad_o;
output we_pad_o;
output reg [(`SDRAM_DATA_WIDTH)-1:0] dq_o /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output reg [(`SDRAM_DATA_WIDTH)-1:0] dq_o /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
output [1:0] dqm_pad_o;
input [(`SDRAM_DATA_WIDTH)-1:0] dq_i /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
input [(`SDRAM_DATA_WIDTH)-1:0] dq_i ;
output dq_oe;
output cke_pad_o;
`endif
4369,6 → 4600,7
input sdram_clk, sdram_rst;
 
wire [0:15] fifo_empty[0:3];
wire [0:15] fifo_flag[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
wire [35:0] fifo_dat_o[0:3];
4385,6 → 4617,11
wire [35:0] tx_fifo_dat_o;
 
wire burst_reading;
reg sdram_fifo_wr_r;
 
generate
if (nr_of_wb_clk_domains > 0) begin
versatile_mem_ctrl_wb
4403,6 → 4640,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[0]),
.sdram_fifo_empty(fifo_empty[0][0:nr_of_wb_ports_clk0-1]),
.sdram_fifo_flag(fifo_flag[0][0:nr_of_wb_ports_clk0-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[0][0:nr_of_wb_ports_clk0-1]),
4409,11 → 4647,13
.sdram_dat_i(fifo_dat_i),
.sdram_fifo_wr(fifo_wr),
.sdram_fifo_we(fifo_we[0][0:nr_of_wb_ports_clk0-1]),
.sdram_burst_reading(burst_reading),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
end
if (nr_of_wb_ports_clk0 < 16) begin
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}};
assign fifo_flag[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b0}};
end
endgenerate
 
4435,6 → 4675,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[1]),
.sdram_fifo_empty(fifo_empty[1][0:nr_of_wb_ports_clk1-1]),
.sdram_fifo_flag(fifo_flag[1][0:nr_of_wb_ports_clk1-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[1][0:nr_of_wb_ports_clk1-1]),
4441,13 → 4682,16
.sdram_dat_i(fifo_dat_i),
.sdram_fifo_wr(fifo_wr),
.sdram_fifo_we(fifo_we[1][0:nr_of_wb_ports_clk1-1]),
.sdram_burst_reading(burst_reading),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk1 < 16) begin
assign fifo_empty[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b1}};
assign fifo_flag[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b0}};
end
end else begin
assign fifo_empty[1] = {16{1'b1}};
assign fifo_flag[1] = {16{1'b0}};
assign fifo_dat_o[1] = {36{1'b0}};
end
endgenerate
4470,6 → 4714,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[2]),
.sdram_fifo_empty(fifo_empty[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_flag(fifo_flag[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[2][0:nr_of_wb_ports_clk2-1]),
4476,13 → 4721,16
.sdram_dat_i(fifo_dat_i),
.sdram_fifo_wr(fifo_wr),
.sdram_fifo_we(fifo_we[2][0:nr_of_wb_ports_clk2-1]),
.sdram_burst_reading(burst_reading),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk2 < 16) begin
assign fifo_empty[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b1}};
assign fifo_flag[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b0}};
end
end else begin
assign fifo_empty[2] = {16{1'b1}};
assign fifo_flag[2] = {16{1'b0}};
assign fifo_dat_o[2] = {36{1'b0}};
end
endgenerate
4505,6 → 4753,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[3]),
.sdram_fifo_empty(fifo_empty[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_flag(fifo_flag[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[3][0:nr_of_wb_ports_clk3-1]),
4511,13 → 4760,16
.sdram_dat_i(fifo_dat_i),
.sdram_fifo_wr(fifo_wr),
.sdram_fifo_we(fifo_we[3][0:nr_of_wb_ports_clk3-1]),
.sdram_burst_reading(burst_reading),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk3 < 16) begin
assign fifo_empty[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b1}};
assign fifo_flag[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b0}};
end
end else begin
assign fifo_empty[3] = {16{1'b1}};
assign fifo_flag[3 ] = {16{1'b0}};
assign fifo_dat_o[3] = {36{1'b0}};
end
endgenerate
4556,7 → 4808,8
`ifdef SDR_16
 
wire ref_cnt_zero;
reg [(`SDRAM_DATA_WIDTH)-1:0] dq_i_reg, dq_i_tmp_reg;
reg [(`SDRAM_DATA_WIDTH)-1:0] dq_i_reg /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
reg [(`SDRAM_DATA_WIDTH)-1:0] dq_i_tmp_reg;
reg [17:0] dq_o_tmp_reg;
wire cmd_aref, cmd_read;
4570,7 → 4823,16
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
 
reg current_fifo_empty_r;
always @(posedge sdram_clk)
current_fifo_empty_r <= current_fifo_empty;
always @(posedge sdram_clk)
sdram_fifo_wr_r <= fifo_wr;
// SDR SDRAM 16 FSM
fsm_sdr_16 fsm_sdr_16_0
(
4578,7 → 4840,7
.we_i(fifo_dat_o[fifo_sel_domain_reg][5]),
.bte_i(fifo_dat_o[fifo_sel_domain_reg][4:3]),
.sel_i({fifo_dat_o[fifo_sel_domain_reg][3:2],dq_o_tmp_reg[1:0]}),
.fifo_empty(current_fifo_empty),
.fifo_empty(current_fifo_empty_r),
.fifo_rd_adr(fifo_rd_adr),
.fifo_rd_data(fifo_rd_data),
.state_idle(idle),
4590,6 → 4852,8
.cmd({ras_pad_o, cas_pad_o, we_pad_o}),
.dq_oe(dq_oe),
.dqm(dqm_pad_o),
.sdram_fifo_wr(sdram_fifo_wr_r),
.sdram_burst_reading(burst_reading),
.sdram_clk(sdram_clk),
.sdram_rst(sdram_rst)
);
4634,13 → 4898,13
// output registers
assign cs_n_pad_o = 1'b0;
assign cke_pad_o = 1'b1;
always @ (posedge sdram_clk)
dq_i_reg <= dq_i;
 
always @(posedge sdram_clk)
dq_i_tmp_reg <= dq_i_reg;
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
{dq_i_reg, dq_i_tmp_reg} <= {16'h0000,16'h0000};
else
{dq_i_reg, dq_i_tmp_reg} <= {dq_i, dq_i_reg};
 
assign fifo_dat_i = {dq_i_tmp_reg, dq_i_reg};
always @ (posedge sdram_clk or posedge sdram_rst)
4702,53 → 4966,62
reg cke, ras, cas, we, cs_n;
wire cke_d, ras_d, cas_d, we_d, cs_n_d;
wire ras_o, cas_o, we_o, cs_n_o;
wire [1:0] ba_o;
wire [1:0] ba_o;
wire [12:0] addr_o;
reg [1:0] ba;
wire [1:0] ba_d;
reg [12:0] addr;
reg [1:0] ba;
wire [1:0] ba_d;
reg [12:0] addr;
wire [12:0] addr_d;
wire dq_en, dqm_en;
reg [15:0] dq_tx_reg;
reg [15:0] dq_tx_reg;
wire [15:0] dq_tx;
reg [31:0] dq_rx_reg;
reg [31:0] dq_rx_reg;
wire [31:0] dq_rx;
wire [15:0] dq_o;
reg [3:0] dqm_tx_reg;
wire [3:0] dqm_tx;
wire [1:0] dqm_o, dqs_o, dqs_n_o;
reg [3:0] dqm_tx_reg;
wire [3:0] dqm_tx;
wire [1:0] dqm_o, dqs_o, dqs_n_o;
wire ref_delay, ref_delay_ack;
wire bl_en, bl_ack;
wire tx_fifo_re, tx_fifo_re_i;
//wire adr_init_delay;
//reg adr_init_delay_i;
reg [3:0] burst_cnt;
wire [3:0] burst_next_cnt, burst_length;
//wire burst_mask;
reg [3:0] burst_cnt;
wire [3:0] burst_next_cnt, burst_length;
reg burst_mask;
wire [12:0] cur_row;
wire [3:0] burst_adr;
//wire [2:0] tx_fifo_b_sel_i_cur;
wire [2:0] rx_fifo_a_sel_i;
//wire [7:0] tx_fifo_empty;
wire rx_fifo_we;
 
wire ref_cnt_zero;
wire cmd_aref;
wire ref_cnt_zero;
wire cmd_aref;
reg [4:0] fill_0;
wire [1:0] bte_i;
reg stall;
wire [0:63] fifo_re_vec, fifo_flag_vec, stall_vec;
wire write_i, burst_avail, burst;
wire open_cur_row, close_cur_row;
wire [12:0] open_row_i, next_row;
wire [1:0] open_bank_i, next_bank;
reg [12:0] open_row[0:3];
reg [3:0] open_ba;
wire next_row_open, current_bank_closed, current_row_open;
reg current_bank_closed_reg, current_row_open_reg;
// refresh counter
ref_counter ref_counter0(
.zq(ref_cnt_zero),
.rst(sdram_rst),
.clk(sdram_clk));
ref_counter ref_counter0
(
.zq(ref_cnt_zero),
.rst(sdram_rst),
.clk(sdram_clk)
);
 
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
if (sdram_rst)
refresh_req <= 1'b0;
else
if (ref_cnt_zero)
refresh_req <= 1'b1;
else if (cmd_aref)
refresh_req <= 1'b0;
 
// DDR SDRAM 16 FSM
ddr_16 ddr_16_0
4759,7 → 5032,7
.tx_fifo_dat_o(fifo_dat_o[fifo_sel_domain_reg]),
.burst_adr(burst_adr),
.fifo_empty(current_fifo_empty),
.fifo_sel(),
.stall(stall),
.read(read),
.write(write),
.ref_req(refresh_req),
4772,11 → 5045,66
.a({ba_o,addr_o}),
.cmd({ras_o,cas_o,we_o}),
.cs_n(cs_n_o),
.cur_row(cur_row),
.open_ba(open_bank_i),
.open_row(open_row_i),
.open_cur_row(open_cur_row),
.close_cur_row(close_cur_row),
.next_row_open(next_row_open),
.clk(sdram_clk_0),
.rst(sdram_rst)
);
 
// Check if a burst is available in FIFO
genvar j;
generate
for (j=0;j<4;j=j+1) begin : array_to_vector
assign fifo_flag_vec[(j*16):(j*16+15)] = fifo_flag[j];
assign fifo_re_vec[(j*16):(j*16+15)] = fifo_re[j];
end
endgenerate
assign write_i = fifo_dat_o[fifo_sel_domain_reg][5];
assign bte_i = fifo_dat_o[fifo_sel_domain_reg][4:3];
assign burst = (bte_i == 2'b01) ? 1'b1 : 1'b0;
assign burst_avail = |(fifo_flag_vec & fifo_re_vec);
 
always @ (write_i or burst or burst_avail)
if (write_i)
if (burst)
if (burst_avail)
stall <= 1'b0; // burst write, with burst in FIFO
else
stall <= 1'b1; // burst write, no burst in FIFO
else
stall <= 1'b0; // single wite
else
stall <= 1'b0; // read (single or burst)
 
// sdram_clock is faster than wb_clk
assign burst_reading = 1'b0;
 
// Keep track of open row in banks
always @ (posedge sdram_clk or posedge sdram_rst)
if (sdram_rst) begin
open_row[0] <= 13'b0;
open_row[1] <= 13'b0;
open_row[2] <= 13'b0;
open_row[3] <= 13'b0;
end else begin
if (open_cur_row)
open_row[open_bank_i] <= open_row_i;
else if (close_cur_row)
open_row[open_bank_i] <= 13'b0;
end
// Bank and row of next read/write operation
assign next_bank = fifo_dat_o[fifo_sel_domain_reg][28:27];
assign next_row = fifo_dat_o[fifo_sel_domain_reg][26:14];
// Check if next row is open
assign next_row_open = (next_row == open_row[next_bank]);
// Calculate the address
inc_adr inc_adr0
(
.adr_i(fifo_dat_o[fifo_sel_domain_reg][9:6]),
4822,8 → 5150,6
else
if (bl_en)
burst_cnt <= burst_next_cnt;
// Burst Mask
//assign burst_mask = (burst_cnt >= burst_length) ? 1'b1 : 1'b0;
 
// Burst Mask
always @ (posedge sdram_clk_0 or posedge sdram_rst)
4832,14 → 5158,16
else
burst_mask <= (burst_cnt >= burst_length) ? 1'b1 : 1'b0;
 
// Delay address and control to compensate for delay in Tx FIOFs
// Delay address and control to compensate for delay in TxFIOFs
defparam delay0.depth=3;
defparam delay0.width=20;
delay delay0 (
delay delay0
(
.d({cs_n_o,1'b1,ras_o,cas_o,we_o,ba_o,addr_o}),
.q({cs_n_d,cke_d,ras_d,cas_d,we_d,ba_d,addr_d}),
.clk(sdram_clk_180),
.rst(sdram_rst));
.rst(sdram_rst)
);
 
// Assing outputs
// Non-DDR outputs
4906,26 → 5234,27
genvar i;
generate
for (i=0; i < 16; i=i+1) begin : dly
 
defparam delay4.depth=`CL+2;
defparam delay4.width=1;
delay delay4 (
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
delay delay4
(
.d(fifo_sel_reg[i]),
.q(fifo_sel_dly[i]),
.clk(sdram_clk),
.rst(sdram_rst)
);
end
defparam delay5.depth=`CL+2;
defparam delay5.width=2;
delay delay5 (
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
delay delay5
(
.d(fifo_sel_domain_reg),
.q(fifo_sel_domain_dly),
.clk(sdram_clk),
.rst(sdram_rst)
);
endgenerate
 
 
// Increment address
4973,7 → 5302,8
.clk_0(sdram_clk_0),
.clk_90(sdram_clk_90),
.clk_180(sdram_clk_180),
.clk_270(sdram_clk_270));
.clk_270(sdram_clk_270)
);
 
`endif // `ifdef DDR_16
/rtl/verilog/versatile_mem_ctrl_ddr.v
432,6 → 432,11
// Assign outport
assign dq_io = dq_en ? dq_o : {16{1'bz}};
 
// DQS strobe
assign dqs_io = dq_en ? dqs_o : {2{1'bz}};
assign dqs_n_io = dq_en ? dqs_n_o : {2{1'bz}};
 
// Data mask
// Data mask from Tx FIFO
assign dqm_tx = dqm_en ? {4{1'b0}} : tx_dat_i[3:0];
/rtl/verilog/versatile_mem_ctrl_defines.v
1,6 → 1,6
//`define ACTEL
`define XILINX
//`define ALTERA
//`define XILINX
`define ALTERA
//`define GENERIC_PRIMITIVES
//`define SDR_16
`define DDR_16
/rtl/verilog/sdr_16.v
216,7 → 216,7
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, fifo_flag, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
228,10 → 228,13
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
 
parameter fifo_flag_value = 4'd4;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
output fifo_flag;
input wclk, rclk, rst;
wire direction;
239,8 → 242,13
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
reg fifo_empty2;
reg [N:0] wptr1, wptr2, wptr_bin, rptr_bin;
reg [N:0] ptr_diff;
 
integer i;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
275,7 → 283,7
 
`line 101 "versatile_fifo_async_cmp.v" 0
`line 109 "versatile_fifo_async_cmp.v" 0
 
 
assign async_empty = (wptr == rptr) && (direction==going_empty);
284,14 → 292,14
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @ (posedge rclk or posedge async_empty)
if (async_empty)
299,8 → 307,38
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
 
// Write-domain to read-domain synchronizer
always @ (posedge wclk or posedge rst)
if (rst)
{wptr2,wptr1} <= {4'b0000,4'b0000};
else
{wptr2,wptr1} <= {wptr1,wptr};
 
// Gray-to-bin conversion
always @(wptr2)
for (i=0;i<4; i=i+1)
wptr_bin[i] = ^(wptr2>>i);
 
always @(rptr)
for (i=0;i<4; i=i+1)
rptr_bin[i] = ^(rptr>>i);
 
// Pointer difference
always @ (wptr_bin or rptr_bin)
if (wptr_bin > rptr_bin)
ptr_diff <= wptr_bin - rptr_bin;
else if (wptr_bin < rptr_bin)
ptr_diff <= ((4'd16 - rptr_bin) + wptr_bin);
else
ptr_diff <= 4'd0;
 
 
assign fifo_flag = (ptr_diff >= fifo_flag_value);
endmodule // async_comp
`line 125 "versatile_fifo_async_cmp.v" 2
`line 163 "versatile_fifo_async_cmp.v" 2
`line 1 "async_fifo_mq.v" 1
// async FIFO with multiple queues
 
375,7 → 413,8
.wptr(fifo_wadr_gray[i]),
.rptr(fifo_radr_gray[i]),
.fifo_empty(fifo_empty[i]),
.fifo_full(fifo_full[i]),
.fifo_full(fifo_full[i]),
.fifo_flag(),
.wclk(clk1),
.rclk(clk2),
.rst(rst1));
412,7 → 451,7
.clk_b(clk2) );
 
endmodule
`line 111 "async_fifo_mq.v" 2
`line 112 "async_fifo_mq.v" 2
`line 1 "delay.v" 1
`timescale 1ns/1ns
module delay (d, q, clk, rst);
654,7 → 693,7
 
module egress_fifo (
d, fifo_full, write, write_enable, clk1, rst1,
q, fifo_empty, read_adr, read_data, read_enable, clk2, rst2
q, fifo_empty, fifo_flag, read_adr, read_data, read_enable, clk2, rst2
);
 
parameter a_hi_size = 4;
670,7 → 709,9
input rst1;
 
output reg [data_width-1:0] q;
output [0:nr_of_queues-1] fifo_empty;
output [0:nr_of_queues-1] fifo_empty;
output [0:nr_of_queues-1] fifo_flag;
input read_adr, read_data;
input [0:nr_of_queues-1] read_enable;
input clk2;
687,6 → 728,8
reg [data_width-1:0] wdata;
wire [data_width-1:0] wdataa[0:nr_of_queues-1];
 
wire [a_hi_size-1:0] fifo_fill_i[0:nr_of_queues-1];
 
reg read_adr_reg;
reg [0:nr_of_queues-1] read_enable_reg;
 
743,7 → 786,8
.wptr(fifo_wadr_gray[i]),
.rptr(fifo_radr_gray[i]),
.fifo_empty(fifo_empty[i]),
.fifo_full(fifo_full[i]),
.fifo_full(fifo_full[i]),
.fifo_flag(fifo_flag[i]),
.wclk(clk1),
.rclk(clk2),
.rst(rst1));
762,6 → 806,19
 
// and-or mux read address
always @*
begin
if (nr_of_queues > 1) begin
radr = {a_lo_size{1'b0}};
for (k=0;k<nr_of_queues;k=k+1) begin
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable_reg[k]}}) | radr;
end
end
else
radr = fifo_radr_bin[0];
end
/* -----\/----- EXCLUDED -----\/-----
always @*
begin
radr = {a_lo_size{1'b0}};
for (k=0;k<nr_of_queues;k=k+1) begin
768,6 → 825,7
radr = (fifo_radr_bin[k] & {a_lo_size{read_enable_reg[k]}}) | radr;
end
end
-----/\----- EXCLUDED -----/\----- */
 
// and-or mux write data
generate
799,10 → 857,10
// Added registering of FIFO output to break a timing path
always@(posedge clk2)
q <= fifo_q;
 
 
endmodule
`line 153 "egress_fifo.v" 2
`line 172 "egress_fifo.v" 2
`line 1 "versatile_fifo_dual_port_ram_dc_sw.v" 1
module vfifo_dual_port_ram_dc_sw
(
1470,7 → 1528,8
wb_stb_i, wb_cyc_i, wb_ack_o,
wb_clk, wb_rst,
// SDRAM controller interface
sdram_dat_o, sdram_fifo_empty, sdram_fifo_rd_adr, sdram_fifo_rd_data, sdram_fifo_re,
sdram_dat_o, sdram_fifo_empty, sdram_fifo_flag, sdram_fifo_rd_adr,
sdram_fifo_rd_data, sdram_fifo_re,
sdram_dat_i, sdram_fifo_wr, sdram_fifo_we, sdram_burst_reading,
sdram_clk, sdram_rst
 
1477,6 → 1536,7
);
 
parameter nr_of_wb_ports = 3;
parameter nr_of_queues = 16;
input [36*nr_of_wb_ports-1:0] wb_adr_i_v;
input [36*nr_of_wb_ports-1:0] wb_dat_i_v;
1489,6 → 1549,7
 
output [35:0] sdram_dat_o;
output [0:nr_of_wb_ports-1] sdram_fifo_empty;
output [0:nr_of_wb_ports-1] sdram_fifo_flag;
input sdram_fifo_rd_adr, sdram_fifo_rd_data;
input [0:nr_of_wb_ports-1] sdram_fifo_re;
input [31:0] sdram_dat_i;
1526,6 → 1587,8
wire [0:nr_of_wb_ports-1] egress_fifo_we, egress_fifo_full;
wire [0:nr_of_wb_ports-1] ingress_fifo_re, ingress_fifo_empty;
 
//wire [4*nr_of_queues-1:0] sdram_fifo_fill;
 
genvar i;
 
assign stall[0] = 1'b0;
1571,7 → 1634,8
.write(|(egress_fifo_we)),
.write_enable(egress_fifo_we),
.q(sdram_dat_o),
.fifo_empty(sdram_fifo_empty),
.fifo_empty(sdram_fifo_empty),
.fifo_flag(sdram_fifo_flag),
.read_adr(sdram_fifo_rd_adr),
.read_data(sdram_fifo_rd_data),
.read_enable(sdram_fifo_re),
1595,7 → 1659,7
assign wb_dat_o_v = {nr_of_wb_ports{wb_dat_o}};
 
endmodule
`line 132 "versatile_mem_ctrl_wb.v" 2
`line 138 "versatile_mem_ctrl_wb.v" 2
`line 1 "versatile_mem_ctrl_top.v" 1
`timescale 1ns/1ns
1774,6 → 1838,7
input sdram_clk, sdram_rst;
 
wire [0:15] fifo_empty[0:3];
wire [0:15] fifo_flag[0:3];
wire current_fifo_empty;
wire [0:15] fifo_re[0:3];
wire [35:0] fifo_dat_o[0:3];
1813,6 → 1878,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[0]),
.sdram_fifo_empty(fifo_empty[0][0:nr_of_wb_ports_clk0-1]),
.sdram_fifo_flag(fifo_flag[0][0:nr_of_wb_ports_clk0-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[0][0:nr_of_wb_ports_clk0-1]),
1825,6 → 1891,7
end
if (nr_of_wb_ports_clk0 < 16) begin
assign fifo_empty[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b1}};
assign fifo_flag[0][nr_of_wb_ports_clk0:15] = {(16-nr_of_wb_ports_clk0){1'b0}};
end
endgenerate
 
1846,6 → 1913,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[1]),
.sdram_fifo_empty(fifo_empty[1][0:nr_of_wb_ports_clk1-1]),
.sdram_fifo_flag(fifo_flag[1][0:nr_of_wb_ports_clk1-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[1][0:nr_of_wb_ports_clk1-1]),
1857,9 → 1925,11
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk1 < 16) begin
assign fifo_empty[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b1}};
assign fifo_flag[1][nr_of_wb_ports_clk1:15] = {(16-nr_of_wb_ports_clk1){1'b0}};
end
end else begin
assign fifo_empty[1] = {16{1'b1}};
assign fifo_flag[1] = {16{1'b0}};
assign fifo_dat_o[1] = {36{1'b0}};
end
endgenerate
1882,6 → 1952,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[2]),
.sdram_fifo_empty(fifo_empty[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_flag(fifo_flag[2][0:nr_of_wb_ports_clk2-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[2][0:nr_of_wb_ports_clk2-1]),
1893,9 → 1964,11
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk2 < 16) begin
assign fifo_empty[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b1}};
assign fifo_flag[2][nr_of_wb_ports_clk2:15] = {(16-nr_of_wb_ports_clk2){1'b0}};
end
end else begin
assign fifo_empty[2] = {16{1'b1}};
assign fifo_flag[2] = {16{1'b0}};
assign fifo_dat_o[2] = {36{1'b0}};
end
endgenerate
1918,6 → 1991,7
// SDRAM controller interface
.sdram_dat_o(fifo_dat_o[3]),
.sdram_fifo_empty(fifo_empty[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_flag(fifo_flag[3][0:nr_of_wb_ports_clk3-1]),
.sdram_fifo_rd_adr(fifo_rd_adr),
.sdram_fifo_rd_data(fifo_rd_data),
.sdram_fifo_re(fifo_re[3][0:nr_of_wb_ports_clk3-1]),
1929,9 → 2003,11
.sdram_rst(sdram_rst) );
if (nr_of_wb_ports_clk3 < 16) begin
assign fifo_empty[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b1}};
assign fifo_flag[3][nr_of_wb_ports_clk3:15] = {(16-nr_of_wb_ports_clk3){1'b0}};
end
end else begin
assign fifo_empty[3] = {16{1'b1}};
assign fifo_flag[3 ] = {16{1'b0}};
assign fifo_dat_o[3] = {36{1'b0}};
end
endgenerate
2146,35 → 2222,44
 
 
 
2202,7 → 2287,62
 
 
 
 
2248,8 → 2388,6
 
2262,10 → 2400,12
 
2314,6 → 2454,16
 
 
 
 
 
 
 
 
 
 
 
 
 
2322,15 → 2472,15
 
2337,11 → 2487,12
 
 
2390,10 → 2541,11
 
 
`line 733 "versatile_mem_ctrl_top.v" 0
`line 811 "versatile_mem_ctrl_top.v" 0
// `ifdef DDR_16
endmodule // wb_sdram_ctrl_top
`line 736 "versatile_mem_ctrl_top.v" 2
`line 814 "versatile_mem_ctrl_top.v" 2
/sim/rtl_sim/bin/wave_ddr.do
3,7 → 3,7
add wave -noupdate -group {CLOCK & RESET} -divider Reset
add wave -noupdate -group {CLOCK & RESET} -format Literal /versatile_mem_ctrl_tb/dut/wb_rst
add wave -noupdate -group {CLOCK & RESET} -divider Clocks
add wave -noupdate -group {CLOCK & RESET} -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_clk
add wave -noupdate -group {CLOCK & RESET} -format Literal /versatile_mem_ctrl_tb/dut/wb_clk
add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
add wave -noupdate -group {CLOCK & RESET} -divider {DCM/PLL generated clocks}
add wave -noupdate -group {CLOCK & RESET} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_0
27,17 → 27,14
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_0
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_0
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_0
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_0
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Logic {/versatile_mem_ctrl_tb/dut/wb_stb_i_0[1]}
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Logic {/versatile_mem_ctrl_tb/dut/wb_cyc_i_0[1]}
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Logic {/versatile_mem_ctrl_tb/dut/wb_ack_o_0[1]}
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_ack_o_0
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_0
add wave -noupdate -group {WISHBONE IF} -expand -group wb0 -divider <NULL>
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_adr_i_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Logic /versatile_mem_ctrl_tb/dut/wb_stb_i_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Logic /versatile_mem_ctrl_tb/dut/wb_cyc_i_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Logic /versatile_mem_ctrl_tb/dut/wb_ack_o_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal /versatile_mem_ctrl_tb/dut/wb_stb_i_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal /versatile_mem_ctrl_tb/dut/wb_cyc_i_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -expand /versatile_mem_ctrl_tb/dut/wb_ack_o_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_1
add wave -noupdate -group {WISHBONE IF} -expand -group wb1 -divider <NULL>
add wave -noupdate -group {WISHBONE IF} -group wb2 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_i_2
54,111 → 51,145
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal /versatile_mem_ctrl_tb/dut/wb_ack_o_3
add wave -noupdate -group {WISHBONE IF} -group wb3 -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/wb_dat_o_3
add wave -noupdate -group {WISHBONE IF} -group wb3 -divider <NULL>
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_adr_i
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Logic /versatile_mem_ctrl_tb/wb0_ack_o
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -divider <NULL>
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_adr_i
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Logic /versatile_mem_ctrl_tb/wb1_ack_o
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -divider <NULL>
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_adr_i
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -format Logic /versatile_mem_ctrl_tb/wb4_ack_o
add wave -noupdate -group {WISHBONE IF} -expand -group Testbench -divider <NULL>
add wave -noupdate -group {TX FIFO} -divider {Tx FIFO Control}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[27]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[26]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[25]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[24]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[23]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[22]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[21]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[20]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[19]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[18]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[17]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[16]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[15]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[14]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[13]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[12]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[11]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[10]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[9]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[8]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[7]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[6]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[5]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[4]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[3]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[2]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[1]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[0]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[31]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[30]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[29]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[28]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[27]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[26]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[25]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[24]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[23]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[22]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[21]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[20]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[19]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[18]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[17]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[16]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[15]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[14]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[13]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[12]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[11]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[10]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[9]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[8]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[7]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[6]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[5]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[4]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[3]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]}
add wave -noupdate -group {TX FIFO} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]}
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/cs_n
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix binary /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_empty
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_sel
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]}
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle
add wave -noupdate -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/cur_row
add wave -noupdate -group {MAIN STATE MACHINE} -divider <NULL>
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
add wave -noupdate -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/burst_mask
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb0i/statename
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_i
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_adr_i
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb0_dat_o
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Logic /versatile_mem_ctrl_tb/wb0_ack_o
add wave -noupdate -group {WISHBONE IF} -group Testbench -divider <NULL>
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb1i/statename
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_i
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_adr_i
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb1_dat_o
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Logic /versatile_mem_ctrl_tb/wb1_ack_o
add wave -noupdate -group {WISHBONE IF} -group Testbench -divider <NULL>
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix ascii /versatile_mem_ctrl_tb/wb4i/statename
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_i
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_adr_i
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/wb4_dat_o
add wave -noupdate -group {WISHBONE IF} -group Testbench -format Logic /versatile_mem_ctrl_tb/wb4_ack_o
add wave -noupdate -group {WISHBONE IF} -group Testbench -divider <NULL>
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[31]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[30]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[29]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[28]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[27]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[26]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[25]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[24]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[23]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[22]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[21]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[20]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[19]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[18]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[17]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -group FIFO_0_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[16]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[15]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[14]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[13]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[12]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[11]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[10]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[9]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[8]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[7]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[6]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[5]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[4]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[3]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[2]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[1]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 0} -expand -group FIFO_0_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/dpram/ram[0]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[31]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[30]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[29]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[28]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[27]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[26]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[25]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[24]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[23]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[22]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[21]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[20]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[19]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[18]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[17]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -group FIFO_1_1 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[16]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[15]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[14]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[13]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[12]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[11]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[10]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[9]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[8]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[7]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[6]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[5]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[4]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[3]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[2]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[1]}
add wave -noupdate -group {TX FIFO (Egress FIFO)} -expand -group {Tx FIFO 1} -expand -group FIFO_1_0 -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/dpram/ram[0]}
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/rst
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/clk
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider State
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider Input
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_ack
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/burst_adr
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_empty
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re_d
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_sel
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/next_row_open
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay_ack
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_req
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/stall
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic -radix hexadecimal {/versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o[5]}
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/tx_fifo_dat_o
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider Output
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/ddr_16_0/a
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/adr_init
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/bl_en
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/close_cur_row
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/cmd
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/cs_n
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/fifo_re
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_ba
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/open_cur_row
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/ddr_16_0/open_row
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/read
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_ack
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/ref_delay
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/write
add wave -noupdate -expand -group {MAIN STATE MACHINE} -divider {Other usefull signals (Non-FSM)}
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal /versatile_mem_ctrl_tb/dut/fifo_sel_domain_reg
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_o
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/ddr_16_0/state_idle
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re_i
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/tx_fifo_re
add wave -noupdate -expand -group {MAIN STATE MACHINE} -format Logic /versatile_mem_ctrl_tb/dut/burst_mask
add wave -noupdate -group {BURST ADDRESS} -divider State
add wave -noupdate -group {BURST ADDRESS} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
add wave -noupdate -group {BURST ADDRESS} -divider {Burst Address}
add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
add wave -noupdate -group {BURST ADDRESS} -divider Input
add wave -noupdate -group {BURST ADDRESS} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/cti_i
add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/bte_i
add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init
add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
add wave -noupdate -group {BURST ADDRESS} -divider Internal
add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/bte
add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
add wave -noupdate -group {BURST ADDRESS} -divider Output
add wave -noupdate -group {BURST ADDRESS} -format Literal /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
add wave -noupdate -group {BURST ADDRESS} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -divider {Micron DDR2 SDRAM}
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Logic /versatile_mem_ctrl_tb/ddr2_sdram/ck
176,119 → 207,62
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/dqs_n
add wave -noupdate -group {DDR2 SDRAM SIMULATIOM MODEL} -format Literal /versatile_mem_ctrl_tb/ddr2_sdram/rdqs_n
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 0}
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/d
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write_enable
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk1
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst1
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read_enable
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk2
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst2
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_full
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/q
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_empty
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/d
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/write_enable
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk1
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst1
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/read_enable
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/clk2
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/rst2
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_full
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/q
add wave -noupdate -group {RX FIFO} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/fifo_empty
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[31]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[30]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[29]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[28]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[27]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[26]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[25]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[24]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[23]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[22]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[21]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[20]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[19]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[18]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[17]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[16]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[15]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[14]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[13]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[12]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[11]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[10]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[9]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[8]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[7]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[6]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[5]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[4]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[3]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[2]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[1]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[0]}
add wave -noupdate -group {RX FIFO} -divider {Rx FIFO 1}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[31]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[30]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[29]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[28]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[27]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[26]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[25]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[24]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[23]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[22]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[21]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[20]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[19]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[18]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[17]}
add wave -noupdate -group {RX FIFO} -group {Fifo 1 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[16]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[15]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[14]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[13]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[12]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[11]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[10]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[9]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[8]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[7]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[6]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[5]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[4]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[3]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[2]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[1]}
add wave -noupdate -group {RX FIFO} -expand -group {Fifo 1 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk3/wb1/ingress_FIFO/dpram/ram[0]}
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/write
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/read
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/rst
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/clk
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_i
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/bte_i
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cti_i
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/init_i
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/inc
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/cnt
add wave -noupdate -group {ADDRESS INCREMENT} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/inc_adr0/adr_o
add wave -noupdate -group {ADDRESS INCREMENT} -format Logic /versatile_mem_ctrl_tb/dut/inc_adr0/done
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
add wave -noupdate -group {Burst length} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
add wave -noupdate -group {Burst length} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
add wave -noupdate -group {Burst length} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -divider {Rx FIFO 0}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/d
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/write_enable
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk1
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst1
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/read_enable
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/clk2
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Logic /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/rst2
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_full
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/q
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -group {Fifo Control} -format Literal /versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/fifo_empty
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[31]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[30]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[29]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[28]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[27]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[26]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[25]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[24]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[23]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[22]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[21]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[20]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[19]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[18]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[17]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 0} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[16]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[15]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[14]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[13]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[12]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[11]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[10]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[9]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[8]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[7]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[6]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[5]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[4]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[3]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[2]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[1]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -expand -group {Fifo 0 1} -format Literal -radix hexadecimal {/versatile_mem_ctrl_tb/dut/genblk1/wb0/ingress_FIFO/dpram/ram[0]}
add wave -noupdate -group {RX FIFO (Ingress FIFO)} -divider {Rx FIFO 1}
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/rst
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/clk
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/cke
add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/length
add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/clear_value
add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/set_value
add wave -noupdate -group {BURST LENGTH} -format Literal /versatile_mem_ctrl_tb/dut/burst_length_counter0/wrap_value
add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/qi
add wave -noupdate -group {BURST LENGTH} -format Literal -radix unsigned /versatile_mem_ctrl_tb/dut/burst_length_counter0/q_next
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq
add wave -noupdate -group {DDR2 IF} -divider FSM
add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
add wave -noupdate -group {DDR2 IF} -divider {Controller side}
328,10 → 302,41
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_en
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dqm_en
add wave -noupdate -group {DDR2 IF} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/tx_dat_i
add wave -noupdate -group {OPEN BANKS & ROWS} -divider State
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename
add wave -noupdate -group {OPEN BANKS & ROWS} -divider {Open bank & row}
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/open_bank_i
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/open_row_i
add wave -noupdate -group {OPEN BANKS & ROWS} -format Logic /versatile_mem_ctrl_tb/dut/open_cur_row
add wave -noupdate -group {OPEN BANKS & ROWS} -format Logic /versatile_mem_ctrl_tb/dut/close_cur_row
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/open_row
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_row
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_row
add wave -noupdate -group {OPEN BANKS & ROWS} -format Literal /versatile_mem_ctrl_tb/dut/next_bank
add wave -noupdate -group {OPEN BANKS & ROWS} -format Logic /versatile_mem_ctrl_tb/dut/next_row_open
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_0_1
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_0_0
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk1/wb0/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_1_1
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider FIFO_1_0
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/wptr_bin}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/rptr_bin}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix unsigned {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/ptr_diff}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_empty}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_full}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Logic {/versatile_mem_ctrl_tb/dut/genblk3/wb1/egress_FIFO/fifo_adr[0]/egresscmp/fifo_flag}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -divider {FIFO Flags on top-level}
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_empty
add wave -noupdate -expand -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_flag
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {287500000 ps} 0}
configure wave -namecolwidth 362
configure wave -valuecolwidth 136
WaveRestoreCursors {{Cursor 1} {300596000 ps} 0}
configure wave -namecolwidth 441
configure wave -valuecolwidth 151
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
344,4 → 349,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {287392403 ps} {287565725 ps}
WaveRestoreZoom {300581153 ps} {300790631 ps}

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