URL
https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
Subversion Repositories versatile_mem_ctrl
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- This comparison shows the changes necessary to convert path
/versatile_mem_ctrl
- from Rev 85 to Rev 86
- ↔ Reverse comparison
Rev 85 → Rev 86
/trunk/rtl/verilog/versatile_mem_ctrl_ip.v
2713,6 → 2713,7
wire [0:0] sub_wire1 = sub_wire0[0:0]; |
wire sub_wire6 = clk_in; |
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; |
wire clk_fb; |
|
assign clk0_out = sub_wire1; |
assign clk90_out = sub_wire2; |
2744,7 → 2745,6
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
.operation_mode("NORMAL"), |
// .operation_mode("SOURCE_SYNCHRONOUS"), |
.pll_type("AUTO"), |
.port_activeclock("PORT_UNUSED"), |
.port_areset("PORT_USED"), |
2791,11 → 2791,11
.using_fbmimicbidir_port("OFF"), |
.width_clock(10)) |
altpll_internal ( |
.fbin (),//(clkfb_in), |
.fbin (clkfb), |
.inclk (sub_wire7), |
.areset (rst), |
.clk (sub_wire0), |
.fbout (),//(clkfb_out), |
.fbout (clkfb), |
.activeclock (), |
.clkbad (), |
.clkena ({6{1'b1}}), |
/trunk/rtl/verilog/dcm_pll.v
124,6 → 124,7
wire [0:0] sub_wire1 = sub_wire0[0:0]; |
wire sub_wire6 = clk_in; |
wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; |
wire clk_fb; |
|
assign clk0_out = sub_wire1; |
assign clk90_out = sub_wire2; |
155,7 → 156,6
.lpm_hint("UNUSED"), |
.lpm_type("altpll"), |
.operation_mode("NORMAL"), |
// .operation_mode("SOURCE_SYNCHRONOUS"), |
.pll_type("AUTO"), |
.port_activeclock("PORT_UNUSED"), |
.port_areset("PORT_USED"), |
202,11 → 202,11
.using_fbmimicbidir_port("OFF"), |
.width_clock(10)) |
altpll_internal ( |
.fbin (),//(clkfb_in), |
.fbin (clkfb), |
.inclk (sub_wire7), |
.areset (rst), |
.clk (sub_wire0), |
.fbout (),//(clkfb_out), |
.fbout (clkfb), |
.activeclock (), |
.clkbad (), |
.clkena ({6{1'b1}}), |
/trunk/sim/rtl_sim/bin/wave_ddr.do
264,6 → 264,7
add wave -noupdate -group {BURST LENGTH} -format Logic /versatile_mem_ctrl_tb/dut/burst_length_counter0/zq |
add wave -noupdate -group {DDR2 IF} -divider FSM |
add wave -noupdate -group {DDR2 IF} -format Literal -radix ascii /versatile_mem_ctrl_tb/dut/ddr_16_0/statename |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270 |
add wave -noupdate -group {DDR2 IF} -divider {Controller side} |
add wave -noupdate -group {DDR2 IF} -divider {Clock & reset} |
add wave -noupdate -group {DDR2 IF} -format Logic /versatile_mem_ctrl_tb/dut/sdram_rst |
331,8 → 332,17
add wave -noupdate -group {FIFO Pointers & Flags} -divider {FIFO Flags on top-level} |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_empty |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_flag |
add wave -noupdate -group {FIFO Pointers & Flags} -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx |
add wave -noupdate -divider tmp |
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/ck_pad_o |
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/dq_pad_io |
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_270 |
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx |
add wave -noupdate -format Logic /versatile_mem_ctrl_tb/dut/sdram_clk_180 |
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/versatile_mem_ctrl_ddr_0/dq_rx_reg |
add wave -noupdate -format Literal -radix hexadecimal /versatile_mem_ctrl_tb/dut/fifo_dat_i |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {301340000 ps} 0} |
WaveRestoreCursors {{Cursor 1} {222981669 ps} 0} |
configure wave -namecolwidth 441 |
configure wave -valuecolwidth 151 |
configure wave -justifyvalue left |
347,4 → 357,4
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {300901312 ps} {301778688 ps} |
WaveRestoreZoom {0 ps} {346500 ns} |
/trunk/syn/altera/bin/versatile_memory_controller.sdc
199,15 → 199,15
# Input Timing Exceptions |
# False path exceptions for opposite-edge transfer |
# Data |
set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] |
set_false_path -setup -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] |
set_false_path -hold -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] |
set_false_path -hold -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] |
set_false_path -setup -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] |
set_false_path -setup -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] |
set_false_path -hold -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_270] |
set_false_path -hold -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_270] |
# Data Strobe |
#set_false_path -setup -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0] |
#set_false_path -setup -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0] |
#set_false_path -hold -rise_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0] |
#set_false_path -hold -fall_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0] |
#set_false_path -setup -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0] |
#set_false_path -setup -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0] |
#set_false_path -hold -rise_from [get_clocks ck_pad_o] -rise_to [get_clocks sdram_clk_0] |
#set_false_path -hold -fall_from [get_clocks ck_pad_o] -fall_to [get_clocks sdram_clk_0] |
|
# Output Timing Exceptions |
# False path exceptions for opposite-edge transfer |