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Rev 98 → Rev 99

/trunk/bench/tb.v
1,4 → 1,4
`include "tb_defines.v"
//`include "tb_defines.v"
`timescale 1ns/1ns
module versatile_mem_ctrl_tb
(
5,315 → 5,227
output OK
);
 
reg wb_clk, wb_rst;
reg sdram_clk, sdram_rst;
reg tb_rst;
`ifdef NR_OF_WBM
parameter nr_of_wbm = `NR_OF_WBM;
`else
parameter nr_of_wbm = 1;
`endif
 
wire [31:0] wbm_dat_i [1:nr_of_wbm];
wire [3:0] wbm_sel_i [1:nr_of_wbm];
wire [31:0] wbm_adr_i [1:nr_of_wbm];
wire [2:0] wbm_cti_i [1:nr_of_wbm];
wire [1:0] wbm_bte_i [1:nr_of_wbm];
wire wbm_cyc_i [1:nr_of_wbm];
wire wbm_stb_i [1:nr_of_wbm];
wire [31:0] wbm_dat_o [1:nr_of_wbm];
wire wbm_ack_o [1:nr_of_wbm];
wire wbm_clk [1:nr_of_wbm];
wire wbm_rst;
`ifdef SDRAM_CLK_PERIOD
parameter sdram_clk_period = `SDRAM_CLK_PERIOD;
`else
parameter sdram_clk_period = 8;
`endif
 
`ifdef WB_CLK_PERIODS
parameter [1:nr_of_wbm] wb_clk_periods = {`WB_CLK_PERIODS};
`else
parameter [1:nr_of_wbm] wb_clk_periods = (20);
`endif
parameter wb_clk_period = 20;
wire [31:0] wbm_a_dat_o [1:nr_of_wbm];
wire [3:0] wbm_a_sel_o [1:nr_of_wbm];
wire [31:0] wbm_a_adr_o [1:nr_of_wbm];
wire [2:0] wbm_a_cti_o [1:nr_of_wbm];
wire [1:0] wbm_a_bte_o [1:nr_of_wbm];
wire wbm_a_we_o [1:nr_of_wbm];
wire wbm_a_cyc_o [1:nr_of_wbm];
wire wbm_a_stb_o [1:nr_of_wbm];
wire [31:0] wbm_a_dat_i [1:nr_of_wbm];
wire wbm_a_ack_i [1:nr_of_wbm];
reg wbm_a_clk [1:nr_of_wbm];
reg wbm_a_rst [1:nr_of_wbm];
 
wire [31:0] wbm_b_dat_o [1:nr_of_wbm];
wire [3:0] wbm_b_sel_o [1:nr_of_wbm];
wire [31:2] wbm_b_adr_o [1:nr_of_wbm];
wire [2:0] wbm_b_cti_o [1:nr_of_wbm];
wire [1:0] wbm_b_bte_o [1:nr_of_wbm];
wire wbm_b_we_o [1:nr_of_wbm];
wire wbm_b_cyc_o [1:nr_of_wbm];
wire wbm_b_stb_o [1:nr_of_wbm];
wire [31:0] wbm_b_dat_i [1:nr_of_wbm];
wire wbm_b_ack_i [1:nr_of_wbm];
 
wire [31:0] wb_sdram_dat_i;
wire [3:0] wb_sdram_sel_i;
wire [31:0] wb_sdram_adr_i;
wire [31:2] wb_sdram_adr_i;
wire [2:0] wb_sdram_cti_i;
wire [1:0] wb_sdram_bte_i;
wire wb_sdram_we_i;
wire wb_sdram_cyc_i;
wire wb_sdram_stb_i;
wire [31:0] wb_sdram_dat_o;
wire wb_sdram_ack_o;
reg wb_sdram_clk;
reg wb_sdram_rst;
wire [1:nr_of_wbm] wbm_OK;
genvar i;
`define DUT sdr_sdram_16_ctrl
`define SDR 16
`ifdef SDR
wire [1:0] ba, ba_pad;
wire [12:0] a, a_pad;
wire [`SDR-1:0] dq_i, dq_o, dq_pad;
wire dq_oe;
wire [1:0] dqm, dqm_pad;
wire cke, cke_pad, cs_n, cs_n_pad, ras, ras_pad, cas, cas_pad, we, we_pad;
assign #1 {ba_pad,a_pad} = {ba,a};
assign #1 {ras_pad, cas_pad, we_pad} = {ras,cas,we};
assign #1 dqm_pad = dqm;
assign #1 cke_pad = cke;
assign cs_n_pad = cs_n;
mt48lc16m16a2 mem(
.Dq(dq_pad),
.Addr(a_pad),
.Ba(ba_pad),
.Clk(wb_sdram_clk),
.Cke(cke_pad),
.Cs_n(cs_n_pad),
.Ras_n(ras_pad),
.Cas_n(cas_pad),
.We_n(we_pad),
.Dqm(dqm_pad));
assign #1 dq_pad = (dq_oe) ? dq_o : {`SDR{1'bz}};
assign #1 dq_i = dq_pad;
`DUT DUT(
// wisbone i/f
.dat_i(wb_sdram_dat_i),
.adr_i({wb_sdram_adr_i[24:2],1'b0}),
.sel_i(wb_sdram_sel_i),
.cti_i(wb_sdram_cti_i),
.bte_i(wb_sdram_bte_i),
.we_i (wb_sdram_we_i),
.cyc_i(wb_sdram_cyc_i),
.stb_i(wb_sdram_stb_i),
.dat_o(wb_sdram_dat_o),
.ack_o(wb_sdram_ack_o),
// SDR SDRAM
.ba(ba),
.a(a),
.cmd({ras, cas, we}),
.cke(cke),
.cs_n(cs_n),
.dqm(dqm),
.dq_i(dq_i),
.dq_o(dq_o),
.dq_oe(dq_oe),
// system
.clk(wb_sdram_clk), .rst(wb_sdram_rst));
`endif
 
wire [1:0] ba, bad;
wire [12:0] a, ad;
wire [15:0] dq_i;
wire [15:0] dq_o;
wire [15:0] dq_io;
wire [1:0] dqs, dqs_n, dqs_i, dqs_o, dqs_n_i, dqs_n_o, dqs_io, dqs_n_io;
wire [1:0] dqm, dqmd, dm_rdqs;
wire dq_oe, dqs_oe;
wire cs_n, cs_nd, ras, rasd, cas, casd, we, wed, cke, cked;
wire ck_fb_i, ck_fb_o;
// wishbone master(s)
generate
for (i=1; i <= nr_of_wbm; i=i+1) begin: wb_master
wbm wbmi(
.adr_o(wbm_a_adr_o[i]),
.bte_o(wbm_a_bte_o[i]),
.cti_o(wbm_a_cti_o[i]),
.dat_o(wbm_a_dat_o[i]),
.sel_o(wbm_a_sel_o[i]),
.we_o (wbm_a_we_o[i]),
.cyc_o(wbm_a_cyc_o[i]),
.stb_o(wbm_a_stb_o[i]),
.dat_i(wbm_a_dat_i[i]),
.ack_i(wbm_a_ack_i[i]),
.clk(wbm_a_clk[i]),
.reset(wbm_a_rst[i]),
.OK(wbm_OK[i])
);
 
`ifdef SDR_16 // SDR SDRAM
wb0 wb0i
(
.adr(wb0_adr_i),
.bte(wb0_bte_i),
.cti(wb0_cti_i),
.cyc(wb0_cyc_i),
.dat(wb0_dat_i),
.sel(wb0_sel_i),
.stb(wb0_stb_i),
.we (wb0_we_i),
.ack(wb0_ack_o),
.clk(wb_clk),
.dat_i(wb0_dat_o),
.reset(wb_rst)
);
wb1 wb1i
(
.adr(wb1_adr_i),
.bte(wb1_bte_i),
.cti(wb1_cti_i),
.cyc(wb1_cyc_i),
.dat(wb1_dat_i),
.sel(wb1_sel_i),
.stb(wb1_stb_i),
.we (wb1_we_i),
.ack(wb1_ack_o),
.clk(wb_clk),
.dat_i(wb1_dat_o),
.reset(wb_rst)
);
wb4 wb4i
(
.adr(wb4_adr_i),
.bte(wb4_bte_i),
.cti(wb4_cti_i),
.cyc(wb4_cyc_i),
.dat(wb4_dat_i),
.sel(wb4_sel_i),
.stb(wb4_stb_i),
.we (wb4_we_i),
.ack(wb4_ack_o),
.clk(wb_clk),
.dat_i(wb4_dat_o),
.reset(wb_rst)
);
`endif
wb3wb3_bridge wbwb_bridgei (
// wishbone slave side
.wbs_dat_i(wbm_a_dat_o[i]),
.wbs_adr_i(wbm_a_adr_o[i][31:2]),
.wbs_sel_i(wbm_a_sel_o[i]),
.wbs_bte_i(wbm_a_bte_o[i]),
.wbs_cti_i(wbm_a_cti_o[i]),
.wbs_we_i (wbm_a_we_o[i]),
.wbs_cyc_i(wbm_a_cyc_o[i]),
.wbs_stb_i(wbm_a_stb_o[i]),
.wbs_dat_o(wbm_a_dat_i[i]),
.wbs_ack_o(wbm_a_ack_i[i]),
.wbs_clk(wbm_a_clk[i]),
.wbs_rst(wbm_a_rst[i]),
// wishbone master side
.wbm_dat_o(wbm_b_dat_o[i]),
.wbm_adr_o(wbm_b_adr_o[i]),
.wbm_sel_o(wbm_b_sel_o[i]),
.wbm_bte_o(wbm_b_bte_o[i]),
.wbm_cti_o(wbm_b_cti_o[i]),
.wbm_we_o (wbm_b_we_o[i]),
.wbm_cyc_o(wbm_b_cyc_o[i]),
.wbm_stb_o(wbm_b_stb_o[i]),
.wbm_dat_i(wbm_b_dat_i[i]),
.wbm_ack_i(wbm_b_ack_i[i]),
.wbm_clk(wb_sdram_clk),
.wbm_rst(wb_sdram_rst));
end
endgenerate
 
`ifdef DDR_16 // DDR2 SDRAM
wb0_ddr wb0i
(
.adr(wb0_adr_i),
.bte(wb0_bte_i),
.cti(wb0_cti_i),
.cyc(wb0_cyc_i),
.dat(wb0_dat_i),
.sel(wb0_sel_i),
.stb(wb0_stb_i),
.we (wb0_we_i),
.ack(wb0_ack_o),
.clk(wb_clk),
.dat_i(wb0_dat_o),
.reset(tb_rst)
);
wb1_ddr wb1i
(
.adr(wb1_adr_i),
.bte(wb1_bte_i),
.cti(wb1_cti_i),
.cyc(wb1_cyc_i),
.dat(wb1_dat_i),
.sel(wb1_sel_i),
.stb(wb1_stb_i),
.we (wb1_we_i),
.ack(wb1_ack_o),
.clk(wb_clk),
.dat_i(wb1_dat_o),
.reset(tb_rst)
);
wb4_ddr wb4i
(
.adr(wb4_adr_i),
.bte(wb4_bte_i),
.cti(wb4_cti_i),
.cyc(wb4_cyc_i),
.dat(wb4_dat_i),
.sel(wb4_sel_i),
.stb(wb4_stb_i),
.we (wb4_we_i),
.ack(wb4_ack_o),
.clk(wb_clk),
.dat_i(wb4_dat_o),
.reset(tb_rst)
);
`define SINGLE_WB
`ifdef SINGLE_WB
assign wb_sdram_dat_i=wbm_b_dat_o[1];
assign wb_sdram_sel_i=wbm_b_sel_o[1];
assign wb_sdram_adr_i=wbm_b_adr_o[1];
assign wb_sdram_we_i =wbm_b_we_o[1];
assign wb_sdram_bte_i=wbm_b_bte_o[1];
assign wb_sdram_cti_i=wbm_b_cti_o[1];
assign wb_sdram_cyc_i=wbm_b_cyc_o[1];
assign wb_sdram_stb_i=wbm_b_stb_o[1];
assign wbm_b_dat_i[1]=wb_sdram_dat_o;
assign wbm_b_ack_i[1]=wb_sdram_ack_o;
`endif
 
versatile_mem_ctrl_top # (
.nr_of_wb_clk_domains(2),
.nr_of_wb_ports_clk0(1),
.nr_of_wb_ports_clk1(1),
.nr_of_wb_ports_clk2(0),
.nr_of_wb_ports_clk3(0))
dut (
.wb_adr_i_0({{wb0_adr_i[31:2],wb0_we_i,wb0_bte_i,wb0_cti_i},{wb1_adr_i[31:2],wb1_we_i,wb1_bte_i,wb1_cti_i}}),
.wb_dat_i_0({{wb0_dat_i,wb0_sel_i},{wb1_dat_i,wb1_sel_i}}),
.wb_dat_o_0({wb0_dat_o,wb1_dat_o}),
.wb_stb_i_0({wb0_stb_i,wb1_stb_i}),
.wb_cyc_i_0({wb0_cyc_i,wb1_cyc_i}),
.wb_ack_o_0({wb0_ack_o,wb1_ack_o}),
assign OK = &wbm_OK;
 
.wb_adr_i_1({wb4_adr_i[31:2],wb4_we_i,wb4_bte_i,wb4_cti_i}),
.wb_dat_i_1({wb4_dat_i,wb4_sel_i}),
.wb_dat_o_1(wb4_dat_o),
.wb_stb_i_1(wb4_stb_i),
.wb_cyc_i_1(wb4_cyc_i),
.wb_ack_o_1(wb4_ack_o),
generate
for (i=1; i <= nr_of_wbm; i=i+1) begin: wb_reset
 
.wb_adr_i_2(2'b0),
.wb_dat_i_2(2'b0),
.wb_dat_o_2(),
.wb_stb_i_2(2'b0),
.wb_cyc_i_2(2'b0),
.wb_ack_o_2(),
// Wishbone reset
initial
begin
#0 wbm_a_rst[i] = 1'b1;
#200 wbm_a_rst[i] = 1'b0;
end
 
.wb_adr_i_3(2'b0),
.wb_dat_i_3(2'b0),
.wb_dat_o_3(),
.wb_stb_i_3(2'b0),
.wb_cyc_i_3(2'b0),
.wb_ack_o_3(),
// Wishbone clock
initial
begin
#0 wbm_a_clk[i] = 1'b0;
forever
#(wb_clk_period/2) wbm_a_clk[i] = !wbm_a_clk[i];
end
 
// SDR SDRAM 16
`ifdef SDR_16
.ba_pad_o(ba),
.a_pad_o(a),
.cs_n_pad_o(cs_n),
.ras_pad_o(ras),
.cas_pad_o(cas),
.we_pad_o(we),
.dq_o(dq_o),
.dqm_pad_o(dqm),
.dq_i(dq_i),
.dq_oe(dq_oe),
.cke_pad_o(cke),
`endif
`ifdef DDR_16
// DDR2 SDRAM 16
.ck_pad_o(ck),
.ck_n_pad_o(ck_n),
.cke_pad_o(cke),
.ck_fb_pad_o(ck_fb_o),
.ck_fb_pad_i(ck_fb_i),
.cs_n_pad_o(cs_n),
.ras_pad_o(ras),
.cas_pad_o(cas),
.we_pad_o(we),
.dm_rdqs_pad_io(dm_rdqs),
.ba_pad_o(ba),
.addr_pad_o(a),
.dq_pad_io(dq_io),
.dqs_pad_io(dqs_io),
.dqs_oe(dqs_oe),
.dqs_n_pad_io(dqs_n_io),
.rdqs_n_pad_i(),
.odt_pad_o(),
`endif
// misc
.wb_clk({wb_clk,wb_clk}),
.wb_rst({wb_rst,wb_rst}),
.sdram_clk(sdram_clk),
.sdram_rst(wb_rst)
);
 
`ifdef SDR_16
assign #1 dq_io = dq_oe ? dq_o : {16{1'bz}};
assign #1 dq_i = dq_io;
assign #1 dqmd = dqm;
assign #1 dqs_io = dqs_oe ? dqs_o : {2{1'bz}};
assign #1 dqs_i = dqs_io;
assign #1 dqs_n_io = dqs_oe ? dqs_n_o : {2{1'bz}};
assign #1 dqs_n_i = dqs_n_io;
`endif
 
`ifdef DDR_16
assign #1 dqmd = dqm;
assign ck_fb_i = ck_fb_o;
`endif
 
assign #1 ad = a;
assign #1 bad = ba;
assign #1 cked = cke;
assign #1 cs_nd = cs_n;
assign #1 rasd = ras;
assign #1 casd = cas;
assign #1 wed = we;
`ifdef SDR_16 // SDR SDRAM Simulation model
mt48lc16m16a2 sdram
(
.Dq(dq_io),
.Addr(ad),
.Ba(bad),
.Clk(sdram_clk),
.Cke(cked),
.Cs_n(cs_nd),
.Ras_n(rasd),
.Cas_n(casd),
.We_n(wed),
.Dqm(dqmd)
);
`endif
`ifdef DDR_16 // DDR2 SDRAM Simulation model
ddr2 ddr2_sdram
(
.ck(ck),
.ck_n(ck_n),
.cke(cke),
.cs_n(cs_n),
.ras_n(ras),
.cas_n(cas),
.we_n(we),
.dm_rdqs(dm_rdqs),
.ba(ba),
.addr(a),
.dq(dq_io),
.dqs(dqs_io),
.dqs_n(dqs_n_io),
.rdqs_n(),
.odt()
);
`endif
 
// Wishbone reset
initial
begin
#0 wb_rst = 1'b1;
#200 wb_rst = 1'b1;
#200000 wb_rst = 1'b0;
end
endgenerate
 
// SDRAM reset
initial
begin
#0 sdram_rst = 1'b1;
#200 sdram_rst = 1'b1;
#200000 sdram_rst = 1'b0;
#0 wb_sdram_rst = 1'b1;
#200 wb_sdram_rst = 1'b0;
end
// Test bench reset
initial
begin
#0 tb_rst = 1'b1;
#200 tb_rst = 1'b1;
//#200000 tb_rst = 1'b0;
#300000 tb_rst = 1'b0; // hold reset to let initialization complete
end
 
// Wishbone clock
initial
begin
#0 wb_clk = 1'b0;
forever
#(wb0_clk_period/2) wb_clk = !wb_clk;
end
 
// SDRAM clock
initial
begin
#0 sdram_clk = 1'b0;
#0 wb_sdram_clk = 1'b0;
forever
#(sdram_clk_period/2) sdram_clk = !sdram_clk;
#(sdram_clk_period/2) wb_sdram_clk = !wb_sdram_clk;
end
endmodule // versatile_mem_ctrl_tb
/trunk/bench/wbm.v
1,3 → 1,4
`timescale 1ns/1ns
module wbm (
output [31:0] adr_o,
output [1:0] bte_o,
24,10 → 25,39
eob = 3'b111;
 
parameter instructions = 32;
 
// {adr_o,bte_o,cti_o,dat_o,sel_o,we_o,cyc_o,stb_o}
parameter [32+2+3+32+4+1+1+1:1] inst_rom [0:instructions-1]= {
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h100,linear,classic,32'h12345678,4'b1111,1'b1,1'b1,1'b1},
{32'h100,linear,classic,32'h0,4'b1111,1'b0,1'b1,1'b1},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'hA000,beat4,inc,32'h00010002,4'b1111,1'b1,1'b1,1'b1}, // write burst
{32'hA004,beat4,inc,32'h00030004,4'b1111,1'b1,1'b1,1'b1},
{32'hA008,beat4,inc,32'h00050006,4'b1111,1'b1,1'b1,1'b1},
{32'hA00C,beat4,eob,32'h00070008,4'b1111,1'b1,1'b1,1'b1},
{32'hA008,linear,classic,32'hA1FFFFFF,4'b1000,1'b1,1'b1,1'b1},// write byte
{32'hA000,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read burst
{32'hA004,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
{32'hA008,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
{32'hA00C,beat4,eob,32'h0,4'b1111,1'b0,1'b1,1'b1},
{32'h1000,linear,inc,32'hdeaddead,4'b1111,1'b1,1'b1,1'b1}, // write
{32'h1004,linear,eob,32'h55555555,4'b1111,1'b1,1'b1,1'b1}, //
{32'h1000,linear,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
{32'h1004,linear,eob,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read
{32'hA008,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1}, // read burst
{32'hA00C,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
{32'hA000,beat4,inc,32'h0,4'b1111,1'b0,1'b1,1'b1},
{32'hA004,beat4,eob,32'h0,4'b1111,1'b0,1'b1,1'b1},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
37,26 → 67,6
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0},
{32'h0,linear,classic,32'h0,4'b1111,1'b0,1'b0,1'b0}};
parameter [31:0] dat [0:instructions-1] = {
63,6 → 73,7
32'h0,
32'h0,
32'h0,
32'h12345678,
32'h0,
32'h0,
32'h0,
69,8 → 80,18
32'h0,
32'h0,
32'h0,
32'h00010002,
32'h00030004,
32'ha1050006,
32'h00070008,
32'h0,
32'h0,
32'hdeaddead,
32'h55555555,
32'ha1050006,
32'h00070008,
32'h00010002,
32'h00030004,
32'h0,
32'h0,
32'h0,
81,16 → 102,6
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0,
32'h0};
// parameter idle = 1'b0;
106,7 → 117,7
if (reset)
i = 0;
else
if ((!stb_o | ack_i) & i < instructions)
if ((!stb_o | ack_i) & i < instructions - 1)
i = i + 1;
 
always @ (posedge clk or posedge reset)
113,9 → 124,10
if (reset)
OK <= 1'b1;
else
if (ack_i & !we_o & (dat_i != dat[i]))
if (ack_i & !we_o & (dat_i != dat[i])) begin
OK <= 1'b0;
//assert "Read error";
$display ("wrong read value %h at %t", dat_i, $time);
end
// always @ (posedge clk or posedge reset)
// if (reset)

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