URL
https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk
Subversion Repositories vhdl_wb_tb
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- This comparison shows the changes necessary to convert path
/vhdl_wb_tb/trunk
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/bench/vhdl/stimulator.vhd
63,13 → 63,13
-- entity ------------------------------------------------------------ |
entity stimulator is |
generic( |
g_number_of_signals : natural := 1 |
number_of_signals_g : natural := 1 |
); |
port( |
wb_i : in wishbone_slave_in_t; |
wb_o : out wishbone_slave_out_t; |
|
signals_o : out std_logic_vector(g_number_of_signals-1 downto 0) |
signals_o : out std_logic_vector(number_of_signals_g-1 downto 0) |
); |
end stimulator; |
|
78,8 → 78,8
--============================================================================ |
-- signal declaration |
--============================================================================ |
signal s_register0 : std_logic_vector(wb_i.dat'left downto 0); |
signal s_register1 : std_logic_vector(wb_i.dat'left downto 0); |
signal register0_s : std_logic_vector(wb_i.dat'left downto 0); |
signal register1_s : std_logic_vector(wb_i.dat'left downto 0); |
--============================================================================ |
begin |
------------------------------------------------------------------------------ |
93,9 → 93,9
begin |
case wb_i.adr(27 downto 0) is |
when 28X"000_0000" => |
wb_o.dat <= s_register0; |
wb_o.dat <= register0_s; |
when 28X"000_0004" => |
wb_o.dat <= s_register1; |
wb_o.dat <= register1_s; |
when others => |
wb_o.dat <= (others =>'U'); |
end case; |
104,15 → 104,15
proc_avalon_write_data : process (all) |
begin |
if (wb_i.rst = '1') then |
s_register0 <= (others => '0'); |
s_register1 <= (others => '0'); |
register0_s <= (others => '0'); |
register1_s <= (others => '0'); |
elsif (rising_edge(wb_i.clk)) then |
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then |
case wb_i.adr(27 downto 0) is |
when 28X"000_0000" => |
s_register0 <= wb_i.dat; |
register0_s <= wb_i.dat; |
when 28X"000_0004" => |
s_register1 <= wb_i.dat; |
register1_s <= wb_i.dat; |
when others => |
end case; |
end if; |
119,7 → 119,7
end if; |
end process; |
------------------------------------------------------------------------------ |
signals_o <= s_register0(signals_o'left downto 0); |
signals_o <= register0_s(signals_o'left downto 0); |
--============================================================================ |
end rtl; --stimulator |
---------------------------------------------------------------------- |
/bench/vhdl/tb_top.vhd
77,28 → 77,28
-- architecture ------------------------------------------------------ |
architecture rtl of tb_top is |
----------------------------------------------------------------------------- |
constant g_wb_clock_period : time := 20.0 ns; -- 50 mhz |
constant wb_clock_period_g : time := 20.0 ns; -- 50 mhz |
----------------------------------------------------------------------------- |
signal s_wb_bfm_out : wishbone_bfm_master_out_t; -- from testcase_top |
signal s_wb_bfm_in : wishbone_bfm_master_in_t; -- to testcase_top |
signal wb_bfm_out_s : wishbone_bfm_master_out_t; -- from testcase_top |
signal wb_bfm_in_s : wishbone_bfm_master_in_t; -- to testcase_top |
|
signal s_wb_master_out : wishbone_master_out_t; -- from wb_decoder |
signal s_wb_master_in : wishbone_master_in_t; -- to wb_decoder |
signal wb_master_out_s : wishbone_master_out_t; -- from wb_decoder |
signal wb_master_in_s : wishbone_master_in_t; -- to wb_decoder |
|
constant number_of_wb_slaves_c : integer := 2; |
signal s_wb_slaves_in : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0); |
signal s_wb_slaves_out : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0); |
signal wb_slaves_in_s : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0); |
signal wb_slaves_out_s : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0); |
|
signal s_wb_clock : std_logic := '0'; |
signal s_wb_clock_locked : std_logic := '0'; |
signal s_wb_reset_p1 : std_logic := '1'; |
signal s_wb_reset_p2 : std_logic := '1'; |
signal s_wb_reset : std_logic := '1'; |
signal wb_clock_s : std_logic := '0'; |
signal wb_clock_locked_s : std_logic := '0'; |
signal wb_reset_p1_s : std_logic := '1'; |
signal wb_reset_p2_s : std_logic := '1'; |
signal wb_reset_s : std_logic := '1'; |
|
constant number_of_stimulus_signals_c : integer := 8; |
constant number_of_verify_signals_c : integer := 8; |
signal s_stimulus : std_logic_vector(number_of_stimulus_signals_c-1 downto 0); |
signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
signal stimulus_s : std_logic_vector(number_of_stimulus_signals_c-1 downto 0); |
signal verify_s : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
----------------------------------------------------------------------------- |
begin |
----------------------------------------------------------------------------- |
105,59 → 105,59
--clocks--------------------------------------------------------------------- |
wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard |
begin |
s_wb_clock <= '0'; |
wait for g_wb_clock_period/2; |
s_wb_clock <= '1'; |
wait for g_wb_clock_period/2; |
s_wb_clock_locked <= '1'; |
wb_clock_s <= '0'; |
wait for wb_clock_period_g/2; |
wb_clock_s <= '1'; |
wait for wb_clock_period_g/2; |
wb_clock_locked_s <= '1'; |
end process; |
----------------------------------------------------------------------------- |
synchronize_reset_proc : process(all) |
begin |
if (s_wb_clock_locked = '0') then |
s_wb_reset_p1 <= '1'; |
s_wb_reset_p2 <= '1'; |
elsif (rising_edge(s_wb_clock)) then |
s_wb_reset_p1 <= '0'; -- or s_tc_reset; |
s_wb_reset_p2 <= s_wb_reset_p1; |
if (wb_clock_locked_s = '0') then |
wb_reset_p1_s <= '1'; |
wb_reset_p2_s <= '1'; |
elsif (rising_edge(wb_clock_s)) then |
wb_reset_p1_s <= '0'; -- or tc_reset_s; |
wb_reset_p2_s <= wb_reset_p1_s; |
end if; |
end process; |
s_wb_reset <= s_wb_reset_p2; |
wb_reset_s <= wb_reset_p2_s; |
----------------------------------------------------------------------------- |
-- instance of test case "player"; runs tc_xxxx modules |
tc_top_inst : entity work.tc_top |
port map ( |
wb_o => s_wb_bfm_out, |
wb_i => s_wb_bfm_in |
wb_o => wb_bfm_out_s, |
wb_i => wb_bfm_in_s |
); |
----------------------------------------------------------------------------- |
-- splits the test case wb bus for all stimulation and verifier modules. |
-- decodes the given bits (g_decoded_address_msb:g_decoded_address_lsb) and# |
-- compares them to 0..n, with n=(g_number_of_ports-1) |
-- decodes the given bits (decoded_address_msb_g:decoded_address_lsb_g) and# |
-- compares them to 0..n, with n=(number_of_ports_g-1) |
proc_readdata_decoder : process (all) |
begin |
s_wb_bfm_in.dat <= (others => 'U'); |
s_wb_bfm_in.ack <= '1'; |
s_wb_bfm_in.clk <= s_wb_clock; |
s_wb_bfm_in.int <= '0'; |
s_wb_bfm_in.rst <= s_wb_reset; |
wb_bfm_in_s.dat <= (others => 'U'); |
wb_bfm_in_s.ack <= '1'; |
wb_bfm_in_s.clk <= wb_clock_s; |
wb_bfm_in_s.int <= '0'; |
wb_bfm_in_s.rst <= wb_reset_s; |
for I in number_of_wb_slaves_c-1 downto 0 loop |
s_wb_slaves_in(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values |
s_wb_slaves_in(I).clk <= s_wb_clock; |
s_wb_slaves_in(I).rst <= s_wb_reset OR s_wb_bfm_out.rst; |
if ( s_wb_bfm_out.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding |
s_wb_bfm_in.dat <= s_wb_slaves_out(I).dat; |
s_wb_bfm_in.ack <= s_wb_slaves_out(I).ack; |
s_wb_slaves_in(I).dat <= s_wb_bfm_out.dat; |
s_wb_slaves_in(I).tgd <= s_wb_bfm_out.tgd; |
s_wb_slaves_in(I).adr <= s_wb_bfm_out.adr; |
s_wb_slaves_in(I).cyc <= s_wb_bfm_out.cyc; |
s_wb_slaves_in(I).lock <= s_wb_bfm_out.lock; |
s_wb_slaves_in(I).sel <= s_wb_bfm_out.sel; |
s_wb_slaves_in(I).stb <= s_wb_bfm_out.stb; |
s_wb_slaves_in(I).tga <= s_wb_bfm_out.tga; |
s_wb_slaves_in(I).tgc <= s_wb_bfm_out.tgc; |
s_wb_slaves_in(I).we <= s_wb_bfm_out.we; |
wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values |
wb_slaves_in_s(I).clk <= wb_clock_s; |
wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst; |
if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding |
wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat; |
wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack; |
wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat; |
wb_slaves_in_s(I).tgd <= wb_bfm_out_s.tgd; |
wb_slaves_in_s(I).adr <= wb_bfm_out_s.adr; |
wb_slaves_in_s(I).cyc <= wb_bfm_out_s.cyc; |
wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock; |
wb_slaves_in_s(I).sel <= wb_bfm_out_s.sel; |
wb_slaves_in_s(I).stb <= wb_bfm_out_s.stb; |
wb_slaves_in_s(I).tga <= wb_bfm_out_s.tga; |
wb_slaves_in_s(I).tgc <= wb_bfm_out_s.tgc; |
wb_slaves_in_s(I).we <= wb_bfm_out_s.we; |
end if; |
end loop; |
end process; |
165,36 → 165,36
-- instance of design under test |
core_top_inst : entity work.core_top |
generic map( |
g_number_of_in_signals => number_of_stimulus_signals_c, |
g_number_of_out_signals => number_of_verify_signals_c |
number_of_in_signals_g => number_of_stimulus_signals_c, |
number_of_out_signals_g => number_of_verify_signals_c |
) |
port map( |
clock_i => s_wb_clock, |
reset_i => s_wb_reset, |
signals_i => s_stimulus, |
signals_o => s_verify |
clock_i => wb_clock_s, |
reset_i => wb_reset_s, |
signals_i => stimulus_s, |
signals_o => verify_s |
); |
----------------------------------------------------------------------------- |
-- instance of stimulator |
stimulator_inst : entity work.stimulator |
generic map( |
g_number_of_signals => number_of_stimulus_signals_c |
number_of_signals_g => number_of_stimulus_signals_c |
) |
port map( |
wb_i => s_wb_slaves_in(0), |
wb_o => s_wb_slaves_out(0), |
signals_o => s_stimulus |
wb_i => wb_slaves_in_s(0), |
wb_o => wb_slaves_out_s(0), |
signals_o => stimulus_s |
); |
----------------------------------------------------------------------------- |
-- instance of stimulator |
verifier_inst : entity work.verifier |
generic map( |
g_number_of_signals => number_of_verify_signals_c |
number_of_signals_g => number_of_verify_signals_c |
) |
port map( |
wb_i => s_wb_slaves_in(1), |
wb_o => s_wb_slaves_out(1), |
signals_i => s_verify |
wb_i => wb_slaves_in_s(1), |
wb_o => wb_slaves_out_s(1), |
signals_i => verify_s |
); |
----------------------------------------------------------------------------- |
end rtl; |
/bench/vhdl/verifier.vhd
65,13 → 65,13
-- entity ------------------------------------------------------------ |
entity verifier is |
generic( |
g_number_of_signals : natural := 1 |
number_of_signals_g : natural := 1 |
); |
port( |
wb_i : in wishbone_slave_in_t; |
wb_o : out wishbone_slave_out_t; |
|
signals_i : in std_logic_vector(g_number_of_signals-1 downto 0) |
signals_i : in std_logic_vector(number_of_signals_g-1 downto 0) |
); |
end verifier; |
|
80,8 → 80,8
------------------------------------------------------------------------------ |
-- signal declaration |
------------------------------------------------------------------------------ |
signal s_register0 : std_logic_vector(31 downto 0); |
signal s_register1 : std_logic_vector(31 downto 0); |
signal register0_s : std_logic_vector(31 downto 0); |
signal register1_s : std_logic_vector(31 downto 0); |
------------------------------------------------------------------------------ |
begin |
------------------------------------------------------------------------------ |
96,9 → 96,9
begin |
case wb_i.adr(27 downto 0) is |
when 28X"000_0000" => |
wb_o.dat <= s_register0; |
wb_o.dat <= register0_s; |
when 28X"000_0004" => |
wb_o.dat <= s_register1; |
wb_o.dat <= register1_s; |
when 28X"000_0008" => |
wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i; |
when others => |
110,15 → 110,15
proc_avalon_write_data : process (all) |
begin |
if (wb_i.rst = '1') then |
s_register0 <= (others => '0'); |
s_register1 <= (others => '0'); |
register0_s <= (others => '0'); |
register1_s <= (others => '0'); |
elsif (rising_edge(wb_i.clk)) then |
if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then |
case wb_i.adr(27 downto 0) is |
when 28X"000_0000" => |
s_register0 <= wb_i.dat; |
register0_s <= wb_i.dat; |
when 28X"000_0004" => |
s_register1 <= wb_i.dat; |
register1_s <= wb_i.dat; |
when others => |
end case; |
end if; |
/doc/src/vhdl_wb_tb_Usage_guide.docx
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
doc/src/vhdl_wb_tb_Usage_guide.docx
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: rtl/vhdl/packages/my_project_pkg.vhd
===================================================================
--- rtl/vhdl/packages/my_project_pkg.vhd (revision 4)
+++ rtl/vhdl/packages/my_project_pkg.vhd (revision 5)
@@ -67,8 +67,8 @@
subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
- --type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
- --type t_wishbone_address_granularity is (BYTE, WORD);
+ --type wishbone_interface_mode_t is (CLASSIC, PIPELINED);
+ --type wishbone_address_granularity_t is (BYTE, WORD);
constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
end my_project_pkg;
/rtl/vhdl/core_top.vhd
63,14 → 63,14
-- entity ------------------------------------------------------------ |
entity core_top is |
generic( |
g_number_of_in_signals : natural := 1; |
g_number_of_out_signals : natural := 1 |
number_of_in_signals_g : natural := 1; |
number_of_out_signals_g : natural := 1 |
); |
port( |
clock_i : in std_logic; |
reset_i : in std_logic; |
signals_i : in std_logic_vector(g_number_of_in_signals-1 downto 0); |
signals_o : out std_logic_vector(g_number_of_out_signals-1 downto 0) |
signals_i : in std_logic_vector(number_of_in_signals_g-1 downto 0); |
signals_o : out std_logic_vector(number_of_out_signals_g-1 downto 0) |
); |
end core_top; |
|
79,7 → 79,7
------------------------------------------------------------------------------ |
-- signal declaration |
------------------------------------------------------------------------------ |
signal shift_register_r : std_logic_vector (g_number_of_out_signals-1 downto 0); |
signal shift_register_r : std_logic_vector (number_of_out_signals_g-1 downto 0); |
signal old_shift_clock_r : std_logic := '0'; |
------------------------------------------------------------------------------ |
begin |
/rtl/vhdl/top.vhd
73,7 → 73,7
architecture rtl of top is |
----------------------------------------------------------------------------- |
-- constant number_of_stimulus_signals_c : integer := 8; |
-- signal s_verify : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
-- signal verify_s : std_logic_vector(number_of_verify_signals_c-1 downto 0); |
----------------------------------------------------------------------------- |
begin |
----------------------------------------------------------------------------- |
80,8 → 80,8
-- instance of design |
core_top_inst : entity work.core_top |
generic map( |
g_number_of_in_signals => 8, |
g_number_of_out_signals => 8 |
number_of_in_signals_g => 8, |
number_of_out_signals_g => 8 |
) |
port map( |
clock_i => clock_i, |
/rtl_sim/run/sim.mpf
338,31 → 338,31
Project_File_0 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/run/sim.mpf |
Project_File_P_0 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type txt ood 1 |
Project_File_1 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/verifier.vhd |
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532177254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_2 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/top.vhd |
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532177254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_3 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/core_top.vhd |
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164727 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532177254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_4 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tc_xxxx.vhd |
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164665 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164665 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_5 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_pkg.vhd |
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_6 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd |
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164891 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532177254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_7 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/wishbone_pkg.vhd |
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_8 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tc_top.vhd |
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_9 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/convert_pkg.vhd |
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_10 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/bin/init.do |
Project_File_P_10 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type tcl ood 1 |
Project_File_11 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd |
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164775 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_12 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/stimulator.vhd |
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532163339 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2008 |
Project_File_11 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/stimulator.vhd |
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532177254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_12 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd |
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164775 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_13 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/my_project_pkg.vhd |
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532165114 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532177254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008 |
Project_File_14 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/bin/s.do |
Project_File_P_14 = folder z_others last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1 |
Project_Sim_Count = 0 |
/rtl_sim/run/vsim.wlf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/rtl_sim/run/wave.do
1,14 → 1,20
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider TestBench_WbMaster |
add wave -noupdate /tb_top/tc_top_inst/wb_o |
add wave -noupdate -format Event -expand /tb_top/tc_top_inst/wb_o |
add wave -noupdate /tb_top/tc_top_inst/wb_i |
add wave -noupdate -divider WbStimulator |
add wave -noupdate /tb_top/stimulator_inst/s_register0 |
add wave -noupdate /tb_top/stimulator_inst/s_register1 |
add wave -noupdate /tb_top/stimulator_inst/wb_i |
add wave -noupdate /tb_top/stimulator_inst/wb_o |
add wave -noupdate /tb_top/stimulator_inst/signals_o |
add wave -noupdate /tb_top/stimulator_inst/register0_s |
add wave -noupdate /tb_top/stimulator_inst/register1_s |
add wave -noupdate -divider WbVerifier |
add wave -noupdate /tb_top/verifier_inst/s_register0 |
add wave -noupdate /tb_top/verifier_inst/s_register1 |
add wave -noupdate /tb_top/verifier_inst/wb_i |
add wave -noupdate /tb_top/verifier_inst/wb_o |
add wave -noupdate /tb_top/verifier_inst/signals_i |
add wave -noupdate /tb_top/verifier_inst/register0_s |
add wave -noupdate /tb_top/verifier_inst/register1_s |
add wave -noupdate -divider Core_top |
add wave -noupdate /tb_top/core_top_inst/clock_i |
add wave -noupdate /tb_top/core_top_inst/reset_i |
33,5 → 39,5
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {7958914428 fs} {7970583452 fs} |
WaveRestoreZoom {0 fs} {1142240758 fs} |
bookmark add wave A {{187592960 fs} {1276319150 fs}} 0 |