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URL https://opencores.org/ocsvn/vhld_tb/vhld_tb/trunk

Subversion Repositories vhld_tb

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  • This comparison shows the changes necessary to convert path 
    /vhld_tb/trunk/examples
    from Rev 19 to Rev 23
    ↔ Reverse comparison
  •

Rev 19 → Rev 23

/packet_gen/build_tb.bat
7,7 → 7,7
vcom -work synthworks -2008 C:\work\vhdl2008c\RandomPkg_2_0\RandomBasePkg.vhd
vcom -work synthworks -2008 C:\work\vhdl2008c\RandomPkg_2_0\RandomPkg.vhd
 
vcom vhdl/tb_pkg_header.vhd vhdl/tb_pkg_body.vhd
vcom ../../source/tb_pkg_header.vhd ../../source/tb_pkg_body.vhd
 
vcom -quiet -2008 vhdl/packet_gen.vhd
 
/packet_gen/vhdl/tb_pkg_header.vhd File deleted
/packet_gen/vhdl/tb_pkg_body.vhd File deleted
/tb_code_snips.vhd
18,9 → 18,22
-- Section 2: Code from CPU emulation: some starter commands
-- Section 3: Code for internal test bench implementation
-- Section 4: Code for Verify commands
--
--
------------------------------------------------------------------------------
-- Redistribution and use in source and binary forms, with or without
-- modification, in whole or part, are permitted:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--###################################################################################
77,7 → 90,7
process(clk, dut_irq)
begin
-- on the falling edge, assume rising edge assertion, one clock wide
if(clk'event and clk = '0') then
if(clk'event and clk = '0') then
if(dut_irq = '1') then
if(irq_expect = true) then
assert (false)
170,7 → 183,7
v_regs(par2) := STM_DAT;
STM_RWN <= '1';
wait for 1 ps;
 
--------------------------------------------------------------------------
-- REG_TO_VAR
-- Write a register array value to a Variable.
191,7 → 204,7
-- par2 reg2 index
elsif(instruction(1 to len) = "MOV") then
v_regs(par2) := v_regs(par1);
 
--------------------------------------------------------------------------
-- MOVI
-- Move value passed to destination register
199,7 → 212,7
-- par2 reg index
elsif(instruction(1 to len) = "MOVI") then
v_regs(par2) := std_logic_vector(conv_unsigned(par1, 32));
 
--------------------------------------------------------------------------
-- AND
-- AND two registers and write results to target register
278,7 → 291,7
v_temp_vec1 := v_regs(par1);
temp_int := par2 - 1;
v_regs(par1) := v_temp_vec1(31-par2 downto 0) & v_temp_vec1(31 downto 31 - temp_int);
 
--------------------------------------------------------------------------
-- SLR
-- Shift the register right rotate the lower bits into the upper bits
288,7 → 301,7
v_temp_vec1 := v_regs(par1);
temp_int := par2 - 1;
v_regs(par1) := v_temp_vec1(temp_int downto 0) & v_temp_vec1(31 downto par2);
 
--------------------------------------------------------------------------
-- CMP
-- Compare one register against another and set CCR bits, no effect on registers
303,11 → 316,11
elsif(v_regs(par1) < v_regs(par2)) then
v_reg_ccr(3) := '1';
end if;
 
if(v_regs(par1) = zeros) then
v_reg_ccr(1) := '0';
end if;
 
--------------------------------------------------------------------------
-- BE
-- Branch if equal
321,8 → 334,8
wh_ptr := 0;
--stack := (others => 0);
--stack_ptr := 0;
end if;
end if;
 
--------------------------------------------------------------------------
-- BZ
-- Branch if Zero
336,8 → 349,8
wh_ptr := 0;
--stack := (others => 0);
--stack_ptr := 0;
end if;
end if;
 
--------------------------------------------------------------------------
-- BB
-- Branch if bit in register is set/clear
360,9 → 373,9
wh_ptr := 0;
--stack := (others => 0);
--stack_ptr := 0;
end if;
end if;
-- ...
end process Read_file;
end process Read_file;
end bhv;
-- Stimulus_file commands used for testing. I used no VERIFY command
-- as I watched the functionality in single stepping through code.
440,20 → 453,20
-- call bin txt to int fuction with dummy fn and sequ idx
result := bin2integer(tmp_str, file_name, idx);
return result;
 
end to_uninteger;
 
 
 
-- Section 2: END
--###################################################################################
 
--
--
--###################################################################################
-- Section 3: Begin
-- This section presents the code needed to make an internal test bench
-- an optional compile item through the use of VHDL generics and generate
-- statements.
-- statements.
 
-- this is the top enity or at the level where you can assign the
-- en_bfm generic and it makes sense
534,8 → 547,8
define_instruction(inst_list, "VERIFY_BIT", 2);
define_instruction(inst_list, "VERIFY_SLICE", 1);
-- ...
 
 
-----------------------------------------------------------------------------
-- SLICE_SET set the slice of the data for testing
-- par1 upper bound value - must be larger than par2 and less than 32
557,13 → 570,13
-- update variables
v_upb := par1;
v_lob := par2;
 
-----------------------------------------------------------------------------
-- VERIFY test that the data in temp_read is the passed value.
-- par1 value to test against.
elsif (instruction(1 to len) = "VERIFY") then
v_temp_vec1 := std_logic_vector(conv_unsigned(par1, 32));
 
assert (v_temp_vec1 = v_temp_read)
report LF & "ERROR: VERIFY command compare value was not as expected!!" &
LF & "Got " & (to_hstring(v_temp_read)) &
570,7 → 583,7
LF & "Expected " & (to_hstring(v_temp_vec1)) & LF &
"Found on line " & (integer'image(file_line)) & " in file " & file_name
severity failure;
 
-----------------------------------------------------------------------------
-- VERIFY_BIT test that the data bit in temp_read is the passed value.
-- par1 index into 32 bit temp_read
590,7 → 603,7
"We tested for " & (integer'image(par2)) & LF &
"Found on line " & (integer'image(file_line)) & " in file " & file_name
severity failure;
 
-----------------------------------------------------------------------------
-- VERIFY_SLICE test that the data in temp_read is the passed value.
-- par1 value
605,6 → 618,6
LF & "Expected " & (to_hstring(v_temp_vec1(v_upb downto v_lob))) & LF &
"Found on line " & (integer'image(file_line)) & " in file " & file_name
severity failure;
 
-- END Section 4
--#######################################################################################

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