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/video_systems/tags/initial/common/color_space converters
- from Rev 24 to Rev 25
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Rev 24 → Rev 25
/rgb2ycrcb/bench/verilog/testbench.v
0,0 → 1,191
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Testbench for Color Space converters //// |
//// //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
//// www.asics.ws //// |
//// //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
// CVS Log |
// |
// $Id: testbench.v,v 1.1.1.1 2002-03-26 07:25:03 rherveille Exp $ |
// |
// $Date: 2002-03-26 07:25:03 $ |
// $Revision: 1.1.1.1 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
|
|
`timescale 1ns/10ps |
|
module testbench(); |
|
parameter emargin = 1; // we allow a small error |
parameter debug = 0; |
parameter r_runlength = 1023; |
parameter g_runlength = 1023; |
parameter b_runlength = 1023; |
|
// variables |
reg clk; |
reg ena; |
|
reg [9:0] r [7:0]; |
reg [9:0] g [7:0]; |
reg [9:0] b [7:0]; |
|
wire [9:0] y, cr, cb; |
|
integer my, mcr, mcb; |
integer iy, icr, icb; |
|
|
// |
// module body |
// |
|
// hookup modules |
rgb2ycrcb dut ( |
.clk(clk), |
.ena(ena), |
.r(r[0]), |
.g(g[0]), |
.b(b[0]), |
.y(y), |
.cr(cr), |
.cb(cb) |
); |
|
always #5 clk <= ~clk; |
|
initial |
begin |
clk = 0; |
ena = 1; |
|
r[0] = 0; |
g[0] = 0; |
b[0] = 0; |
|
$display ("\n *** Color Space Converter testbench started ***\n"); |
end |
|
always |
while ( (r[0] <= r_runlength) && (g[0] <= g_runlength) && (b[0] <= b_runlength)) |
begin |
@(posedge clk); |
|
b[0] <= #1 b[0] +1; |
if (b[0] == b_runlength) |
begin |
b[0] <= #1 0; |
|
g[0] <= #1 g[0] +1; |
if (g[0] == g_runlength) |
begin |
g[0] <= #1 0; |
|
r[0] <= #1 r[0] +1; |
end |
end |
|
if (debug) |
$display("r[0] = %d, g[0] = %d, b[0] = %d", r[0], g[0], b[0]); |
|
if ( (r[0]==r_runlength) && (g[0]==g_runlength) && (b[0]==b_runlength) ) |
begin |
$display ("\n *** Color Space Converter testbench ended ***\n"); |
$stop; |
end |
end |
|
|
integer n; |
always@(posedge clk) |
begin |
for (n = 0; n < 7; n = n +1) |
begin |
r[n +1] <= #1 r[n]; |
g[n +1] <= #1 g[n]; |
b[n +1] <= #1 b[n]; |
end |
end |
|
always@(r[3] or g[3] or b[3]) |
begin |
my = (299 * r[3]) + (587 * g[3]) + (114 * b[3]); |
if (my < 0) |
my = 0; |
|
my = my /1000; |
if (my > 1024) |
my = 1024; |
|
mcr = (500 * r[3]) - (419 * g[3]) - ( 81 * b[3]); |
if (mcr < 0) |
mcr = 0; |
|
mcr = mcr /1000; |
if (mcr > 1024) |
mcr = 1024; |
|
mcb = (500 * b[3]) - (169 * r[3]) - (332 * g[3]); |
if (mcb < 0) |
mcb = 0; |
|
mcb = mcb /1000; |
if (mcb > 1024) |
mcb = 1024; |
end |
|
always@(posedge clk) |
begin |
|
// check results |
iy = y; |
if ( ( iy < my - emargin) || (iy > my + emargin) ) |
$display("Y-value error. Received %d, expected %d. R = %d, G = %d, B = %d", y, my, r[3], g[3], b[3]); |
|
icr = cr; |
if ( ( icr < mcr - emargin) || (icr > mcr + emargin) ) |
$display("Cr-value error. Received %d, expected %d. R = %d, G = %d, B = %d", cr, mcr, r[3], g[3], b[3]); |
|
icb = cb; |
if ( ( icb < mcb - emargin) || (icb > mcb + emargin) ) |
$display("Cb-value error. Received %d, expected %d. R = %d, G = %d, B = %d", cb, mcb, r[3], g[3], b[3]); |
end |
|
endmodule |
|
/rgb2ycrcb/rtl/verilog/rgb2ycrcb.v
0,0 → 1,155
///////////////////////////////////////////////////////////////////// |
//// //// |
//// RGB to YCrCb Color Space converter //// |
//// //// |
//// Converts RGB values to YCrCB (YUV) values //// |
//// Y = 0.299R + 0.587G + 0.114B //// |
//// Cr = 0.713(R - Y) //// |
//// Cb = 0.565(B - Y) //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
//// www.asics.ws //// |
//// //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
// CVS Log |
// |
// $Id: rgb2ycrcb.v,v 1.1.1.1 2002-03-26 07:25:01 rherveille Exp $ |
// |
// $Date: 2002-03-26 07:25:01 $ |
// $Revision: 1.1.1.1 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
|
|
`timescale 1ns/10ps |
|
module rgb2ycrcb(clk, ena, r, g, b, y, cr, cb); |
// |
// inputs & outputs |
// |
input clk; |
input ena; |
input [9:0] r, g, b; |
|
output [9:0] y, cr, cb; |
reg [9:0] y, cr, cb; |
|
|
// |
// variables |
// |
reg [21:0] y1, cr1, cb1; |
|
// |
// module body |
// |
|
|
// step 1: Calculate Y, Cr, Cb |
// |
// Use N.M format for multiplication: |
// Y = 0.299 * R.000 + 0.587 * G.000 + 0.114 * B.000 |
// Y = 0x132 * R + 0x259 * G + 0x074 * B |
// |
// Cr = 0.713(R - Y) |
// Cr = 0.500 * R.000 + -0.419 * G.000 - 0.0813 * B.000 |
// Cr = (R >> 1) - 0x1AD * G - 0x053 * B |
// |
// Cb = 0.565(B - Y) |
// Cb = -0.169 * R.000 + -0.332 * G.000 + 0.500 * B.000 |
// Cb = (B >> 1) - 0x0AD * R - 0x153 * G |
|
|
// calculate Y |
reg [19:0] yr, yg, yb; |
|
always@(posedge clk) |
if (ena) |
begin |
yr <= #1 10'h132 * r; |
yg <= #1 10'h259 * g; |
yb <= #1 10'h074 * b; |
|
y1 <= #1 yr + yg + yb; |
end |
|
// calculate Cr |
reg [19:0] crr, crg, crb; |
|
always@(posedge clk) |
if (ena) |
begin |
crr <= #1 r << 9; |
crg <= #1 10'h1ad * g; |
crb <= #1 10'h053 * b; |
|
cr1 <= #1 crr - crg - crb; |
end |
|
// calculate Cb |
reg [19:0] cbr, cbg, cbb; |
|
always@(posedge clk) |
if (ena) |
begin |
cbr <= #1 10'h0ad * r; |
cbg <= #1 10'h153 * g; |
cbb <= #1 b << 9; |
|
cb1 <= #1 cbb - cbr - cbg; |
end |
|
// |
// step2: check boundaries |
// |
always@(posedge clk) |
if (ena) |
begin |
// check Y |
y <= #1 (y1[19:10] & {10{!y1[21]}}) | {10{(!y1[21] && y1[20])}}; |
|
// check Cr |
cr <= #1 (cr1[19:10] & {10{!cr1[21]}}) | {10{(!cr1[21] && cr1[20])}}; |
|
// check Cb |
cb <= #1 (cb1[19:10] & {10{!cb1[21]}}) | {10{(!cb1[21] && cb1[20])}}; |
end |
endmodule |
|
|
|
|
|
|
|
/ycrcb2rgb/bench/verilog/testbench.v
0,0 → 1,183
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Testbench for Color Space converters //// |
//// //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
//// www.asics.ws //// |
//// //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
// CVS Log |
// |
// $Id: testbench.v,v 1.1.1.1 2002-03-26 07:25:07 rherveille Exp $ |
// |
// $Date: 2002-03-26 07:25:07 $ |
// $Revision: 1.1.1.1 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
|
|
`timescale 1ns/10ps |
|
module testbench(); |
|
parameter emargin = 1; // we allow a small (rounding) error |
parameter debug = 0; |
parameter y_runlength = 1023; |
parameter cr_runlength = 1023; |
parameter cb_runlength = 1023; |
|
// variables |
reg clk; |
reg ena; |
|
reg [9:0] y [3:0]; |
reg [9:0] cr [3:0]; |
reg [9:0] cb [3:0]; |
|
wire [9:0] r, g, b; |
|
integer yc, crc, cbc; |
|
integer mr, mg, mb; |
integer ir, ig, ib; |
|
// |
// module body |
// |
|
// hookup modules |
ycrcb2rgb dut ( |
.clk(clk), |
.ena(ena), |
.y(y[0]), |
.cr(cr[0]), |
.cb(cb[0]), |
.r(r), |
.g(g), |
.b(b) |
); |
|
always #5 clk <= ~clk; |
|
initial |
begin |
clk = 0; |
ena = 1; |
|
y[0] = 0; |
cr[0] = 0; |
cb[0] = 0; |
|
$display ("\n *** Color Space Converter testbench started ***\n"); |
|
for (cbc = 0; cbc <= cb_runlength; cbc = cbc +1) |
for (crc = 0; crc <= cr_runlength; crc = crc +1) |
for (yc = 0; yc <= y_runlength; yc = yc +1) |
begin |
@(posedge clk); |
#1; |
|
y[0] = yc; |
cr[0] = crc; |
cb[0] = cbc; |
|
if (debug) |
$display("y[0] = %d, cr[0] = %d, cb[0] = %d", y[0], cr[0], cb[0]); |
end |
|
$display ("\n *** Color Space Converter testbench ended ***\n"); |
$stop; |
end |
|
|
integer n; |
always@(posedge clk) |
begin |
for (n = 0; n < 3; n = n +1) |
begin |
y[n +1] <= #1 y[n]; |
cr[n +1] <= #1 cr[n]; |
cb[n +1] <= #1 cb[n]; |
end |
end |
|
always@(y[3] or cr[3] or cb[3]) |
begin |
mr = (y[3] * 1000) + (1403 * cr[3]); |
if (mr < 0) |
mr = 0; |
|
mr = mr /1000; |
if (mr > 1023) |
mr = 1023; |
|
mg = (y[3] * 1000) - ( (344 * cb[3]) + (714 * cr[3]) ); |
if (mg < 0) |
mg = 0; |
|
mg = mg /1000; |
if (mg > 1023) |
mg = 1023; |
|
mb = (y[3] * 1000) + (1770 * cb[3]); |
if (mb < 0) |
mb = 0; |
|
mb = mb /1000; |
if (mb > 1023) |
mb = 1023; |
end |
|
always@(posedge clk) |
begin |
// check RGB results |
ir = r; |
if ( ( ir < mr - emargin) || (ir > mr + emargin) ) |
$display("R-value error. Received %d, expected %d. Y = %d, Cr = %d, Cb = %d", ir, mr, y[3], cr[3], cb[3]); |
|
ig = g; |
if ( ( ig < mg - emargin) || (ig > mg + emargin) ) |
$display("G-value error. Received %d, expected %d. Y = %d, Cr = %d, Cb = %d", ig, mg, y[3], cr[3], cb[3]); |
|
ib = b; |
if ( ( ib < mb - emargin) || (ib > mb + emargin) ) |
$display("B-value error. Received %d, expected %d. Y = %d, Cr = %d, Cb = %d", ib, mb, y[3], cr[3], cb[3]); |
end |
|
endmodule |
|
|
|
|
/ycrcb2rgb/rtl/verilog/ycrcb2rgb.v
0,0 → 1,156
///////////////////////////////////////////////////////////////////// |
//// //// |
//// YCrCb to RGB Color Space converter //// |
//// //// |
//// Converts YCrCb (YUV) values to RGB values //// |
//// R = Y + 1.403Cr //// |
//// G = Y - 0.344Cb - 0.714Cr //// |
//// B = Y + 1.770Cb //// |
//// //// |
//// Author: Richard Herveille //// |
//// richard@asics.ws //// |
//// www.asics.ws //// |
//// //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001 Richard Herveille //// |
//// richard@asics.ws //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// |
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// |
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// |
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// |
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// |
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// |
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// |
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// |
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// |
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// |
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// |
//// POSSIBILITY OF SUCH DAMAGE. //// |
//// //// |
///////////////////////////////////////////////////////////////////// |
|
// CVS Log |
// |
// $Id: ycrcb2rgb.v,v 1.1.1.1 2002-03-26 07:25:09 rherveille Exp $ |
// |
// $Date: 2002-03-26 07:25:09 $ |
// $Revision: 1.1.1.1 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
|
|
`timescale 1ns/10ps |
|
module ycrcb2rgb(clk, ena, y, cr, cb, r, g, b); |
// |
// inputs & outputs |
// |
input clk; |
input ena; |
input [9:0] y, cr, cb; |
|
output [9:0] r, g, b; |
reg [9:0] r, g, b; |
|
|
reg [9:0] dy, dcr, dcb; |
|
// |
// variables |
// |
reg [22:0] ir, ig, ib; |
|
// |
// module body |
// |
|
|
// step 1: Calculate R, G, B |
// |
// Use N.M format for multiplication: |
// R = Y + 1.403Cr = Y + Cr + 0.403Cr |
// R = Y + Cr + 0x19C*Cr |
// |
// G = Y - 0.344Cb - 0.714Cr |
// G = Y - 0x160*Cb - 0x2DB*Cr |
// |
// B = Y + 1.770Cb = Y + Cb + 0.770Cb |
// B = Y + Cb + 0x314*Cb |
|
|
// delay y, cr and cb |
always@(posedge clk) |
if (ena) |
begin |
dy <= #1 y; |
dcr <= #1 cr; |
dcb <= #1 cb; |
end |
|
// calculate R |
reg [19:0] rm; |
|
always@(posedge clk) |
if (ena) |
begin |
rm <= #1 10'h19C * cr; |
|
ir <= #1 ( (dy + dcr) << 10) + rm; |
end |
|
// calculate G |
reg [19:0] gm1, gm2; |
|
always@(posedge clk) |
if (ena) |
begin |
gm1 <= #1 10'h160 * cb; |
gm2 <= #1 10'h2DB * cr; |
|
ig <= #1 (dy << 10) - (gm1 + gm2); |
end |
|
// calculate B |
reg [19:0] bm; |
|
always@(posedge clk) |
if (ena) |
begin |
bm <= #1 10'h314 * cb; |
|
ib <= #1 ( (dy + dcb) << 10) + bm; |
end |
|
// |
// step2: check boundaries |
// |
always@(posedge clk) |
if (ena) |
begin |
// check R |
r <= #1 (ir[19:10] & {10{!ir[22]}}) | {10{(!ir[22] && (ir[21] || ir[20]))}}; |
|
// check G |
g <= #1 (ig[19:10] & {10{!ig[22]}}) | {10{(!ig[22] && (ig[21] || ig[20]))}}; |
|
// check B |
b <= #1 (ib[19:10] & {10{!ib[22]}}) | {10{(!ib[22] && (ib[21] || ib[20]))}}; |
end |
endmodule |
|
|
|
|