OpenCores
URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /virtex7_pcie_dma/trunk
    from Rev 11 to Rev 12
    ↔ Reverse comparison
  •

Rev 11 → Rev 12

/firmware/sources/pcie/cache_fifo.xci File deleted
/firmware/sources/pcie/dma_write_cache.vhd File deleted
/firmware/sources/pcie/intr_ctrl.vhd
70,7 → 70,11
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
interrupt_table_en : in std_logic;
interrupt_vector : in interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
reset : in std_logic);
reset : in std_logic;
s_axis_cc : in axis_type;
s_axis_cq : in axis_type;
s_axis_rc : in axis_type;
s_axis_rq : in axis_type);
end entity intr_ctrl;
 
 
92,6 → 96,8
attribute dont_touch : string;
attribute dont_touch of monitor_cfg_interrupt_msix_data : signal is "true";
attribute dont_touch of monitor_cfg_interrupt_msix_address : signal is "true";
signal axi_busy : std_logic;
 
begin
 
149,22 → 155,30
end if; --reset
end process;
 
--cfg_interrupt_msix_int <= s_cfg_interrupt_msix_int;
cfg_interrupt_msix_data <= s_cfg_interrupt_msix_data;
cfg_interrupt_msix_address <= s_cfg_interrupt_msix_address;
axi_busy <= (s_axis_cc.tvalid or s_axis_cq.tvalid) or (s_axis_rc.tvalid or s_axis_rq.tvalid);
regSync250: process(clk)
variable cfg_interrupt_msix_int_v : std_logic;
variable axi_busy_p1 : std_logic;
variable request_int: std_logic;
begin
if(rising_edge(clk)) then
--cfg_interrupt_msix_data <= s_cfg_interrupt_msix_data;
--cfg_interrupt_msix_address <= s_cfg_interrupt_msix_address;
if(cfg_interrupt_msix_int_v = '0' and s_cfg_interrupt_msix_int = '1') then --detect rising edge
if(request_int = '1' and (axi_busy = '0' and axi_busy_p1 = '0')) then --two axi idle clockcycles, don't send in between two DMA TLP's
request_int := '0';
cfg_interrupt_msix_int <= '1';
else
request_int := request_int;
cfg_interrupt_msix_int <= '0';
end if;
if(cfg_interrupt_msix_int_v = '0' and s_cfg_interrupt_msix_int = '1') then --detect rising edge
request_int := '1';
end if;
cfg_interrupt_msix_int_v := s_cfg_interrupt_msix_int; -- pipeline
axi_busy_p1 := axi_busy;
end if;
end process;
/firmware/sources/pcie/dma_control.vhd
88,23 → 88,19
 
 
architecture rtl of dma_control is
type completer_state_type is(IDLE, READ_REGISTER, WRITE_REGISTER_READ, WRITE_REGISTER_MODIFYWRITE, SEND_UNKNOWN_REQUEST, SEND_COMPLETER_ABORT, WAIT_FOR_TLAST);
 
type completer_state_type is(IDLE, READ_REGISTER, WRITE_REGISTER_READ, WRITE_REGISTER_MODIFYWRITE, SEND_UNKNOWN_REQUEST);
signal completer_state: completer_state_type := IDLE;
signal completer_state_slv: std_logic_vector(3 downto 0);
signal completer_state_slv: std_logic_vector(2 downto 0);
attribute dont_touch : string;
attribute dont_touch of completer_state_slv : signal is "true";
constant IDLE_SLV : std_logic_vector(3 downto 0) := "0000";
constant READ_REGISTER_SLV : std_logic_vector(3 downto 0) := "0001";
constant WRITE_REGISTER_READ_SLV : std_logic_vector(3 downto 0) := "0011";
constant WRITE_REGISTER_MODIFYWRITE_SLV : std_logic_vector(3 downto 0) := "0100";
constant SEND_UNKNOWN_REQUEST_SLV : std_logic_vector(3 downto 0) := "0111";
constant SEND_COMPLETER_ABORT_SLV : std_logic_vector(3 downto 0) := "1000";
constant WAIT_FOR_TLAST_SLV : std_logic_vector(3 downto 0) := "1001";
constant IDLE_SLV : std_logic_vector(2 downto 0) := "000";
constant READ_REGISTER_SLV : std_logic_vector(2 downto 0) := "001";
constant WRITE_REGISTER_READ_SLV : std_logic_vector(2 downto 0) := "011";
constant WRITE_REGISTER_MODIFYWRITE_SLV : std_logic_vector(2 downto 0) := "100";
constant SEND_UNKNOWN_REQUEST_SLV : std_logic_vector(2 downto 0) := "111";
signal dma_descriptors_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_descriptors_40_r_s : dma_descriptors_type(0 to 7);
signal dma_descriptors_40_w_s : dma_descriptors_type(0 to 7);
130,7 → 126,7
signal bar0_valid : std_logic;
signal transaction_class_s : std_logic_vector(2 downto 0);
signal attributes_s : std_logic_vector(2 downto 0);
signal seen_tlast_s : std_logic;
--signal seen_tlast_s : std_logic;
signal register_data_s : std_logic_vector(127 downto 0);
signal register_data_r : std_logic_vector(127 downto 0); --temporary register for read/modify/write
signal register_map_monitor_s : register_map_monitor_type;
297,7 → 293,7
else
if(rising_edge(clk)) then
--defaults:
seen_tlast_s <= seen_tlast_s;
--seen_tlast_s <= seen_tlast_s;
address_type_s <= address_type_s;
register_address_s <= register_address_s;
dword_count_s <= dword_count_s;
404,7 → 400,6
end if;
end loop;
case (completer_state) is
when IDLE =>
completer_state_slv <= IDLE_SLV;
423,7 → 418,6
transaction_class_s <= s_axis_cq.tdata(123 downto 121);
attributes_s <= s_axis_cq.tdata(126 downto 124);
register_data_s <= s_axis_cq.tdata(255 downto 128);
seen_tlast_s <= s_axis_cq.tlast;
if(s_axis_cq.tdata(31 downto 20) = (bar0(31 downto 20))) then
bar0_valid <= '1';
else
462,7 → 456,6
when others => m_axis_cc.tkeep <= x"FF";
end case;
seen_tlast_s <= s_axis_cq.tlast or seen_tlast_s;
--wait for reply from 40 MHz sync:
if(register_read_done_250_s = '1') then
474,12 → 467,7
s_axis_r_cq.tready <= '0';
completer_state <= READ_REGISTER;
else
if(seen_tlast_s = '1') then
completer_state <= IDLE;
else
s_axis_r_cq.tready <= '0';
completer_state <= SEND_COMPLETER_ABORT;
end if;
completer_state <= IDLE;
end if;
else
register_read_enable_250_s <= '1';
518,12 → 506,7
else
m_axis_cc.tlast <= '1';
m_axis_cc.tvalid <= '1';
if(seen_tlast_s = '1') then
completer_state <= IDLE;
else
completer_state <= SEND_COMPLETER_ABORT;
s_axis_r_cq.tready <= '0';
end if;
completer_state <= IDLE;
end if;
--wait for reply from 40 MHz sync:
elsif(register_read_done_250_s = '1') then
541,7 → 524,6
completion_status_v := "000";
locked_completion_v := '0';
m_axis_cc.tkeep <= x"07";
seen_tlast_s <= s_axis_cq.tlast or seen_tlast_s;
m_axis_cc.tdata(255 downto 96) <= (others => '0');
when WRITE_REGISTER_MODIFYWRITE =>
585,12 → 567,7
else
m_axis_cc.tlast <= '1';
m_axis_cc.tvalid <= '1';
if(seen_tlast_s = '1') then
completer_state <= IDLE;
else
completer_state <= SEND_COMPLETER_ABORT;
s_axis_r_cq.tready <= '0';
end if;
completer_state <= IDLE;
end if;
else
m_axis_cc.tlast <= '0';
605,7 → 582,6
completion_status_v := "000";
locked_completion_v := '0';
m_axis_cc.tkeep <= x"07";
seen_tlast_s <= s_axis_cq.tlast or seen_tlast_s;
m_axis_cc.tdata(255 downto 96) <= (others => '0');
when SEND_UNKNOWN_REQUEST =>
completer_state_slv <= SEND_UNKNOWN_REQUEST_SLV;
615,7 → 591,6
completion_status_v := "001"; --unsupported request
locked_completion_v := '0';
m_axis_cc.tkeep <= x"07";
seen_tlast_s <= s_axis_cq.tlast or seen_tlast_s;
m_axis_cc.tlast <= '1';
m_axis_cc.tvalid <= '1';
if(m_axis_r_cc.tready = '0') then
622,46 → 597,8
completer_state <= SEND_UNKNOWN_REQUEST;
s_axis_r_cq.tready <= '0';
else
if(seen_tlast_s = '1') then
completer_state <= IDLE;
else
completer_state <= SEND_COMPLETER_ABORT;
s_axis_r_cq.tready <= '0';
end if;
completer_state <= IDLE;
end if;
when SEND_COMPLETER_ABORT =>
completer_state_slv <= SEND_COMPLETER_ABORT_SLV;
poisoned_completion_v := '0';
dword_count_v := std_logic_vector(to_unsigned(1,11));
byte_count_v := dword_count_v&"00";
completion_status_v := "100"; --completer abort
locked_completion_v := '0';
m_axis_cc.tkeep <= x"07";
seen_tlast_s <= s_axis_cq.tlast or seen_tlast_s;
m_axis_cc.tlast <= '1';
m_axis_cc.tvalid <= '1';
if(m_axis_r_cc.tready = '0') then
completer_state <= SEND_COMPLETER_ABORT;
s_axis_r_cq.tready <= '0';
else
if(seen_tlast_s = '1') then
completer_state <= IDLE;
else
completer_state <= WAIT_FOR_TLAST;
s_axis_r_cq.tready <= '0';
end if;
end if;
when WAIT_FOR_TLAST =>
tlast_timer_s <= tlast_timer_s - 1;
completer_state_slv <= WAIT_FOR_TLAST_SLV;
if(s_axis_cq.tlast = '1' or tlast_timer_s=x"00") then
completer_state <= IDLE;
else
completer_state <= WAIT_FOR_TLAST;
s_axis_r_cq.tready <= '0';
end if;
when others =>
completer_state <= IDLE;
completer_state_slv <= IDLE_SLV;
671,10 → 608,10
m_axis_cc.tdata(7) <= '0';
m_axis_cc.tdata(9 downto 8) <= address_type_s;
m_axis_cc.tdata(15 downto 10) <= "000000";
m_axis_cc.tdata(28 downto 16) <= byte_count_v;
m_axis_cc.tdata(28 downto 16) <= "00000000"&byte_count_v(4 downto 0);
m_axis_cc.tdata(29) <= locked_completion_v;
m_axis_cc.tdata(31 downto 30) <= "00";
m_axis_cc.tdata(42 downto 32) <= dword_count_v;
m_axis_cc.tdata(42 downto 32) <= "00000000"&dword_count_v(2 downto 0);
m_axis_cc.tdata(45 downto 43) <= completion_status_v;
m_axis_cc.tdata(46) <= poisoned_completion_v;
m_axis_cc.tdata(47) <= '0';
/firmware/sources/pcie/pcie_init.vhd
61,6 → 61,13
bar0 : out std_logic_vector(31 downto 0);
bar1 : out std_logic_vector(31 downto 0);
bar2 : out std_logic_vector(31 downto 0);
cfg_fc_cpld : in std_logic_vector(11 downto 0);
cfg_fc_cplh : in std_logic_vector(7 downto 0);
cfg_fc_npd : in std_logic_vector(11 downto 0);
cfg_fc_nph : in std_logic_vector(7 downto 0);
cfg_fc_pd : in std_logic_vector(11 downto 0);
cfg_fc_ph : in std_logic_vector(7 downto 0);
cfg_fc_sel : out std_logic_vector(2 downto 0);
cfg_mgmt_addr : out std_logic_vector(18 downto 0);
cfg_mgmt_byte_enable : out std_logic_vector(3 downto 0);
cfg_mgmt_read : out std_logic;
76,15 → 83,74
 
architecture rtl of pcie_init is
 
signal s_cfg_fc_cpld : std_logic_vector(11 downto 0);
signal s_cfg_fc_cplh : std_logic_vector(7 downto 0);
signal s_cfg_fc_npd : std_logic_vector(11 downto 0);
signal s_cfg_fc_nph : std_logic_vector(7 downto 0);
signal s_cfg_fc_pd : std_logic_vector(11 downto 0);
signal s_cfg_fc_ph : std_logic_vector(7 downto 0);
 
attribute dont_touch : string;
--attribute dont_touch of s_cfg_fc_cpld : signal is "true";
--attribute dont_touch of s_cfg_fc_cplh : signal is "true";
--attribute dont_touch of s_cfg_fc_npd : signal is "true";
--attribute dont_touch of s_cfg_fc_nph : signal is "true";
--attribute dont_touch of s_cfg_fc_pd : signal is "true";
--attribute dont_touch of s_cfg_fc_ph : signal is "true";
 
signal bar0_s: std_logic_vector(31 downto 0);
signal bar1_s: std_logic_vector(31 downto 0);
signal bar2_s: std_logic_vector(31 downto 0);
signal write_cfg_done_1: std_logic;
signal bar_index : std_logic_vector(1 downto 0);
signal bar_index : std_logic_vector(2 downto 0);
signal uncor_err_stat: std_logic_vector(31 downto 0); --config register 104
signal cor_err_stat: std_logic_vector(31 downto 0); --config register 110
signal adv_err_cap: std_logic_vector(31 downto 0); --config register 118
attribute dont_touch of uncor_err_stat : signal is "true";
attribute dont_touch of cor_err_stat : signal is "true";
attribute dont_touch of adv_err_cap : signal is "true";
--COMPONENT vio_0
-- PORT (
-- clk : IN STD_LOGIC;
-- probe_in0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- probe_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- probe_in2 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- probe_in3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- probe_in4 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- probe_in5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe_out1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
-- );
--END COMPONENT;
begin
 
--vio_inst : vio_0
-- PORT MAP (
-- clk => clk,
-- probe_in0 => s_cfg_fc_pd,
-- probe_in1 => s_cfg_fc_ph,
-- probe_in2 => s_cfg_fc_npd,
-- probe_in3 => s_cfg_fc_nph,
-- probe_in4 => s_cfg_fc_cpld,
-- probe_in5 => s_cfg_fc_cplh,
-- probe_out0(0) => vio_rst_n,
-- probe_out1 => cfg_fc_sel
-- );
 
cfg_fc_sel <= "100";
 
s_cfg_fc_cpld <= cfg_fc_cpld ;
s_cfg_fc_cplh <= cfg_fc_cplh ;
s_cfg_fc_npd <= cfg_fc_npd ;
s_cfg_fc_nph <= cfg_fc_nph ;
s_cfg_fc_pd <= cfg_fc_pd ;
s_cfg_fc_ph <= cfg_fc_ph ;
 
cfg_write_skp_nolfsr : process(clk)
begin
if(rising_edge(clk)) then
95,7 → 161,10
bar1_s <= bar1_s;
bar2_s <= bar2_s;
uncor_err_stat <= uncor_err_stat;
cor_err_stat <= cor_err_stat;
adv_err_cap <= adv_err_cap;
if (reset = '1') then
cfg_mgmt_addr <= "000"&x"0000";
cfg_mgmt_write_data <= x"00000000";
103,29 → 172,49
cfg_mgmt_write <= '0';
cfg_mgmt_read <= '0';
write_cfg_done_1 <= '0';
bar_index <= "00";
bar_index <= "000";
elsif(write_cfg_done_1 = '1') then
case(bar_index) is
when "00" =>
when "000" =>
--Addresses in cfg_mgmt_addr are the same as addresses in PCIe configuration space, however divided by 4
cfg_mgmt_addr <= "000"&x"0004"; --read BAR0
if(cfg_mgmt_read_write_done = '1') then
bar0_s <= cfg_mgmt_read_data;
bar_index <= "01";
bar_index <= "001";
end if;
when "01" =>
when "001" =>
cfg_mgmt_addr <= "000"&x"0005"; --read BAR1
if(cfg_mgmt_read_write_done = '1') then
bar1_s <= cfg_mgmt_read_data;
bar_index <= "10";
bar_index <= "010";
end if;
when "10" =>
when "010" =>
cfg_mgmt_addr <= "000"&x"0006"; --read BAR2
if(cfg_mgmt_read_write_done = '1') then
bar2_s <= cfg_mgmt_read_data;
bar_index <= "00";
bar_index <= "011";
end if;
when "011" =>
cfg_mgmt_addr <= "000"&x"0041"; --read Uncorrectable error status register
if(cfg_mgmt_read_write_done = '1') then
uncor_err_stat <= cfg_mgmt_read_data;
bar_index <= "100";
end if;
when "100" =>
cfg_mgmt_addr <= "000"&x"0044"; --read Correctable error status register
if(cfg_mgmt_read_write_done = '1') then
cor_err_stat <= cfg_mgmt_read_data;
bar_index <= "101";
end if;
when "101" =>
cfg_mgmt_addr <= "000"&x"0046"; --read Advanced error cap and control register
if(cfg_mgmt_read_write_done = '1') then
adv_err_cap <= cfg_mgmt_read_data;
bar_index <= "000";
end if;
when others =>
bar_index <= "00";
bar_index <= "000";
end case;
cfg_mgmt_write_data <= (others => '0');
cfg_mgmt_byte_enable <= x"F";
/firmware/sources/pcie/dma_read_write.vhd
60,7 → 60,6
generic(
NUMBER_OF_DESCRIPTORS : integer := 8);
port (
cache_tready : in std_logic;
clk : in std_logic;
dma_descriptors : in dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
dma_soft_reset : in std_logic;
130,18 → 129,19
type receive_tag_status_type is array (0 to 15) of receive_tag_status_record_type;
signal receive_tag_status_s: receive_tag_status_type;
signal current_receive_tag_s: integer range 0 to 15;
signal s_m_axis_rq : axis_type;
 
begin
 
m_axis_rq <= s_m_axis_rq;
 
 
re: process(rw_state, m_axis_r_rq, dma_descriptors, active_descriptor_s, fifo_empty, current_descriptor, cache_tready)
re: process(rw_state, m_axis_r_rq, dma_descriptors, active_descriptor_s, fifo_empty, current_descriptor)
begin
fifo_re <= '0';
case(rw_state) is
when IDLE =>
if(((fifo_empty = '0') and (m_axis_r_rq.tready = '1')) and cache_tready = '1') then
if((fifo_empty = '0') and (m_axis_r_rq.tready = '1')) then
if((dma_descriptors(active_descriptor_s).enable = '1') and (dma_descriptors(active_descriptor_s).read_not_write = '0')) then
fifo_re <= '1';
end if;
189,10 → 189,10
rw_state <= IDLE;
fifo_dout_pipe <= fifo_dout(255 downto 128);
req_tag <= req_tag;
m_axis_rq.tvalid <= '0';
m_axis_rq.tdata <= (others => '0');
m_axis_rq.tkeep <= x"00";
m_axis_rq.tlast <= '0';
s_m_axis_rq.tvalid <= '0';
s_m_axis_rq.tdata <= (others => '0');
s_m_axis_rq.tkeep <= x"00";
s_m_axis_rq.tlast <= '0';
current_receive_tag_s <= current_receive_tag_s ;
active_descriptor_s <= active_descriptor_s;
receive_tags_s <= receive_tags_s;
218,11 → 218,11
current_descriptor <= dma_descriptors(active_descriptor_s);
active_descriptor_s <= next_active_descriptor_v;
if((m_axis_r_rq.tready = '1') and (dma_descriptors(active_descriptor_s).enable = '1')) then
if(((dma_descriptors(active_descriptor_s).read_not_write = '0') and (fifo_empty = '0')) and (cache_tready = '1')) then
if(((dma_descriptors(active_descriptor_s).read_not_write = '0') and (fifo_empty = '0'))) then
rw_state <= START_WRITE;
descriptor_done_s(active_descriptor_s) <= '1'; --pulse only once
end if;
if(((dma_descriptors(active_descriptor_s).read_not_write = '1') and (fifo_full = '0')) and (cache_tready = '1')) then
if(((dma_descriptors(active_descriptor_s).read_not_write = '1') and (fifo_full = '0'))) then
rw_state <= START_READ;
descriptor_done_s(active_descriptor_s) <= '1'; --pulse only once
end if;
232,7 → 232,7
if(m_axis_r_rq.tready = '1') then
current_descriptor.dword_count <= current_descriptor.dword_count - 4;
-----DW 7-4
m_axis_rq.tdata <= fifo_dout(127 downto 0) & --128 bits data
s_m_axis_rq.tdata <= fifo_dout(127 downto 0) & --128 bits data
-----DW 3
'0'& --31 - 1 bit reserved 127
req_attr & --30-28 3 bits Attr 124-126
249,71 → 249,73
--DW 1-0
current_descriptor.current_address(63 downto 2) & "00"; --62 bit word address address + 2 bit Address type (0, untranslated)
if(current_descriptor.dword_count <= 4) then
m_axis_rq.tlast <= '1';
s_m_axis_rq.tlast <= '1';
rw_state <= IDLE;
req_tag <= req_tag + 1;
current_descriptor.dword_count <= (others => '0');
case(current_descriptor.dword_count(3 downto 0)) is
when x"4" => m_axis_rq.tkeep <= x"FF";
when x"3" => m_axis_rq.tkeep <= x"7F";
when x"2" => m_axis_rq.tkeep <= x"3F";
when x"1" => m_axis_rq.tkeep <= x"1F";
when x"0" => m_axis_rq.tkeep <= x"0F";
when others => m_axis_rq.tkeep <= x"FF";
when x"4" => s_m_axis_rq.tkeep <= x"FF";
when x"3" => s_m_axis_rq.tkeep <= x"7F";
when x"2" => s_m_axis_rq.tkeep <= x"3F";
when x"1" => s_m_axis_rq.tkeep <= x"1F";
when x"0" => s_m_axis_rq.tkeep <= x"0F";
when others => s_m_axis_rq.tkeep <= x"FF";
end case;
else
m_axis_rq.tkeep <= x"FF";
s_m_axis_rq.tkeep <= x"FF";
rw_state <= CONT_WRITE;
m_axis_rq.tlast <= '0';
s_m_axis_rq.tlast <= '0';
end if;
m_axis_rq.tvalid <= '1';
s_m_axis_rq.tvalid <= '1';
else
m_axis_rq.tvalid <= '0';
s_m_axis_rq.tvalid <= '0';
current_descriptor.dword_count <= current_descriptor.dword_count;
rw_state <= START_WRITE;
end if;
when CONT_WRITE =>
rw_state_slv <= CONT_WRITE_SLV;
rw_state <= CONT_WRITE; --default
if(m_axis_r_rq.tready = '1') then
current_descriptor.dword_count <= current_descriptor.dword_count - 8;
-----DW 7-4
m_axis_rq.tdata <= fifo_dout(127 downto 0) & --128 bits data
fifo_dout_pipe; --128 bits data from last clock cycle
if(current_descriptor.dword_count <= 8) then
m_axis_rq.tlast <= '1';
s_m_axis_rq.tdata <= fifo_dout(127 downto 0) & --128 bits data
fifo_dout_pipe; --128 bits data from last clock cycle
else
fifo_dout_pipe <= fifo_dout_pipe;
s_m_axis_rq.tdata <= s_m_axis_rq.tdata;
end if;
-----DW 7-4
if(current_descriptor.dword_count <= 8) then
s_m_axis_rq.tlast <= '1';
if(m_axis_r_rq.tready = '1') then
rw_state <= IDLE;
req_tag <= req_tag + 1;
current_descriptor.dword_count <= (others => '0');
case(current_descriptor.dword_count(3 downto 0)) is
when x"8" => m_axis_rq.tkeep <= x"FF";
when x"7" => m_axis_rq.tkeep <= x"7F";
when x"6" => m_axis_rq.tkeep <= x"3F";
when x"5" => m_axis_rq.tkeep <= x"1F";
when x"4" => m_axis_rq.tkeep <= x"0F";
when x"3" => m_axis_rq.tkeep <= x"07";
when x"2" => m_axis_rq.tkeep <= x"03";
when x"1" => m_axis_rq.tkeep <= x"01";
when x"0" => m_axis_rq.tkeep <= x"00";
when others => m_axis_rq.tkeep <= x"FF";
end case;
else
rw_state <= CONT_WRITE;
m_axis_rq.tlast <= '0';
m_axis_rq.tkeep <= x"FF";
end if;
m_axis_rq.tvalid <= '1';
case(current_descriptor.dword_count(3 downto 0)) is
when x"8" => s_m_axis_rq.tkeep <= x"FF";
when x"7" => s_m_axis_rq.tkeep <= x"7F";
when x"6" => s_m_axis_rq.tkeep <= x"3F";
when x"5" => s_m_axis_rq.tkeep <= x"1F";
when x"4" => s_m_axis_rq.tkeep <= x"0F";
when x"3" => s_m_axis_rq.tkeep <= x"07";
when x"2" => s_m_axis_rq.tkeep <= x"03";
when x"1" => s_m_axis_rq.tkeep <= x"01";
when x"0" => s_m_axis_rq.tkeep <= x"00";
when others => s_m_axis_rq.tkeep <= x"FF";
end case;
else
fifo_dout_pipe <= fifo_dout_pipe;
m_axis_rq.tvalid <= '0';
current_descriptor.dword_count <= current_descriptor.dword_count;
rw_state <= CONT_WRITE;
s_m_axis_rq.tlast <= '0';
s_m_axis_rq.tkeep <= x"FF";
end if;
s_m_axis_rq.tvalid <= '1';
when START_READ =>
rw_state_slv <= START_READ_SLV;
if(m_axis_r_rq.tready = '1') then
-----DW 7-4
m_axis_rq.tdata <= x"00000000"&x"00000000"&x"00000000"&x"00000000"& --128 bits data
s_m_axis_rq.tdata <= x"00000000"&x"00000000"&x"00000000"&x"00000000"& --128 bits data
-----DW 3
'0' & --31 - 1 bit reserved
req_attr & --30-28 3 bits Attr
329,7 → 331,7
current_descriptor.dword_count& -- 10-0 DWord Count 0 - IO Write completions
--DW 1-0
current_descriptor.current_address(63 downto 2)&"00"; --62 bit word address address + 2 bit Address type (0, untranslated)
m_axis_rq.tlast <= '1';
s_m_axis_rq.tlast <= '1';
rw_state <= IDLE;
req_tag <= req_tag + 1;
receive_tags_s(current_receive_tag_s).tag <= "0001"&req_tag;
341,10 → 343,10
current_receive_tag_s <= 0;
end if;
m_axis_rq.tkeep <= x"0F";
m_axis_rq.tvalid <= '1';
s_m_axis_rq.tkeep <= x"0F";
s_m_axis_rq.tvalid <= '1';
else
m_axis_rq.tvalid <= '0';
s_m_axis_rq.tvalid <= '0';
rw_state <= START_READ;
end if;
when others =>
/firmware/sources/pcie/DMA_Core.vhd
98,9 → 98,6
 
signal dma_status : dma_statuses_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal u1_dma_descriptors : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal u0_m_axis_rq : axis_type;
signal u2_m_axis_r_rq : axis_r_type;
signal cache_tready : std_logic;
signal dma_soft_reset : std_logic;
 
component dma_read_write
107,7 → 104,6
generic(
NUMBER_OF_DESCRIPTORS : integer := 8);
port (
cache_tready : in std_logic;
clk : in std_logic;
dma_descriptors : in dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
dma_soft_reset : in std_logic;
125,20 → 121,6
s_axis_rc : in axis_type);
end component dma_read_write;
 
component dma_write_cache
generic(
USE_BACKUP_CACHE : boolean := true);
port (
cache_tready : out std_logic;
clk : in std_logic;
dma_soft_reset : in std_logic;
m_axis_r_rq : in axis_r_type;
m_axis_rq : out axis_type;
reset : in std_logic;
s_axis_r_rq : out axis_r_type;
s_axis_rq : in axis_type);
end component dma_write_cache;
 
component dma_control
generic(
NUMBER_OF_DESCRIPTORS : integer := 8;
176,7 → 158,6
generic map(
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS)
port map(
cache_tready => cache_tready,
clk => clk,
dma_descriptors => u1_dma_descriptors,
dma_soft_reset => dma_soft_reset,
187,25 → 168,12
fifo_full => fifo_full,
fifo_re => fifo_re,
fifo_we => fifo_we,
m_axis_r_rq => u2_m_axis_r_rq,
m_axis_rq => u0_m_axis_rq,
m_axis_r_rq => m_axis_r_rq,
m_axis_rq => m_axis_rq,
reset => reset,
s_axis_r_rc => s_axis_r_rc,
s_axis_rc => s_axis_rc);
 
u2: dma_write_cache
generic map(
USE_BACKUP_CACHE => true)
port map(
cache_tready => cache_tready,
clk => clk,
dma_soft_reset => dma_soft_reset,
m_axis_r_rq => m_axis_r_rq,
m_axis_rq => m_axis_rq,
reset => reset,
s_axis_r_rq => u2_m_axis_r_rq,
s_axis_rq => u0_m_axis_rq);
 
u1: dma_control
generic map(
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
/firmware/sources/pcie/pcie_dma_wrap.vhd
91,13 → 91,9
 
architecture structure of pcie_dma_wrap is
 
signal m_axis_MM2S : axis_type;
signal m_axis_r_MM2S : axis_r_type;
signal s_axis_S2MM : axis_type;
signal s_axis_r_S2MM : axis_r_type;
signal m_axis_CNTRL : axis_type;
signal m_axis_r_CNTRL : axis_r_type;
signal s_axis_STS : axis_type;
signal s_axis_r_STS : axis_r_type;
signal user_lnk_up : std_logic;
signal cfg_interrupt_msix_sent : std_logic;
122,9 → 118,28
signal interrupt_table_en : std_logic;
signal clkDiv6 : std_logic;
signal dma_interrupt_call : STD_LOGIC_VECTOR(3 downto 0);
signal m_axis_cq : axis_type;
signal m_axis_cc : axis_type;
signal m_axis_rc : axis_type;
signal m_axis_rq : axis_type;
signal cfg_fc_ph : std_logic_vector(7 downto 0);
signal cfg_fc_pd : std_logic_vector(11 downto 0);
signal cfg_fc_nph : std_logic_vector(7 downto 0);
signal cfg_fc_npd : std_logic_vector(11 downto 0);
signal cfg_fc_cplh : std_logic_vector(7 downto 0);
signal cfg_fc_cpld : std_logic_vector(11 downto 0);
signal cfg_fc_sel : std_logic_vector(2 downto 0);
signal sys_rst_n : std_logic;
 
component pcie_ep_wrap
port (
cfg_fc_cpld : out std_logic_vector(11 downto 0);
cfg_fc_cplh : out std_logic_vector(7 downto 0);
cfg_fc_npd : out std_logic_vector(11 downto 0);
cfg_fc_nph : out std_logic_vector(7 downto 0);
cfg_fc_pd : out std_logic_vector(11 downto 0);
cfg_fc_ph : out std_logic_vector(7 downto 0);
cfg_fc_sel : in std_logic_vector(2 downto 0);
cfg_interrupt_msix_address : in std_logic_vector(63 downto 0);
cfg_interrupt_msix_data : in std_logic_vector(31 downto 0);
cfg_interrupt_msix_enable : out std_logic_vector(1 downto 0);
211,7 → 226,11
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
interrupt_table_en : in std_logic;
interrupt_vector : in interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
reset : in std_logic);
reset : in std_logic;
s_axis_cc : in axis_type;
s_axis_cq : in axis_type;
s_axis_rc : in axis_type;
s_axis_rq : in axis_type);
end component intr_ctrl;
 
component pcie_init
219,6 → 238,13
bar0 : out std_logic_vector(31 downto 0);
bar1 : out std_logic_vector(31 downto 0);
bar2 : out std_logic_vector(31 downto 0);
cfg_fc_cpld : in std_logic_vector(11 downto 0);
cfg_fc_cplh : in std_logic_vector(7 downto 0);
cfg_fc_npd : in std_logic_vector(11 downto 0);
cfg_fc_nph : in std_logic_vector(7 downto 0);
cfg_fc_pd : in std_logic_vector(11 downto 0);
cfg_fc_ph : in std_logic_vector(7 downto 0);
cfg_fc_sel : out std_logic_vector(2 downto 0);
cfg_mgmt_addr : out std_logic_vector(18 downto 0);
cfg_mgmt_byte_enable : out std_logic_vector(3 downto 0);
cfg_mgmt_read : out std_logic;
243,9 → 269,17
fifo_rd_clk <= clk;
fifo_wr_clk <= clk;
appreg_clk <= clkDiv6;
sys_rst_n <= sys_reset_n;
 
u1: pcie_ep_wrap
port map(
cfg_fc_cpld => cfg_fc_cpld,
cfg_fc_cplh => cfg_fc_cplh,
cfg_fc_npd => cfg_fc_npd,
cfg_fc_nph => cfg_fc_nph,
cfg_fc_pd => cfg_fc_pd,
cfg_fc_ph => cfg_fc_ph,
cfg_fc_sel => cfg_fc_sel,
cfg_interrupt_msix_address => cfg_interrupt_msix_address,
cfg_interrupt_msix_data => cfg_interrupt_msix_data,
cfg_interrupt_msix_enable => cfg_interrupt_msix_enable,
260,22 → 294,22
cfg_mgmt_write => cfg_mgmt_write,
cfg_mgmt_write_data => cfg_mgmt_write_data,
clk => clk,
m_axis_cq => s_axis_STS,
m_axis_cq => m_axis_cq,
m_axis_r_cq => s_axis_r_STS,
m_axis_r_rc => s_axis_r_S2MM,
m_axis_rc => s_axis_S2MM,
m_axis_rc => m_axis_rc,
pci_exp_rxn => pcie_rxn,
pci_exp_rxp => pcie_rxp,
pci_exp_txn => pcie_txn,
pci_exp_txp => pcie_txp,
reset => reset,
s_axis_cc => m_axis_CNTRL,
s_axis_cc => m_axis_cc,
s_axis_r_cc => m_axis_r_CNTRL,
s_axis_r_rq => m_axis_r_MM2S,
s_axis_rq => m_axis_MM2S,
s_axis_rq => m_axis_rq,
sys_clk_n => sys_clk_n,
sys_clk_p => sys_clk_p,
sys_rst_n => sys_reset_n,
sys_rst_n => sys_rst_n,
user_lnk_up => user_lnk_up);
 
dma0: DMA_Core
300,18 → 334,18
flush_fifo => flush_fifo,
interrupt_table_en => interrupt_table_en,
interrupt_vector => interrupt_vector,
m_axis_cc => m_axis_CNTRL,
m_axis_cc => m_axis_cc,
m_axis_r_cc => m_axis_r_CNTRL,
m_axis_r_rq => m_axis_r_MM2S,
m_axis_rq => m_axis_MM2S,
m_axis_rq => m_axis_rq,
register_map_control => register_map_control,
register_map_monitor => register_map_monitor,
reset => reset,
reset_global_soft => reset_soft,
s_axis_cq => s_axis_STS,
s_axis_cq => m_axis_cq,
s_axis_r_cq => s_axis_r_STS,
s_axis_r_rc => s_axis_r_S2MM,
s_axis_rc => s_axis_S2MM,
s_axis_rc => m_axis_rc,
user_lnk_up => user_lnk_up);
 
u2: intr_ctrl
330,7 → 364,11
interrupt_call => interrupt_call,
interrupt_table_en => interrupt_table_en,
interrupt_vector => interrupt_vector,
reset => reset);
reset => reset,
s_axis_cc => m_axis_cc,
s_axis_cq => m_axis_cq,
s_axis_rc => m_axis_rc,
s_axis_rq => m_axis_rq);
 
u0: pcie_init
port map(
337,6 → 375,13
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
cfg_fc_cpld => cfg_fc_cpld,
cfg_fc_cplh => cfg_fc_cplh,
cfg_fc_npd => cfg_fc_npd,
cfg_fc_nph => cfg_fc_nph,
cfg_fc_pd => cfg_fc_pd,
cfg_fc_ph => cfg_fc_ph,
cfg_fc_sel => cfg_fc_sel,
cfg_mgmt_addr => cfg_mgmt_addr,
cfg_mgmt_byte_enable => cfg_mgmt_byte_enable,
cfg_mgmt_read => cfg_mgmt_read,
352,7 → 397,7
clk => clk,
clkDiv6 => clkDiv6,
pll_locked => pll_locked,
reset_n => sys_reset_n,
reset_n => sys_rst_n,
reset_out => reset_hard);
end architecture structure ; -- of pcie_dma_wrap
 
/firmware/sources/pcie/pcie_ep_wrap.vhd
56,6 → 56,13
 
entity pcie_ep_wrap is
port (
cfg_fc_cpld : out std_logic_vector(11 downto 0);
cfg_fc_cplh : out std_logic_vector(7 downto 0);
cfg_fc_npd : out std_logic_vector(11 downto 0);
cfg_fc_nph : out std_logic_vector(7 downto 0);
cfg_fc_pd : out std_logic_vector(11 downto 0);
cfg_fc_ph : out std_logic_vector(7 downto 0);
cfg_fc_sel : in std_logic_vector(2 downto 0);
cfg_interrupt_msix_address : in std_logic_vector(63 downto 0);
cfg_interrupt_msix_data : in std_logic_vector(31 downto 0);
cfg_interrupt_msix_enable : out std_logic_vector(1 downto 0);
493,13 → 500,13
cfg_msg_transmit_type => "000",
cfg_msg_transmit_data => x"00000000",
cfg_msg_transmit_done => open,
cfg_fc_ph => open,
cfg_fc_pd => open,
cfg_fc_nph => open,
cfg_fc_npd => open,
cfg_fc_cplh => open,
cfg_fc_cpld => open,
cfg_fc_sel => "000",
cfg_fc_ph => cfg_fc_ph,
cfg_fc_pd => cfg_fc_pd,
cfg_fc_nph => cfg_fc_nph,
cfg_fc_npd => cfg_fc_npd,
cfg_fc_cplh => cfg_fc_cplh,
cfg_fc_cpld => cfg_fc_cpld,
cfg_fc_sel => cfg_fc_sel,
cfg_per_func_status_control => "000",
cfg_per_func_status_data => open,
cfg_per_function_number => "000",
/firmware/sources/application/application.vhd
116,6 → 116,7
signal cnt: std_logic_vector(31 downto 0);
signal reset: std_logic;
signal s_flush_fifo: std_logic;
begin
 
130,12 → 131,14
 
fifo_full <= '0';
s_flush_fifo <= flush_fifo or reset;
--!
--! Instantiation of the fifo (PCIe => PC)
fifo0 : fifo_256x256
PORT MAP (
clk => fifo_rd_clk,
rst => flush_fifo,
rst => s_flush_fifo,
-- Towards DMA core
rd_en => fifo_re,
dout => fifo_dout,
/firmware/simulation/pcie_dma_top/project.do
31,7 → 31,6
project addfile ../../sources/pcie/pcie_ep_wrap.vhd
project addfile ../../sources/pcie/pcie_dma_wrap.vhd
project addfile ../../sources/pcie/intr_ctrl.vhd
project addfile ../../sources/pcie/dma_write_cache.vhd
project addfile ../../sources/pcie/dma_read_write.vhd
 
project addfile ../../sources/pcie/dma_control.vhd
39,7 → 38,6
 
project addfile ../../Projects/pcie_dma_top/pcie_dma_top.srcs/sources_1/ip/clk_wiz_40/clk_wiz_40_funcsim.vhdl
project addfile ../../Projects/pcie_dma_top/pcie_dma_top.srcs/sources_1/ip/pcie_x8_gen3_3_0/pcie_x8_gen3_3_0_funcsim.vhdl
project addfile ../../Projects/pcie_dma_top/pcie_dma_top.srcs/sources_1/ip/cache_fifo/cache_fifo_funcsim.vhdl
 
# ----------------------------------------------------------
# example application
/firmware/simulation/pcie_dma_top/start.do
163,6 → 163,10
#enable descriptor 0 and 1
write_reg32 64'hfbb00400 128'h3
#enable interrupt table
run 15ns
force -freeze sim:/virtex7_dma_top/u1/dma0/m_axis_r_rq.tready 0 0
run 12ns
force -freeze sim:/virtex7_dma_top/u1/dma0/m_axis_r_rq.tready 1 0
#write_reg32 64'hfba0100 32'h1
 
run 100ns
/firmware/constraints/pcie_dma_top_HTG710.xdc
118,7 → 118,7
###############################################################################
 
set_false_path -from [get_ports sys_reset_n]
set_false_path -reset_path -from [get_pins u1/u1/u1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset_reg/C]
set_false_path -reset_path -from [get_pins u1/u1/u1/inst/gt_top_i/pipe_wrapper_i/pipe_reset_i/cpllreset_reg/C]
###############################################################################
# End
###############################################################################
/firmware/scripts/pcie_dma_top/do_implementation.tcl File deleted
/firmware/scripts/pcie_dma_top/vivado_import_VC709.tcl File deleted
/firmware/scripts/pcie_dma_top/vivado_import_htg710.tcl File deleted
/firmware/scripts/pcie_dma_top/do_implementation_VC709.tcl
0,0 → 1,69
set IMPL_RUN [get_runs impl*]
set SYNTH_RUN [get_runs synth*]
set PROJECT_NAME "pcie_dma_top_VC709"
set scriptdir [pwd]
set HDLDIR $scriptdir/../../
 
foreach design [get_designs] {
puts "Closing design: $design"
current_design $design
close_design
}
 
reset_run $SYNTH_RUN
 
set svn_hash [exec svn info]
set svn_hash_lines [split $svn_hash "\n"]
set svn_version "0"
cd $HDLDIR
foreach line $svn_hash_lines {
if [regexp {Last Changed Rev: } $line ] {
set svn_version [ lindex [split $line] 3 ]
}
}
cd $scriptdir
 
puts "SVN_VERSION = $svn_version"
 
 
set systemTime [clock seconds]
set build_date "40'h[clock format $systemTime -format %y%m%d%H%M]"
puts "BUILD_DATE = $build_date"
 
 
set_property is_enabled false [get_files $HDLDIR/constraints/pcie_dma_top_HTG710.xdc]
set_property is_enabled true [get_files $HDLDIR/constraints/pcie_dma_top_VC709.xdc]
 
#set to true in order to generate the GBT links
set NUMBER_OF_INTERRUPTS 8
set NUMBER_OF_DESCRIPTORS 8
 
set_property generic "BUILD_DATETIME=$build_date SVN_VERSION=$svn_version NUMBER_OF_INTERRUPTS=$NUMBER_OF_INTERRUPTS NUMBER_OF_DESCRIPTORS=$NUMBER_OF_DESCRIPTORS" [current_fileset]
 
launch_runs $SYNTH_RUN
launch_runs $IMPL_RUN
#launch_runs $IMPL_RUN -to_step write_bitstream
#cd $HDLDIR/Synt/
wait_on_run $IMPL_RUN
set TIMESTAMP [clock format $systemTime -format {%y%m%d_%H_%M}]
 
 
 
open_run $IMPL_RUN
current_run $IMPL_RUN
 
write_bitstream $HDLDIR/output/${PROJECT_NAME}_${TIMESTAMP}.bit
 
cd $HDLDIR/output/
 
 
set BitFile ${PROJECT_NAME}_$TIMESTAMP.bit
set IMPL_DIR [get_property DIRECTORY [current_run]]
 
write_cfgmem -force -format MCS -size 128 -interface BPIx16 -loadbit "up 0x00000000 $BitFile" ${PROJECT_NAME}_$TIMESTAMP.mcs
if {[file exists $IMPL_DIR/debug_nets.ltx] == 1} {
file copy $IMPL_DIR/debug_nets.ltx ${PROJECT_NAME}_debug_nets_$TIMESTAMP.ltx
}
 
 
cd $scriptdir
/firmware/scripts/pcie_dma_top/do_implementation_HTG710.tcl
0,0 → 1,69
set IMPL_RUN [get_runs impl*]
set SYNTH_RUN [get_runs synth*]
set PROJECT_NAME "pcie_dma_top_HTG"
set scriptdir [pwd]
set HDLDIR $scriptdir/../../
 
foreach design [get_designs] {
puts "Closing design: $design"
current_design $design
close_design
}
 
reset_run $SYNTH_RUN
 
set svn_hash [exec svn info]
set svn_hash_lines [split $svn_hash "\n"]
set svn_version "0"
cd $HDLDIR
foreach line $svn_hash_lines {
if [regexp {Last Changed Rev: } $line ] {
set svn_version [ lindex [split $line] 3 ]
}
}
cd $scriptdir
 
puts "SVN_VERSION = $svn_version"
 
 
set systemTime [clock seconds]
set build_date "40'h[clock format $systemTime -format %y%m%d%H%M]"
puts "BUILD_DATE = $build_date"
 
 
set_property is_enabled true [get_files $HDLDIR/constraints/pcie_dma_top_HTG710.xdc]
set_property is_enabled false [get_files $HDLDIR/constraints/pcie_dma_top_VC709.xdc]
 
#set to true in order to generate the GBT links
set NUMBER_OF_INTERRUPTS 8
set NUMBER_OF_DESCRIPTORS 8
 
set_property generic "BUILD_DATETIME=$build_date SVN_VERSION=$svn_version NUMBER_OF_INTERRUPTS=$NUMBER_OF_INTERRUPTS NUMBER_OF_DESCRIPTORS=$NUMBER_OF_DESCRIPTORS" [current_fileset]
 
launch_runs $SYNTH_RUN
launch_runs $IMPL_RUN
#launch_runs $IMPL_RUN -to_step write_bitstream
#cd $HDLDIR/Synt/
wait_on_run $IMPL_RUN
set TIMESTAMP [clock format $systemTime -format {%y%m%d_%H_%M}]
 
 
 
open_run $IMPL_RUN
current_run $IMPL_RUN
 
write_bitstream $HDLDIR/output/${PROJECT_NAME}_${TIMESTAMP}.bit
 
cd $HDLDIR/output/
 
 
set BitFile ${PROJECT_NAME}_$TIMESTAMP.bit
set IMPL_DIR [get_property DIRECTORY [current_run]]
 
write_cfgmem -force -format MCS -size 128 -interface BPIx16 -loadbit "up 0x00000000 $BitFile" ${PROJECT_NAME}_$TIMESTAMP.mcs
if {[file exists $IMPL_DIR/debug_nets.ltx] == 1} {
file copy $IMPL_DIR/debug_nets.ltx ${PROJECT_NAME}_debug_nets_$TIMESTAMP.ltx
}
 
 
cd $scriptdir
/firmware/scripts/pcie_dma_top/vivado_import.tcl
0,0 → 1,72
#
# File import script for the PCIe DMA core hdl project
#
#
 
#Script Configuration
 
set proj_name pcie_dma_top
# Set the supportfiles directory path
set scriptdir [pwd]
set proj_dir $scriptdir/../../
 
#Close currently open project and create a new one. (OVERWRITES PROJECT!!)
close_project -quiet
 
create_project -force -part xc7vx690tffg1761-2 $proj_name $proj_dir/Projects/$proj_name
 
set_property target_language VHDL [current_project]
set_property default_lib work [current_project]
 
# ----------------------------------------------------------
# PCIe DMA top module
# ----------------------------------------------------------
read_vhdl -library work $proj_dir/sources/shared/virtex7_dma_top.vhd
# ----------------------------------------------------------
# packages
# ----------------------------------------------------------
read_vhdl -library work $proj_dir/sources/packages/pcie_package.vhd
 
# ----------------------------------------------------------
# dma sources
# ----------------------------------------------------------
 
read_vhdl -library work $proj_dir/sources/pcie/DMA_Core.vhd
read_vhdl -library work $proj_dir/sources/pcie/dma_read_write.vhd
read_vhdl -library work $proj_dir/sources/pcie/intr_ctrl.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_dma_wrap.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_ep_wrap.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_init.vhd
read_vhdl -library work $proj_dir/sources/pcie/dma_control.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_clocking.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_slow_clock.vhd
 
import_ip $proj_dir/sources/pcie/pcie_x8_gen3_3_0.xci
import_ip $proj_dir/sources/pcie/clk_wiz_40.xci
 
# ----------------------------------------------------------
# example application
# ----------------------------------------------------------
 
read_vhdl -library work $proj_dir/sources/application/application.vhd
import_ip $proj_dir/sources/application/fifo_256x256.xci
 
upgrade_ip [get_ips {pcie_x8_gen3_3_0 cache_fifo clk_wiz_40 fifo_256x256}]
 
read_xdc -verbose $proj_dir/constraints/pcie_dma_top_VC709.xdc
read_xdc -verbose $proj_dir/constraints/pcie_dma_top_HTG710.xdc
close [ open $proj_dir/constraints/probes.xdc w ]
read_xdc -verbose $proj_dir/constraints/probes.xdc
set_property target_constrs_file $proj_dir/constraints/probes.xdc [current_fileset -constrset]
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE MoreGlobalIterations [get_runs impl_1]
 
set_property top virtex7_dma_top [current_fileset]
 
puts "INFO: Done!"
 
 
 
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.