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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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  • This comparison shows the changes necessary to convert path 
    /virtex7_pcie_dma/trunk
    from Rev 12 to Rev 13
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  •

Rev 12 → Rev 13

/firmware/scripts/pcie_dma_top/do_implementation_VC709.tcl File deleted
/firmware/scripts/pcie_dma_top/do_implementation_HTG710.tcl File deleted
/firmware/scripts/pcie_dma_top/vivado_import.tcl File deleted
/firmware/scripts/Wupper/do_implementation_VC709.tcl
0,0 → 1,69
set IMPL_RUN [get_runs impl*]
set SYNTH_RUN [get_runs synth*]
set PROJECT_NAME "pcie_dma_top_VC709"
set scriptdir [pwd]
set HDLDIR $scriptdir/../../
 
foreach design [get_designs] {
puts "Closing design: $design"
current_design $design
close_design
}
 
reset_run $SYNTH_RUN
 
set svn_hash [exec svn info]
set svn_hash_lines [split $svn_hash "\n"]
set svn_version "0"
cd $HDLDIR
foreach line $svn_hash_lines {
if [regexp {Last Changed Rev: } $line ] {
set svn_version [ lindex [split $line] 3 ]
}
}
cd $scriptdir
 
puts "SVN_VERSION = $svn_version"
 
 
set systemTime [clock seconds]
set build_date "40'h[clock format $systemTime -format %y%m%d%H%M]"
puts "BUILD_DATE = $build_date"
 
 
set_property is_enabled false [get_files $HDLDIR/constraints/pcie_dma_top_HTG710.xdc]
set_property is_enabled true [get_files $HDLDIR/constraints/pcie_dma_top_VC709.xdc]
 
#set to true in order to generate the GBT links
set NUMBER_OF_INTERRUPTS 8
set NUMBER_OF_DESCRIPTORS 8
 
set_property generic "BUILD_DATETIME=$build_date SVN_VERSION=$svn_version NUMBER_OF_INTERRUPTS=$NUMBER_OF_INTERRUPTS NUMBER_OF_DESCRIPTORS=$NUMBER_OF_DESCRIPTORS" [current_fileset]
 
launch_runs $SYNTH_RUN
launch_runs $IMPL_RUN
#launch_runs $IMPL_RUN -to_step write_bitstream
#cd $HDLDIR/Synt/
wait_on_run $IMPL_RUN
set TIMESTAMP [clock format $systemTime -format {%y%m%d_%H_%M}]
 
 
 
open_run $IMPL_RUN
current_run $IMPL_RUN
 
write_bitstream $HDLDIR/output/${PROJECT_NAME}_${TIMESTAMP}.bit
 
cd $HDLDIR/output/
 
 
set BitFile ${PROJECT_NAME}_$TIMESTAMP.bit
set IMPL_DIR [get_property DIRECTORY [current_run]]
 
write_cfgmem -force -format MCS -size 128 -interface BPIx16 -loadbit "up 0x00000000 $BitFile" ${PROJECT_NAME}_$TIMESTAMP.mcs
if {[file exists $IMPL_DIR/debug_nets.ltx] == 1} {
file copy $IMPL_DIR/debug_nets.ltx ${PROJECT_NAME}_debug_nets_$TIMESTAMP.ltx
}
 
 
cd $scriptdir
/firmware/scripts/Wupper/do_implementation_HTG710.tcl
0,0 → 1,69
set IMPL_RUN [get_runs impl*]
set SYNTH_RUN [get_runs synth*]
set PROJECT_NAME "pcie_dma_top_HTG"
set scriptdir [pwd]
set HDLDIR $scriptdir/../../
 
foreach design [get_designs] {
puts "Closing design: $design"
current_design $design
close_design
}
 
reset_run $SYNTH_RUN
 
set svn_hash [exec svn info]
set svn_hash_lines [split $svn_hash "\n"]
set svn_version "0"
cd $HDLDIR
foreach line $svn_hash_lines {
if [regexp {Last Changed Rev: } $line ] {
set svn_version [ lindex [split $line] 3 ]
}
}
cd $scriptdir
 
puts "SVN_VERSION = $svn_version"
 
 
set systemTime [clock seconds]
set build_date "40'h[clock format $systemTime -format %y%m%d%H%M]"
puts "BUILD_DATE = $build_date"
 
 
set_property is_enabled true [get_files $HDLDIR/constraints/pcie_dma_top_HTG710.xdc]
set_property is_enabled false [get_files $HDLDIR/constraints/pcie_dma_top_VC709.xdc]
 
#set to true in order to generate the GBT links
set NUMBER_OF_INTERRUPTS 8
set NUMBER_OF_DESCRIPTORS 8
 
set_property generic "BUILD_DATETIME=$build_date SVN_VERSION=$svn_version NUMBER_OF_INTERRUPTS=$NUMBER_OF_INTERRUPTS NUMBER_OF_DESCRIPTORS=$NUMBER_OF_DESCRIPTORS" [current_fileset]
 
launch_runs $SYNTH_RUN
launch_runs $IMPL_RUN
#launch_runs $IMPL_RUN -to_step write_bitstream
#cd $HDLDIR/Synt/
wait_on_run $IMPL_RUN
set TIMESTAMP [clock format $systemTime -format {%y%m%d_%H_%M}]
 
 
 
open_run $IMPL_RUN
current_run $IMPL_RUN
 
write_bitstream $HDLDIR/output/${PROJECT_NAME}_${TIMESTAMP}.bit
 
cd $HDLDIR/output/
 
 
set BitFile ${PROJECT_NAME}_$TIMESTAMP.bit
set IMPL_DIR [get_property DIRECTORY [current_run]]
 
write_cfgmem -force -format MCS -size 128 -interface BPIx16 -loadbit "up 0x00000000 $BitFile" ${PROJECT_NAME}_$TIMESTAMP.mcs
if {[file exists $IMPL_DIR/debug_nets.ltx] == 1} {
file copy $IMPL_DIR/debug_nets.ltx ${PROJECT_NAME}_debug_nets_$TIMESTAMP.ltx
}
 
 
cd $scriptdir
/firmware/scripts/Wupper/vivado_import.tcl
0,0 → 1,72
#
# File import script for the PCIe DMA core hdl project
#
#
 
#Script Configuration
 
set proj_name pcie_dma_top
# Set the supportfiles directory path
set scriptdir [pwd]
set proj_dir $scriptdir/../../
 
#Close currently open project and create a new one. (OVERWRITES PROJECT!!)
close_project -quiet
 
create_project -force -part xc7vx690tffg1761-2 $proj_name $proj_dir/Projects/$proj_name
 
set_property target_language VHDL [current_project]
set_property default_lib work [current_project]
 
# ----------------------------------------------------------
# PCIe DMA top module
# ----------------------------------------------------------
read_vhdl -library work $proj_dir/sources/shared/virtex7_dma_top.vhd
# ----------------------------------------------------------
# packages
# ----------------------------------------------------------
read_vhdl -library work $proj_dir/sources/packages/pcie_package.vhd
 
# ----------------------------------------------------------
# dma sources
# ----------------------------------------------------------
 
read_vhdl -library work $proj_dir/sources/pcie/DMA_Core.vhd
read_vhdl -library work $proj_dir/sources/pcie/dma_read_write.vhd
read_vhdl -library work $proj_dir/sources/pcie/intr_ctrl.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_dma_wrap.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_ep_wrap.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_init.vhd
read_vhdl -library work $proj_dir/sources/pcie/dma_control.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_clocking.vhd
read_vhdl -library work $proj_dir/sources/pcie/pcie_slow_clock.vhd
 
import_ip $proj_dir/sources/pcie/pcie_x8_gen3_3_0.xci
import_ip $proj_dir/sources/pcie/clk_wiz_40.xci
 
# ----------------------------------------------------------
# example application
# ----------------------------------------------------------
 
read_vhdl -library work $proj_dir/sources/application/application.vhd
import_ip $proj_dir/sources/application/fifo_256x256.xci
 
upgrade_ip [get_ips {pcie_x8_gen3_3_0 cache_fifo clk_wiz_40 fifo_256x256}]
 
read_xdc -verbose $proj_dir/constraints/pcie_dma_top_VC709.xdc
read_xdc -verbose $proj_dir/constraints/pcie_dma_top_HTG710.xdc
close [ open $proj_dir/constraints/probes.xdc w ]
read_xdc -verbose $proj_dir/constraints/probes.xdc
set_property target_constrs_file $proj_dir/constraints/probes.xdc [current_fileset -constrset]
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE MoreGlobalIterations [get_runs impl_1]
 
set_property top virtex7_dma_top [current_fileset]
 
puts "INFO: Done!"
 
 
 
 
 
 
 

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