URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
Compare Revisions
- This comparison shows the changes necessary to convert path
/w11/tags/w11a_V0.5/rtl/bplib
- from Rev 3 to Rev 7
- ↔ Reverse comparison
Rev 3 → Rev 7
/issi/is61lv25616al.vhd
0,0 → 1,169
-- $Id: is61lv25616al.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: is61lv25616al - sim |
-- Description: ISSI 61LV25612AL SRAM model |
-- Currently a truely minimalistic functional model, without |
-- any timing checks. It assumes, that addr/data is stable at |
-- the trailing edge of we. |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted |
-- 2007-12-14 101 1.0 Initial version (written on warsaw airport) |
------------------------------------------------------------------------------ |
-- Truth table accoring to data sheet: |
-- |
-- Mode WE_N CE_N OE_N LB_N UB_N D(7:0) D(15:8) |
-- Not selected X H X X X high-Z high-Z |
-- Output disabled H L H X X high-Z high-Z |
-- X L X H H high-Z high-Z |
-- Read H L L L H D_out high-Z |
-- H L L H L high-Z D_out |
-- H L L L L D_out D_out |
-- Write L L X L H D_in high-Z |
-- L L X H L high-Z D_in |
-- L L X L L D_in D_in |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
|
use work.slvtypes.all; |
|
entity is61lv25616al is -- ISSI 61LV25612AL SRAM model |
port ( |
CE_N : in slbit; -- chip enable (act.low) |
OE_N : in slbit; -- output enable (act.low) |
WE_N : in slbit; -- write enable (act.low) |
UB_N : in slbit; -- upper byte enable (act.low) |
LB_N : in slbit; -- lower byte enable (act.low) |
ADDR : in slv18; -- address lines |
DATA : inout slv16 -- data lines |
); |
end is61lv25616al; |
|
|
architecture sim of is61lv25616al is |
|
signal CE : slbit := '0'; |
signal OE : slbit := '0'; |
signal WE : slbit := '0'; |
signal BE_L : slbit := '0'; |
signal BE_U : slbit := '0'; |
|
component is61lv25616al_bank is -- ISSI 61LV25612AL bank |
port ( |
CE : in slbit; -- chip enable (act.high) |
OE : in slbit; -- output enable (act.high) |
WE : in slbit; -- write enable (act.high) |
BE : in slbit; -- byte enable (act.high) |
ADDR : in slv18; -- address lines |
DATA : inout slv8 -- data lines |
); |
end component; |
|
begin |
|
CE <= not CE_N; |
OE <= not OE_N; |
WE <= not WE_N; |
BE_L <= not LB_N; |
BE_U <= not UB_N; |
|
BANK_L : is61lv25616al_bank port map ( |
CE => CE, |
OE => OE, |
WE => WE, |
BE => BE_L, |
ADDR => ADDR, |
DATA => DATA(7 downto 0)); |
|
BANK_U : is61lv25616al_bank port map ( |
CE => CE, |
OE => OE, |
WE => WE, |
BE => BE_U, |
ADDR => ADDR, |
DATA => DATA(15 downto 8)); |
|
end sim; |
|
-- ---------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
|
use work.slvtypes.all; |
|
entity is61lv25616al_bank is -- ISSI 61LV25612AL bank |
port ( |
CE : in slbit; -- chip enable (act.high) |
OE : in slbit; -- output enable (act.high) |
WE : in slbit; -- write enable (act.high) |
BE : in slbit; -- byte enable (act.high) |
ADDR : in slv18; -- address lines |
DATA : inout slv8 -- data lines |
); |
end is61lv25616al_bank; |
|
architecture sim of is61lv25616al_bank is |
|
constant T_rc : time := 10 ns; -- read cycle time (min) |
constant T_aa : time := 10 ns; -- address access time (max) |
constant T_oha : time := 2 ns; -- output hold time (min) |
constant T_ace : time := 10 ns; -- ce access time (max) |
constant T_doe : time := 4 ns; -- oe access time (max) |
constant T_hzoe : time := 4 ns; -- oe to high-Z output (max) |
constant T_lzoe : time := 0 ns; -- oe to low-Z output (min) |
constant T_hzce : time := 4 ns; -- ce to high-Z output (min=0,max=4) |
constant T_lzce : time := 3 ns; -- ce to low-Z output (min) |
constant T_ba : time := 4 ns; -- lb,ub access time (max) |
constant T_hzb : time := 3 ns; -- lb,ub to high-Z output (min=0,max=3) |
constant T_lzb : time := 0 ns; -- lb,ub low-Z output (min) |
|
constant memsize : positive := 2**(ADDR'length); |
constant datzero : slv(DATA'range) := (others=>'0'); |
type ram_type is array (0 to memsize-1) of slv(DATA'range); |
|
signal WE_EFF : slbit := '0'; |
|
begin |
|
WE_EFF <= CE and WE and BE; |
|
proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA) |
variable ram : ram_type := (others=>datzero); |
begin |
|
if WE_EFF'event and WE_EFF='0' then -- end of write cycle |
-- note: to_x01 used below to prevent |
-- that 'z' a written into mem. |
ram(conv_integer(unsigned(ADDR))) := to_x01(DATA); |
end if; |
|
if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver |
DATA <= ram(conv_integer(unsigned(ADDR))); |
else |
DATA <= (others=>'Z'); |
end if; |
|
end process proc_sram; |
|
end sim; |
/issi/is61lv25616al.vbom
0,0 → 1,5
# libs |
../../vlib/slvtypes.vhd |
# components |
# design |
is61lv25616al.vhd |
/issi/Makefile
0,0 → 1,19
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2007-12-14 101 1.0 Initial version |
# |
# |
.phony : clean |
# |
clean : ghdl_clean |
# |
#----- |
# |
include $(RETROBASE)/rtl/vlib/Makefile.ghdl |
# |
VBOM_all = $(wildcard *.vbom) |
# |
include $(VBOM_all:.vbom=.dep_ghdl) |
# |
issi
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: micron/mt45w8mw16b.vhd
===================================================================
--- micron/mt45w8mw16b.vhd (nonexistent)
+++ micron/mt45w8mw16b.vhd (revision 7)
@@ -0,0 +1,242 @@
+-- $Id: mt45w8mw16b.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: mt45w8mw16b - sim
+-- Description: Micron MT45W8MW16B CellularRAM model
+-- Currently a much simplified model
+-- - only async accesses
+-- - ignores CLK and CRE
+-- - simple model for response of DATA lines, but no
+-- check for timing violations of control lines
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
+-- 2010-06-03 298 1.3 add timing model again
+-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
+-- 2010-05-21 293 1.1 add BCR (only read of default so far)
+-- 2010-05-16 291 1.0 Initial version (inspired by is61lv25616al)
+------------------------------------------------------------------------------
+-- Truth table accoring to data sheet:
+--
+-- Asynchronous Mode (BCR(15)=1)
+-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
+-- Read L L L L H L L act data-out
+-- Write L L L X L L L act data-in
+-- Standby L X H X X L X 'z' 'z'
+-- CRE write L L L H L H X act 'z'
+-- CRE read L L L L H H L act conf-out
+--
+-- Burst Mode (BCR(15)=0)
+-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA
+-- Async read L L L L H L L act data-out
+-- Async write L L L X L L L act data-in
+-- Standby L X H X X L X 'z' 'z'
+-- Initial burst read 0-1 L L X H L L act X
+-- Initial burst write 0-1 L L H L L X act X
+-- Burst continue 0-1 H L X X X X act data-in/out
+-- CRE write 0-1 L L H L H X act 'z'
+-- CRE read 0-1 L L L H H L act conf-out
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity mt45w8mw16b is -- Micron MT45W8MW16B CellularRAM model
+ port (
+ CLK : in slbit; -- clock for synchonous operation
+ CE_N : in slbit; -- chip enable (act.low)
+ OE_N : in slbit; -- output enable (act.low)
+ WE_N : in slbit; -- write enable (act.low)
+ UB_N : in slbit; -- upper byte enable (act.low)
+ LB_N : in slbit; -- lower byte enable (act.low)
+ ADV_N : in slbit; -- address valid (act.low)
+ CRE : in slbit; -- control register enable
+ MWAIT : out slbit; -- wait (for burst read/write)
+ ADDR : in slv23; -- address lines
+ DATA : inout slv16 -- data lines
+ );
+end mt45w8mw16b;
+
+
+architecture sim of mt45w8mw16b is
+
+ -- timing constants for -701 speed grade (70 ns; 104 MHz)
+ constant T_aa : time := 70 ns; -- address access time (max)
+ constant T_apa : time := 20 ns; -- page acess time (max)
+ constant T_oh : time := 5 ns; -- output hold from addr change (max)
+ constant T_oe : time := 20 ns; -- output enable to valid output (max)
+ constant T_ohz : time := 8 ns; -- output disable to high-z output (max)
+ constant T_olz : time := 3 ns; -- output enable to low-z output (min)
+ constant T_lz : time := 10 ns; -- chip enable to low-z output (min)
+ constant T_hz : time := 8 ns; -- chip disable to high-z output (max)
+
+ constant memsize : positive := 2**(ADDR'length);
+ constant datzero : slv(DATA'range) := (others=>'0');
+ type ram_type is array (0 to memsize-1) of slv(DATA'range);
+
+ constant bcr_f_mode : integer := 15; -- operating mode
+ constant bcr_f_ilat : integer := 14; -- initial latency
+ subtype bcr_f_lc is integer range 13 downto 11; -- latency counter
+ constant bcr_f_wp : integer := 10; -- wait polarity
+ constant bcr_f_wc : integer := 8; -- wait configuration
+ subtype bcr_f_drive is integer range 5 downto 4; -- drive strength
+ constant bcr_f_bw : integer := 3; -- burst wrap
+ subtype bcr_f_bl is integer range 2 downto 0; -- burst length
+
+ subtype f_byte1 is integer range 15 downto 8;
+ subtype f_byte0 is integer range 7 downto 0;
+
+ signal CE : slbit := '0';
+ signal OE : slbit := '0';
+ signal WE : slbit := '0';
+ signal BE_L : slbit := '0';
+ signal BE_U : slbit := '0';
+ signal ADV : slbit := '0';
+ signal WE_L_EFF : slbit := '0';
+ signal WE_U_EFF : slbit := '0';
+
+ signal R_BCR_MODE : slbit := '1'; -- mode: def: async
+ signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable
+ signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3
+ signal R_BCR_WP : slbit := '1'; -- wp: def: active high
+ signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before
+ signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2
+ signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap
+ signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous
+
+ signal L_ADDR : slv23 := (others=>'0');
+ signal DOUT_VAL_EN : slbit := '0';
+ signal DOUT_VAL_AA : slbit := '0';
+ signal DOUT_VAL_PA : slbit := '0';
+ signal DOUT_VAL_OE : slbit := '0';
+ signal DOUT_LZ_CE : slbit := '0';
+ signal DOUT_LZ_OE : slbit := '0';
+
+ signal OEWE : slbit := '0';
+ signal DOUT : slv16 := (others=>'0');
+begin
+
+ CE <= not CE_N;
+ OE <= not OE_N;
+ WE <= not WE_N;
+ BE_L <= not LB_N;
+ BE_U <= not UB_N;
+ ADV <= not ADV_N;
+
+ WE_L_EFF <= CE and WE and BE_L;
+ WE_U_EFF <= CE and WE and BE_U;
+
+ -- address valid logic, latch ADDR when ADV true
+ proc_adv: process (ADV, ADDR)
+ begin
+ if ADV = '1' then
+ L_ADDR <= ADDR;
+ end if;
+ end process proc_adv;
+
+ proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR)
+ variable addr_last : slv23 := (others=>'1');
+ begin
+ if (CE'event and CE='1') or
+ (BE_L'event and BE_L='1') or
+ (BE_U'event and BE_U='1') or
+ (WE'event and WE='0') or
+ (ADV'event and ADV='1') then
+ DOUT_VAL_EN <= '0', '1' after T_aa;
+ end if;
+ if L_ADDR'event then
+ DOUT_VAL_PA <= '0', '1' after T_apa;
+ if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then
+ DOUT_VAL_AA <= '0', '1' after T_aa;
+ end if;
+ addr_last := L_ADDR;
+ end if;
+ if OE'event and OE='1' then
+ DOUT_VAL_OE <= '0', '1' after T_oe;
+ end if;
+ end process proc_dout_val;
+
+ -- to simplify things assume that OE and (not WE) have same effect on output
+ -- drivers. The timing rules are very similar indeed...
+ OEWE <= OE and (not WE);
+
+ proc_dout_lz: process (CE, OEWE)
+ begin
+ if (CE'event) then
+ if CE = '1' then
+ DOUT_LZ_CE <= '1' after T_lz;
+ else
+ DOUT_LZ_CE <= '0' after T_hz;
+ end if;
+ end if;
+ if (OEwe'event) then
+ if OEWE = '1' then
+ DOUT_LZ_OE <= '1' after T_olz;
+ else
+ DOUT_LZ_OE <= '0' after T_ohz;
+ end if;
+ end if;
+ end process proc_dout_lz;
+
+ proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA)
+ variable ram : ram_type := (others=>datzero);
+ begin
+
+ -- end of write cycle
+ -- note: to_x01 used below to prevent that 'z' a written into mem.
+ if WE_L_EFF'event and WE_L_EFF='0' then
+ ram(conv_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
+ end if;
+ if WE_U_EFF'event and WE_U_EFF='0' then
+ ram(conv_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
+ end if;
+
+ DOUT <= ram(conv_integer(unsigned(L_ADDR)));
+
+ end process proc_cram;
+
+ proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE,
+ DOUT_LZ_CE, DOUT_LZ_OE)
+ variable idout : slv16 := (others=>'0');
+ begin
+ idout := DOUT;
+ if DOUT_VAL_EN='0' or DOUT_VAL_AA='0' or
+ DOUT_VAL_PA='0' or DOUT_VAL_OE='0' then
+ idout := (others=>'X');
+ end if;
+ if DOUT_LZ_CE='0' or DOUT_LZ_OE='0' then
+ idout := (others=>'Z');
+ end if;
+ DATA <= idout;
+ end process proc_data;
+
+ proc_mwait: process (CE)
+ begin
+ -- WT driver (just a dummy)
+ if CE = '1' then
+ MWAIT <= '1';
+ else
+ MWAIT <= 'Z';
+ end if;
+ end process proc_mwait;
+
+end sim;
Index: micron/mt45w8mw16b.vbom
===================================================================
--- micron/mt45w8mw16b.vbom (nonexistent)
+++ micron/mt45w8mw16b.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../../vlib/slvtypes.vhd
+# components
+# design
+mt45w8mw16b.vhd
Index: micron
===================================================================
--- micron (nonexistent)
+++ micron (revision 7)
micron
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: nexys2/tb/tbw.dat
===================================================================
--- nexys2/tb/tbw.dat (nonexistent)
+++ nexys2/tb/tbw.dat (revision 7)
@@ -0,0 +1,4 @@
+# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
+#
+[tb_n2_cram_memctl_as]
+tb_n2_cram_memctl_stim = tb_n2_cram_memctl_stim.dat
Index: nexys2/tb/tb_nexys2_core.vhd
===================================================================
--- nexys2/tb/tb_nexys2_core.vhd (nonexistent)
+++ nexys2/tb/tb_nexys2_core.vhd (revision 7)
@@ -0,0 +1,97 @@
+-- $Id: tb_nexys2_core.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_nexys2_core - sim
+-- Description: Test bench for nexys2 - core device handling
+--
+-- Dependencies: vlib/parts/micron/mt45w8mw16b
+--
+-- To test: generic, any nexys2 target
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+use work.simbus.all;
+
+entity tb_nexys2_core is
+ port (
+ I_SWI : out slv8; -- n2 switches
+ I_BTN : out slv4; -- n2 buttons
+ O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : in slbit; -- cram: clock
+ O_MEM_CRE : in slbit; -- cram: command register enable
+ I_MEM_WAIT : out slbit; -- cram: mem wait
+ O_FLA_CE_N : in slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : in slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end tb_nexys2_core;
+
+architecture sim of tb_nexys2_core is
+
+ signal R_SWI : slv8 := (others=>'0');
+ signal R_BTN : slv4 := (others=>'0');
+
+ constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8);
+ constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8);
+
+begin
+
+ MEM : entity work.mt45w8mw16b
+ port map (
+ CLK => O_MEM_CLK,
+ CE_N => O_MEM_CE_N,
+ OE_N => O_MEM_OE_N,
+ WE_N => O_MEM_WE_N,
+ UB_N => O_MEM_BE_N(1),
+ LB_N => O_MEM_BE_N(0),
+ ADV_N => O_MEM_ADV_N,
+ CRE => O_MEM_CRE,
+ MWAIT => I_MEM_WAIT,
+ ADDR => O_MEM_ADDR,
+ DATA => IO_MEM_DATA
+ );
+
+ proc_simbus: process (SB_VAL)
+ begin
+ if SB_VAL'event and to_x01(SB_VAL)='1' then
+ if SB_ADDR = sbaddr_swi then
+ R_SWI <= to_x01(SB_DATA(R_SWI'range));
+ end if;
+ if SB_ADDR = sbaddr_btn then
+ R_BTN <= to_x01(SB_DATA(R_BTN'range));
+ end if;
+ end if;
+ end process proc_simbus;
+
+ I_SWI <= R_SWI;
+ I_BTN <= R_BTN;
+
+end sim;
Index: nexys2/tb/tb_nexys2_core.vbom
===================================================================
--- nexys2/tb/tb_nexys2_core.vbom (nonexistent)
+++ nexys2/tb/tb_nexys2_core.vbom (revision 7)
@@ -0,0 +1,10 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/serport/serport.vhd
+../../../vlib/simlib/simbus.vhd
+# components
+../../../vlib/serport/serport_uart_rx.vbom
+../../../vlib/serport/serport_uart_tx.vbom
+../../micron/mt45w8mw16b.vbom
+# design
+tb_nexys2_core.vhd
Index: nexys2/tb/tb_nexys2_fusp.vhd
===================================================================
--- nexys2/tb/tb_nexys2_fusp.vhd (nonexistent)
+++ nexys2/tb/tb_nexys2_fusp.vhd (revision 7)
@@ -0,0 +1,232 @@
+-- $Id: tb_nexys2_fusp.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_nexys2_fusp - sim
+-- Description: Test bench for nexys2 (base+fusp)
+--
+-- Dependencies: vlib/rri/tb/rritb_core
+-- tb_nexys2_core
+-- vlib/serport/serport_uart_rxtx
+-- nexys2_fusp_aif [UUT]
+--
+-- To test: generic, any nexys2_fusp_aif target
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.rrilib.all;
+use work.rritblib.all;
+use work.serport.all;
+use work.nexys2lib.all;
+use work.simlib.all;
+use work.simbus.all;
+
+entity tb_nexys2_fusp is
+end tb_nexys2_fusp;
+
+architecture sim of tb_nexys2_fusp is
+
+ signal CLK : slbit := '0';
+
+ signal RESET : slbit := '0';
+ signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXERR : slbit := '0';
+ signal RXACT : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal RX_HOLD : slbit := '0';
+
+ signal I_RXD : slbit := '1';
+ signal O_TXD : slbit := '1';
+ signal I_SWI : slv8 := (others=>'0');
+ signal I_BTN : slv4 := (others=>'0');
+ signal O_LED : slv8 := (others=>'0');
+ signal O_ANO_N : slv4 := (others=>'0');
+ signal O_SEG_N : slv8 := (others=>'0');
+
+ signal O_MEM_CE_N : slbit := '1';
+ signal O_MEM_BE_N : slv2 := (others=>'1');
+ signal O_MEM_WE_N : slbit := '1';
+ signal O_MEM_OE_N : slbit := '1';
+ signal O_MEM_ADV_N : slbit := '1';
+ signal O_MEM_CLK : slbit := '0';
+ signal O_MEM_CRE : slbit := '0';
+ signal I_MEM_WAIT : slbit := '0';
+ signal O_FLA_CE_N : slbit := '0';
+ signal O_MEM_ADDR : slv23 := (others=>'Z');
+ signal IO_MEM_DATA : slv16 := (others=>'0');
+
+ signal O_FUSP_RTS_N : slbit := '0';
+ signal I_FUSP_CTS_N : slbit := '0';
+ signal I_FUSP_RXD : slbit := '1';
+ signal O_FUSP_TXD : slbit := '1';
+
+ signal UART_RESET : slbit := '0';
+ signal UART_RXD : slbit := '1';
+ signal UART_TXD : slbit := '1';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal R_PORTSEL : slbit := '0';
+
+ constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant setup_time : time := 5 ns;
+ constant c2out_time : time := 10 ns;
+
+begin
+
+ TBCORE : rritb_core
+ generic map (
+ CLK_PERIOD => clock_period,
+ CLK_OFFSET => clock_offset,
+ SETUP_TIME => setup_time,
+ C2OUT_TIME => c2out_time)
+ port map (
+ CLK => CLK,
+ RX_DATA => TXDATA,
+ RX_VAL => TXENA,
+ RX_HOLD => RX_HOLD,
+ TX_DATA => RXDATA,
+ TX_ENA => RXVAL
+ );
+
+ RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
+
+ N2CORE : entity work.tb_nexys2_core
+ port map (
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_FLA_CE_N => O_FLA_CE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ UUT : nexys2_fusp_aif
+ port map (
+ CLK => CLK,
+ I_RXD => I_RXD,
+ O_TXD => O_TXD,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_FLA_CE_N => O_FLA_CE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA,
+ O_FUSP_RTS_N => O_FUSP_RTS_N,
+ I_FUSP_CTS_N => I_FUSP_CTS_N,
+ I_FUSP_RXD => I_FUSP_RXD,
+ O_FUSP_TXD => O_FUSP_TXD
+ );
+
+ UART : serport_uart_rxtx
+ generic map (
+ CDWIDTH => CLKDIV'length)
+ port map (
+ CLK => CLK,
+ RESET => UART_RESET,
+ CLKDIV => CLKDIV,
+ RXSD => UART_RXD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD => UART_TXD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
+ O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
+ begin
+
+ if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
+ I_RXD <= UART_TXD; -- write port 0 inputs
+ UART_RXD <= O_TXD; -- get port 0 outputs
+ RTS_N <= '0';
+ I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
+ I_FUSP_CTS_N <= '0';
+ else -- otherwise use pmod1 rs232
+ I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
+ I_FUSP_CTS_N <= CTS_N;
+ UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
+ RTS_N <= O_FUSP_RTS_N;
+ I_RXD <= '1'; -- port 0 inputs to idle state
+ end if;
+
+ end process proc_port_mux;
+
+ proc_moni: process
+ variable oline : line;
+ begin
+
+ loop
+ wait until CLK'event and CLK='1';
+ wait for c2out_time;
+
+ if RXERR = '1' then
+ writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
+ writeline(output, oline);
+ end if;
+
+ end loop;
+
+ end process proc_moni;
+
+ proc_simbus: process (SB_VAL)
+ begin
+ if SB_VAL'event and to_x01(SB_VAL)='1' then
+ if SB_ADDR = sbaddr_portsel then
+ R_PORTSEL <= to_x01(SB_DATA(0));
+ end if;
+ end if;
+ end process proc_simbus;
+
+end sim;
Index: nexys2/tb/tb_nexys2_fusp.vbom
===================================================================
--- nexys2/tb/tb_nexys2_fusp.vbom (nonexistent)
+++ nexys2/tb/tb_nexys2_fusp.vbom (revision 7)
@@ -0,0 +1,20 @@
+# Not meant for direct top level usage. Used with
+# tb_nexys2_fusp_(....)[_ssim].vbom and config
+# lines to generate the different cases.
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/rri/rrilib.vhd
+../../../vlib/rri/tb/rritblib.vhd
+../../../vlib/serport/serport.vhd
+../nexys2lib.vhd
+../../../vlib/simlib/simlib.vhd
+../../../vlib/simlib/simbus.vhd
+# components
+../../../vlib/rri/tb/rritb_core.vbom
+tb_nexys2_core.vbom
+../../../vlib/serport/serport_uart_rxtx.vbom
+nexys2_fusp_aif : nexys2_fusp_dummy.vbom
+# design
+tb_nexys2_fusp.vhd
+@top:tb_nexys2_fusp
Index: nexys2/tb/.cvsignore
===================================================================
--- nexys2/tb/.cvsignore (nonexistent)
+++ nexys2/tb/.cvsignore (revision 7)
@@ -0,0 +1,7 @@
+tb_nexys2_dummy
+tb_nexys2_fusp_dummy
+tb_n2_cram_memctl_as
+tb_n2_cram_memctl_as_[sft]sim
+tb_n2_cram_memctl_as_ISim
+tb_n2_cram_memctl_as_ISim_[sft]sim
+tb_n2_cram_memctl_stim
Index: nexys2/tb/Makefile
===================================================================
--- nexys2/tb/Makefile (nonexistent)
+++ nexys2/tb/Makefile (revision 7)
@@ -0,0 +1,33 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now
+# 2010-05-28 295 1.0.1 add tb_.._dummy's
+# 2007-09-23 84 1.0 Initial version
+#
+EXE_all = tb_nexys2_dummy tb_nexys2_fusp_dummy tb_n2_cram_memctl_as
+#
+ISE_PATH = xc3s1200e-fg320-4
+#
+.phony : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean isim_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+include $(RETROBASE)/rtl/vlib/Makefile.isim
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(VBOM_all:.vbom=.dep_isim)
+include $(wildcard *.o.dep_ghdl)
+#
Index: nexys2/tb
===================================================================
--- nexys2/tb (nonexistent)
+++ nexys2/tb (revision 7)
nexys2/tb
Property changes :
Added: svn:ignore
## -0,0 +1,39 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_nexys2_dummy
+tb_nexys2_fusp_dummy
+tb_n2_cram_memctl_as
+tb_n2_cram_memctl_as_[sft]sim
+tb_n2_cram_memctl_as_ISim
+tb_n2_cram_memctl_as_ISim_[sft]sim
+tb_n2_cram_memctl_stim
Index: nexys2/nexys2lib.vhd
===================================================================
--- nexys2/nexys2lib.vhd (nonexistent)
+++ nexys2/nexys2lib.vhd (revision 7)
@@ -0,0 +1,136 @@
+-- $Id: nexys2lib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: nexys2lib
+-- Description: Nexys 2 components
+--
+-- Dependencies: -
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
+-- 2010-05-23 294 1.0.2 add n2_cram_dummy;
+-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl
+-- 2010-05-21 292 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package nexys2lib is
+
+component nexys2_aif is -- NEXYS 2, abstract iface, base
+ port (
+ CLK : in slbit; -- clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- s3 switches
+ I_BTN : in slv4; -- s3 buttons
+ O_LED : out slv8; -- s3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end component;
+
+component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
+ port (
+ CLK : in slbit; -- clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- s3 switches
+ I_BTN : in slv4; -- s3 buttons
+ O_LED : out slv8; -- s3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end component;
+
+component n2_cram_dummy is -- CRAM protection dummy
+ port (
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end component;
+
+component n2_cram_memctl_as is -- CRAM driver (async+page mode)
+ generic (
+ READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
+ READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
+ WRITEDELAY : positive := 3); -- write delay in clock cycles
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ REQ : in slbit; -- request
+ WE : in slbit; -- write enable
+ BUSY : out slbit; -- controller busy
+ ACK_R : out slbit; -- acknowledge read
+ ACK_W : out slbit; -- acknowledge write
+ ACT_R : out slbit; -- signal active read
+ ACT_W : out slbit; -- signal active write
+ ADDR : in slv22; -- address (32 bit word address)
+ BE : in slv4; -- byte enable
+ DI : in slv32; -- data in (memory view)
+ DO : out slv32; -- data out (memory view)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end component;
+
+end nexys2lib;
Index: nexys2/n2_cram_memctl_as.vhd
===================================================================
--- nexys2/n2_cram_memctl_as.vhd (nonexistent)
+++ nexys2/n2_cram_memctl_as.vhd (revision 7)
@@ -0,0 +1,562 @@
+-- $Id: n2_cram_memctl_as.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: n2_cram_memctl_as - syn
+-- Description: nexys2: CRAM driver - async and page mode
+--
+-- Dependencies: vlib/xlib/iob_reg_o
+-- vlib/xlib/iob_reg_o_gen
+-- vlib/xlib/iob_reg_io_gen
+-- Test bench: tb/tb_n2_cram_memctl
+-- fw_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7
+-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7
+-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
+-- cycle;
+-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
+-- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1
+-- 2010-05-23 293 1.0 Initial version
+--
+-- Notes:
+-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests
+-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A
+-- short READ1 delay works in sim, but not on fpga where the data od the
+-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt).
+-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is
+-- 40ns or 50 ns, only T_apa 60 ns fails !
+-- Unclear what is wrong here, the timing of the memory model seems ok.
+-- 2. There is no 'bus-turn-around' cycle needed for a write->read change
+-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit
+-- transition simultaneously. The FPGA will go high-Z quickly, the memory
+-- low-Z delay by the IOB and internal memory delays. No clash.
+-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change.
+-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with
+-- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
+-- Again no clash due to the 1 cycle delay.
+--
+-- Timing of some signals:
+--
+-- single read request:
+--
+-- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1|
+-- 0 20 40 60 80 100 120
+-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
+--
+-- REQ _______|^^^^^|_____________________________________________
+-- WE ___________________________________________________________
+--
+-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+-- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+--
+-- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h
+-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________
+-- ACK_R ___________________________________________________________|^^^^^^^|_
+--
+-- single write request:
+--
+-- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle |
+-- 0 20 40 60 80 100 120
+-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|
+--
+-- REQ _______|^^^^^|______________________________________
+-- WE _______|^^^^^|______________________________________
+--
+-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+-- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_
+-- IOB_OE ____________________________________________________
+-- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____
+--
+-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________
+-- ACK_W __________________________________________|^^^^^^^|_
+--
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity n2_cram_memctl_as is -- CRAM driver (async+page mode)
+ generic (
+ READ0DELAY : positive := 2; -- read word 0 delay in clock cycles
+ READ1DELAY : positive := 2; -- read word 1 delay in clock cycles
+ WRITEDELAY : positive := 3); -- write delay in clock cycles
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ REQ : in slbit; -- request
+ WE : in slbit; -- write enable
+ BUSY : out slbit; -- controller busy
+ ACK_R : out slbit; -- acknowledge read
+ ACK_W : out slbit; -- acknowledge write
+ ACT_R : out slbit; -- signal active read
+ ACT_W : out slbit; -- signal active write
+ ADDR : in slv22; -- address (32 bit word address)
+ BE : in slv4; -- byte enable
+ DI : in slv32; -- data in (memory view)
+ DO : out slv32; -- data out (memory view)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end n2_cram_memctl_as;
+
+
+architecture syn of n2_cram_memctl_as is
+
+ type state_type is (
+ s_idle, -- s_idle: wait for req
+ s_rdinit, -- s_rdinit: read init cycle
+ s_rdwait0, -- s_rdwait0: read wait low word
+ s_rdget0, -- s_rdget0: read get low word
+ s_rdwait1, -- s_rdwait1: read wait high word
+ s_rdget1, -- s_rdget1: read get high word
+ s_wrinit, -- s_wrinit: write init cycle
+ s_wrwait0, -- s_rdwait0: write wait 1st word
+ s_wrput0, -- s_rdput0: write put 1st word
+ s_wrini1, -- s_wrini1: write init 2nd word
+ s_wrwait1, -- s_wrwait1: write wait 2nd word
+ s_wrput1 -- s_wrput1: write put 2nd word
+ );
+
+ type regs_type is record
+ state : state_type; -- state
+ ackr : slbit; -- signal ack_r
+ addr0 : slbit; -- current addr0
+ be2nd : slv2; -- be's of 2nd write cycle
+ cntdly : slv2; -- wait delay counter
+ cntce : slv7; -- ce counter
+ fidle : slbit; -- force idle flag
+ memdo0 : slv16; -- mem data out, low word
+ memdi : slv32; -- mem data in
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ s_idle, --
+ '0', -- ackr
+ '0', -- addr0
+ "00", -- be2nd
+ (others=>'0'), -- cntdly
+ (others=>'0'), -- cntce
+ '0', -- fidle
+ (others=>'0'), -- memdo0
+ (others=>'0') -- memdi
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ signal CLK_180 : slbit := '0';
+ signal MEM_CE_N : slbit := '1';
+ signal MEM_BE_N : slv2 := "11";
+ signal MEM_WE_N : slbit := '1';
+ signal MEM_OE_N : slbit := '1';
+ signal BE_CE : slbit := '0';
+ signal ADDRH_CE : slbit := '0';
+ signal ADDR0_CE : slbit := '0';
+ signal ADDR0 : slbit := '0';
+ signal DATA_CEI : slbit := '0';
+ signal DATA_CEO : slbit := '0';
+ signal DATA_OE : slbit := '0';
+ signal MEM_DO : slv16 := (others=>'0');
+ signal MEM_DI : slv16 := (others=>'0');
+
+-- these attributes aren't accepted by ghdl 0.26
+-- attribute s : string;
+-- attribute s of I_MEM_WAIT : signal is "true";
+
+begin
+
+ CLK_180 <= not CLK;
+
+ IOB_MEM_CE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => '1',
+ DO => MEM_CE_N,
+ PAD => O_MEM_CE_N
+ );
+
+ IOB_MEM_BE : iob_reg_o_gen
+ generic map (
+ DWIDTH => 2,
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => BE_CE,
+ DO => MEM_BE_N,
+ PAD => O_MEM_BE_N
+ );
+
+ IOB_MEM_WE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK_180,
+ CE => '1',
+ DO => MEM_WE_N,
+ PAD => O_MEM_WE_N
+ );
+
+ IOB_MEM_OE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => '1',
+ DO => MEM_OE_N,
+ PAD => O_MEM_OE_N
+ );
+
+ IOB_MEM_ADDRH : iob_reg_o_gen
+ generic map (
+ DWIDTH => 22)
+ port map (
+ CLK => CLK,
+ CE => ADDRH_CE,
+ DO => ADDR,
+ PAD => O_MEM_ADDR(22 downto 1)
+ );
+
+ IOB_MEM_ADDR0 : iob_reg_o
+ port map (
+ CLK => CLK,
+ CE => ADDR0_CE,
+ DO => ADDR0,
+ PAD => O_MEM_ADDR(0)
+ );
+
+ IOB_MEM_DATA : iob_reg_io_gen
+ generic map (
+ DWIDTH => 16,
+ PULL => "KEEP")
+ port map (
+ CLK => CLK,
+ CEI => DATA_CEI,
+ CEO => DATA_CEO,
+ OE => DATA_OE,
+ DI => MEM_DO,
+ DO => MEM_DI,
+ PAD => IO_MEM_DATA
+ );
+
+ O_MEM_ADV_N <= '0';
+ O_MEM_CLK <= '0';
+ O_MEM_CRE <= '0';
+ O_FLA_CE_N <= '1';
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+ variable ibusy : slbit := '0';
+ variable iackw : slbit := '0';
+ variable iactr : slbit := '0';
+ variable iactw : slbit := '0';
+ variable imem_ce : slbit := '0';
+ variable imem_be : slv2 := "00";
+ variable imem_we : slbit := '0';
+ variable imem_oe : slbit := '0';
+ variable ibe_ce : slbit := '0';
+ variable iaddrh_ce : slbit := '0';
+ variable iaddr0_ce : slbit := '0';
+ variable iaddr0 : slbit := '0';
+ variable idata_cei : slbit := '0';
+ variable idata_ceo : slbit := '0';
+ variable idata_oe : slbit := '0';
+
+ procedure do_dispatch(nstate : out state_type;
+ iaddrh_ce : out slbit;
+ iaddr0_ce : out slbit;
+ iaddr0 : out slbit;
+ ibe_ce : out slbit;
+ imem_be : out slv2;
+ imem_ce : out slbit;
+ imem_oe : out slbit;
+ nbe2nd : out slv2) is
+ begin
+ iaddrh_ce := '1'; -- latch address (high part)
+ iaddr0_ce := '1'; -- latch address 0 bit
+ ibe_ce := '1'; -- latch be's
+ imem_ce := '1'; -- ce CRAM next cycle
+ nbe2nd := "00"; -- assume no 2nd write cycle
+ if WE = '0' then -- if READ requested
+ iaddr0 := '0'; -- go first for low word
+ imem_be := "11"; -- on read always on
+ imem_oe := '1'; -- oe CRAM next cycle
+ nstate := s_rdinit; -- next: read init part
+ else -- if WRITE requested
+ if BE(1 downto 0) /= "00" then -- low word write
+ iaddr0 := '0'; -- access word 0
+ imem_be := BE(1 downto 0); -- set be's for 1st cycle
+ nbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle
+ else -- high word write
+ iaddr0 := '1'; -- access word 1
+ imem_be := BE(3 downto 2); -- set be's for 1st cycle
+ end if;
+ nstate := s_wrinit; -- next: write init part
+ end if;
+ end procedure do_dispatch;
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+ n.ackr := '0';
+
+ ibusy := '0';
+ iackw := '0';
+ iactr := '0';
+ iactw := '0';
+
+ imem_ce := '0';
+ imem_be := "11";
+ imem_we := '0';
+ imem_oe := '0';
+ ibe_ce := '0';
+ iaddrh_ce := '0';
+ iaddr0_ce := '0';
+ iaddr0 := '0';
+ idata_cei := '0';
+ idata_ceo := '0';
+ idata_oe := '0';
+
+ if unsigned(r.cntdly) /= 0 then
+ n.cntdly := unsigned(r.cntdly) - 1;
+ end if;
+
+ case r.state is
+ when s_idle => -- s_idle: wait for req
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+
+ when s_rdinit => -- s_rdinit: read init cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ n.cntdly:= conv_std_logic_vector(READ0DELAY-1, n.cntdly'length);
+ n.state := s_rdwait0; -- next: wait
+
+ when s_rdwait0 => -- s_rdwait0: read wait low word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_rdget0; -- next: get low word
+ end if;
+
+ when s_rdget0 => -- s_rdget0: read get low word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ idata_cei := '1'; -- latch input data
+ iaddr0_ce := '1'; -- latch address 0 bit
+ iaddr0 := '1'; -- now go for high word
+ n.cntdly:= conv_std_logic_vector(READ1DELAY-1, n.cntdly'length);
+ n.state := s_rdwait1; -- next: wait high word
+
+ when s_rdwait1 => -- s_rdwait1: read wait high word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_oe := '1'; -- oe CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_rdget1; -- next: get low word
+ end if; --
+
+ when s_rdget1 => -- s_rdget1: read get high word
+ iactr := '1'; -- signal mem read
+ n.memdo0:= MEM_DO; -- save low word data
+ idata_cei := '1'; -- latch input data
+ n.ackr := '1'; -- ACK_R next cycle
+ n.state := s_idle; -- next: wait next request
+ if r.fidle = '1' then -- forced idle cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ else
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+ end if;
+
+ when s_wrinit => -- s_wrinit: write init cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ iackw := '1'; -- signal write done (all latched)
+ idata_ceo:= '1'; -- latch output data
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM in half cycle
+ n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length);
+ n.state := s_wrwait0; -- next: wait
+
+ when s_wrwait0 => -- s_rdput0: write wait 1st word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_wrput0; -- next: put 1st word
+ end if;
+
+ when s_wrput0 => -- s_rdput0: write put 1st word
+ iactw := '1'; -- signal mem write
+ imem_we := '0'; -- deassert we CRAM in half cycle
+ if r.be2nd /= "00" then
+ ibusy := '1'; -- signal busy, unable to handle req
+ imem_ce := '1'; -- ce CRAM next cycle
+ iaddr0_ce := '1'; -- latch address 0 bit
+ iaddr0 := '1'; -- now go for high word
+ ibe_ce := '1'; -- latch be's
+ imem_be := r.be2nd; -- now be's of high word
+ n.state := s_wrini1; -- next: start 2nd write
+ else
+ n.state := s_idle; -- next: wait next request
+ if r.fidle = '1' then -- forced idle cycle
+ ibusy := '1'; -- signal busy
+ else
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+ end if;
+ end if;
+
+ when s_wrini1 => -- s_wrini1: write init 2nd word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ idata_ceo:= '1'; -- latch output data
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM in half cycle
+ n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length);
+ n.state := s_wrwait1; -- next: wait
+
+ when s_wrwait1 => -- s_wrwait1: write wait 2nd word
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := '1'; -- ce CRAM next cycle
+ imem_we := '1'; -- we CRAM next cycle
+ if unsigned(r.cntdly) = 0 then -- wait expired ?
+ n.state := s_wrput1; -- next: put 2nd word
+ end if;
+
+ when s_wrput1 => -- s_wrput1: write put 2nd word
+ iactw := '1'; -- signal mem write
+ imem_we := '0'; -- deassert we CRAM in half cycle
+ n.state := s_idle; -- next: wait next request
+ if r.fidle = '1' then -- forced idle cycle
+ ibusy := '1'; -- signal busy, unable to handle req
+ else
+ if REQ = '1' then -- if IO requested
+ do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0,
+ ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd);
+ end if;
+ end if;
+
+ when others => null;
+ end case;
+
+ if imem_ce = '0' then -- if cmem not active
+ n.cntce := (others=>'0'); -- clear counter
+ n.fidle := '0'; -- clear force idle flag
+ else -- if cmem active
+ if unsigned(r.cntce) >= 127 then -- if max ce count expired
+ n.fidle := '1'; -- set forced idle flag
+ else -- if max ce count not yet reached
+ n.cntce := unsigned(r.cntce) + 1; -- increment counter
+ end if;
+ end if;
+
+ if iaddrh_ce = '1' then -- if addresses are latched
+ n.memdi := DI; -- latch data too...
+ end if;
+
+ if iaddr0_ce = '1' then -- if address bit 0 changed
+ n.addr0 := iaddr0; -- mirror it in state regs
+ end if;
+
+ N_REGS <= n;
+
+ MEM_CE_N <= not imem_ce;
+ MEM_WE_N <= not imem_we;
+ MEM_BE_N <= not imem_be;
+ MEM_OE_N <= not imem_oe;
+
+ if r.addr0 = '0' then
+ MEM_DI <= r.memdi(15 downto 0);
+ else
+ MEM_DI <= r.memdi(31 downto 16);
+ end if;
+
+ BE_CE <= ibe_ce;
+ ADDRH_CE <= iaddrh_ce;
+ ADDR0_CE <= iaddr0_ce;
+ ADDR0 <= iaddr0;
+ DATA_CEI <= idata_cei;
+ DATA_CEO <= idata_ceo;
+ DATA_OE <= idata_oe;
+
+ BUSY <= ibusy;
+ ACK_R <= r.ackr;
+ ACK_W <= iackw;
+ ACT_R <= iactr;
+ ACT_W <= iactw;
+
+ DO <= MEM_DO & r.memdo0;
+
+ end process proc_next;
+
+end syn;
Index: nexys2/nexys2_pins_pmb0_rs232.ucf
===================================================================
--- nexys2/nexys2_pins_pmb0_rs232.ucf (nonexistent)
+++ nexys2/nexys2_pins_pmb0_rs232.ucf (revision 7)
@@ -0,0 +1,12 @@
+## $Id: nexys2_pins_pmb0_rs232.ucf 311 2010-06-30 17:52:37Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2010-05-28 295 1.0 Initial version
+##
+## Pmod connector B top / usage RS232 for FTDI USB serport -------------------
+##
+NET "O_FUSP_RTS_N" LOC = "m13" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
+NET "I_FUSP_CTS_N" LOC = "r18" | IOSTANDARD=LVCMOS33 | PULLDOWN;
+NET "I_FUSP_RXD" LOC = "r15" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "O_FUSP_TXD" LOC = "t17" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
Index: nexys2/n2_cram_memctl_as.vbom
===================================================================
--- nexys2/n2_cram_memctl_as.vbom (nonexistent)
+++ nexys2/n2_cram_memctl_as.vbom (revision 7)
@@ -0,0 +1,9 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/xlib/xlib.vhd
+# components
+../../vlib/xlib/iob_reg_o.vbom
+../../vlib/xlib/iob_reg_o_gen.vbom
+../../vlib/xlib/iob_reg_io_gen.vbom
+# design
+n2_cram_memctl_as.vhd
Index: nexys2/n2_cram_dummy.vhd
===================================================================
--- nexys2/n2_cram_dummy.vhd (nonexistent)
+++ nexys2/n2_cram_dummy.vhd (revision 7)
@@ -0,0 +1,65 @@
+-- $Id: n2_cram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: n2_cram_dummy - syn
+-- Description: nexys2: CRAM protection dummy
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-28 295 1.0.1 use _ADV_N
+-- 2010-05-21 292 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity n2_cram_dummy is -- CRAM protection dummy
+ port (
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16 -- cram: data lines
+ );
+end n2_cram_dummy;
+
+
+architecture syn of n2_cram_dummy is
+begin
+
+ O_MEM_CE_N <= '1'; -- disable cram chip
+ O_MEM_BE_N <= "11";
+ O_MEM_WE_N <= '1';
+ O_MEM_OE_N <= '1';
+ O_MEM_ADV_N <= '1';
+ O_MEM_CLK <= '0';
+ O_MEM_CRE <= '0';
+ O_FLA_CE_N <= '1';
+ O_MEM_ADDR <= (others=>'0');
+ IO_MEM_DATA <= (others=>'0');
+
+end syn;
Index: nexys2/Makefile
===================================================================
--- nexys2/Makefile (nonexistent)
+++ nexys2/Makefile (revision 7)
@@ -0,0 +1,23 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-05-23 293 1.0 Initial version (cloned..)
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+ISE_PATH = xc3s1200e-fg320-4
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: nexys2/nexys2_pins.ucf
===================================================================
--- nexys2/nexys2_pins.ucf (nonexistent)
+++ nexys2/nexys2_pins.ucf (revision 7)
@@ -0,0 +1,123 @@
+## $Id: nexys2_pins.ucf 311 2010-06-30 17:52:37Z mueller $
+##
+## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
+## internal RS232
+## human I/O (switches, buttons, leds, display)
+## cram
+##
+## Revision History:
+## Date Rev Version Comment
+## 2010-05-23 294 1.0.1 use ADV_N rather ADV
+## 2010-05-16 291 1.0 Initial version
+##
+## Note: default is DRIVE=12 | SLEW=SLOW
+##
+## clocks --------------------------------------------------------------------
+NET "CLK" LOC = "b8" | IOSTANDARD=LVCMOS33;
+##
+## RS232 interface -----------------------------------------------------------
+NET "I_RXD" LOC = "u6" | IOSTANDARD=LVCMOS33;
+NET "O_TXD" LOC = "p9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
+##
+## switches and buttons ------------------------------------------------------
+NET "I_SWI<0>" LOC = "g18" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<1>" LOC = "h18" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<2>" LOC = "k18" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<3>" LOC = "k17" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<4>" LOC = "l14" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<5>" LOC = "l13" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<6>" LOC = "n17" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<7>" LOC = "r17" | IOSTANDARD=LVCMOS33;
+##
+NET "I_BTN<0>" LOC = "b18" | IOSTANDARD=LVCMOS33;
+NET "I_BTN<1>" LOC = "d18" | IOSTANDARD=LVCMOS33;
+NET "I_BTN<2>" LOC = "e18" | IOSTANDARD=LVCMOS33;
+NET "I_BTN<3>" LOC = "h13" | IOSTANDARD=LVCMOS33;
+##
+## LEDs ----------------------------------------------------------------------
+NET "O_LED<0>" LOC = "j14" | IOSTANDARD=LVCMOS33;
+NET "O_LED<1>" LOC = "j15" | IOSTANDARD=LVCMOS33;
+NET "O_LED<2>" LOC = "k15" | IOSTANDARD=LVCMOS33;
+NET "O_LED<3>" LOC = "k14" | IOSTANDARD=LVCMOS33;
+NET "O_LED<4>" LOC = "e16" | IOSTANDARD=LVCMOS33;
+NET "O_LED<5>" LOC = "p16" | IOSTANDARD=LVCMOS33;
+NET "O_LED<6>" LOC = "e4" | IOSTANDARD=LVCMOS33;
+NET "O_LED<7>" LOC = "p4" | IOSTANDARD=LVCMOS33;
+NET "O_LED<*>" DRIVE=12 | SLEW=SLOW;
+##
+## 7 segment display ---------------------------------------------------------
+NET "O_ANO_N<0>" LOC = "f17" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<1>" LOC = "h17" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<2>" LOC = "c18" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<3>" LOC = "f15" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW;
+##
+NET "O_SEG_N<0>" LOC = "l18" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<1>" LOC = "f18" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<2>" LOC = "d17" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<3>" LOC = "d16" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<4>" LOC = "g14" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<5>" LOC = "j17" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<6>" LOC = "h14" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<7>" LOC = "c17" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW;
+##
+## CRAM ----------------------------------------------------------------------
+NET "O_MEM_CE_N" LOC = "r6" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_WE_N" LOC = "n7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_OE_N" LOC = "t2" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_BE_N<0>" LOC = "k5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<1>" LOC = "k4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_ADV_N" LOC = "j4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_CLK" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_CRE" LOC = "p7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "I_MEM_WAIT" LOC = "f5" | IOSTANDARD=LVCMOS33 | PULLDOWN;
+##
+NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_ADDR<0>" LOC = "j1" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<1>" LOC = "j2" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<2>" LOC = "h4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<3>" LOC = "h1" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<4>" LOC = "h2" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<5>" LOC = "j5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<6>" LOC = "h3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<7>" LOC = "h6" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<8>" LOC = "f1" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<9>" LOC = "g3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<10>" LOC = "g6" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<11>" LOC = "g5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<12>" LOC = "g4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<13>" LOC = "f2" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<14>" LOC = "e1" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<15>" LOC = "m5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<16>" LOC = "e2" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<17>" LOC = "c2" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<18>" LOC = "c1" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<19>" LOC = "d2" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<20>" LOC = "k3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<21>" LOC = "d1" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<22>" LOC = "k6" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST;
+##
+NET "IO_MEM_DATA<0>" LOC = "l1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<1>" LOC = "l4" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<2>" LOC = "l6" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<3>" LOC = "m4" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<4>" LOC = "n5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<5>" LOC = "p1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<6>" LOC = "p2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<7>" LOC = "r2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<8>" LOC = "l3" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<9>" LOC = "l5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<10>" LOC = "m3" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<11>" LOC = "m6" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<12>" LOC = "l2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<13>" LOC = "n4" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<14>" LOC = "r3" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<15>" LOC = "t1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
+##
Index: nexys2/n2_cram_dummy.vbom
===================================================================
--- nexys2/n2_cram_dummy.vbom (nonexistent)
+++ nexys2/n2_cram_dummy.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../../vlib/slvtypes.vhd
+# components
+# design
+n2_cram_dummy.vhd
Index: nexys2
===================================================================
--- nexys2 (nonexistent)
+++ nexys2 (revision 7)
nexys2
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: s3board/tb/tb_s3board_fusp.vhd
===================================================================
--- s3board/tb/tb_s3board_fusp.vhd (nonexistent)
+++ s3board/tb/tb_s3board_fusp.vhd (revision 7)
@@ -0,0 +1,220 @@
+-- $Id: tb_s3board_fusp.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_s3board_fusp - sim
+-- Description: Test bench for s3board (base+fusp)
+--
+-- Dependencies: vlib/rri/tb/rritb_core
+-- tb_s3board_core
+-- vlib/serport/serport_uart_rxtx
+-- s3board_fusp_aif [UUT]
+--
+-- To test: generic, any s3board_fusp_aif target
+--
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
+-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
+-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8
+-- 2010-05-01 286 1.0 Initial version (derived from tb_s3board)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.rrilib.all;
+use work.rritblib.all;
+use work.serport.all;
+use work.s3boardlib.all;
+use work.simlib.all;
+use work.simbus.all;
+
+entity tb_s3board_fusp is
+end tb_s3board_fusp;
+
+architecture sim of tb_s3board_fusp is
+
+ signal CLK : slbit := '0';
+
+ signal RESET : slbit := '0';
+ signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXERR : slbit := '0';
+ signal RXACT : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal RX_HOLD : slbit := '0';
+
+ signal I_RXD : slbit := '1';
+ signal O_TXD : slbit := '1';
+ signal I_SWI : slv8 := (others=>'0');
+ signal I_BTN : slv4 := (others=>'0');
+ signal O_LED : slv8 := (others=>'0');
+ signal O_ANO_N : slv4 := (others=>'0');
+ signal O_SEG_N : slv8 := (others=>'0');
+
+ signal O_MEM_CE_N : slv2 := (others=>'1');
+ signal O_MEM_BE_N : slv4 := (others=>'1');
+ signal O_MEM_WE_N : slbit := '1';
+ signal O_MEM_OE_N : slbit := '1';
+ signal O_MEM_ADDR : slv18 := (others=>'Z');
+ signal IO_MEM_DATA : slv32 := (others=>'0');
+
+ signal O_FUSP_RTS_N : slbit := '0';
+ signal I_FUSP_CTS_N : slbit := '0';
+ signal I_FUSP_RXD : slbit := '1';
+ signal O_FUSP_TXD : slbit := '1';
+
+ signal UART_RESET : slbit := '0';
+ signal UART_RXD : slbit := '1';
+ signal UART_TXD : slbit := '1';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal R_PORTSEL : slbit := '0';
+
+ constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant setup_time : time := 5 ns;
+ constant c2out_time : time := 10 ns;
+
+begin
+
+ TBCORE : rritb_core
+ generic map (
+ CLK_PERIOD => clock_period,
+ CLK_OFFSET => clock_offset,
+ SETUP_TIME => setup_time,
+ C2OUT_TIME => c2out_time)
+ port map (
+ CLK => CLK,
+ RX_DATA => TXDATA,
+ RX_VAL => TXENA,
+ RX_HOLD => RX_HOLD,
+ TX_DATA => RXDATA,
+ TX_ENA => RXVAL
+ );
+
+ RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
+
+ S3CORE : entity work.tb_s3board_core
+ port map (
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ UUT : s3board_fusp_aif
+ port map (
+ CLK => CLK,
+ I_RXD => I_RXD,
+ O_TXD => O_TXD,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA,
+ O_FUSP_RTS_N => O_FUSP_RTS_N,
+ I_FUSP_CTS_N => I_FUSP_CTS_N,
+ I_FUSP_RXD => I_FUSP_RXD,
+ O_FUSP_TXD => O_FUSP_TXD
+ );
+
+ UART : serport_uart_rxtx
+ generic map (
+ CDWIDTH => CLKDIV'length)
+ port map (
+ CLK => CLK,
+ RESET => UART_RESET,
+ CLKDIV => CLKDIV,
+ RXSD => UART_RXD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD => UART_TXD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
+ O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
+ begin
+
+ if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
+ I_RXD <= UART_TXD; -- write port 0 inputs
+ UART_RXD <= O_TXD; -- get port 0 outputs
+ RTS_N <= '0';
+ I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
+ I_FUSP_CTS_N <= '0';
+ else -- otherwise use pmod1 rs232
+ I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
+ I_FUSP_CTS_N <= CTS_N;
+ UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
+ RTS_N <= O_FUSP_RTS_N;
+ I_RXD <= '1'; -- port 0 inputs to idle state
+ end if;
+
+ end process proc_port_mux;
+
+ proc_moni: process
+ variable oline : line;
+ begin
+
+ loop
+ wait until CLK'event and CLK='1';
+ wait for c2out_time;
+
+ if RXERR = '1' then
+ writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
+ writeline(output, oline);
+ end if;
+
+ end loop;
+
+ end process proc_moni;
+
+ proc_simbus: process (SB_VAL)
+ begin
+ if SB_VAL'event and to_x01(SB_VAL)='1' then
+ if SB_ADDR = sbaddr_portsel then
+ R_PORTSEL <= to_x01(SB_DATA(0));
+ end if;
+ end if;
+ end process proc_simbus;
+
+end sim;
Index: s3board/tb/tb_s3board_fusp.vbom
===================================================================
--- s3board/tb/tb_s3board_fusp.vbom (nonexistent)
+++ s3board/tb/tb_s3board_fusp.vbom (revision 7)
@@ -0,0 +1,20 @@
+# Not meant for direct top level usage. Used with
+# tb_s3board_fusp_(....)[_ssim].vbom and config
+# lines to generate the different cases.
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/rri/rrilib.vhd
+../../../vlib/rri/tb/rritblib.vhd
+../../../vlib/serport/serport.vhd
+../s3boardlib.vbom
+../../../vlib/simlib/simlib.vhd
+../../../vlib/simlib/simbus.vhd
+# components
+../../../vlib/rri/tb/rritb_core.vbom
+tb_s3board_core.vbom
+../../../vlib/serport/serport_uart_rxtx.vbom
+s3board_fusp_aif : s3board_fusp_dummy.vbom
+# design
+tb_s3board_fusp.vhd
+@top:tb_s3board_fusp
Index: s3board/tb/tbw.dat
===================================================================
--- s3board/tb/tbw.dat (nonexistent)
+++ s3board/tb/tbw.dat (revision 7)
@@ -0,0 +1,6 @@
+# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
+#
+[tb_s3board_dummy]
+tb_rriext_fifo_rx =
+tb_rriext_fifo_tx =
+tb_rriext_conf =
Index: s3board/tb/tb_s3board_core.vhd
===================================================================
--- s3board/tb/tb_s3board_core.vhd (nonexistent)
+++ s3board/tb/tb_s3board_core.vhd (revision 7)
@@ -0,0 +1,100 @@
+-- $Id: tb_s3board_core.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_s3board_core - sim
+-- Description: Test bench for s3board - core device handling
+--
+-- Dependencies: vlib/parts/issi/is61lv25616al
+--
+-- To test: generic, any s3board target
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
+-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+use work.simbus.all;
+
+entity tb_s3board_core is
+ port (
+ I_SWI : out slv8; -- s3 switches
+ I_BTN : out slv4; -- s3 buttons
+ O_MEM_CE_N : in slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : in slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : in slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : in slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : in slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32 -- sram: data lines
+ );
+end tb_s3board_core;
+
+architecture sim of tb_s3board_core is
+
+ signal R_SWI : slv8 := (others=>'0');
+ signal R_BTN : slv4 := (others=>'0');
+
+ constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8);
+ constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8);
+
+begin
+
+ MEM_L : entity work.is61lv25616al
+ port map (
+ CE_N => O_MEM_CE_N(0),
+ OE_N => O_MEM_OE_N,
+ WE_N => O_MEM_WE_N,
+ UB_N => O_MEM_BE_N(1),
+ LB_N => O_MEM_BE_N(0),
+ ADDR => O_MEM_ADDR,
+ DATA => IO_MEM_DATA(15 downto 0)
+ );
+
+ MEM_U : entity work.is61lv25616al
+ port map (
+ CE_N => O_MEM_CE_N(1),
+ OE_N => O_MEM_OE_N,
+ WE_N => O_MEM_WE_N,
+ UB_N => O_MEM_BE_N(3),
+ LB_N => O_MEM_BE_N(2),
+ ADDR => O_MEM_ADDR,
+ DATA => IO_MEM_DATA(31 downto 16)
+ );
+
+ proc_simbus: process (SB_VAL)
+ begin
+ if SB_VAL'event and to_x01(SB_VAL)='1' then
+ if SB_ADDR = sbaddr_swi then
+ R_SWI <= to_x01(SB_DATA(R_SWI'range));
+ end if;
+ if SB_ADDR = sbaddr_btn then
+ R_BTN <= to_x01(SB_DATA(R_BTN'range));
+ end if;
+ end if;
+ end process proc_simbus;
+
+ I_SWI <= R_SWI;
+ I_BTN <= R_BTN;
+
+end sim;
Index: s3board/tb/tb_s3board_core.vbom
===================================================================
--- s3board/tb/tb_s3board_core.vbom (nonexistent)
+++ s3board/tb/tb_s3board_core.vbom (revision 7)
@@ -0,0 +1,10 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/serport/serport.vhd
+../../../vlib/simlib/simbus.vhd
+# components
+../../../vlib/serport/serport_uart_rx.vbom
+../../../vlib/serport/serport_uart_tx.vbom
+../../issi/is61lv25616al.vbom
+# design
+tb_s3board_core.vhd
Index: s3board/tb/Makefile
===================================================================
--- s3board/tb/Makefile (nonexistent)
+++ s3board/tb/Makefile (revision 7)
@@ -0,0 +1,35 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-05-16 291 1.2.2 rename tb_memctl_s3sram->tb_s3_sram_memctl
+# 2010-05-01 286 1.2.1 add tb_s3board_usp_dummy
+# 2009-11-21 252 1.2 add ISim support
+# 2007-11-26 98 1.1 use make includes
+# 2007-09-23 84 1.0 Initial version
+#
+EXE_all = tb_s3board_dummy tb_s3board_fusp_dummy tb_s3_sram_memctl
+#
+ISE_PATH = xc3s1000-ft256-4
+#
+.phony : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean isim_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+include $(RETROBASE)/rtl/vlib/Makefile.isim
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(VBOM_all:.vbom=.dep_isim)
+include $(wildcard *.o.dep_ghdl)
+#
Index: s3board/tb/.cvsignore
===================================================================
--- s3board/tb/.cvsignore (nonexistent)
+++ s3board/tb/.cvsignore (revision 7)
@@ -0,0 +1,13 @@
+tb_s3board_dummy
+tb_s3board_dummy_[sft]sim
+tb_s3board_dummy_ISim
+tb_s3board_dummy_ISim_[sft]sim
+tb_s3board_fusp_dummy
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+tb_s3_sram_memctl
+tb_s3_sram_memctl_[sft]sim
+tb_s3_sram_memctl_stim
+tb_s3_sram_memctl_ISim
+tb_s3_sram_memctl_ISim_[sft]sim
Index: s3board/tb
===================================================================
--- s3board/tb (nonexistent)
+++ s3board/tb (revision 7)
s3board/tb
Property changes :
Added: svn:ignore
## -0,0 +1,45 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_s3board_dummy
+tb_s3board_dummy_[sft]sim
+tb_s3board_dummy_ISim
+tb_s3board_dummy_ISim_[sft]sim
+tb_s3board_fusp_dummy
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+tb_s3_sram_memctl
+tb_s3_sram_memctl_[sft]sim
+tb_s3_sram_memctl_stim
+tb_s3_sram_memctl_ISim
+tb_s3_sram_memctl_ISim_[sft]sim
Index: s3board/s3_dispdrv.vbom
===================================================================
--- s3board/s3_dispdrv.vbom (nonexistent)
+++ s3board/s3_dispdrv.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../../vlib/slvtypes.vhd
+# components
+# design
+s3_dispdrv.vhd
Index: s3board/s3_humanio_rri.vbom
===================================================================
--- s3board/s3_humanio_rri.vbom (nonexistent)
+++ s3board/s3_humanio_rri.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/rri/rrilib.vhd
+s3boardlib.vbom
+# components
+s3_humanio.vbom
+# design
+s3_humanio_rri.vhd
Index: s3board/s3_rs232_iob_int_ext.vhd
===================================================================
--- s3board/s3_rs232_iob_int_ext.vhd (nonexistent)
+++ s3board/s3_rs232_iob_int_ext.vhd (revision 7)
@@ -0,0 +1,106 @@
+-- $Id: s3_rs232_iob_int_ext.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_rs232_iob_int_ext - syn
+-- Description: iob's for internal + external rs232, with select
+--
+-- Dependencies: s3_rs232_iob_int
+-- s3_rs232_iob_ext
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-17 278 1.0 Initial version
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.s3boardlib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity s3_rs232_iob_int_ext is -- iob's for int+ext rs232, with select
+ port (
+ CLK : in slbit; -- clock
+ SEL : in slbit; -- select, '0' for port 0
+ RXD : out slbit; -- receive data (board view)
+ TXD : in slbit; -- transmit data (board view)
+ CTS_N : out slbit; -- clear to send (act. low)
+ RTS_N : in slbit; -- request to send (act. low)
+ I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
+ O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
+ I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
+ O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
+ I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
+ O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
+ );
+end s3_rs232_iob_int_ext;
+
+architecture syn of s3_rs232_iob_int_ext is
+ signal RXD0 : slbit := '0';
+ signal TXD0 : slbit := '0';
+ signal RXD1 : slbit := '0';
+ signal TXD1 : slbit := '0';
+ signal CTS1_N : slbit := '0';
+ signal RTS1_N : slbit := '0';
+begin
+
+ P0 : s3_rs232_iob_int
+ port map (
+ CLK => CLK,
+ RXD => RXD0,
+ TXD => TXD0,
+ I_RXD => I_RXD0,
+ O_TXD => O_TXD0
+ );
+
+ P1 : s3_rs232_iob_ext
+ port map (
+ CLK => CLK,
+ RXD => RXD1,
+ TXD => TXD1,
+ CTS_N => CTS1_N,
+ RTS_N => RTS1_N,
+ I_RXD => I_RXD1,
+ O_TXD => O_TXD1,
+ I_CTS_N => I_CTS1_N,
+ O_RTS_N => O_RTS1_N
+ );
+
+ proc_port_mux: process (SEL, RXD0, TXD, RXD1, CTS1_N, RTS_N)
+ begin
+ if SEL = '0' then -- use main board rs232, no flow cntl
+ RXD <= RXD0; -- get port 0 inputs
+ CTS_N <= '0';
+ TXD0 <= TXD; -- set port 0 output
+ TXD1 <= '1'; -- port 1 outputs to idle state
+ RTS1_N <= '0';
+ else -- otherwise use pmod1 rs232
+ RXD <= RXD1; -- get port 1 inputs
+ CTS_N <= CTS1_N;
+ TXD1 <= TXD; -- set port 1 outputs
+ RTS1_N <= RTS_N;
+ TXD0 <= '1'; -- port 0 output to idle state
+ end if;
+ end process proc_port_mux;
+
+end syn;
Index: s3board/s3_sram_dummy.vbom
===================================================================
--- s3board/s3_sram_dummy.vbom (nonexistent)
+++ s3board/s3_sram_dummy.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../../vlib/slvtypes.vhd
+# components
+# design
+s3_sram_dummy.vhd
Index: s3board/s3_humanio.vhd
===================================================================
--- s3board/s3_humanio.vhd (nonexistent)
+++ s3board/s3_humanio.vhd (revision 7)
@@ -0,0 +1,147 @@
+-- $Id: s3_humanio.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_humanio - syn
+-- Description: All BTN, SWI, LED and DSP handling for s3board
+--
+-- Dependencies: xlib/iob_reg_i_gen
+-- xlib/iob_reg_o_gen
+-- genlib/debounce_gen
+-- s3board/s3_dispdrv
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-04-10 275 11.4 L68 xc3s1000-4 80 87 0 53 s 5.2 ns
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv
+-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic
+-- 2010-04-10 275 1.0 Initial version
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.s3boardlib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity s3_humanio is -- human i/o handling: swi,btn,led,dsp
+ generic (
+ DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CE_MSEC : in slbit; -- 1 ms clock enable
+ SWI : out slv8; -- switch settings, debounced
+ BTN : out slv4; -- button settings, debounced
+ LED : in slv8; -- led data
+ DSP_DAT : in slv16; -- display data
+ DSP_DP : in slv4; -- display decimal points
+ I_SWI : in slv8; -- pad-i: switches
+ I_BTN : in slv4; -- pad-i: buttons
+ O_LED : out slv8; -- pad-o: leds
+ O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
+ O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
+ );
+end s3_humanio;
+
+architecture syn of s3_humanio is
+
+ signal RI_SWI : slv8 := (others=>'0');
+ signal RI_BTN : slv4 := (others=>'0');
+
+ signal N_ANO_N : slv4 := (others=>'0');
+ signal N_SEG_N : slv8 := (others=>'0');
+
+begin
+
+ IOB_SWI : iob_reg_i_gen
+ generic map (DWIDTH => 8)
+ port map (CLK => CLK, CE => '1', DI => RI_SWI, PAD => I_SWI);
+
+ IOB_BTN : iob_reg_i_gen
+ generic map (DWIDTH => 4)
+ port map (CLK => CLK, CE => '1', DI => RI_BTN, PAD => I_BTN);
+
+ IOB_LED : iob_reg_o_gen
+ generic map (DWIDTH => 8)
+ port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED);
+
+ IOB_ANO_N : iob_reg_o_gen
+ generic map (DWIDTH => 4)
+ port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N);
+
+ IOB_SEG_N : iob_reg_o_gen
+ generic map (DWIDTH => 8)
+ port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
+
+ DEB: if DEBOUNCE generate
+
+ DEB_SWI : debounce_gen
+ generic map (
+ CWIDTH => 2,
+ CEDIV => 3,
+ DWIDTH => 8)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_INT => CE_MSEC,
+ DI => RI_SWI,
+ DO => SWI
+ );
+
+ DEB_BTN : debounce_gen
+ generic map (
+ CWIDTH => 2,
+ CEDIV => 3,
+ DWIDTH => 4)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_INT => CE_MSEC,
+ DI => RI_BTN,
+ DO => BTN
+ );
+
+ end generate DEB;
+
+ NODEB: if not DEBOUNCE generate
+ SWI <= RI_SWI;
+ BTN <= RI_BTN;
+ end generate NODEB;
+
+ DRV : s3_dispdrv
+ generic map (
+ CDWIDTH => 6)
+ port map (
+ CLK => CLK,
+ DIN => DSP_DAT,
+ DP => DSP_DP,
+ ANO_N => N_ANO_N,
+ SEG_N => N_SEG_N
+ );
+
+end syn;
Index: s3board/s3_rs232_iob_int.vbom
===================================================================
--- s3board/s3_rs232_iob_int.vbom (nonexistent)
+++ s3board/s3_rs232_iob_int.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/xlib/xlib.vhd
+# components
+../../vlib/xlib/iob_reg_i.vbom
+../../vlib/xlib/iob_reg_o.vbom
+# design
+s3_rs232_iob_int.vhd
Index: s3board/s3boardlib.vbom
===================================================================
--- s3board/s3boardlib.vbom (nonexistent)
+++ s3board/s3boardlib.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/rri/rrilib.vhd
+s3boardlib.vhd
Index: s3board/s3_sram_memctl.vhd
===================================================================
--- s3board/s3_sram_memctl.vhd (nonexistent)
+++ s3board/s3_sram_memctl.vhd (revision 7)
@@ -0,0 +1,365 @@
+-- $Id: s3_sram_memctl.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_sram_memctl - syn
+-- Description: s3board: SRAM driver
+--
+-- Dependencies: vlib/xlib/iob_reg_o
+-- vlib/xlib/iob_reg_o_gen
+-- vlib/xlib/iob_reg_io_gen
+-- Test bench: tb/tb_s3_sram_memctl
+-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-05-23 293 11.4 L68 xc3s1000-4 7 22 0 14 s 8.5
+-- 2008-02-16 116 8.2.03 I34 xc3s1000-4 5 30 0 17 s 7.0
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
+-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
+-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface
+-- 2008-01-20 113 1.0.2 rename memdrv -> memctl_s3sram
+-- 2007-12-15 101 1.0.1 use _N for active low; get ce/we clocking right
+-- 2007-12-08 100 1.0 Initial version
+--
+-- Timing of some signals:
+--
+-- single read request:
+--
+-- state |_idle |_read |_idle |
+--
+-- CLK __|^^^|___|^^^|___|^^^|___|^
+--
+-- REQ _______|^^^^^|______________
+-- WE ____________________________
+--
+-- IOB_CE __________|^^^^^^^|_________
+-- IOB_OE __________|^^^^^^^|_________
+--
+-- DO oooooooooooooooooo|ddddddd|d
+-- BUSY ____________________________
+-- ACK_R __________________|^^^^^^^|_
+--
+-- single write request:
+--
+-- state |_idle |_write1|_write2|_idle |
+--
+-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^
+--
+-- REQ _______|^^^^^|______________
+-- WE _______|^^^^^|______________
+--
+-- IOB_CE __________|^^^^^^^^^^^^^^^|_________
+-- IOB_BE __________|^^^^^^^^^^^^^^^|_________
+-- IOB_OE ____________________________________
+-- IOB_WE ______________|^^^^^^^|_____________
+--
+-- BUSY __________|^^^^^^^|_________________
+-- ACK_W __________________|^^^^^^^|_________
+--
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity s3_sram_memctl is -- SRAM driver for S3BOARD
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ REQ : in slbit; -- request
+ WE : in slbit; -- write enable
+ BUSY : out slbit; -- controller busy
+ ACK_R : out slbit; -- acknowledge read
+ ACK_W : out slbit; -- acknowledge write
+ ACT_R : out slbit; -- signal active read
+ ACT_W : out slbit; -- signal active write
+ ADDR : in slv18; -- address
+ BE : in slv4; -- byte enable
+ DI : in slv32; -- data in (memory view)
+ DO : out slv32; -- data out (memory view)
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32 -- sram: data lines
+ );
+end s3_sram_memctl;
+
+
+architecture syn of s3_sram_memctl is
+
+ type state_type is (
+ s_idle, -- s_idle: wait for req
+ s_read, -- s_read: read cycle
+ s_write1, -- s_write1: write cycle, 1st half
+ s_write2, -- s_write2: write cycle, 2nd half
+ s_bta_r2w, -- s_bta_r2w: bus turn around: r->w
+ s_bta_w2r -- s_bta_w2r: bus turn around: w->r
+ );
+
+ type regs_type is record
+ state : state_type; -- state
+ ackr : slbit; -- signal ack_r
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ s_idle,
+ '0' -- ackr
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ signal CLK_180 : slbit := '0';
+ signal MEM_CE_N : slv2 := "00";
+ signal MEM_BE_N : slv4 := "0000";
+ signal MEM_WE_N : slbit := '0';
+ signal MEM_OE_N : slbit := '0';
+ signal ADDR_CE : slbit := '0';
+ signal DATA_CEI : slbit := '0';
+ signal DATA_CEO : slbit := '0';
+ signal DATA_OE : slbit := '0';
+
+begin
+
+ CLK_180 <= not CLK;
+
+ IOB_MEM_CE : iob_reg_o_gen
+ generic map (
+ DWIDTH => 2,
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => '1',
+ DO => MEM_CE_N,
+ PAD => O_MEM_CE_N
+ );
+
+ IOB_MEM_BE : iob_reg_o_gen
+ generic map (
+ DWIDTH => 4,
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => ADDR_CE,
+ DO => MEM_BE_N,
+ PAD => O_MEM_BE_N
+ );
+
+ IOB_MEM_WE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK_180,
+ CE => '1',
+ DO => MEM_WE_N,
+ PAD => O_MEM_WE_N
+ );
+
+ IOB_MEM_OE : iob_reg_o
+ generic map (
+ INIT => '1')
+ port map (
+ CLK => CLK,
+ CE => '1',
+ DO => MEM_OE_N,
+ PAD => O_MEM_OE_N
+ );
+
+ IOB_MEM_ADDR : iob_reg_o_gen
+ generic map (
+ DWIDTH => 18)
+ port map (
+ CLK => CLK,
+ CE => ADDR_CE,
+ DO => ADDR,
+ PAD => O_MEM_ADDR
+ );
+
+ IOB_MEM_DATA : iob_reg_io_gen
+ generic map (
+ DWIDTH => 32,
+ PULL => "KEEP")
+ port map (
+ CLK => CLK,
+ CEI => DATA_CEI,
+ CEO => DATA_CEO,
+ OE => DATA_OE,
+ DI => DO,
+ DO => DI,
+ PAD => IO_MEM_DATA
+ );
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, REQ, WE, BE)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+ variable ibusy : slbit := '0';
+ variable iackw : slbit := '0';
+ variable iactr : slbit := '0';
+ variable iactw : slbit := '0';
+ variable imem_ce : slv2 := "00";
+ variable imem_be : slv4 := "0000";
+ variable imem_we : slbit := '0';
+ variable imem_oe : slbit := '0';
+ variable iaddr_ce : slbit := '0';
+ variable idata_cei : slbit := '0';
+ variable idata_ceo : slbit := '0';
+ variable idata_oe : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+ n.ackr := '0';
+
+ ibusy := '0';
+ iackw := '0';
+ iactr := '0';
+ iactw := '0';
+
+ imem_ce := "00";
+ imem_be := "1111";
+ imem_we := '0';
+ imem_oe := '0';
+ iaddr_ce := '0';
+ idata_cei := '0';
+ idata_ceo := '0';
+ idata_oe := '0';
+
+ case r.state is
+ when s_idle => -- s_idle: wait for req
+ if REQ = '1' then -- if IO requested
+ if WE = '0' then -- if READ requested
+ iaddr_ce := '1'; -- latch address and be's
+ imem_ce := "11"; -- ce SRAM next cycle
+ imem_oe := '1'; -- oe SRAM next cycle
+ n.state := s_read; -- next: read
+ else -- if WRITE requested
+ iaddr_ce := '1'; -- latch address and be's
+ idata_ceo := '1'; -- latch output data
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := "11"; -- ce SRAM next cycle
+ imem_be := BE; -- use request BE's
+ n.state := s_write1; -- next: write 1st part
+ end if;
+ end if;
+
+ when s_read => -- s_read: read cycle
+ idata_cei := '1'; -- latch input data
+ iactr := '1'; -- signal mem read
+ n.ackr := '1'; -- ACK_R next cycle
+ if REQ = '1' then -- if IO requested
+ if WE = '0' then -- if READ requested
+ iaddr_ce := '1'; -- latch address and be's
+ imem_ce := "11"; -- ce SRAM next cycle
+ imem_oe := '1'; -- oe SRAM next cycle
+ n.state := s_read; -- next: continue read
+ else -- if WRITE requested
+ iaddr_ce := '1'; -- latch address and be's
+ idata_ceo := '1'; -- latch output data
+ imem_be := BE; -- use request BE's
+ n.state := s_bta_r2w; -- next: bus turn around cycle
+ end if;
+ else
+ n.state := s_idle; -- next: idle if nothing to do
+ end if;
+
+ when s_write1 => -- s_write1: write cycle, 1st half
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := "11"; -- ce SRAM next cycle
+ imem_we := '1'; -- we SRAM next shifted cycle
+ n.state := s_write2; -- next: write cycle, 2nd half
+
+ when s_write2 => -- s_write2: write cycle, 2nd half
+ iactw := '1'; -- signal mem write
+ iackw := '1'; -- signal write acknowledge
+ idata_cei := '1'; -- latch input data (from SRAM)
+ if REQ = '1' then -- if IO requested
+ if WE = '1' then -- if WRITE requested
+ iaddr_ce := '1'; -- latch address and be's
+ idata_ceo := '1'; -- latch output data
+ idata_oe := '1'; -- oe FPGA next cycle
+ imem_ce := "11"; -- ce SRAM next cycle
+ imem_be := BE; -- use request BE's
+ n.state := s_write1; -- next: continue read
+ else -- if READ requested
+ iaddr_ce := '1'; -- latch address and be's
+ n.state := s_bta_w2r; -- next: bus turn around cycle
+ end if;
+ else
+ n.state := s_idle; -- next: idle if nothing to do
+ end if;
+
+ when s_bta_r2w => -- s_bta_r2w: bus turn around: r->w
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactw := '1'; -- signal mem write
+ imem_ce := "11"; -- ce SRAM next cycle
+ idata_oe := '1'; -- oe FPGA next cycle
+ n.state := s_write1; -- next: start write
+
+ when s_bta_w2r => -- s_bta_w2r: bus turn around: w->r
+ ibusy := '1'; -- signal busy, unable to handle req
+ iactr := '1'; -- signal mem read
+ imem_ce := "11"; -- ce SRAM next cycle
+ imem_oe := '1'; -- oe SRAM next cycle
+ n.state := s_read; -- next: start read
+
+ when others => null;
+ end case;
+
+ N_REGS <= n;
+
+ MEM_CE_N <= not imem_ce;
+ MEM_WE_N <= not imem_we;
+ MEM_BE_N <= not imem_be;
+ MEM_OE_N <= not imem_oe;
+ ADDR_CE <= iaddr_ce;
+ DATA_CEI <= idata_cei;
+ DATA_CEO <= idata_ceo;
+ DATA_OE <= idata_oe;
+
+ BUSY <= ibusy;
+ ACK_R <= r.ackr;
+ ACK_W <= iackw;
+ ACT_R <= iactr;
+ ACT_W <= iactw;
+
+ end process proc_next;
+
+end syn;
Index: s3board/s3_rs232_iob_ext.vbom
===================================================================
--- s3board/s3_rs232_iob_ext.vbom (nonexistent)
+++ s3board/s3_rs232_iob_ext.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/xlib/xlib.vhd
+# components
+../../vlib/xlib/iob_reg_i.vbom
+../../vlib/xlib/iob_reg_o.vbom
+# design
+s3_rs232_iob_ext.vhd
Index: s3board/s3_dispdrv.vhd
===================================================================
--- s3board/s3_dispdrv.vhd (nonexistent)
+++ s3board/s3_dispdrv.vhd (revision 7)
@@ -0,0 +1,151 @@
+-- $Id: s3_dispdrv.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_dispdrv - syn
+-- Description: s3board: 7 segment display driver
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-17 278 1.1.1 renamed from dispdrv
+-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
+-- delay and to avoid cross talk between digits
+-- 2007-12-16 101 1.0.1 use _N for active low
+-- 2007-09-16 83 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity s3_dispdrv is -- 7 segment display driver
+ generic (
+ CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
+ port (
+ CLK : in slbit; -- clock
+ DIN : in slv16; -- data
+ DP : in slv4; -- decimal points
+ ANO_N : out slv4; -- anodes (act.low)
+ SEG_N : out slv8 -- segements (act.low)
+ );
+end s3_dispdrv;
+
+architecture syn of s3_dispdrv is
+
+ type regs_type is record
+ cdiv : std_logic_vector(CDWIDTH-1 downto 0); -- clock divider counter
+ dcnt : slv2; -- digit counter
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ conv_std_logic_vector(0,CDWIDTH),
+ (others=>'0')
+ );
+
+ type hex2segtbl_type is array (0 to 15) of slv7;
+
+ constant hex2segtbl : hex2segtbl_type :=
+ ("0111111", -- 0: "0000"
+ "0000110", -- 1: "0001"
+ "1011011", -- 2: "0010"
+ "1001111", -- 3: "0011"
+ "1100110", -- 4: "0100"
+ "1101101", -- 5: "0101"
+ "1111101", -- 6: "0110"
+ "0000111", -- 7: "0111"
+ "1111111", -- 8: "1000"
+ "1101111", -- 9: "1001"
+ "1110111", -- a: "1010"
+ "1111100", -- b: "1011"
+ "0111001", -- c: "1100"
+ "1011110", -- d: "1101"
+ "1111001", -- e: "1110"
+ "1110001" -- f: "1111"
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ assert CDWIDTH >= 5
+ report "assert(CDWIDTH >= 5): CDWIDTH too small"
+ severity FAILURE;
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ R_REGS <= N_REGS;
+ end if;
+
+ end process proc_regs;
+
+
+ proc_next: process (R_REGS, DIN, DP)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+ variable cano : slv4 := "0000";
+ variable chex : slv4 := "0000";
+ variable cdp : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ n.cdiv := unsigned(r.cdiv) - 1;
+ if unsigned(r.cdiv) = 0 then
+ n.dcnt := unsigned(r.dcnt) + 1;
+ end if;
+
+ chex := "0000";
+ cdp := '0';
+
+ case r.dcnt is
+ when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
+ when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
+ when "10" => chex := DIN(11 downto 8); cdp := DP(2);
+ when "11" => chex := DIN(15 downto 12); cdp := DP(3);
+ when others => chex := "----"; cdp := '-';
+ end case;
+
+ -- the logic below ensures that the anode PNP driver transistor is switched
+ -- off 16 cycles before the cathode drivers change. This prevents 'cross
+ -- talk' between digits due to transistor turn off delays. With no or 4
+ -- cycles gap one gets well visible cross talk, with 8 cycles still some
+ -- weak cross talk. With 16 cycles (at 50MHz) none is visible. The
+ -- turn-off delay of the anode driver PNP's this therefore larger 160 ns
+ -- and below 320 ns.
+ -- As consquence CDWIDTH should be at least 5, better 6.
+
+ cano := "1111";
+ if unsigned(r.cdiv) >= 16 then
+ cano(conv_integer(unsigned(r.dcnt))) := '0';
+ end if;
+
+ N_REGS <= n;
+
+ ANO_N <= cano;
+ SEG_N <= not (cdp & hex2segtbl(conv_integer(unsigned(chex))));
+
+ end process proc_next;
+
+end syn;
Index: s3board/s3_humanio_rri.vhd
===================================================================
--- s3board/s3_humanio_rri.vhd (nonexistent)
+++ s3board/s3_humanio_rri.vhd (revision 7)
@@ -0,0 +1,277 @@
+-- $Id: s3_humanio_rri.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_humanio_rri - syn
+-- Description: s3_humanio with rri interceptor
+--
+-- Dependencies: s3board/s3_humanio
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_
+-- 2010-06-03 300 1.0 Initial version
+------------------------------------------------------------------------------
+--
+-- rbus registers:
+--
+-- Address Bits Name r/w/f Function
+-- bbbbbb00 cntl r/w/- Control register and BTN access
+-- 11 dat_en r/w/- if 1 display data will be driven by rri
+-- 10 dp_en r/w/- if 1 display dp's will be driven by rri
+-- 9 led_en r/w/- if 1 LED will be driven by rri
+-- 8 swi_en r/w/- if 1 SWI will be driven by rri
+-- 3:00 btn r/w/- r: return hio BTN status
+-- w: BTN is hio BTN ored with this fields
+--
+-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status
+-- w: will drive SWI when swi_en=1
+--
+-- bbbbbb10 leddp r/w/- interface to LED and DSP_DP
+-- 11:09 dsp_dp r/w/- r: returns DSP_DP status
+-- w: will drive display dp's when dp_en=1
+-- 7:00 led r/w/- r: returns LED status
+-- w: will drive led's when led_en=1
+--
+-- bbbbbb11 15:00 dsp_dat r/w/- r: return hio DSP_DAT status
+-- w: will drive DSP_DAT when dat_en=1
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.rrilib.all;
+use work.s3boardlib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity s3_humanio_rri is -- human i/o handling with rri intercept
+ generic (
+ DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
+ RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CE_MSEC : in slbit; -- 1 ms clock enable
+ RB_MREQ : in rb_mreq_type; -- rbus: request
+ RB_SRES : out rb_sres_type; -- rbus: response
+ SWI : out slv8; -- switch settings, debounced
+ BTN : out slv4; -- button settings, debounced
+ LED : in slv8; -- led data
+ DSP_DAT : in slv16; -- display data
+ DSP_DP : in slv4; -- display decimal points
+ I_SWI : in slv8; -- pad-i: switches
+ I_BTN : in slv4; -- pad-i: buttons
+ O_LED : out slv8; -- pad-o: leds
+ O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
+ O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
+ );
+end s3_humanio_rri;
+
+architecture syn of s3_humanio_rri is
+
+ type regs_type is record
+ swi : slv8; -- rri swi
+ btn : slv4; -- rri btn
+ led : slv8; -- rri led
+ dsp_dat : slv16; -- rri dsp_dat
+ dsp_dp : slv4; -- rri dsp_dp
+ swi_en : slbit; -- enable: swi from rri
+ led_en : slbit; -- enable: led from rri
+ dat_en : slbit; -- enable: dsp_dat from rri
+ dp_en : slbit; -- enable: dsp_dp from rri
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ (others=>'0'), -- swi
+ (others=>'0'), -- btn
+ (others=>'0'), -- led
+ (others=>'0'), -- dsp_dat
+ (others=>'0'), -- dsp_dp
+ '0','0','0','0' -- (swi|led|dat|dp)_en
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ constant cntl_rbf_dat_en: integer := 11;
+ constant cntl_rbf_dp_en: integer := 10;
+ constant cntl_rbf_led_en: integer := 9;
+ constant cntl_rbf_swi_en: integer := 8;
+ subtype cntl_rbf_btn is integer range 3 downto 0;
+ subtype leddp_rbf_dsp_dp is integer range 11 downto 8;
+ subtype leddp_rbf_led is integer range 7 downto 0;
+
+ constant rbaddr_cntl: slv2 := "00"; -- 0 -/r/w
+ constant rbaddr_swi: slv2 := "01"; -- 1 -/r/w
+ constant rbaddr_leddp: slv2 := "10"; -- 2 -/r/w
+ constant rbaddr_dsp: slv2 := "11"; -- 3 -/r/w
+
+ signal HIO_SWI : slv8 := (others=>'0');
+ signal HIO_BTN : slv4 := (others=>'0');
+ signal HIO_LED : slv8 := (others=>'0');
+ signal HIO_DSP_DAT : slv16 := (others=>'0');
+ signal HIO_DSP_DP : slv4 := (others=>'0');
+
+begin
+
+ HIO : s3_humanio
+ generic map (
+ DEBOUNCE => DEBOUNCE)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ SWI => HIO_SWI,
+ BTN => HIO_BTN,
+ LED => HIO_LED,
+ DSP_DAT => HIO_DSP_DAT,
+ DSP_DP => HIO_DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
+ HIO_SWI, HIO_BTN, HIO_LED, HIO_DSP_DAT, HIO_DSP_DP)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable irb_sel : slbit := '0';
+ variable irb_ack : slbit := '0';
+ variable irb_busy : slbit := '0';
+ variable irb_err : slbit := '0';
+ variable irb_dout : slv16 := (others=>'0');
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ irb_sel := '0';
+ irb_ack := '0';
+ irb_busy := '0';
+ irb_err := '0';
+ irb_dout := (others=>'0');
+
+ if RB_MREQ.req='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
+ irb_sel := '1';
+ irb_ack := '1';
+ end if;
+
+ if irb_sel = '1' then
+ case RB_MREQ.addr(1 downto 0) is
+
+ when rbaddr_cntl =>
+ irb_dout(cntl_rbf_dat_en) := r.dat_en;
+ irb_dout(cntl_rbf_dp_en) := r.dp_en;
+ irb_dout(cntl_rbf_led_en) := r.led_en;
+ irb_dout(cntl_rbf_swi_en) := r.swi_en;
+ irb_dout(cntl_rbf_btn) := HIO_BTN;
+ if RB_MREQ.we = '1' then
+ n.dat_en := RB_MREQ.din(cntl_rbf_dat_en);
+ n.dp_en := RB_MREQ.din(cntl_rbf_dp_en);
+ n.led_en := RB_MREQ.din(cntl_rbf_led_en);
+ n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
+ n.btn := RB_MREQ.din(cntl_rbf_btn);
+ end if;
+
+ when rbaddr_swi =>
+ irb_dout(HIO_SWI'range) := HIO_SWI;
+ if RB_MREQ.we = '1' then
+ n.swi := RB_MREQ.din(n.swi'range);
+ end if;
+
+ when rbaddr_leddp =>
+ irb_dout(leddp_rbf_dsp_dp) := HIO_DSP_DP;
+ irb_dout(leddp_rbf_led) := HIO_LED;
+ if RB_MREQ.we = '1' then
+ n.dsp_dp := RB_MREQ.din(leddp_rbf_dsp_dp);
+ n.led := RB_MREQ.din(leddp_rbf_led);
+ end if;
+
+ when rbaddr_dsp =>
+ irb_dout := HIO_DSP_DAT;
+ if RB_MREQ.we = '1' then
+ n.dsp_dat := RB_MREQ.din;
+ end if;
+
+ when others => null;
+ end case;
+
+ end if;
+
+ BTN <= HIO_BTN or r.btn;
+
+ if r.swi_en = '0' then
+ SWI <= HIO_SWI;
+ else
+ SWI <= r.swi;
+ end if;
+
+ if r.led_en = '0' then
+ HIO_LED <= LED;
+ else
+ HIO_LED <= r.led;
+ end if;
+
+ if r.dp_en = '0' then
+ HIO_DSP_DP <= DSP_DP;
+ else
+ HIO_DSP_DP <= r.dsp_dp;
+ end if;
+
+ if r.dat_en = '0' then
+ HIO_DSP_DAT <= DSP_DAT;
+ else
+ HIO_DSP_DAT <= r.dsp_dat;
+ end if;
+
+ N_REGS <= n;
+
+ RB_SRES <= rb_sres_init;
+ RB_SRES.ack <= irb_ack;
+ RB_SRES.busy <= irb_busy;
+ RB_SRES.err <= irb_err;
+ RB_SRES.dout <= irb_dout;
+
+ end process proc_next;
+
+end syn;
Index: s3board/s3board_pins.ucf
===================================================================
--- s3board/s3board_pins.ucf (nonexistent)
+++ s3board/s3board_pins.ucf (revision 7)
@@ -0,0 +1,132 @@
+## $Id: s3board_pins.ucf 311 2010-06-30 17:52:37Z mueller $
+##
+## Pin locks for S3BOARD core functionality:
+## internal RS232
+## human I/O (switches, buttons, leds, display)
+## sram
+##
+## Revision History:
+## Date Rev Version Comment
+## 2008-05-25 150 1.1 Use DRIVE=6|SLEW=SLOW|KEEPER for memory data lines
+## 2008-02-17 101 1.0 Initial version
+##
+## Note: default is DRIVE=12 | SLEW=SLOW
+##
+## clocks --------------------------------------------------------------------
+NET "CLK" LOC = "t9" | IOSTANDARD=LVCMOS33;
+##
+## RS232 interface -----------------------------------------------------------
+NET "I_RXD" LOC = "t13" | IOSTANDARD=LVCMOS33;
+NET "O_TXD" LOC = "r13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
+##
+## switches and buttons ------------------------------------------------------
+NET "I_SWI<0>" LOC = "f12" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<1>" LOC = "g12" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<2>" LOC = "h14" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<3>" LOC = "h13" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<4>" LOC = "j14" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<5>" LOC = "j13" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<6>" LOC = "k14" | IOSTANDARD=LVCMOS33;
+NET "I_SWI<7>" LOC = "k13" | IOSTANDARD=LVCMOS33;
+##
+NET "I_BTN<0>" LOC = "m13" | IOSTANDARD=LVCMOS33;
+NET "I_BTN<1>" LOC = "m14" | IOSTANDARD=LVCMOS33;
+NET "I_BTN<2>" LOC = "l13" | IOSTANDARD=LVCMOS33;
+NET "I_BTN<3>" LOC = "l14" | IOSTANDARD=LVCMOS33;
+##
+## LEDs ----------------------------------------------------------------------
+NET "O_LED<0>" LOC = "k12" | IOSTANDARD=LVCMOS33;
+NET "O_LED<1>" LOC = "p14" | IOSTANDARD=LVCMOS33;
+NET "O_LED<2>" LOC = "l12" | IOSTANDARD=LVCMOS33;
+NET "O_LED<3>" LOC = "n14" | IOSTANDARD=LVCMOS33;
+NET "O_LED<4>" LOC = "p13" | IOSTANDARD=LVCMOS33;
+NET "O_LED<5>" LOC = "n12" | IOSTANDARD=LVCMOS33;
+NET "O_LED<6>" LOC = "p12" | IOSTANDARD=LVCMOS33;
+NET "O_LED<7>" LOC = "p11" | IOSTANDARD=LVCMOS33;
+NET "O_LED<*>" DRIVE=12 | SLEW=SLOW;
+##
+## 7 segment display ---------------------------------------------------------
+NET "O_ANO_N<0>" LOC = "d14" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<1>" LOC = "g14" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<2>" LOC = "f14" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<3>" LOC = "e13" | IOSTANDARD=LVCMOS33;
+NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW;
+##
+NET "O_SEG_N<0>" LOC = "e14" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<1>" LOC = "g13" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<2>" LOC = "n15" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<3>" LOC = "p15" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<4>" LOC = "r16" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<5>" LOC = "f13" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<6>" LOC = "n16" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<7>" LOC = "p16" | IOSTANDARD=LVCMOS33;
+NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW;
+##
+## SRAM ----------------------------------------------------------------------
+NET "O_MEM_CE_N<0>" LOC = "p7" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_CE_N<1>" LOC = "n5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_CE_N<*>" DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_BE_N<0>" LOC = "p6" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<1>" LOC = "t4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<2>" LOC = "p5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<3>" LOC = "r4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_WE_N" LOC = "g3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_MEM_OE_N" LOC = "k4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_MEM_ADDR<0>" LOC = "l5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<1>" LOC = "n3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<2>" LOC = "m4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<3>" LOC = "m3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<4>" LOC = "l4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<5>" LOC = "g4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<6>" LOC = "f3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<7>" LOC = "f4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<8>" LOC = "e3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<9>" LOC = "e4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<10>" LOC = "g5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<11>" LOC = "h3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<12>" LOC = "h4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<13>" LOC = "j4" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<14>" LOC = "j3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<15>" LOC = "k3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<16>" LOC = "k5" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<17>" LOC = "l3" | IOSTANDARD=LVCMOS33;
+NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST;
+##
+NET "IO_MEM_DATA<0>" LOC = "n7" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<1>" LOC = "t8" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<2>" LOC = "r6" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<3>" LOC = "t5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<4>" LOC = "r5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<5>" LOC = "c2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<6>" LOC = "c1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<7>" LOC = "b1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<8>" LOC = "d3" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<9>" LOC = "p8" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<10>" LOC = "f2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<11>" LOC = "h1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<12>" LOC = "j2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<13>" LOC = "l2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<14>" LOC = "p1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<15>" LOC = "r1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<16>" LOC = "p2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<17>" LOC = "n2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<18>" LOC = "m2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<19>" LOC = "k1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<20>" LOC = "j1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<21>" LOC = "g2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<22>" LOC = "e1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<23>" LOC = "d1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<24>" LOC = "d2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<25>" LOC = "e2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<26>" LOC = "g1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<27>" LOC = "f5" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<28>" LOC = "c3" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<29>" LOC = "k2" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<30>" LOC = "m1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<31>" LOC = "n1" | IOSTANDARD=LVCMOS33;
+NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
+##
Index: s3board/s3_sram_dummy.vhd
===================================================================
--- s3board/s3_sram_dummy.vhd (nonexistent)
+++ s3board/s3_sram_dummy.vhd (revision 7)
@@ -0,0 +1,57 @@
+-- $Id: s3_sram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_sram_dummy - syn
+-- Description: s3board: SRAM protection dummy
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-17 278 1.0.2 renamed from sram_dummy
+-- 2007-12-09 101 1.0.1 use _N for active low
+-- 2007-12-08 100 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity s3_sram_dummy is -- SRAM protection dummy
+ port (
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32 -- sram: data lines
+ );
+end s3_sram_dummy;
+
+
+architecture syn of s3_sram_dummy is
+begin
+
+ O_MEM_CE_N <= "11"; -- disable sram chips
+ O_MEM_BE_N <= "1111";
+ O_MEM_WE_N <= '1';
+ O_MEM_OE_N <= '1';
+ O_MEM_ADDR <= (others=>'0');
+ IO_MEM_DATA <= (others=>'0');
+
+end syn;
Index: s3board/s3board_a2_pm1_rs232.ucf
===================================================================
--- s3board/s3board_a2_pm1_rs232.ucf (nonexistent)
+++ s3board/s3board_a2_pm1_rs232.ucf (revision 7)
@@ -0,0 +1,15 @@
+## $Id: s3board_a2_pm1_rs232.ucf 311 2010-06-30 17:52:37Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2010-05-22 293 1.1 Rename PM1 -> FUSP
+## 2010-04-24 281 1.0 Initial version
+##
+## expansion connector A2 / slot PMod 1 / usage RS232 for FTDI USB serport ---
+##
+## PmodRS232: pins: 1 RTS; 2 CTS; 3 RXD; 4 TXD; 5 GND; 6 VCC
+##
+NET "O_FUSP_RTS_N" LOC = "c6" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
+NET "I_FUSP_CTS_N" LOC = "e7" | IOSTANDARD=LVCMOS33 | PULLDOWN;
+NET "I_FUSP_RXD" LOC = "c7" | IOSTANDARD=LVCMOS33 | PULLUP;
+NET "O_FUSP_TXD" LOC = "d7" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
Index: s3board/s3_rs232_iob_int.vhd
===================================================================
--- s3board/s3_rs232_iob_int.vhd (nonexistent)
+++ s3board/s3_rs232_iob_int.vhd (revision 7)
@@ -0,0 +1,62 @@
+-- $Id: s3_rs232_iob_int.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_rs232_iob_int - syn
+-- Description: iob's for internal rs232
+--
+-- Dependencies: xlib/iob_reg_i
+-- xlib/iob_reg_o
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-17 278 1.0 Initial version
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity s3_rs232_iob_int is -- iob's for internal rs232
+ port (
+ CLK : in slbit; -- clock
+ RXD : out slbit; -- receive data (board view)
+ TXD : in slbit; -- transmit data (board view)
+ I_RXD : in slbit; -- pad-i: receive data (board view)
+ O_TXD : out slbit -- pad-o: transmit data (board view)
+ );
+end s3_rs232_iob_int;
+
+architecture syn of s3_rs232_iob_int is
+begin
+
+ IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
+ generic map (INIT => '1')
+ port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
+
+ IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
+ generic map (INIT => '1')
+ port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
+
+end syn;
Index: s3board/s3boardlib.vhd
===================================================================
--- s3board/s3boardlib.vhd (nonexistent)
+++ s3board/s3boardlib.vhd (revision 7)
@@ -0,0 +1,219 @@
+-- $Id: s3boardlib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: s3boardlib
+-- Description: S3BOARD components
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib)
+-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_
+-- 2010-05-16 291 1.2.1 rename memctl_s3sram -> s3_sram_memctl; _usp->_fusp
+-- 2010-05-01 286 1.2 added s3board_usp_aif (base+pm1_rs232)
+-- 2010-04-17 278 1.1.6 rename, prefix dispdrv,sram_summy with s3_;
+-- add s3_rs232_iob_(int|ext|int_ext)
+-- 2010-04-11 276 1.1.5 add DEBOUNCE for s3_humanio
+-- 2010-04-10 275 1.1.4 add s3_humanio
+-- 2008-02-17 117 1.1.3 memctl_s3sram: use req,we interface
+-- 2008-01-20 113 1.1.2 rename memdrv -> memctl_s3sram
+-- 2007-12-16 101 1.1.1 use _N for active low
+-- 2007-12-09 100 1.1 add sram memory signals; sram_dummy; memdrv
+-- 2007-09-23 84 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.rrilib.all;
+
+package s3boardlib is
+
+component s3board_aif is -- S3BOARD, abstract iface, base
+ port (
+ CLK : in slbit; -- clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- s3 switches
+ I_BTN : in slv4; -- s3 buttons
+ O_LED : out slv8; -- s3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32 -- sram: data lines
+ );
+end component;
+
+component s3board_fusp_aif is -- S3BOARD, abstract iface, base+fusp
+ port (
+ CLK : in slbit; -- clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- s3 switches
+ I_BTN : in slv4; -- s3 buttons
+ O_LED : out slv8; -- s3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32; -- sram: data lines
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end component;
+
+component s3_dispdrv is -- 7 segment display driver
+ generic (
+ CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
+ port (
+ CLK : in slbit; -- clock
+ DIN : in slv16; -- data
+ DP : in slv4; -- decimal points
+ ANO_N : out slv4; -- anodes (act.low)
+ SEG_N : out slv8 -- segements (act.low)
+ );
+end component;
+
+component s3_humanio is -- human i/o handling: swi,btn,led,dsp
+ generic (
+ DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CE_MSEC : in slbit; -- 1 ms clock enable
+ SWI : out slv8; -- switch settings, debounced
+ BTN : out slv4; -- button settings, debounced
+ LED : in slv8; -- led data
+ DSP_DAT : in slv16; -- display data
+ DSP_DP : in slv4; -- display decimal points
+ I_SWI : in slv8; -- pad-i: switches
+ I_BTN : in slv4; -- pad-i: buttons
+ O_LED : out slv8; -- pad-o: leds
+ O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
+ O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
+ );
+end component;
+
+component s3_humanio_rri is -- human i/o handling with rri intercept
+ generic (
+ DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
+ RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CE_MSEC : in slbit; -- 1 ms clock enable
+ RB_MREQ : in rb_mreq_type; -- rbus: request
+ RB_SRES : out rb_sres_type; -- rbus: response
+ SWI : out slv8; -- switch settings, debounced
+ BTN : out slv4; -- button settings, debounced
+ LED : in slv8; -- led data
+ DSP_DAT : in slv16; -- display data
+ DSP_DP : in slv4; -- display decimal points
+ I_SWI : in slv8; -- pad-i: switches
+ I_BTN : in slv4; -- pad-i: buttons
+ O_LED : out slv8; -- pad-o: leds
+ O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
+ O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
+ );
+end component;
+
+component s3_rs232_iob_int is -- iob's for internal rs232
+ port (
+ CLK : in slbit; -- clock
+ RXD : out slbit; -- receive data (board view)
+ TXD : in slbit; -- transmit data (board view)
+ I_RXD : in slbit; -- pad-i: receive data (board view)
+ O_TXD : out slbit -- pad-o: transmit data (board view)
+ );
+end component;
+
+component s3_rs232_iob_ext is -- iob's for external rs232 (Pmod)
+ port (
+ CLK : in slbit; -- clock
+ RXD : out slbit; -- receive data (board view)
+ TXD : in slbit; -- transmit data (board view)
+ CTS_N : out slbit; -- clear to send (act. low)
+ RTS_N : in slbit; -- request to send (act. low)
+ I_RXD : in slbit; -- pad-i: receive data (board view)
+ O_TXD : out slbit; -- pad-o: transmit data (board view)
+ I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
+ O_RTS_N : out slbit -- pad-o: request to send (act. low)
+ );
+end component;
+
+component s3_rs232_iob_int_ext is -- iob's for int+ext rs232, with select
+ port (
+ CLK : in slbit; -- clock
+ SEL : in slbit; -- select, '0' for port 0
+ RXD : out slbit; -- receive data (board view)
+ TXD : in slbit; -- transmit data (board view)
+ CTS_N : out slbit; -- clear to send (act. low)
+ RTS_N : in slbit; -- request to send (act. low)
+ I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
+ O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
+ I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
+ O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
+ I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
+ O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
+ );
+end component;
+
+component s3_sram_dummy is -- SRAM protection dummy
+ port (
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32 -- sram: data lines
+ );
+end component;
+
+component s3_sram_memctl is -- SRAM driver
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ REQ : in slbit; -- request
+ WE : in slbit; -- write enable
+ BUSY : out slbit; -- controller busy
+ ACK_R : out slbit; -- acknowledge read
+ ACK_W : out slbit; -- acknowledge write
+ ACT_R : out slbit; -- signal active read
+ ACT_W : out slbit; -- signal active write
+ ADDR : in slv18; -- address
+ BE : in slv4; -- byte enable
+ DI : in slv32; -- data in (memory view)
+ DO : out slv32; -- data out (memory view)
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32 -- sram: data lines
+ );
+end component;
+
+end s3boardlib;
Index: s3board/s3_rs232_iob_int_ext.vbom
===================================================================
--- s3board/s3_rs232_iob_int_ext.vbom (nonexistent)
+++ s3board/s3_rs232_iob_int_ext.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+s3boardlib.vbom
+# components
+s3_rs232_iob_int.vbom
+s3_rs232_iob_ext.vbom
+# design
+s3_rs232_iob_int_ext.vhd
Index: s3board/s3_humanio.vbom
===================================================================
--- s3board/s3_humanio.vbom (nonexistent)
+++ s3board/s3_humanio.vbom (revision 7)
@@ -0,0 +1,13 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/genlib/genlib.vhd
+../../vlib/xlib/xlib.vhd
+s3boardlib.vbom
+## sys_conf : sys_conf.vhd
+# components
+../../vlib/xlib/iob_reg_i_gen.vbom
+../../vlib/xlib/iob_reg_o_gen.vbom
+../../vlib/genlib/debounce_gen.vbom
+s3_dispdrv.vbom
+# design
+s3_humanio.vhd
Index: s3board/s3_rs232_iob_ext.vhd
===================================================================
--- s3board/s3_rs232_iob_ext.vhd (nonexistent)
+++ s3board/s3_rs232_iob_ext.vhd (revision 7)
@@ -0,0 +1,72 @@
+-- $Id: s3_rs232_iob_ext.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: s3_rs232_iob_ext - syn
+-- Description: iob's for external rs232 (PMod)
+--
+-- Dependencies: xlib/iob_reg_i
+-- xlib/iob_reg_o
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-17 278 1.0 Initial version
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity s3_rs232_iob_ext is -- iob's for external rs232 (PMod)
+ port (
+ CLK : in slbit; -- clock
+ RXD : out slbit; -- receive data (board view)
+ TXD : in slbit; -- transmit data (board view)
+ CTS_N : out slbit; -- clear to send (act. low)
+ RTS_N : in slbit; -- request to send (act. low)
+ I_RXD : in slbit; -- pad-i: receive data (board view)
+ O_TXD : out slbit; -- pad-o: transmit data (board view)
+ I_CTS_N : in slbit; -- pad-i: clear to send (act. low)
+ O_RTS_N : out slbit -- pad-o: request to send (act. low)
+ );
+end s3_rs232_iob_ext;
+
+architecture syn of s3_rs232_iob_ext is
+begin
+
+ IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1
+ generic map (INIT => '1')
+ port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD);
+
+ IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1
+ generic map (INIT => '1')
+ port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD);
+
+ IOB_CTS : iob_reg_i
+ port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N);
+
+ IOB_RTS : iob_reg_o
+ port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N);
+
+end syn;
Index: s3board/s3_sram_memctl.vbom
===================================================================
--- s3board/s3_sram_memctl.vbom (nonexistent)
+++ s3board/s3_sram_memctl.vbom (revision 7)
@@ -0,0 +1,9 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/xlib/xlib.vhd
+# components
+../../vlib/xlib/iob_reg_o.vbom
+../../vlib/xlib/iob_reg_o_gen.vbom
+../../vlib/xlib/iob_reg_io_gen.vbom
+# design
+s3_sram_memctl.vhd
Index: s3board/Makefile
===================================================================
--- s3board/Makefile (nonexistent)
+++ s3board/Makefile (revision 7)
@@ -0,0 +1,24 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-12-09 100 1.0.1 drop ISE_p definition
+# 2007-09-16 83 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+ISE_PATH = xc3s1000-ft256-4
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: s3board
===================================================================
--- s3board (nonexistent)
+++ s3board (revision 7)
s3board
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 7)
.
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log