URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
Compare Revisions
- This comparison shows the changes necessary to convert path
/w11/tags/w11a_V0.5/rtl/sys_gen
- from Rev 3 to Rev 7
- ↔ Reverse comparison
Rev 3 → Rev 7
/w11a/tb/dorri
0,0 → 1,200
#!/usr/bin/perl -w |
# $Id: dorri 311 2010-06-30 17:52:37Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2010-05-29 296 1.4 allow -ux,baud (usb devnum and baudrate) |
# 2010-05-28 295 1.3 w11a_s3/w11a_n2 support: -s3 and -n2 instead of -f |
# add -tmu option |
# 2010-05-03 287 1.2 add -u[123] options for fast usb serport |
# 2009-08-01 237 1.1.1 use 115200 instead of 38400 as default baud rate |
# 2009-04-26 209 1.1 add -b (batch) option |
# 2009-04-11 206 1.0 Initial version |
# |
|
use 5.005; # require Perl 5.005 or higher |
use strict; # require strict checking |
use FileHandle; |
|
sub print_usage; |
|
autoflush STDOUT 1; # autoflush, so noting lost on exec later |
|
my $opt_b; |
my $opt_io; |
my $opt_tmu; |
my $pirri; |
my $val_cmax="3"; |
my $val_time="3."; |
my $val_term=",115200,1"; |
my $val_log="rri.log"; |
my $val_tb_s3="tbw ../s3board/tb/tb_w11a_s3"; |
my $val_tb_n2="tbw ../nexys2/tb/tb_w11a_n2"; |
my $val_tb; |
my $val_e; |
|
my @arglist; |
|
my %baudtbl = ( |
"57" => 57600, |
"115" => 115200, |
"230" => 230400, |
"460" => 460800, |
"500" => 500000, |
"1000" => 1000000, |
"2000" => 2000000, |
"3000" => 2000000 |
); |
|
# |
# process dorri options |
# |
while (scalar(@ARGV)) { |
my $curarg = $ARGV[0]; |
if ($curarg =~ m{^-b$} ) { # -b |
$opt_b = 1; |
shift @ARGV; |
} elsif ($curarg =~ m{^-tmu$} ) { # -tmu |
$opt_tmu = 1; |
shift @ARGV; |
} elsif ($curarg =~ m{^-s3$} ) { # -s3 |
$opt_io = "f"; |
$val_tb = $val_tb_s3; |
shift @ARGV; |
} elsif ($curarg =~ m{^-n2$} ) { # -n2 |
$opt_io = "f"; |
$val_tb = $val_tb_n2; |
shift @ARGV; |
} elsif ($curarg =~ m{^-t$} ) { # -t |
$opt_io = "t"; |
|
} elsif ($curarg =~ m{^-u(\d)} ) { # -ux... |
my $devnum = $1; |
my $rest = $'; |
my $baudspec = "115"; |
my $baudrate; |
if ($rest ne "") { |
if ($rest =~ m{^,(\d*)$}) { |
$baudspec = $1; |
} else { |
print STDERR "dorri-E: invalid format of -u option\n"; |
exit 1; |
} |
} |
if (defined $baudtbl{$baudspec}) { |
$baudrate = $baudtbl{$baudspec}; |
} else { |
print STDERR "dorri-E: invalid baudrate specification\n"; |
exit 1; |
} |
$opt_io = "t"; |
$val_term = sprintf "/dev/ttyUSB%d,%d,1", $devnum, $baudrate; |
shift @ARGV; |
|
} elsif ($curarg =~ m{^-e$} ) { # -e <file> |
print STDERR "dorri-W: multiple -e options, only last taken\n" |
if defined $val_e; |
shift @ARGV; |
if (scalar(@ARGV) == 0 || $ARGV[0] =~ m{^-}) { |
print STDERR "dorri-E: no file name after -e option\n"; |
exit 1; |
} else { |
$val_e = shift @ARGV; |
if (not -r $val_e) { |
print STDERR "dorri-E: file '$val_e' not found\n"; |
exit 1; |
} |
} |
} else { |
last; |
} |
} |
|
# |
# rename old log file |
# |
if (-r $val_log) { |
my $old_log = $val_log; |
$old_log =~ s{\.log}{\.old\.log}; |
rename $val_log, $old_log |
or die "failed to rename: $!"; |
} |
|
# |
# check that either -s3/n2 or -t given |
# setup pi_rri options for either case |
# |
|
if ($opt_io eq "f") { |
push @arglist, "--fifo"; |
push @arglist, "--run"; |
push @arglist, $val_tb; |
} elsif ($opt_io eq "t") { |
push @arglist, "--term=$val_term"; |
} else { |
print STDERR "dorri-E: neither -s3/-n2 nor -t specified\n"; |
print_usage(); |
exit 1; |
} |
|
# |
# setup all other options |
# |
|
push @arglist, "--timeout=$val_time"; |
push @arglist, "--cmax=$val_cmax"; |
push @arglist, "--log=$val_log"; |
push @arglist, "--dserv"; |
push @arglist, "--tserv"; |
push @arglist, "--int" unless $opt_b; |
|
if (defined $val_e) { |
push @arglist, ".mode serv11"; |
push @arglist, "ldabs $val_e"; |
push @arglist, "set sim tmu 1" if $opt_tmu; |
push @arglist, "start 200"; |
} |
|
while (scalar(@ARGV)) { |
my $curarg = shift @ARGV; |
if ($curarg =~ m{^@(.*)$} && ! -r $1) { |
print STDERR "dorri-E: file '$1' not found\n"; |
exit 1; |
} |
push @arglist,$curarg; |
} |
|
if (defined $val_e) { |
push @arglist, "server"; |
} |
|
# |
# find pi_rri executable |
# |
|
$pirri=`which pi_rri`; |
chomp $pirri; |
if ($pirri eq "" || ! -e $pirri) { |
print STDERR "dorri-E: failed to locate pi_rri\n"; |
exit 1; |
} |
|
# |
# print command file |
# |
if (1) { |
print "pi_rri ", join (" ", map {(m{\s}) ? "\"$_\"" : $_} @arglist) , "\n"; |
} |
|
# |
# and do it |
# |
exec $pirri, @arglist |
or die "failed to exec: $!"; |
|
exit 1; |
|
# ---------------------------------------------------------------------------- |
sub print_usage { |
print "usage: dorri [-f] [-t] [-u(123) [-e file] <pi_rri opts and cmds>...\n"; |
} |
w11a/tb/dorri
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: w11a/tb/uv5_boot.pcmd
===================================================================
--- w11a/tb/uv5_boot.pcmd (nonexistent)
+++ w11a/tb/uv5_boot.pcmd (revision 7)
@@ -0,0 +1,22 @@
+; $Id: uv5_boot.pcmd 312 2010-07-04 18:25:58Z mueller $
+;
+; Setup file for Unix V5 System
+;
+; Usage:
+;
+; telnet_starter -d DL0 &
+;
+; dorri -s3 @uv5_boot.pcmd (for ghdl sim of tb_w11a_s3)
+; dorri -n2 @uv5_boot.pcmd (for ghdl sim of tb_w11a_n2)
+;
+; dorri -t @uv5_boot.pcmd (fpga link via /dev/ttyS0)
+; dorri -u0,460 @uv5_boot.pcmd (fpga link via /dev/ttyUSB0)
+;
+.mode serv11
+;
+att TT0 8000
+;
+reset
+att rk0 unix_v5_rk.dsk
+boot rk0
+server
Index: w11a/tb/211bsd_rk_boot.pcmd
===================================================================
--- w11a/tb/211bsd_rk_boot.pcmd (nonexistent)
+++ w11a/tb/211bsd_rk_boot.pcmd (revision 7)
@@ -0,0 +1,28 @@
+; $Id: 211bsd_rk_boot.pcmd 312 2010-07-04 18:25:58Z mueller $
+;
+; Setup file for 211bsd RK based system (w11a, in sys/tb area...)
+;
+; Usage:
+;
+; telnet_starter -d DL0 &
+; telnet_starter -d DL1 &
+;
+; dorri -s3 @211bsd_rk_boot.pcmd (for ghdl sim of tb_w11a_s3)
+; dorri -n2 @211bsd_rk_boot.pcmd (for ghdl sim of tb_w11a_n2)
+;
+; dorri -t @211bsd_rk_boot.pcmd (fpga link via /dev/ttyS0)
+; dorri -u0,460 @211bsd_rk_boot.pcmd (fpga link via /dev/ttyUSB0)
+;
+.mode serv11
+;
+att TT0 8000
+att TT1 8001
+;
+reset
+att rk0 211bsd_rk_root.dsk
+att rk1 211bsd_rk_swap.dsk
+att rk2 211bsd_rk_tmp.dsk
+att rk3 211bsd_rk_bin.dsk
+att rk4 211bsd_rk_usr.dsk
+boot rk0
+server
Index: w11a/tb/.cvsignore
===================================================================
--- w11a/tb/.cvsignore (nonexistent)
+++ w11a/tb/.cvsignore (revision 7)
@@ -0,0 +1,14 @@
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+to_ptp
+to_lda
+tmu_ofile
+*.dsk
+*.log
+*.log.gz
+*.lst
+*.lda
+lpt.dat
+ptp.dat
+*.LOG
Index: w11a/tb
===================================================================
--- w11a/tb (nonexistent)
+++ w11a/tb (revision 7)
w11a/tb
Property changes :
Added: svn:ignore
## -0,0 +1,46 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+to_ptp
+to_lda
+tmu_ofile
+*.dsk
+*.log
+*.log.gz
+*.lst
+*.lda
+lpt.dat
+ptp.dat
+*.LOG
Index: w11a/nexys2/tb/tb_w11a_n2.vbom
===================================================================
--- w11a/nexys2/tb/tb_w11a_n2.vbom (nonexistent)
+++ w11a/nexys2/tb/tb_w11a_n2.vbom (revision 7)
@@ -0,0 +1,7 @@
+# configure tb_nexys2_fusp with sys_w11a_n2 target;
+# use vhdl configure file (tb_w11a_n2.vhd) to allow
+# that all configurations will co-exist in work library
+nexys2_fusp_aif = ../sys_w11a_n2.vbom
+sys_conf = sys_conf_sim.vhd
+../../../../bplib/nexys2/tb/tb_nexys2_fusp.vbom
+tb_w11a_n2.vhd
Index: w11a/nexys2/tb/tbw.dat
===================================================================
--- w11a/nexys2/tb/tbw.dat (nonexistent)
+++ w11a/nexys2/tb/tbw.dat (revision 7)
@@ -0,0 +1,6 @@
+# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
+#
+[tb_w11a_n2]
+tb_rriext_fifo_rx =
+tb_rriext_fifo_tx =
+tb_rriext_conf =
Index: w11a/nexys2/tb/sys_w11a_n2.ucf_cpp
===================================================================
--- w11a/nexys2/tb/sys_w11a_n2.ucf_cpp (nonexistent)
+++ w11a/nexys2/tb/sys_w11a_n2.ucf_cpp (revision 7)
@@ -0,0 +1 @@
+link ../sys_w11a_n2.ucf_cpp
\ No newline at end of file
w11a/nexys2/tb/sys_w11a_n2.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: w11a/nexys2/tb/sys_conf_sim.vhd
===================================================================
--- w11a/nexys2/tb/sys_conf_sim.vhd (nonexistent)
+++ w11a/nexys2/tb/sys_conf_sim.vhd (revision 7)
@@ -0,0 +1,58 @@
+-- $Id: sys_conf_sim.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_w11a_n2 (for simulation)
+--
+-- Dependencies: -
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-28 295 1.0 Initial version (cloned from _s3)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+ constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+ constant sys_conf_bram : integer := 0; -- no bram, use cache
+ constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
+ constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
+--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
+
+-- constant sys_conf_bram : integer := 1; -- bram only
+-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
+-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
+
+ constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
+
+end package sys_conf;
+
+-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
+-- 2 211 111 111 110 000 000 000
+-- 1 098 765 432 109 876 543 210
+--
+-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
+-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
+-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
+-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
+-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
+-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
+-- upper 256 kB excluded for 11/70 UB
Index: w11a/nexys2/tb/tb_w11a_n2.vhd
===================================================================
--- w11a/nexys2/tb/tb_w11a_n2.vhd (nonexistent)
+++ w11a/nexys2/tb/tb_w11a_n2.vhd (revision 7)
@@ -0,0 +1,40 @@
+-- $Id: tb_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_w11a_n2
+-- Description: Configuration for tb_w11a_n2 for tb_nexys2_fusp
+--
+-- Dependencies: sys_w11a_n2
+--
+-- To test: sys_w11a_n2
+--
+-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat
+-- (#2) ../../tb/tb_pdp11_core_stim.dat):
+-- Date Rev Code ghdl ise Target Comment
+-- 2010-05-28 295 - -.-- - - -:--
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-26 295 1.0 Initial version (cloned from _s3)
+------------------------------------------------------------------------------
+
+configuration tb_w11a_n2 of tb_nexys2_fusp is
+
+ for sim
+ for all : nexys2_fusp_aif
+ use entity work.sys_w11a_n2;
+ end for;
+ end for;
+
+end tb_w11a_n2;
Index: w11a/nexys2/tb/.cvsignore
===================================================================
--- w11a/nexys2/tb/.cvsignore (nonexistent)
+++ w11a/nexys2/tb/.cvsignore (revision 7)
@@ -0,0 +1,8 @@
+tb_w11a_n2
+tb_w11a_n2_[sft]sim
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+tmu_ofile
+sys_w11a_n2.ucf
+*.dep_ucf_cpp
Index: w11a/nexys2/tb/Makefile
===================================================================
--- w11a/nexys2/tb/Makefile (nonexistent)
+++ w11a/nexys2/tb/Makefile (revision 7)
@@ -0,0 +1,30 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-05-26 295 1.0 Initial version
+#
+EXE_all = tb_w11a_n2
+#
+ISE_PATH = xc3s1200e-fg320-4
+#
+#
+.phony : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(wildcard *.o.dep_ghdl)
+#
Index: w11a/nexys2/tb
===================================================================
--- w11a/nexys2/tb (nonexistent)
+++ w11a/nexys2/tb (revision 7)
w11a/nexys2/tb
Property changes :
Added: svn:ignore
## -0,0 +1,40 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_w11a_n2
+tb_w11a_n2_[sft]sim
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+tmu_ofile
+sys_w11a_n2.ucf
+*.dep_ucf_cpp
Index: w11a/nexys2/sys_conf.vhd
===================================================================
--- w11a/nexys2/sys_conf.vhd (nonexistent)
+++ w11a/nexys2/sys_conf.vhd (revision 7)
@@ -0,0 +1,58 @@
+-- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_w11a_n2 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-05 295 1.0 Initial version (derived from _s3 version)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+ constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200
+
+ constant sys_conf_bram : integer := 0; -- no bram, use cache
+ constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
+ constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
+--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
+
+-- constant sys_conf_bram : integer := 1; -- bram only
+-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
+-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
+
+ constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
+
+end package sys_conf;
+
+-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
+-- 2 211 111 111 110 000 000 000
+-- 1 098 765 432 109 876 543 210
+--
+-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
+-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
+-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
+-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
+-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
+-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
+-- upper 256 kB excluded for 11/70 UB
Index: w11a/nexys2/sys_w11a_n2.ucf_cpp
===================================================================
--- w11a/nexys2/sys_w11a_n2.ucf_cpp (nonexistent)
+++ w11a/nexys2/sys_w11a_n2.ucf_cpp (revision 7)
@@ -0,0 +1,19 @@
+## $Id: sys_w11a_n2.ucf_cpp 311 2010-06-30 17:52:37Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2010-05-26 295 1.0 Initial version
+##
+
+NET "CLK" TNM_NET = "CLK";
+TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "CLK";
+OFFSET = OUT 20 ns AFTER "CLK";
+
+## std board
+##
+#include "bplib/nexys2/nexys2_pins.ucf"
+##
+## Pmod B0 - RS232
+##
+#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
Index: w11a/nexys2/sys_w11a_n2.vhd
===================================================================
--- w11a/nexys2/sys_w11a_n2.vhd (nonexistent)
+++ w11a/nexys2/sys_w11a_n2.vhd (revision 7)
@@ -0,0 +1,553 @@
+-- $Id: sys_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_w11a_n2 - syn
+-- Description: w11a test design for nexys2
+--
+-- Dependencies: vlib/genlib/clkdivce
+-- bplib/s3board/s3_rs232_iob_int_ext
+-- bplib/s3board/s3_humanio_rri
+-- vlib/rri/rri_core_serport
+-- vlib/rri/rb_sres_or_3
+-- w11a/pdp11_core_rri
+-- w11a/pdp11_core
+-- w11a/pdp11_bram
+-- vlib/nexys2/n2_cram_dummy
+-- w11a/pdp11_cache
+-- w11a/pdp11_mem70
+-- bplib/nexys2/n2_cram_memctl
+-- ibus/ib_sres_or_2
+-- ibus/ibdr_minisys
+-- ibus/ibdr_maxisys
+-- w11a/pdp11_tmu_sb [sim only]
+--
+-- Test bench: tb/tb_s3board_w11a_n2
+--
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26 - 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+I
+-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II
+-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II
+-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II
+-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II
+-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II
+-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II
+-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II
+-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II
+-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II
+-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II
+-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II
+-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
+-- BUGFIX: resolve rbus address clash hio<->ibr
+-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;
+-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
+-- remove pdp11_ibdr_rri
+-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
+-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust)
+-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
+-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport
+-- use s3_humanio_rri
+-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7
+-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3)
+------------------------------------------------------------------------------
+--
+-- w11a test design for nexys2
+-- w11a + rri + serport
+--
+-- Usage of Nexys 2 Switches, Buttons, LEDs:
+--
+-- SWI(0): 0 -> main board RS232 port
+-- 1 -> Pmod B/top RS232 port
+--
+-- LED(0:4): if cpugo=1 show cpu mode activity
+-- (0) user mode
+-- (1) supervisor mode
+-- (2) kernel mode, wait
+-- (3) kernel mode, pri=0
+-- (4) kernel mode, pri>0
+-- if cpugo=0 shows cpurust
+-- (3:0) cpurust code
+-- (4) '1'
+-- (5) cmdbusy (all rri access, mostly rdma)
+-- (6) MEM_ACT_R
+-- (7) MEM_ACT_W
+--
+-- DP(0): RXSD (inverted to signal activity)
+-- DP(1): RTS_N (shows rx back preasure)
+-- DP(2): TXSD (inverted to signal activity)
+-- DP(3): CTS_N (shows tx back preasure)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.genlib.all;
+use work.rrilib.all;
+use work.s3boardlib.all;
+use work.nexys2lib.all;
+use work.iblib.all;
+use work.ibdlib.all;
+use work.pdp11.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_w11a_n2 is -- top level
+ -- implements nexys2_fusp_aif
+ port (
+ CLK : in slbit; -- clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- s3 switches
+ I_BTN : in slv4; -- s3 buttons
+ O_LED : out slv8; -- s3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_w11a_n2;
+
+architecture syn of sys_w11a_n2 is
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '0';
+ signal RTS_N : slbit := '0';
+ signal CTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal RB_LAM : slv16 := (others=>'0');
+ signal RB_STAT : slv3 := (others=>'0');
+
+ signal RB_MREQ : rb_mreq_type := rb_mreq_init;
+ signal RB_SRES : rb_sres_type := rb_sres_init;
+ signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
+ signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
+ signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
+
+ signal RESET : slbit := '0';
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal CPU_RESET : slbit := '0';
+ signal CP_CNTL : cp_cntl_type := cp_cntl_init;
+ signal CP_ADDR : cp_addr_type := cp_addr_init;
+ signal CP_DIN : slv16 := (others=>'0');
+ signal CP_STAT : cp_stat_type := cp_stat_init;
+ signal CP_DOUT : slv16 := (others=>'0');
+
+ signal EI_PRI : slv3 := (others=>'0');
+ signal EI_VECT : slv9_2 := (others=>'0');
+ signal EI_ACKM : slbit := '0';
+
+ signal EM_MREQ : em_mreq_type := em_mreq_init;
+ signal EM_SRES : em_sres_type := em_sres_init;
+
+ signal HM_ENA : slbit := '0';
+ signal MEM70_FMISS : slbit := '0';
+ signal CACHE_FMISS : slbit := '0';
+ signal CACHE_CHIT : slbit := '0';
+
+ signal MEM_REQ : slbit := '0';
+ signal MEM_WE : slbit := '0';
+ signal MEM_BUSY : slbit := '0';
+ signal MEM_ACK_R : slbit := '0';
+ signal MEM_ACT_R : slbit := '0';
+ signal MEM_ACT_W : slbit := '0';
+ signal MEM_ADDR : slv20 := (others=>'0');
+ signal MEM_BE : slv4 := (others=>'0');
+ signal MEM_DI : slv32 := (others=>'0');
+ signal MEM_DO : slv32 := (others=>'0');
+
+ signal MEM_ADDR_EXT : slv22 := (others=>'0');
+
+ signal BRESET : slbit := '0';
+ signal IB_MREQ : ib_mreq_type := ib_mreq_init;
+ signal IB_SRES : ib_sres_type := ib_sres_init;
+
+ signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
+ signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
+
+ signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
+ signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
+ signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
+ signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
+
+ signal DISPREG : slv16 := (others=>'0');
+
+ constant rbaddr_core0 : slv8 := "00000000";
+ constant rbaddr_ibus : slv8 := "10000000";
+ constant rbaddr_hio : slv8 := "11000000";
+
+begin
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 6,
+ USECDIV => 50,
+ MSECDIV => 1000)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC
+ );
+
+ IOB_RS232 : s3_rs232_iob_int_ext
+ port map (
+ CLK => CLK,
+ SEL => SWI(0),
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ HIO : s3_humanio_rri
+ generic map (
+ DEBOUNCE => sys_conf_hio_debounce,
+ RB_ADDR => rbaddr_hio)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES_HIO,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RRI : rri_core_serport
+ generic map (
+ ATOWIDTH => 6, -- 64 cycles access timeout
+ ITOWIDTH => 6, -- 64 periods max idle timeout
+ CDWIDTH => 13,
+ CDINIT => sys_conf_ser2rri_cdinit)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ CE_INT => CE_MSEC,
+ RESET => RESET,
+ RXSD => RXD,
+ TXSD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES,
+ RB_LAM => RB_LAM,
+ RB_STAT => RB_STAT
+ );
+
+ RB_SRES_OR : rb_sres_or_3
+ port map (
+ RB_SRES_1 => RB_SRES_CPU,
+ RB_SRES_2 => RB_SRES_IBD,
+ RB_SRES_3 => RB_SRES_HIO,
+ RB_SRES_OR => RB_SRES
+ );
+
+ RB2CP : pdp11_core_rri
+ generic map (
+ RB_ADDR_CORE => rbaddr_core0,
+ RB_ADDR_IBUS => rbaddr_ibus)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES_CPU,
+ RB_STAT => RB_STAT,
+ RRI_LAM => RB_LAM(0),
+ CPU_RESET => CPU_RESET,
+ CP_CNTL => CP_CNTL,
+ CP_ADDR => CP_ADDR,
+ CP_DIN => CP_DIN,
+ CP_STAT => CP_STAT,
+ CP_DOUT => CP_DOUT
+ );
+
+ CORE : pdp11_core
+ port map (
+ CLK => CLK,
+ RESET => CPU_RESET,
+ CP_CNTL => CP_CNTL,
+ CP_ADDR => CP_ADDR,
+ CP_DIN => CP_DIN,
+ CP_STAT => CP_STAT,
+ CP_DOUT => CP_DOUT,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ EI_ACKM => EI_ACKM,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES,
+ BRESET => BRESET,
+ IB_MREQ_M => IB_MREQ,
+ IB_SRES_M => IB_SRES,
+ DM_STAT_DP => DM_STAT_DP,
+ DM_STAT_VM => DM_STAT_VM,
+ DM_STAT_CO => DM_STAT_CO
+ );
+
+ MEM_BRAM: if sys_conf_bram > 0 generate
+ signal HM_VAL_BRAM : slbit := '0';
+ begin
+
+ MEM : pdp11_bram
+ generic map (
+ AWIDTH => sys_conf_bram_awidth)
+ port map (
+ CLK => CLK,
+ GRESET => CPU_RESET,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES
+ );
+
+ HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
+
+ MEM70: pdp11_mem70
+ port map (
+ CLK => CLK,
+ CRESET => BRESET,
+ HM_ENA => EM_MREQ.req,
+ HM_VAL => HM_VAL_BRAM,
+ CACHE_FMISS => MEM70_FMISS,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_MEM70
+ );
+
+ SRAM_PROT : n2_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_FLA_CE_N => O_FLA_CE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ end generate MEM_BRAM;
+
+ MEM_SRAM: if sys_conf_bram = 0 generate
+
+ CACHE: pdp11_cache
+ port map (
+ CLK => CLK,
+ GRESET => CPU_RESET,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES,
+ FMISS => CACHE_FMISS,
+ CHIT => CACHE_CHIT,
+ MEM_REQ => MEM_REQ,
+ MEM_WE => MEM_WE,
+ MEM_BUSY => MEM_BUSY,
+ MEM_ACK_R => MEM_ACK_R,
+ MEM_ADDR => MEM_ADDR,
+ MEM_BE => MEM_BE,
+ MEM_DI => MEM_DI,
+ MEM_DO => MEM_DO
+ );
+
+ MEM70: pdp11_mem70
+ port map (
+ CLK => CLK,
+ CRESET => BRESET,
+ HM_ENA => HM_ENA,
+ HM_VAL => CACHE_CHIT,
+ CACHE_FMISS => MEM70_FMISS,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_MEM70
+ );
+
+ HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
+ CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
+
+ MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB)
+
+ SRAM_CTL: n2_cram_memctl_as
+ generic map (
+ READ0DELAY => 2,
+ READ1DELAY => 2,
+ WRITEDELAY => 3)
+ port map (
+ CLK => CLK,
+ RESET => CPU_RESET,
+ REQ => MEM_REQ,
+ WE => MEM_WE,
+ BUSY => MEM_BUSY,
+ ACK_R => MEM_ACK_R,
+ ACK_W => open,
+ ACT_R => MEM_ACT_R,
+ ACT_W => MEM_ACT_W,
+ ADDR => MEM_ADDR_EXT,
+ BE => MEM_BE,
+ DI => MEM_DI,
+ DO => MEM_DO,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_FLA_CE_N => O_FLA_CE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ end generate MEM_SRAM;
+
+ IB_SRES_OR : ib_sres_or_2
+ port map (
+ IB_SRES_1 => IB_SRES_MEM70,
+ IB_SRES_2 => IB_SRES_IBDR,
+ IB_SRES_OR => IB_SRES
+ );
+
+ IBD_MINI : if false generate
+ begin
+ IBDR_SYS : ibdr_minisys
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RESET => CPU_RESET,
+ BRESET => BRESET,
+ RRI_LAM => RB_LAM(15 downto 1),
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_IBDR,
+ EI_ACKM => EI_ACKM,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ DISPREG => DISPREG
+ );
+ end generate IBD_MINI;
+
+ IBD_MAXI : if true generate
+ begin
+ IBDR_SYS : ibdr_maxisys
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RESET => CPU_RESET,
+ BRESET => BRESET,
+ RRI_LAM => RB_LAM(15 downto 1),
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_IBDR,
+ EI_ACKM => EI_ACKM,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ DISPREG => DISPREG
+ );
+ end generate IBD_MAXI;
+
+ DSP_DAT(15 downto 0) <= DISPREG;
+ DSP_DP(0) <= not RXD;
+ DSP_DP(1) <= RTS_N;
+ DSP_DP(2) <= not TXD;
+ DSP_DP(3) <= CTS_N;
+
+ proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw)
+ variable iled : slv8 := (others=>'0');
+ begin
+ iled := (others=>'0');
+ iled(7) := MEM_ACT_W;
+ iled(6) := MEM_ACT_R;
+ iled(5) := CP_STAT.cmdbusy;
+ if CP_STAT.cpugo = '1' then
+ case DM_STAT_DP.psw.cmode is
+ when c_psw_kmode =>
+ if CP_STAT.cpuwait = '1' then
+ iled(2) := '1';
+ elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
+ iled(3) := '1';
+ else
+ iled(4) := '1';
+ end if;
+ when c_psw_smode =>
+ iled(1) := '1';
+ when c_psw_umode =>
+ iled(0) := '1';
+ when others => null;
+ end case;
+ else
+ iled(4) := '1';
+ iled(3 downto 0) := CP_STAT.cpurust;
+ end if;
+ LED <= iled;
+ end process;
+
+-- synthesis translate_off
+ DM_STAT_SY.emmreq <= EM_MREQ;
+ DM_STAT_SY.emsres <= EM_SRES;
+ DM_STAT_SY.chit <= CACHE_CHIT;
+
+ TMU : pdp11_tmu_sb
+ generic map (
+ ENAPIN => 13)
+ port map (
+ CLK => CLK,
+ DM_STAT_DP => DM_STAT_DP,
+ DM_STAT_VM => DM_STAT_VM,
+ DM_STAT_CO => DM_STAT_CO,
+ DM_STAT_SY => DM_STAT_SY
+ );
+
+-- synthesis translate_on
+end syn;
Index: w11a/nexys2/sys_w11a_n2.vbom
===================================================================
--- w11a/nexys2/sys_w11a_n2.vbom (nonexistent)
+++ w11a/nexys2/sys_w11a_n2.vbom (revision 7)
@@ -0,0 +1,30 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/genlib/genlib.vhd
+../../../vlib/rri/rrilib.vhd
+../../../bplib/s3board/s3boardlib.vbom
+../../../bplib/nexys2/nexys2lib.vhd
+../../../ibus/iblib.vhd
+../../../ibus/ibdlib.vhd
+../../../w11a/pdp11.vhd
+sys_conf = sys_conf.vhd
+# components
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
+../../../bplib/s3board/s3_humanio_rri.vbom
+../../../vlib/rri/rri_core_serport.vbom
+../../../vlib/rri/rb_sres_or_3.vbom
+../../../w11a/pdp11_core_rri.vbom
+../../../w11a/pdp11_core.vbom
+../../../w11a/pdp11_bram.vbom
+../../../bplib/nexys2/n2_cram_dummy.vbom
+../../../w11a/pdp11_cache.vbom
+../../../w11a/pdp11_mem70.vbom
+../../../bplib/nexys2/n2_cram_memctl_as.vbom
+../../../ibus/ib_sres_or_2.vbom
+../../../ibus/ibdr_minisys.vbom
+../../../ibus/ibdr_maxisys.vbom
+[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom
+# design
+sys_w11a_n2.vhd
+@ucf_cpp: sys_w11a_n2.ucf
Index: w11a/nexys2/Makefile
===================================================================
--- w11a/nexys2/Makefile (nonexistent)
+++ w11a/nexys2/Makefile (revision 7)
@@ -0,0 +1,32 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-05-28 295 1.0 Initial version (derived from _s3 version)
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+ISE_BOARD = nexys2
+ISE_PATH = xc3s1200e-fg320-4
+#
+.phony : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f sys_w11a_n2.ucf
+#
+sys_w11a_n2.mcs : sys_w11a_n2.bit
+ promgen -w -x xcf04s -p mcs -u 0 sys_w11a_n2
+ mv sys_w11a_n2.prm sys_w11a_n2_prm.log
+ mv sys_w11a_n2.cfi sys_w11a_n2_cfi.log
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
Index: w11a/nexys2/.cvsignore
===================================================================
--- w11a/nexys2/.cvsignore (nonexistent)
+++ w11a/nexys2/.cvsignore (revision 7)
@@ -0,0 +1,4 @@
+sys_w11a_n2.ucf
+*.dep_ucf_cpp
+log_*
+_impact*
Index: w11a/nexys2
===================================================================
--- w11a/nexys2 (nonexistent)
+++ w11a/nexys2 (revision 7)
w11a/nexys2
Property changes :
Added: svn:ignore
## -0,0 +1,36 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+sys_w11a_n2.ucf
+*.dep_ucf_cpp
+log_*
+_impact*
Index: w11a/s3board/tb/tb_w11a_s3.vhd
===================================================================
--- w11a/s3board/tb/tb_w11a_s3.vhd (nonexistent)
+++ w11a/s3board/tb/tb_w11a_s3.vhd (revision 7)
@@ -0,0 +1,49 @@
+-- $Id: tb_w11a_s3.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_w11a_s3
+-- Description: Configuration for tb_w11a_s3 for tb_s3board_fusp
+--
+-- Dependencies: sys_w11a_s3
+--
+-- To test: sys_w11a_s3
+--
+-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat
+-- (#2) ../../tb/tb_pdp11_core_stim.dat):
+-- Date Rev Code ghdl ise Target Comment
+-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#2) 91497s; 632m
+-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#1) 3356s; 632m
+-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#2) 2227s
+-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#1) 82s
+-- 2007-10-21 91 - 0.26 - - d:ok (#2)
+-- 2007-10-19 90 - 0.26 - - d:ok (#2)
+-- 2007-10-19 90 - 0.26 - - d:ok (#1)
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-26 295 1.1.2 rename tb_s3board_pdp11core -> tb_w11a_s3
+-- 2010-05-16 291 1.1.1 use now tb_s3board_fusp
+-- 2010-05-02 287 1.1 use now tb_s3board_usp
+-- 2007-09-23 84 1.0 Initial version
+------------------------------------------------------------------------------
+
+configuration tb_w11a_s3 of tb_s3board_fusp is
+
+ for sim
+ for all : s3board_fusp_aif
+ use entity work.sys_w11a_s3;
+ end for;
+ end for;
+
+end tb_w11a_s3;
Index: w11a/s3board/tb/tbw.dat
===================================================================
--- w11a/s3board/tb/tbw.dat (nonexistent)
+++ w11a/s3board/tb/tbw.dat (revision 7)
@@ -0,0 +1,6 @@
+# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
+#
+[tb_w11a_s3]
+tb_rriext_fifo_rx =
+tb_rriext_fifo_tx =
+tb_rriext_conf =
Index: w11a/s3board/tb/tb_w11a_s3.vbom
===================================================================
--- w11a/s3board/tb/tb_w11a_s3.vbom (nonexistent)
+++ w11a/s3board/tb/tb_w11a_s3.vbom (revision 7)
@@ -0,0 +1,7 @@
+# configure tb_s3board_fusp with sys_w11a_s3 target;
+# use vhdl configure file (tb_w11a_s3.vhd) to allow
+# that all configurations will co-exist in work library
+s3board_fusp_aif = ../sys_w11a_s3.vbom
+sys_conf = sys_conf_sim.vhd
+../../../../bplib/s3board/tb/tb_s3board_fusp.vbom
+tb_w11a_s3.vhd
Index: w11a/s3board/tb/sys_w11a_s3.ucf_cpp
===================================================================
--- w11a/s3board/tb/sys_w11a_s3.ucf_cpp (nonexistent)
+++ w11a/s3board/tb/sys_w11a_s3.ucf_cpp (revision 7)
@@ -0,0 +1 @@
+link ../sys_w11a_s3.ucf_cpp
\ No newline at end of file
w11a/s3board/tb/sys_w11a_s3.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: w11a/s3board/tb/sys_conf_sim.vhd
===================================================================
--- w11a/s3board/tb/sys_conf_sim.vhd (nonexistent)
+++ w11a/s3board/tb/sys_conf_sim.vhd (revision 7)
@@ -0,0 +1,60 @@
+-- $Id: sys_conf_sim.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_w11a_s3 (for simulation)
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce
+-- 2008-02-23 118 1.1 add memory config
+-- 2007-09-23 84 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+ constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+ constant sys_conf_bram : integer := 0; -- no bram, use cache
+ constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
+ constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte
+--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
+
+-- constant sys_conf_bram : integer := 1; -- bram only
+-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB)
+-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte
+
+ constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
+
+end package sys_conf;
+
+-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
+-- 2 211 111 111 110 000 000 000
+-- 1 098 765 432 109 876 543 210
+--
+-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
+-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
+-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
+-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
+-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
+-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
+-- upper 256 kB excluded for 11/70 UB
Index: w11a/s3board/tb/.cvsignore
===================================================================
--- w11a/s3board/tb/.cvsignore (nonexistent)
+++ w11a/s3board/tb/.cvsignore (revision 7)
@@ -0,0 +1,8 @@
+tb_w11a_s3
+tb_w11a_s3_[sft]sim
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+tmu_ofile
+sys_w11a_s3.ucf
+*.dep_ucf_cpp
Index: w11a/s3board/tb/Makefile
===================================================================
--- w11a/s3board/tb/Makefile (nonexistent)
+++ w11a/s3board/tb/Makefile (revision 7)
@@ -0,0 +1,32 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-05-26 295 1.2 rename tb_s3board_pdp11core -> tb_w11a_s3
+# 2007-11-26 98 1.1 add all_ssim and all_tsim targets
+# 2007-09-23 84 1.0 Initial version
+#
+EXE_all = tb_w11a_s3
+#
+ISE_PATH = xc3s1000-ft256-4
+#
+#
+.phony : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(wildcard *.o.dep_ghdl)
+#
Index: w11a/s3board/tb
===================================================================
--- w11a/s3board/tb (nonexistent)
+++ w11a/s3board/tb (revision 7)
w11a/s3board/tb
Property changes :
Added: svn:ignore
## -0,0 +1,40 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_w11a_s3
+tb_w11a_s3_[sft]sim
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
+tmu_ofile
+sys_w11a_s3.ucf
+*.dep_ucf_cpp
Index: w11a/s3board/sys_conf.vhd
===================================================================
--- w11a/s3board/sys_conf.vhd (nonexistent)
+++ w11a/s3board/sys_conf.vhd (revision 7)
@@ -0,0 +1,60 @@
+-- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_w11a_s3 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce
+-- 2008-02-23 118 1.1 add memory config
+-- 2007-09-23 84 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+ constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200
+
+ constant sys_conf_bram : integer := 0; -- no bram, use cache
+ constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
+ constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte
+--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
+
+-- constant sys_conf_bram : integer := 1; -- bram only
+-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
+-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
+
+ constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
+
+end package sys_conf;
+
+-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
+-- 2 211 111 111 110 000 000 000
+-- 1 098 765 432 109 876 543 210
+--
+-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
+-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
+-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
+-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
+-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
+-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
+-- upper 256 kB excluded for 11/70 UB
Index: w11a/s3board/sys_w11a_s3.ucf_cpp
===================================================================
--- w11a/s3board/sys_w11a_s3.ucf_cpp (nonexistent)
+++ w11a/s3board/sys_w11a_s3.ucf_cpp (revision 7)
@@ -0,0 +1,21 @@
+## $Id: sys_w11a_s3.ucf_cpp 311 2010-06-30 17:52:37Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2010-05-02 287 2.0 added defs for pm1 rs232
+## 2007-12-16 101 1.1 converted to ucf_cpp, factor out std pins
+## 2007-12-09 100 1.0 Initial version
+##
+
+NET "CLK" TNM_NET = "CLK";
+TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "CLK";
+OFFSET = OUT 20 ns AFTER "CLK";
+
+## std board
+##
+#include "bplib/s3board/s3board_pins.ucf"
+##
+## Pmod1-RS232 on A2 connector
+##
+#include "bplib/s3board/s3board_a2_pm1_rs232.ucf"
Index: w11a/s3board/sys_w11a_s3.vhd
===================================================================
--- w11a/s3board/sys_w11a_s3.vhd (nonexistent)
+++ w11a/s3board/sys_w11a_s3.vhd (revision 7)
@@ -0,0 +1,519 @@
+-- $Id: sys_w11a_s3.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_w11a_s3 - syn
+-- Description: w11a test design for s3board
+--
+-- Dependencies: vlib/genlib/clkdivce
+-- bplib/s3board/s3_rs232_iob_int_ext
+-- bplib/s3board/s3_humanio
+-- vlib/rri/rri_core_serport
+-- vlib/rri/rb_sres_or_2
+-- w11a/pdp11_core_rri
+-- w11a/pdp11_core
+-- w11a/pdp11_bram
+-- vlib/s3board/s3_sram_dummy
+-- w11a/pdp11_cache
+-- w11a/pdp11_mem70
+-- bplib/s3board/s3_sram_memctl
+-- ibus/ib_sres_or_2
+-- ibus/ibdr_minisys
+-- ibus/ibdr_maxisys
+-- w11a/pdp11_tmu_sb [sim only]
+--
+-- Test bench: tb/tb_s3board_w11a_s3
+--
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 11.4; ghdl 0.18-0.26
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II
+-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II
+-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II
+-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II
+-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II
+-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK
+-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK
+-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK
+-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK
+-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK
+-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK
+-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK
+-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK
+-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32
+-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16
+-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK
+-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16
+-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK
+-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK
+-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL
+-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK
+-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK
+-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK
+-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8
+-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)
+-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
+-- remove pdp11_ibdr_rri
+-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core
+-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ
+-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport
+-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3
+-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_
+-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl
+-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce
+-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
+-- drop RP_IINT from interfaces; drop RTSFLUSH generic
+-- add pm1 rs232 (usp) support
+-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport
+-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy
+-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3)
+-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes
+-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys
+-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu
+-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames
+-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust
+-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg)
+-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu
+-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys
+-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs
+-- 2008-02-23 118 1.3.1 add _mem70
+-- 2008-02-17 117 1.3 use ext. memory interface of _core;
+-- use _cache + memctl or _bram (configurable)
+-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05)
+-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET
+-- add _ib_mux2
+-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack
+-- instanciate all parts directly
+-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb
+-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO
+-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them
+-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch
+-- 2007-09-23 84 1.0 Initial version
+------------------------------------------------------------------------------
+--
+-- w11a test design for s3board
+-- w11a + rri + serport
+--
+-- Usage of S3BOARD Switches, Buttons, LEDs:
+-- LED(7..0):last RXDATA
+--
+-- DP(0): RXSD (inverted to signal activity)
+-- DP(1): RTS_N (shows rx back preasure)
+-- DP(2): TXSD (inverted to signal activity)
+-- DP(3): CTS_N (shows tx back preasure)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.genlib.all;
+use work.rrilib.all;
+use work.s3boardlib.all;
+use work.iblib.all;
+use work.ibdlib.all;
+use work.pdp11.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_w11a_s3 is -- top level
+ -- implements s3board_fusp_aif
+ port (
+ CLK : in slbit; -- clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- s3 switches
+ I_BTN : in slv4; -- s3 buttons
+ O_LED : out slv8; -- s3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32; -- sram: data lines
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_w11a_s3;
+
+architecture syn of sys_w11a_s3 is
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '0';
+ signal RTS_N : slbit := '0';
+ signal CTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal RB_LAM : slv16 := (others=>'0');
+ signal RB_STAT : slv3 := (others=>'0');
+
+ signal RB_MREQ : rb_mreq_type := rb_mreq_init;
+ signal RB_SRES : rb_sres_type := rb_sres_init;
+ signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
+ signal RB_SRES_IBD : rb_sres_type := rb_sres_init;
+
+ signal RESET : slbit := '0';
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal CPU_RESET : slbit := '0';
+ signal CP_CNTL : cp_cntl_type := cp_cntl_init;
+ signal CP_ADDR : cp_addr_type := cp_addr_init;
+ signal CP_DIN : slv16 := (others=>'0');
+ signal CP_STAT : cp_stat_type := cp_stat_init;
+ signal CP_DOUT : slv16 := (others=>'0');
+
+ signal EI_PRI : slv3 := (others=>'0');
+ signal EI_VECT : slv9_2 := (others=>'0');
+ signal EI_ACKM : slbit := '0';
+
+ signal EM_MREQ : em_mreq_type := em_mreq_init;
+ signal EM_SRES : em_sres_type := em_sres_init;
+
+ signal HM_ENA : slbit := '0';
+ signal MEM70_FMISS : slbit := '0';
+ signal CACHE_FMISS : slbit := '0';
+ signal CACHE_CHIT : slbit := '0';
+
+ signal MEM_REQ : slbit := '0';
+ signal MEM_WE : slbit := '0';
+ signal MEM_BUSY : slbit := '0';
+ signal MEM_ACK_R : slbit := '0';
+ signal MEM_ADDR : slv20 := (others=>'0');
+ signal MEM_BE : slv4 := (others=>'0');
+ signal MEM_DI : slv32 := (others=>'0');
+ signal MEM_DO : slv32 := (others=>'0');
+
+ signal BRESET : slbit := '0';
+ signal IB_MREQ : ib_mreq_type := ib_mreq_init;
+ signal IB_SRES : ib_sres_type := ib_sres_init;
+
+ signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
+ signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
+
+ signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
+ signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
+ signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
+ signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init;
+
+ signal DISPREG : slv16 := (others=>'0');
+
+ constant rbaddr_core0 : slv8 := "00000000";
+ constant rbaddr_ibus : slv8 := "10000000";
+ constant rbaddr_hio : slv8 := "11000000";
+
+begin
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 6,
+ USECDIV => 50,
+ MSECDIV => 1000)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC
+ );
+
+ IOB_RS232 : s3_rs232_iob_int_ext
+ port map (
+ CLK => CLK,
+ SEL => SWI(0),
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ HIO : s3_humanio
+ generic map (
+ DEBOUNCE => sys_conf_hio_debounce)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RRI : rri_core_serport
+ generic map (
+ ATOWIDTH => 6, -- 64 cycles access timeout
+ ITOWIDTH => 6, -- 64 periods max idle timeout
+ CDWIDTH => 13,
+ CDINIT => sys_conf_ser2rri_cdinit)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ CE_INT => CE_MSEC,
+ RESET => RESET,
+ RXSD => RXD,
+ TXSD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES,
+ RB_LAM => RB_LAM,
+ RB_STAT => RB_STAT
+ );
+
+ RB_SRES_OR : rb_sres_or_2
+ port map (
+ RB_SRES_1 => RB_SRES_CPU,
+ RB_SRES_2 => RB_SRES_IBD,
+ RB_SRES_OR => RB_SRES
+ );
+
+ RP2CP : pdp11_core_rri
+ generic map (
+ RB_ADDR_CORE => rbaddr_core0,
+ RB_ADDR_IBUS => rbaddr_ibus)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ RB_MREQ => RB_MREQ,
+ RB_SRES => RB_SRES_CPU,
+ RB_STAT => RB_STAT,
+ RRI_LAM => RB_LAM(0),
+ CPU_RESET => CPU_RESET,
+ CP_CNTL => CP_CNTL,
+ CP_ADDR => CP_ADDR,
+ CP_DIN => CP_DIN,
+ CP_STAT => CP_STAT,
+ CP_DOUT => CP_DOUT
+ );
+
+ CORE : pdp11_core
+ port map (
+ CLK => CLK,
+ RESET => CPU_RESET,
+ CP_CNTL => CP_CNTL,
+ CP_ADDR => CP_ADDR,
+ CP_DIN => CP_DIN,
+ CP_STAT => CP_STAT,
+ CP_DOUT => CP_DOUT,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ EI_ACKM => EI_ACKM,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES,
+ BRESET => BRESET,
+ IB_MREQ_M => IB_MREQ,
+ IB_SRES_M => IB_SRES,
+ DM_STAT_DP => DM_STAT_DP,
+ DM_STAT_VM => DM_STAT_VM,
+ DM_STAT_CO => DM_STAT_CO
+ );
+
+ MEM_BRAM: if sys_conf_bram > 0 generate
+ signal HM_VAL_BRAM : slbit := '0';
+ begin
+
+ MEM : pdp11_bram
+ generic map (
+ AWIDTH => sys_conf_bram_awidth)
+ port map (
+ CLK => CLK,
+ GRESET => CPU_RESET,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES
+ );
+
+ HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write
+
+ MEM70: pdp11_mem70
+ port map (
+ CLK => CLK,
+ CRESET => BRESET,
+ HM_ENA => EM_MREQ.req,
+ HM_VAL => HM_VAL_BRAM,
+ CACHE_FMISS => MEM70_FMISS,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_MEM70
+ );
+
+ SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ end generate MEM_BRAM;
+
+ MEM_SRAM: if sys_conf_bram = 0 generate
+
+ CACHE: pdp11_cache
+ port map (
+ CLK => CLK,
+ GRESET => CPU_RESET,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES,
+ FMISS => CACHE_FMISS,
+ CHIT => CACHE_CHIT,
+ MEM_REQ => MEM_REQ,
+ MEM_WE => MEM_WE,
+ MEM_BUSY => MEM_BUSY,
+ MEM_ACK_R => MEM_ACK_R,
+ MEM_ADDR => MEM_ADDR,
+ MEM_BE => MEM_BE,
+ MEM_DI => MEM_DI,
+ MEM_DO => MEM_DO
+ );
+
+ MEM70: pdp11_mem70
+ port map (
+ CLK => CLK,
+ CRESET => BRESET,
+ HM_ENA => HM_ENA,
+ HM_VAL => CACHE_CHIT,
+ CACHE_FMISS => MEM70_FMISS,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_MEM70
+ );
+
+ HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
+ CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
+
+ SRAM_CTL: s3_sram_memctl
+ port map (
+ CLK => CLK,
+ RESET => CPU_RESET,
+ REQ => MEM_REQ,
+ WE => MEM_WE,
+ BUSY => MEM_BUSY,
+ ACK_R => MEM_ACK_R,
+ ACK_W => open,
+ ACT_R => open,
+ ACT_W => open,
+ ADDR => MEM_ADDR(17 downto 0),
+ BE => MEM_BE,
+ DI => MEM_DI,
+ DO => MEM_DO,
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ end generate MEM_SRAM;
+
+ IB_SRES_OR : ib_sres_or_2
+ port map (
+ IB_SRES_1 => IB_SRES_MEM70,
+ IB_SRES_2 => IB_SRES_IBDR,
+ IB_SRES_OR => IB_SRES);
+
+ IBD_MINI : if false generate
+ begin
+ IBDR_SYS : ibdr_minisys
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RESET => CPU_RESET,
+ BRESET => BRESET,
+ RRI_LAM => RB_LAM(15 downto 1),
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_IBDR,
+ EI_ACKM => EI_ACKM,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ DISPREG => DISPREG);
+ end generate IBD_MINI;
+
+ IBD_MAXI : if true generate
+ begin
+ IBDR_SYS : ibdr_maxisys
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RESET => CPU_RESET,
+ BRESET => BRESET,
+ RRI_LAM => RB_LAM(15 downto 1),
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_IBDR,
+ EI_ACKM => EI_ACKM,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ DISPREG => DISPREG);
+ end generate IBD_MAXI;
+
+ DSP_DAT(15 downto 0) <= DISPREG;
+ DSP_DP(0) <= not RXD;
+ DSP_DP(1) <= RTS_N;
+ DSP_DP(2) <= not TXD;
+ DSP_DP(3) <= CTS_N;
+
+ LED(0) <= CP_STAT.cpugo;
+ LED(1) <= CP_STAT.cpuhalt;
+ LED(5 downto 2) <= CP_STAT.cpurust;
+ LED(6) <= SWI(0) or SWI(1) or SWI(2) or SWI(3) or
+ SWI(4) or SWI(5) or SWI(6) or SWI(7);
+ LED(7) <= BTN(0) or BTN(1) or BTN(2) or BTN(3);
+
+-- synthesis translate_off
+ DM_STAT_SY.emmreq <= EM_MREQ;
+ DM_STAT_SY.emsres <= EM_SRES;
+ DM_STAT_SY.chit <= CACHE_CHIT;
+
+ TMU : pdp11_tmu_sb
+ generic map (
+ ENAPIN => 13)
+ port map (
+ CLK => CLK,
+ DM_STAT_DP => DM_STAT_DP,
+ DM_STAT_VM => DM_STAT_VM,
+ DM_STAT_CO => DM_STAT_CO,
+ DM_STAT_SY => DM_STAT_SY
+ );
+
+-- synthesis translate_on
+end syn;
Index: w11a/s3board/.cvsignore
===================================================================
--- w11a/s3board/.cvsignore (nonexistent)
+++ w11a/s3board/.cvsignore (revision 7)
@@ -0,0 +1,4 @@
+sys_w11a_s3.ucf
+*.dep_ucf_cpp
+log_*
+_impact*
Index: w11a/s3board/Makefile
===================================================================
--- w11a/s3board/Makefile (nonexistent)
+++ w11a/s3board/Makefile (revision 7)
@@ -0,0 +1,37 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-05-28 295 1.1.4 rename sys_pdp11core -> sys_w11a_s3
+# 2010-04-24 282 1.1.3 use %.impact rule, all=BIT_all now
+# 2009-11-20 251 1.1.2 add .mcs rule
+# 2009-07-26 236 1.1.1 add program: rule
+# 2007-11-26 98 1.1 include $(RETROBASE)/vlib/Makefile.(ghdl|xflow)
+# 2007-07-08 65 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+ISE_BOARD = s3board
+ISE_PATH = xc3s1000-ft256-4
+#
+.phony : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f sys_w11a_s3.ucf
+#
+sys_w11a_s3.mcs : sys_w11a_s3.bit
+ promgen -w -x xcf04s -p mcs -u 0 sys_w11a_s3
+ mv sys_w11a_s3.prm sys_w11a_s3_prm.log
+ mv sys_w11a_s3.cfi sys_w11a_s3_cfi.log
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
Index: w11a/s3board/sys_w11a_s3.vbom
===================================================================
--- w11a/s3board/sys_w11a_s3.vbom (nonexistent)
+++ w11a/s3board/sys_w11a_s3.vbom (revision 7)
@@ -0,0 +1,29 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/genlib/genlib.vhd
+../../../vlib/rri/rrilib.vhd
+../../../bplib/s3board/s3boardlib.vbom
+../../../ibus/iblib.vhd
+../../../ibus/ibdlib.vhd
+../../../w11a/pdp11.vhd
+sys_conf = sys_conf.vhd
+# components
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
+../../../bplib/s3board/s3_humanio.vbom
+../../../vlib/rri/rri_core_serport.vbom
+../../../vlib/rri/rb_sres_or_2.vbom
+../../../w11a/pdp11_core_rri.vbom
+../../../w11a/pdp11_core.vbom
+../../../w11a/pdp11_bram.vbom
+../../../bplib/s3board/s3_sram_dummy.vbom
+../../../w11a/pdp11_cache.vbom
+../../../w11a/pdp11_mem70.vbom
+../../../bplib/s3board/s3_sram_memctl.vbom
+../../../ibus/ib_sres_or_2.vbom
+../../../ibus/ibdr_minisys.vbom
+../../../ibus/ibdr_maxisys.vbom
+[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom
+# design
+sys_w11a_s3.vhd
+@ucf_cpp: sys_w11a_s3.ucf
Index: w11a/s3board
===================================================================
--- w11a/s3board (nonexistent)
+++ w11a/s3board (revision 7)
w11a/s3board
Property changes :
Added: svn:ignore
## -0,0 +1,36 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+sys_w11a_s3.ucf
+*.dep_ucf_cpp
+log_*
+_impact*
Index: w11a
===================================================================
--- w11a (nonexistent)
+++ w11a (revision 7)
w11a
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 7)
.
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log