OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.5/rtl/vlib/comlib/misc
    from Rev 3 to Rev 7
    ↔ Reverse comparison
  •

Rev 3 → Rev 7

/gen_crc8_tbl_check.vhd
0,0 → 1,100
-- $Id: gen_crc8_tbl_check.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to test crc8 transition table
--
-- Dependencies: -
--
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
--use work.slvtypes.all;
--use work.comlib.all;
 
entity gen_crc8_tbl_check is
end gen_crc8_tbl_check;
 
architecture sim of gen_crc8_tbl_check is
begin
process
type crc8_tbl_type is array (0 to 255) of integer;
variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
( 0, 29, 58, 39, 116, 105, 78, 83,
232, 245, 210, 207, 156, 129, 166, 187,
205, 208, 247, 234, 185, 164, 131, 158,
37, 56, 31, 2, 81, 76, 107, 118,
135, 154, 189, 160, 243, 238, 201, 212,
111, 114, 85, 72, 27, 6, 33, 60,
74, 87, 112, 109, 62, 35, 4, 25,
162, 191, 152, 133, 214, 203, 236, 241,
19, 14, 41, 52, 103, 122, 93, 64,
251, 230, 193, 220, 143, 146, 181, 168,
222, 195, 228, 249, 170, 183, 144, 141,
54, 43, 12, 17, 66, 95, 120, 101,
148, 137, 174, 179, 224, 253, 218, 199,
124, 97, 70, 91, 8, 21, 50, 47,
89, 68, 99, 126, 45, 48, 23, 10,
177, 172, 139, 150, 197, 216, 255, 226,
38, 59, 28, 1, 82, 79, 104, 117,
206, 211, 244, 233, 186, 167, 128, 157,
235, 246, 209, 204, 159, 130, 165, 184,
3, 30, 57, 36, 119, 106, 77, 80,
161, 188, 155, 134, 213, 200, 239, 242,
73, 84, 115, 110, 61, 32, 7, 26,
108, 113, 86, 75, 24, 5, 34, 63,
132, 153, 190, 163, 240, 237, 202, 215,
53, 40, 15, 18, 65, 92, 123, 102,
221, 192, 231, 250, 169, 180, 147, 142,
248, 229, 194, 223, 140, 145, 182, 171,
16, 13, 42, 55, 100, 121, 94, 67,
178, 175, 136, 149, 198, 219, 252, 225,
90, 71, 96, 125, 46, 51, 20, 9,
127, 98, 69, 88, 11, 22, 49, 44,
151, 138, 173, 176, 227, 254, 217, 196
);
variable crc : integer := 0;
variable oline : line;
begin
loop_i: for i in 0 to 255 loop
write(oline, i, right, 4);
write(oline, string'(": cycle length = "));
crc := i;
loop_n: for n in 1 to 256 loop
crc := crc8_tbl(crc);
if crc = i then
write(oline, n, right, 4);
writeline(output, oline);
exit loop_n;
end if;
end loop; -- n
end loop; -- i
wait;
end process;
 
end sim;
/gen_crc8_tbl_check.vbom
0,0 → 1,6
#libs
#../../slvtypes.vhd
#../comlib.vhd
#components
#design
gen_crc8_tbl_check.vhd
/gen_crc8_tbl.vhd
0,0 → 1,61
-- $Id: gen_crc8_tbl.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gen_crc8_tbl - sim
-- Description: stand-alone program to print crc8 transition table
--
-- Dependencies: comlib/crc8_update (procedure)
--
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-07-08 65 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.comlib.all;
 
entity gen_crc8_tbl is
end gen_crc8_tbl;
 
architecture sim of gen_crc8_tbl is
begin
process
variable crc : slv8 := (others=>'0');
variable dat : slv8 := (others=>'0');
variable oline : line;
begin
for i in 0 to 255 loop
crc := (others=>'0');
dat := conv_std_logic_vector(i,8);
crc8_update(crc, dat);
write(oline, conv_integer(unsigned(crc)), right, 4);
if i /= 255 then
write(oline, string'(","));
end if;
if (i mod 8) = 7 then
writeline(output, oline);
end if;
end loop; -- i
wait;
end process;
 
end sim;
/gen_crc8_tbl.vbom
0,0 → 1,6
#libs
../../slvtypes.vhd
../comlib.vhd
#components
#design
gen_crc8_tbl.vhd
/Makefile
0,0 → 1,25
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2007-11-26 98 1.0 Initial version
#
EXE_all = gen_crc8_tbl gen_crc8_tbl_check
#
#
.phony : all clean
#
all : $(EXE_all)
#
clean : ghdl_clean
#
#-----
#
include $(RETROBASE)/rtl/vlib/Makefile.ghdl
#
VBOM_all = $(wildcard *.vbom)
#
include $(VBOM_all:.vbom=.dep_ghdl)
#
#-----
#
/.cvsignore
0,0 → 1,2
gen_crc8_tbl
gen_crc8_tbl_check
/.
. Property changes : Added: svn:ignore ## -0,0 +1,34 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +gen_crc8_tbl +gen_crc8_tbl_check

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.