Subversion Repositories w11

/misc/gen_crc8_tbl_check.vhd

/misc/gen_crc8_tbl_check.vbom

/misc/gen_crc8_tbl.vhd

/misc/gen_crc8_tbl.vbom

/misc/Makefile

/misc/.cvsignore

/misc

misc Property changes : Added: svn:ignore ## -0,0 +1,34 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +gen_crc8_tbl +gen_crc8_tbl_check Index: crc8.vhd =================================================================== --- crc8.vhd (nonexistent) +++ crc8.vhd (revision 7) @@ -0,0 +1,101 @@ +-- $Id: crc8.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: crc8 - syn +-- Description: 8bit CRC generator, use CRC-8-SAE J1850 polynomial. +-- Based on CRC-8-SAE J1850 polynomial: +-- x^8 + x^4 + x^3 + x^2 + 1 (0x1d) +-- It is irreducible, and can be implemented with <= 54 xor's +-- +-- Notes: # XST synthesis for a Spartan-3 gives: +-- 1-bit xor2 : 11 +-- 1-bit xor4 : 5 +-- 1-bit xor5 : 1 +-- Number of 4 input LUTs: 20 +-- # Synthesis with crc8_update_tbl gives a lut-rom based table +-- design. Even though a 256x8 bit ROM is behind, the optimizer +-- gets it into 12 slices with 22 4 input LUTs, thus only +-- little larger than with xor's. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2007-07-08 65 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.comlib.all; + +entity crc8 is -- crc-8 generator, checker + generic ( + INIT: slv8 := "00000000"); -- initial state of crc register + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + ENA : in slbit; -- update enable + DI : in slv8; -- input data + CRC : out slv8 -- crc code + ); +end crc8; + + +architecture syn of crc8 is + + signal R_CRC : slv8 := INIT; -- state registers + signal N_CRC : slv8 := INIT; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + if RESET = '1' then + R_CRC <= INIT; + else + R_CRC <= N_CRC; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_CRC, DI, ENA) + + variable r : slv8 := INIT; + variable n : slv8 := INIT; + + begin + + r := R_CRC; + n := R_CRC; + + if ENA = '1' then + crc8_update(n, DI); + end if; + + N_CRC <= n; + + CRC <= R_CRC; + + end process proc_next; + + +end syn; Index: crc8.vbom =================================================================== --- crc8.vbom (nonexistent) +++ crc8.vbom (revision 7) @@ -0,0 +1,5 @@ +# libs +../slvtypes.vhd +comlib.vhd +# design +crc8.vhd Index: cdata2byte.vhd =================================================================== --- cdata2byte.vhd (nonexistent) +++ cdata2byte.vhd (revision 7) @@ -0,0 +1,168 @@ +-- $Id: cdata2byte.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: cdata2byte - syn +-- Description: 9 bit comma,data to Byte stream converter +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-06-30 62 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; + +entity cdata2byte is -- 9bit comma,data -> byte stream + generic ( + CPREF : slv4 := "1000"; -- comma prefix + NCOMM : positive := 4); -- number of comma chars + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + DI : in slv9; -- input data; bit 8 = komma flag + ENA : in slbit; -- write enable + BUSY : out slbit; -- write port hold + DO : out slv8; -- output data + VAL : out slbit; -- read valid + HOLD : in slbit -- read hold + ); +end cdata2byte; + + +architecture syn of cdata2byte is + + type state_type is ( + s_idle, + s_data, + s_comma, + s_escape, + s_edata + ); + + type regs_type is record + data : slv8; -- current data + state : state_type; -- state + end record regs_type; + + constant regs_init : regs_type := ( + (others=>'0'), + s_idle + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + assert NCOMM <= 14 + report "assert(NCOMM <= 14)" + severity FAILURE; + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, DI, ENA, HOLD) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable ido : slv8 := (others=>'0'); + variable ival : slbit := '0'; + variable ibusy : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + ido := r.data; + ival := '0'; + ibusy := '1'; + + case r.state is + + when s_idle => + ibusy := '0'; + if ENA = '1' then + n.data := DI(7 downto 0); + n.state := s_data; + if DI(8) = '1' then + n.state := s_comma; + else + if DI(7 downto 4)=CPREF and + (DI(3 downto 0)="1111" or + unsigned(DI(3 downto 0))<=NCOMM) then + n.state := s_escape; + end if; + end if; + end if; + + when s_data => + ival := '1'; + if HOLD = '0' then + n.state := s_idle; + end if; + + when s_comma => + ido := CPREF & r.data(3 downto 0); + ival := '1'; + if HOLD = '0' then + n.state := s_idle; + end if; + + when s_escape => + ido := CPREF & "1111"; + ival := '1'; + if HOLD = '0' then + n.state := s_edata; + end if; + + when s_edata => + ido := (not CPREF) & r.data(3 downto 0); + ival := '1'; + if HOLD = '0' then + n.state := s_idle; + end if; + + when others => null; + end case; + + N_REGS <= n; + + DO <= ido; + VAL <= ival; + BUSY <= ibusy; + + end process proc_next; + + +end syn; Index: byte2cdata.vhd =================================================================== --- byte2cdata.vhd (nonexistent) +++ byte2cdata.vhd (revision 7) @@ -0,0 +1,149 @@ +-- $Id: byte2cdata.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: byte2cdata - syn +-- Description: Byte stream to 9 bit comma,data converter +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-08-27 76 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; + +entity byte2cdata is -- byte stream -> 9bit comma,data + generic ( + CPREF : slv4 := "1000"; -- comma prefix + NCOMM : positive := 4); -- number of comma chars + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + DI : in slv8; -- input data + ENA : in slbit; -- write enable + BUSY : out slbit; -- write port hold + DO : out slv9; -- output data; bit 8 = komma flag + VAL : out slbit; -- read valid + HOLD : in slbit -- read hold + ); +end byte2cdata; + + +architecture syn of byte2cdata is + + type state_type is ( + s_idle, + s_data, + s_escape + ); + + type regs_type is record + data : slv9; -- current data + state : state_type; -- state + end record regs_type; + + constant regs_init : regs_type := ( + (others=>'0'), + s_idle + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + assert NCOMM <= 14 + report "assert(NCOMM <= 14)" + severity FAILURE; + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, DI, ENA, HOLD) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable ival : slbit := '0'; + variable ibusy : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + ival := '0'; + ibusy := '1'; + + case r.state is + + when s_idle => + ibusy := '0'; + if ENA = '1' then + n.data := "0" & DI; + n.state := s_data; + if DI(7 downto 4) = CPREF then + if DI(3 downto 0) = "1111" then + n.state := s_escape; + elsif unsigned(DI(3 downto 0)) <= NCOMM then + n.data := "10000" & DI(3 downto 0); + n.state := s_data; + end if; + end if; + end if; + + when s_data => + ival := '1'; + if HOLD = '0' then + n.state := s_idle; + end if; + + when s_escape => + ibusy := '0'; + if ENA = '1' then + n.data := "0" & CPREF & DI(3 downto 0); + n.state := s_data; + end if; + + when others => null; + end case; + + N_REGS <= n; + + DO <= r.data; + VAL <= ival; + BUSY <= ibusy; + + end process proc_next; + + +end syn; Index: byte2cdata.vbom =================================================================== --- byte2cdata.vbom (nonexistent) +++ byte2cdata.vbom (revision 7) @@ -0,0 +1,4 @@ +# libs +../slvtypes.vhd +# design +byte2cdata.vhd Index: cdata2byte.vbom =================================================================== --- cdata2byte.vbom (nonexistent) +++ cdata2byte.vbom (revision 7) @@ -0,0 +1,4 @@ +# libs +../slvtypes.vhd +# design +cdata2byte.vhd Index: comlib.vhd =================================================================== --- comlib.vhd (nonexistent) +++ comlib.vhd (revision 7) @@ -0,0 +1,155 @@ +-- $Id: comlib.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: comlib +-- Description: communication components +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-07-08 65 1.2 added procedure crc8_update_tbl +-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT +-- 2007-06-17 58 1.1 add crc8 +-- 2007-06-03 45 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; + +package comlib is + +component cdata2byte is -- 9bit comma,data -> byte stream + generic ( + CPREF : slv4 := "1000"; -- comma prefix + NCOMM : positive := 4); -- number of comma chars + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + DI : in slv9; -- input data; bit 8 = komma flag + ENA : in slbit; -- write enable + BUSY : out slbit; -- write port hold + DO : out slv8; -- output data + VAL : out slbit; -- read valid + HOLD : in slbit -- read hold + ); +end component; + +component byte2cdata is -- byte stream -> 9bit comma,data + generic ( + CPREF : slv4 := "1000"; -- comma prefix + NCOMM : positive := 4); -- number of comma chars + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + DI : in slv8; -- input data + ENA : in slbit; -- write enable + BUSY : out slbit; -- write port hold + DO : out slv9; -- output data; bit 8 = komma flag + VAL : out slbit; -- read valid + HOLD : in slbit -- read hold + ); +end component; + +component crc8 is -- crc-8 generator, checker + generic ( + INIT: slv8 := "00000000"); -- initial state of crc register + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + ENA : in slbit; -- update enable + DI : in slv8; -- input data + CRC : out slv8 -- crc code + ); +end component; + + procedure crc8_update (crc : inout slv8; + data : in slv8); + procedure crc8_update_tbl (crc : inout slv8; + data : in slv8); + +end comlib; + +-- ---------------------------------------------------------------------------- + +package body comlib is + + procedure crc8_update (crc : inout slv8; + data : in slv8) is + variable t : slv8 := (others=>'0'); + begin + + t := data xor crc; + crc(0) := t(0) xor t(4) xor t(5) xor t(6); + crc(1) := t(1) xor t(5) xor t(6) xor t(7); + crc(2) := t(0) xor t(2) xor t(4) xor t(5) xor t(7); + crc(3) := t(0) xor t(1) xor t(3) xor t(4); + crc(4) := t(0) xor t(1) xor t(2) xor t(6); + crc(5) := t(1) xor t(2) xor t(3) xor t(7); + crc(6) := t(2) xor t(3) xor t(4); + crc(7) := t(3) xor t(4) xor t(5); + + end procedure crc8_update; + + procedure crc8_update_tbl (crc : inout slv8; + data : in slv8) is + + type crc8_tbl_type is array (0 to 255) of integer; + variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl + ( 0, 29, 58, 39, 116, 105, 78, 83, + 232, 245, 210, 207, 156, 129, 166, 187, + 205, 208, 247, 234, 185, 164, 131, 158, + 37, 56, 31, 2, 81, 76, 107, 118, + 135, 154, 189, 160, 243, 238, 201, 212, + 111, 114, 85, 72, 27, 6, 33, 60, + 74, 87, 112, 109, 62, 35, 4, 25, + 162, 191, 152, 133, 214, 203, 236, 241, + 19, 14, 41, 52, 103, 122, 93, 64, + 251, 230, 193, 220, 143, 146, 181, 168, + 222, 195, 228, 249, 170, 183, 144, 141, + 54, 43, 12, 17, 66, 95, 120, 101, + 148, 137, 174, 179, 224, 253, 218, 199, + 124, 97, 70, 91, 8, 21, 50, 47, + 89, 68, 99, 126, 45, 48, 23, 10, + 177, 172, 139, 150, 197, 216, 255, 226, + 38, 59, 28, 1, 82, 79, 104, 117, + 206, 211, 244, 233, 186, 167, 128, 157, + 235, 246, 209, 204, 159, 130, 165, 184, + 3, 30, 57, 36, 119, 106, 77, 80, + 161, 188, 155, 134, 213, 200, 239, 242, + 73, 84, 115, 110, 61, 32, 7, 26, + 108, 113, 86, 75, 24, 5, 34, 63, + 132, 153, 190, 163, 240, 237, 202, 215, + 53, 40, 15, 18, 65, 92, 123, 102, + 221, 192, 231, 250, 169, 180, 147, 142, + 248, 229, 194, 223, 140, 145, 182, 171, + 16, 13, 42, 55, 100, 121, 94, 67, + 178, 175, 136, 149, 198, 219, 252, 225, + 90, 71, 96, 125, 46, 51, 20, 9, + 127, 98, 69, 88, 11, 22, 49, 44, + 151, 138, 173, 176, 227, 254, 217, 196 + ); + + begin + + crc := conv_std_logic_vector( + crc8_tbl(conv_integer(unsigned(data xor crc))), 8); + + end procedure crc8_update_tbl; + +end package body comlib; Index: Makefile =================================================================== --- Makefile (nonexistent) +++ Makefile (revision 7) @@ -0,0 +1,22 @@ +# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2007-07-06 64 1.1 use Makefile.xflow +# 2007-06-03 45 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +.phony : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/vlib/Makefile.xflow +# +include $(VBOM_all:.vbom=.dep_xst) +# Index: . =================================================================== --- . (nonexistent) +++ . (revision 7)

. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log