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  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.5/rtl/vlib/genlib
    from Rev 3 to Rev 7
    ↔ Reverse comparison
  •

Rev 3 → Rev 7

/debounce_gen.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
debounce_gen.vhd
/genlib.vhd
0,0 → 1,156
-- $Id: genlib.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: genlib
-- Description: some general purpose components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
-- 2010-04-02 273 1.0.6 add timer
-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
-- 2007-12-25 105 1.0.3 RESET:='0' defaults
-- 2007-06-17 58 1.0.2 added debounce_gen
-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package genlib is
 
component clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end component;
component cnt_array_dram is -- counter array, dram based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : out slv(AWIDTH-1 downto 0); -- counter address
DATA : out slv(DWIDTH-1 downto 0); -- counter data
ACT : out slbit -- active (not reseting)
);
end component;
 
component cnt_array_regs is -- counter array, register based
generic (
AWIDTH : positive := 4; -- address width
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- clear counters
CE : in slv(2**AWIDTH-1 downto 0); -- count enables
ADDR : in slv(AWIDTH-1 downto 0); -- address
DATA : out slv(DWIDTH-1 downto 0) -- counter data
);
end component;
 
component debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
 
component gray_cnt_gen is -- gray code counter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
 
component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end component;
 
component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end component;
 
component gray_cnt_n is -- n bit gray code counter
generic (
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
 
component gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end component;
 
component timer is -- retriggerable timer
generic (
TWIDTH : positive := 4; -- timer counter width
RETRIG : boolean := true); -- re-triggerable true/false
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
START : in slbit; -- start timer
STOP : in slbit := '0'; -- stop timer
DONE : out slbit; -- mark last delay cycle
BUSY : out slbit -- timer running
);
end component;
 
end genlib;
/clkdivce.vhd
0,0 → 1,114
-- $Id: clkdivce.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: clkgen - syn
-- Description: Generate usec and msec enable signals
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
 
entity clkdivce is -- generate usec/msec ce pulses
generic (
CDUWIDTH : positive := 6; -- usec clock divider width
USECDIV : positive := 50; -- divider ratio for usec pulse
MSECDIV : positive := 1000); -- divider ratio for msec pulse
port (
CLK : in slbit; -- input clock
CE_USEC : out slbit; -- usec pulse
CE_MSEC : out slbit -- msec pulse
);
end clkdivce;
 
 
architecture syn of clkdivce is
 
type regs_type is record
ucnt : slv(CDUWIDTH-1 downto 0); -- usec clock divider counter
mcnt : slv10; -- msec clock divider counter
usec : slbit; -- usec pulse
msec : slbit; -- msec pulse
end record regs_type;
 
constant regs_init : regs_type := (
conv_std_logic_vector(USECDIV-1,CDUWIDTH),
conv_std_logic_vector(MSECDIV-1,10),
'0','0'
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
 
assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024
report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " &
"USECDIV too large for given CDUWIDTH or MSECDIV>1024"
severity FAILURE;
 
proc_regs: process (CLK)
begin
 
if CLK'event and CLK='1' then
R_REGS <= N_REGS;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
begin
 
r := R_REGS;
n := R_REGS;
 
n.usec := '0';
n.msec := '0';
 
n.ucnt := unsigned(r.ucnt) - 1;
if unsigned(r.ucnt) = 0 then
n.usec := '1';
n.ucnt := conv_std_logic_vector(USECDIV-1,CDUWIDTH);
n.mcnt := unsigned(r.mcnt) - 1;
if unsigned(r.mcnt) = 0 then
n.msec := '1';
n.mcnt := conv_std_logic_vector(MSECDIV-1,10);
end if;
end if;
N_REGS <= n;
 
CE_USEC <= r.usec;
CE_MSEC <= r.msec;
end process proc_next;
 
 
end syn;
/clkdivce.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
clkdivce.vhd
/debounce_gen.vhd
0,0 → 1,132
-- $Id: debounce_gen.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: debounce_gen - syn
-- Description: Generic signal debouncer
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 105 1.0.2 add default for RESET
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-29 61 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
 
entity debounce_gen is -- debounce, generic vector
generic (
CWIDTH : positive := 2; -- clock interval counter width
CEDIV : positive := 3; -- clock interval divider
DWIDTH : positive := 8); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_INT : in slbit; -- clock interval enable (usec or msec)
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end entity debounce_gen;
 
 
architecture syn of debounce_gen is
 
constant cntzero : slv(CWIDTH-1 downto 0) := (others=>'0');
constant datazero : slv(dWIDTH-1 downto 0) := (others=>'0');
 
type regs_type is record
cecnt : slv(CWIDTH-1 downto 0); -- clock interval counter
dref : slv(DWIDTH-1 downto 0); -- data reference
dchange : slv(DWIDTH-1 downto 0); -- data change flag
dout : slv(DWIDTH-1 downto 0); -- data output
end record regs_type;
constant regs_init : regs_type := (
cntzero,
datazero,
datazero,
datazero
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
begin
 
assert CEDIV<=2**CWIDTH report "assert(CEDIV<=2**CWIDTH)" severity failure;
 
proc_regs: process (CLK)
begin
 
if CLK'event and CLK='1' then
if RESET = '1' then
R_REGS.cecnt <= cntzero;
R_REGS.dref <= DI;
R_REGS.dchange <= datazero;
R_REGS.dout <= DI;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, CE_INT, DI)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
begin
 
r := R_REGS;
n := R_REGS;
 
for i in DI'range loop
if DI(i) /= r.dref(i) then
n.dchange(i) := '1';
end if;
end loop;
 
if CE_INT = '1' then
if unsigned(r.cecnt) = 0 then
n.cecnt := conv_std_logic_vector(CEDIV-1,CWIDTH);
n.dref := DI;
n.dchange := datazero;
for i in DI'range loop
if r.dchange(i) = '0' then
n.dout(i) := r.dref(i);
end if;
end loop;
 
else
n.cecnt := unsigned(r.cecnt) - 1;
end if;
end if;
N_REGS <= n;
 
DO <= r.dout;
 
end process proc_next;
 
 
end syn;
 
/Makefile
0,0 → 1,23
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2007-12-09 100 1.1.1 drop ISE_p definition
# 2007-06-03 47 1.1 use Makefile.xflow
# 2007-06-03 45 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
.phony : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/vlib/Makefile.xflow
#
include $(VBOM_all:.vbom=.dep_xst)
#
/.
. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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