OpenCores

tb Property changes : Added: svn:ignore ## -0,0 +1,47 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_serport_autobaud +tb_serport_autobaud_stim +tb_serport_autobaud_[sft]sim +tb_serport_autobaud_ISim +tb_serport_autobaud_ISim_[sft]sim +tb_serport_uart_rx +tb_serport_uart_rx_stim +tb_serport_uart_rx_[sft]sim +tb_serport_uart_rx_ISim +tb_serport_uart_rx_ISim_[sft]sim +tb_serport_uart_rxtx +tb_serport_uart_rxtx_stim +tb_serport_uart_rxtx_[sft]sim +tb_serport_uart_rxtx_ISim +tb_serport_uart_rxtx_ISim_[sft]sim Index: serport_uart_autobaud.vbom =================================================================== --- serport_uart_autobaud.vbom (nonexistent) +++ serport_uart_autobaud.vbom (revision 7) @@ -0,0 +1,4 @@ +# libs +../slvtypes.vhd +# design +serport_uart_autobaud.vhd Index: serport_uart_rxtx.vbom =================================================================== --- serport_uart_rxtx.vbom (nonexistent) +++ serport_uart_rxtx.vbom (revision 7) @@ -0,0 +1,8 @@ +# libs +../slvtypes.vhd +serport.vhd +# components +serport_uart_rx.vbom +serport_uart_tx.vbom +# design +serport_uart_rxtx.vhd Index: serport_uart_rxtx_ab.vhd =================================================================== --- serport_uart_rxtx_ab.vhd (nonexistent) +++ serport_uart_rxtx_ab.vhd (revision 7) @@ -0,0 +1,100 @@ +-- $Id: serport_uart_rxtx_ab.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_rxtx_ab - syn +-- Description: serial port UART - transmitter-receiver + autobauder +-- +-- Dependencies: serport_uart_autobaud +-- serport_uart_rxtx +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2007-06-24 60 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.serport.all; + +entity serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT: natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit; -- receiver active + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit busy + ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid + ABDONE : out slbit -- autobaud resync done + ); +end serport_uart_rxtx_ab; + +architecture syn of serport_uart_rxtx_ab is + + signal CLKDIV : slv(CDWIDTH-1 downto 0) := conv_std_logic_vector(0, CDWIDTH); + signal ABACT_L : slbit := '0'; -- local readable copy of ABACT + signal UART_RESET : slbit := '0'; + +begin + + AB : serport_uart_autobaud + generic map ( + CDWIDTH => CDWIDTH, + CDINIT => CDINIT) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + RXSD => RXSD, + CLKDIV => CLKDIV, + ACT => ABACT_L, + DONE => ABDONE + ); + + UART_RESET <= ABACT_L or RESET; + ABACT <= ABACT_L; + + RXTX : serport_uart_rxtx + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => UART_RESET, + CLKDIV => CLKDIV, + RXSD => RXSD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => TXSD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + +end syn; Index: serport_uart_rx.vhd =================================================================== --- serport_uart_rx.vhd (nonexistent) +++ serport_uart_rx.vhd (revision 7) @@ -0,0 +1,312 @@ +-- $Id: serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007-2009 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +-- The uart expects CLKDIV+1 wide input bit symbols. +-- This implementation counts the number of 1's in the first CLKDIV clock +-- cycles, and checks in the last cycle of the symbol time whether the +-- number of 1's was > CLKDIV/2. This supresses short glitches nicely, +-- especially for larger clock dividers. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_rx - syn +-- Description: serial port UART - receiver +-- +-- Dependencies: - +-- Test bench: tb/tb_serport_uart_rxtx +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2009-07-12 233 2.0.2 remove snoopers +-- 2008-03-02 121 2.0.1 comment out snoopers +-- 2007-10-21 91 2.0 re-designed and -implemented with state machine. +-- allow CLKDIV=0 with 1 stop bit; allow max. CLKDIV +-- (all 1's); aborts bad start bit after 1/2 cell; +-- accepts stop bit after 1/2 cell, permits tx clock +-- be ~3 percent faster than rx clock. +-- for 3s1000ft256: 50 -> 58 slices for CDWIDTH=13 +-- 2007-10-14 89 1.1 almost full rewrite, handles now CLKDIV=0 properly +-- for 3s1000ft256: 43 -> 50 slices for CDWIDTH=13 +-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-06-30 62 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +-- synthesis translate_off +use ieee.std_logic_textio.all; +use std.textio.all; +-- synthesis translate_on + +use work.slvtypes.all; + +entity serport_uart_rx is -- serial port uart: receive part + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit -- receiver active + ); +end serport_uart_rx; + + +architecture syn of serport_uart_rx is + + type state_type is ( + s_idle, -- s_idle: idle + s_colb0, -- s_colb0: collect b0 (start bit) + s_endb0, -- s_endb0: finish b0 (start bit) + s_colbx, -- s_colbx: collect bx + s_endbx, -- s_endbx: finish bx + s_colb9, -- s_colb9: collect bx (stop bit) + s_endb9 -- s_endb9: finish bx (stop bit) + ); + + type regs_type is record + state : state_type; -- state + ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter + dcnt : slv(CDWIDTH downto 0); -- data '1' counter + bcnt : slv4; -- bit counter + sreg : slv8; -- input shift register + end record regs_type; + + constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0'); + constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0'); + constant regs_init : regs_type := ( + s_idle, + ccntzero, + dcntzero, + (others=>'0'), + (others=>'0') + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + R_REGS <= N_REGS; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RESET, CLKDIV, RXSD) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable dbit : slbit := '0'; + variable ld_ccnt : slbit := '0'; + variable tc_ccnt : slbit := '0'; + variable tc_bcnt : slbit := '0'; + variable ld_dcnt : slbit := '0'; + variable ld_bcnt : slbit := '0'; + variable ce_bcnt : slbit := '0'; + variable iact : slbit := '0'; + variable ival : slbit := '0'; + variable ierr : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + dbit := '0'; + ld_ccnt := '0'; + tc_ccnt := '0'; + tc_bcnt := '0'; + ld_dcnt := '0'; + ld_bcnt := '0'; + ce_bcnt := '0'; + iact := '1'; + ival := '0'; + ierr := '0'; + + if unsigned(r.ccnt) = 0 then + tc_ccnt := '1'; + end if; + if unsigned(r.bcnt) = 9 then + tc_bcnt := '1'; + end if; + + if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then + dbit := '1'; + end if; + + case r.state is + + when s_idle => -- s_idle: idle ---------------------- + iact := '0'; + ld_dcnt := '1'; -- always keep dcnt in reset + if RXSD = '0' then -- if start bit seen + if tc_ccnt = '1' then + n.state := s_endb0; -- finish b0 + ld_ccnt := '1'; -- start next bit + ce_bcnt := '1'; + else + n.state := s_colb0; -- collect b0 + end if; + else -- otherwise + ld_ccnt := '1'; -- keep all counters in reset + ld_bcnt := '1'; + end if; + + when s_colb0 => -- s_colb0: collect b0 (start bit) --- + if tc_ccnt = '1' then -- last cycle of b0 ? + n.state := s_endb0; -- finish b0 + ld_ccnt := '1'; -- " + ce_bcnt := '1'; + else -- continue in b0 ? + if dbit='1' and RXSD='1' then -- too many 1's ? + n.state := s_idle; -- abort to idle + ld_dcnt := '1'; -- put counters in reset + ld_ccnt := '1'; + ld_bcnt := '1'; + end if; + end if; + + when s_endb0 => -- s_endb0: finish b0 (start bit) --- + ld_dcnt := '1'; -- start next bit + if dbit = '1' then -- was it a 1 ? + n.state := s_idle; -- abort to idle + ld_ccnt := '1'; -- put counters in reset + ld_bcnt := '1'; + else + if tc_ccnt = '1' then -- last cycle of bx ? + n.state := s_endbx; -- finish bx + ld_ccnt := '1'; + ce_bcnt := '1'; + else -- continue in b0 ? + n.state := s_colbx; -- collect bx + end if; + end if; + + when s_colbx => -- s_colbx: collect bx --------------- + if tc_ccnt = '1' then -- last cycle of bx ? + n.state := s_endbx; -- finish bx + ld_ccnt := '1'; + ce_bcnt := '1'; + end if; + + when s_endbx => -- s_endbx: finish bx --------------- + ld_dcnt := '1'; -- start next bit + n.sreg := dbit & r.sreg(7 downto 1); + if tc_ccnt = '1' then -- last cycle of bx ? + if tc_bcnt = '1' then + n.state := s_endb9; -- finish b9 + ld_bcnt := '1'; -- and wrap bcnt + else + n.state := s_endbx; -- finish bx + ce_bcnt := '1'; + end if; + ld_ccnt := '1'; + else -- continue in bx ? + if tc_bcnt = '1' then + n.state := s_colb9; -- collect b9 + else + n.state := s_colbx; -- collect bx + end if; + end if; + + when s_colb9 => -- s_colb9: collect bx (stop bit) ---- + if tc_ccnt = '1' then -- last cycle of b9 ? + n.state := s_endb9; -- finish b9 + ld_ccnt := '1'; -- " + ld_bcnt := '1'; -- and wrap bcnt + else -- continue in b9 ? + if dbit='1' and RXSD='1' then -- already enough 1's ? + n.state := s_idle; -- finish to idle + ld_dcnt := '1'; -- put counters in reset + ld_ccnt := '1'; + ld_bcnt := '1'; + ival := '1'; + end if; + end if; + + when s_endb9 => -- s_endb9: finish bx (stop bit) ---- + ld_dcnt := '1'; -- start next bit + if dbit = '1' then -- was it a valid stop bit ? + ival := '1'; + else + ierr := '1'; + end if; + if RXSD = '1' then -- line in idle state ? + n.state := s_idle; -- finish to idle state + ld_ccnt := '1'; -- and put counters in reset + ld_bcnt := '1'; -- " + else + if tc_ccnt = '1' then -- last cycle of b9 ? + n.state := s_endb0; -- finish b0 + ld_ccnt := '1'; -- " + ce_bcnt := '1'; + else -- continue in b0 ? + n.state := s_colb0; -- collect bx + end if; + end if; + + when others => null; -- ----------------------------------- + + end case; + + if RESET = '1' then -- RESET seen + ld_ccnt := '1'; -- keep all counters in reset + ld_dcnt := '1'; + ld_bcnt := '1'; + n.state := s_idle; + end if; + + if ld_ccnt = '1' then -- implement ccnt + n.ccnt := CLKDIV; + else + n.ccnt := unsigned(r.ccnt) - 1; + end if; + + if ld_dcnt = '1' then -- implement dcnt + n.dcnt(CDWIDTH downto 1) := (others=>'0'); + n.dcnt(0) := RXSD; + else + if RXSD = '1' then + n.dcnt := unsigned(r.dcnt) + 1; + end if; + end if; + + if ld_bcnt = '1' then -- implement bcnt + n.bcnt := (others=>'0'); + else + if ce_bcnt = '1' then + n.bcnt := unsigned(r.bcnt) + 1; + end if; + end if; + + N_REGS <= n; + + RXDATA <= r.sreg; + RXACT <= iact; + RXVAL <= ival; + RXERR <= ierr; + + end process proc_next; + +end syn; Index: serport_uart_rxtx_ab.vbom =================================================================== --- serport_uart_rxtx_ab.vbom (nonexistent) +++ serport_uart_rxtx_ab.vbom (revision 7) @@ -0,0 +1,8 @@ +# libs +../slvtypes.vhd +serport.vhd +# components +serport_uart_autobaud.vbom +serport_uart_rxtx.vbom +# design +serport_uart_rxtx_ab.vhd Index: serport_uart_rx.vbom =================================================================== --- serport_uart_rx.vbom (nonexistent) +++ serport_uart_rx.vbom (revision 7) @@ -0,0 +1,4 @@ +# libs +../slvtypes.vhd +# design +serport_uart_rx.vhd Index: serport_uart_tx.vhd =================================================================== --- serport_uart_tx.vhd (nonexistent) +++ serport_uart_tx.vhd (revision 7) @@ -0,0 +1,132 @@ +-- $Id: serport_uart_tx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_tx - syn +-- Description: serial port UART - transmitter +-- +-- Dependencies: - +-- Test bench: tb/tb_serport_uart_rxtx +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2007-10-21 91 1.0.3 use 1 stop bits (redesigned _rx allows this) +-- 2007-10-19 90 1.0.2 use 2 stop bits (allow CLKDIV=0 operation in sim) +-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-06-30 62 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; + +entity serport_uart_tx is -- serial port uart: transmit part + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit -- transmit busy + ); +end serport_uart_tx; + + +architecture syn of serport_uart_tx is + + type regs_type is record + ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter + bcnt : slv4; -- bit counter + sreg : slv9; -- output shift register + busy : slbit; + end record regs_type; + + constant cntzero : slv(CDWIDTH-1 downto 0) := (others=>'0'); + constant regs_init : regs_type := ( + cntzero, + (others=>'0'), + (others=>'1'), -- sreg to all 1 !! + '0' + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + R_REGS <= N_REGS; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RESET, CLKDIV, TXDATA, TXENA) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ld_ccnt : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + ld_ccnt := '0'; + + if r.busy = '0' then + ld_ccnt := '1'; + n.bcnt := (others=>'0'); + if TXENA = '1' then + n.sreg := TXDATA & '0'; -- add start (0) bit + n.busy := '1'; + end if; + + else + + if unsigned(r.ccnt) = 0 then + ld_ccnt := '1'; + n.sreg := '1' & r.sreg(8 downto 1); + n.bcnt := unsigned(r.bcnt) + 1; + if unsigned(r.bcnt) = 9 then -- if 10 bits send + n.busy := '0'; -- declare all done + end if; + end if; + end if; + + if RESET = '1' then + ld_ccnt := '1'; + n.busy := '0'; + end if; + + if ld_ccnt = '1' then + n.ccnt := CLKDIV; + else + n.ccnt := unsigned(r.ccnt) - 1; + end if; + + N_REGS <= n; + + TXBUSY <= r.busy; + TXSD <= r.sreg(0); + + end process proc_next; + +end syn; Index: serport_uart_tx.vbom =================================================================== --- serport_uart_tx.vbom (nonexistent) +++ serport_uart_tx.vbom (revision 7) @@ -0,0 +1,4 @@ +# libs +../slvtypes.vhd +# design +serport_uart_tx.vhd Index: serport_uart_autobaud.vhd =================================================================== --- serport_uart_autobaud.vhd (nonexistent) +++ serport_uart_autobaud.vhd (revision 7) @@ -0,0 +1,173 @@ +-- $Id: serport_uart_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_autobaud - syn +-- Description: serial port UART - autobauder +-- +-- Dependencies: - +-- Test bench: tb/tb_serport_autobaud +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding +-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0 +-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned +-- 2007-06-30 62 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; + +entity serport_uart_autobaud is -- serial port uart: autobauder + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT: natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (uart view) + CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting + ACT : out slbit; -- active; if 1 clkdiv is invalid + DONE : out slbit -- resync done + ); +end serport_uart_autobaud; + + +architecture syn of serport_uart_autobaud is + + type state_type is ( + s_idle, + s_break, + s_wait, + s_sync + ); + + type regs_type is record + ccnt : slv(CDWIDTH-1+3 downto 0); -- clock divider counter + mcnt : slv7; -- msec counter + seen1 : slbit; -- seen a '1' in this msec + state : state_type; -- state + end record regs_type; + + -- Note on initialization of ccnt: + -- - in the current logic ccnt is incremented n-1 times when n is number + -- clock cycles with a RXD of '0'. When running at 50 MBaud, ccnt will + -- be incremented 7 (not 8!) times. + -- - the three LSBs of ccnt should be at 100 under perfect conditions, this + -- gives the best rounded estimate of CLKDIV. + -- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100 + -- --> ccntinit = -3 + + constant ccntinit : slv(CDWIDTH-1+3 downto 0) := + conv_std_logic_vector(2**(CDWIDTH+3)-3, CDWIDTH+3); + constant mcntzero : slv7 := (others=>'0'); + constant mcntlast : slv7 := (others=>'1'); + constant regs_init : regs_type := ( + conv_std_logic_vector(CDINIT,CDWIDTH)&"000", + (others=>'0'), + '0', + s_idle + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + assert CDINIT <= 2**CDWIDTH-1 + report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH" + severity FAILURE; + + proc_regs: process (CLK) + begin + + if CLK'event and CLK='1' then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, RESET, RXSD) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable iact : slbit := '0'; + variable idone : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + iact := '1'; + idone := '0'; + + case r.state is + when s_idle => -- s_idle: idle, detect break -------- + iact := '0'; + if CE_MSEC = '1' then -- if end of msec + if r.seen1 = '0' then -- if no '1' seen on RXD + n.mcnt := unsigned(r.mcnt) + 1; -- up break timer counter + if r.mcnt = mcntlast then -- after 127 msec + n.state := s_break; -- break detected ! + end if; + else -- otherwise if '1' seen + n.mcnt := mcntzero; -- clear break timer again + end if; + n.seen1 := RXSD; -- latch current RXD value + else -- otherwise if not at end-of-msec + n.seen1 := r.seen1 or RXSD; -- remember whether RXS=1 seen + end if; + + when s_break => -- s_break: detect end of break ------ + if RXSD = '1' then -- if end of break seen + n.state := s_wait; -- to s_wait to wait for sync char + n.ccnt := ccntinit; -- and initialize ccnt + end if; -- otherwise stay in s_break + + when s_wait => -- s_wait: wait for sync char -------- + if RXSD = '0' then -- if start bit if sync char seen + n.state := s_sync; -- to s_sync to wait for end of '0' + end if; -- otherwise stay in s_wait + + when s_sync => -- s_sync: wait for end of '0' bits -- + if RXSD = '1' then -- if end of '0' bits seen + n.state := s_idle; -- to s_idle, autobauding done + idone := '1'; -- emit done pulse + else -- otherwise still in '0' of sync + n.ccnt := unsigned(n.ccnt) + 1; -- increment ccnt + end if; + + when others => null; -- ----------------------------------- + end case; + + N_REGS <= n; + + CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3); + ACT <= iact or RESET; + DONE <= idone; + + end process proc_next; + +end syn; Index: Makefile =================================================================== --- Makefile (nonexistent) +++ Makefile (revision 7) @@ -0,0 +1,22 @@ +# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2007-12-09 100 1.0.1 drop ISE_p definition +# 2007-07-03 45 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +.phony : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/vlib/Makefile.xflow +# +include $(VBOM_all:.vbom=.dep_xst) +# Index: serport.vhd =================================================================== --- serport.vhd (nonexistent) +++ serport.vhd (revision 7) @@ -0,0 +1,134 @@ +-- $Id: serport.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: serport +-- Description: serial port interface components +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2010-04-10 276 1.2 add clock divider constant defs +-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned +-- 2007-06-03 45 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package serport is + +-- clock divider constants assume 50 MHz clock + + constant serport_clkdiv_009600 : integer := 5208-1; -- 50000000/ 9600=5208.33 + constant serport_clkdiv_019200 : integer := 2604-1; -- 50000000/ 19200=2604.16 + constant serport_clkdiv_038400 : integer := 1302-1; -- 50000000/ 38400=1302.08 + constant serport_clkdiv_057600 : integer := 868-1; -- 50000000/ 57600= 868.05 + constant serport_clkdiv_115200 : integer := 434-1; -- 50000000/115200= 434.02 + constant serport_clkdiv_230400 : integer := 217-1; -- 50000000/230400= 217.01 + constant serport_clkdiv_460800 : integer := 109-1; -- 50000000/460800= 108.51 + constant serport_clkdiv_500000 : integer := 100-1; -- 50000000/500000= 100 + constant serport_clkdiv_576000 : integer := 87-1; -- 50000000/576000= 86.80 + constant serport_clkdiv_921600 : integer := 54-1; -- 50000000/921600= 54.25 + constant serport_clkdiv_1M : integer := 50-1; -- 50000000/1M = 50 + constant serport_clkdiv_2M : integer := 24-1; -- 50000000/2M = 25 + +component serport_uart_rxtx is -- serial port uart: rx+tx combo + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit; -- receiver active + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit -- transmit busy + ); +end component; + +component serport_uart_rx is -- serial port uart: receive part + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit -- receiver active + ); +end component; + +component serport_uart_tx is -- serial port uart: transmit part + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit -- transmit busy + ); +end component; + +component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT: natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit; -- receiver active + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit busy + ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid + ABDONE : out slbit -- autobaud resync done + ); +end component; + +component serport_uart_autobaud is -- serial port uart: autobauder + generic ( + CDWIDTH : positive := 13; -- clk divider width + CDINIT: natural := 15); -- clk divider initial/reset setting + port ( + CLK : in slbit; -- clock + CE_MSEC : in slbit; -- 1 msec clock enable + RESET : in slbit; -- reset + RXSD : in slbit; -- receive serial data (uart view) + CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting + ACT : out slbit; -- active; if 1 clkdiv is invalid + DONE : out slbit -- resync done + ); +end component; + +end serport; Index: serport_uart_rxtx.vhd =================================================================== --- serport_uart_rxtx.vhd (nonexistent) +++ serport_uart_rxtx.vhd (revision 7) @@ -0,0 +1,85 @@ +-- $Id: serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: serport_uart_rxtx - syn +-- Description: serial port UART - transmitter + receiver +-- +-- Dependencies: serport_uart_rx +-- serport_uart_tx +-- Test bench: tb/tb_serport_uart_rxtx +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2007-06-24 60 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; + +use work.slvtypes.all; +use work.serport.all; + +entity serport_uart_rxtx is -- serial port uart: rx+tx combo + generic ( + CDWIDTH : positive := 13); -- clk divider width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting + RXSD : in slbit; -- receive serial data (uart view) + RXDATA : out slv8; -- receiver data out + RXVAL : out slbit; -- receiver data valid + RXERR : out slbit; -- receiver data error (frame error) + RXACT : out slbit; -- receiver active + TXSD : out slbit; -- transmit serial data (uart view) + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit -- transmit busy + ); +end serport_uart_rxtx; + +architecture syn of serport_uart_rxtx is + +begin + + RX : serport_uart_rx + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + RXSD => RXSD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT + ); + + TX : serport_uart_tx + generic map ( + CDWIDTH => CDWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CLKDIV => CLKDIV, + TXSD => TXSD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + +end syn; Index: . =================================================================== --- . (nonexistent) +++ . (revision 7)

. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

Browse

Tools

Subversion Repositories w11

Compare Revisions

Rev 3 → Rev 7