URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
Compare Revisions
- This comparison shows the changes necessary to convert path
/w11/tags/w11a_V0.5/rtl/vlib
- from Rev 5 to Rev 7
- ↔ Reverse comparison
Rev 5 → Rev 7
/Makefile.xflow
0,0 → 1,244
# $Id: Makefile.xflow 317 2010-07-22 19:36:56Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2010-05-06 289 1.5.7 add xilinx_tsim_xon support |
# 2010-04-24 282 1.5.6 add %.impact rule to run impact_wrapper |
# 2010-04-17 278 1.4.5 add '|| true' after grep in diag summary to prevent |
# a make abort in case no diags are seen |
# 2010-04-02 273 1.4.4 add -I{RETROBASE} to ucf_cpp processing rules |
# 2010-03-14 268 1.4.3 add XFLOWOPT_SYN and XFLOWOPT_IMP |
# 2009-11-21 252 1.4.2 use bitgen directly, use ISE_USERID |
# 2007-12-17 102 1.4.1 fix %.dep_ucf_cpp : %.ucf_cpp rule |
# 2007-12-16 101 1.4 add ucf_cpp rules |
# 2007-12-09 100 1.3.7 ifndef define ISE_PATH to xc3s1000-ft256-4 |
# 2007-11-02 94 1.3.6 use .SECONDARY to keep intermediate files |
# 2007-10-28 93 1.3.5 call xst_count_bels -xsts when _ssim is generated |
# 2007-10-12 88 1.3.4 support <design>.xcf files, if provided |
# 2007-10-06 87 1.3.3 remove *_twr.log in clean |
# 2007-07-20 67 1.3.2 handle local/global xst_vhdl.opt |
# 2007-07-15 66 1.3.1 add rule "%.ngc: ../%.vbom" to support _*sim in ./tb |
# add XST diagnostics summary at end of listing |
# 2007-07-06 64 1.3 all vbom based now |
# 2007-06-16 57 1.2.1 cleanup ghdl_clean handling (rm _[sft]sim) |
# 2007-06-10 52 1.2 reorganized svn directory structure |
# 2007-06-10 51 1.1 consolidate test bench generation |
# 2007-06-03 45 1.0 Initial version |
#--- |
# |
# setup default board (for impact), device and userid (for bitgen) |
# |
ifndef ISE_BOARD |
ISE_BOARD = s3board |
endif |
# |
ifndef ISE_PATH |
ISE_PATH = xc3s1000-ft256-4 |
endif |
# |
ifndef ISE_USERID |
ISE_USERID = 0xffffffff |
endif |
# |
# setup defaults for xflow option files for synthesis and implementation |
# |
ifndef XFLOWOPT_SYN |
XFLOWOPT_SYN = xst_vhdl.opt |
endif |
# |
ifndef XFLOWOPT_IMP |
XFLOWOPT_IMP = balanced.opt |
endif |
# |
XFLOW = xflow -p ${ISE_PATH} |
# |
# $@ first target |
# $< first dependency |
# $* stem in rule match |
# |
# when chaining, don't delete 'expensive' intermediate files: |
.SECONDARY : |
# |
# Synthesize (xst) |
# input: %.vbom vbom project description |
# output: %.ngc |
# %_xst.log xst log file |
# |
%.ngc: %.vbom |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
(cd ./ise; vbomconv --xst_prj ../$< > $*.prj) |
(cd ./ise; touch $*.xcf) |
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi |
if [ -r ${RETROBASE}/vlib/${XFLOWOPT_SYN} ]; then \ |
cp ${RETROBASE}/vlib/${XFLOWOPT_SYN} ./ise; fi |
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi |
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj |
(cd ./ise; chmod -x *.* ) |
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi |
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi |
@ echo "===============================================================" |
@ echo "* Makefile.xflow: XST Diagnostic Summary *" |
@ echo "===============================================================" |
@ grep -i -A 1 ":.*:" $*_xst.log || true |
@ echo "===============================================================" |
# |
# the following rule needed to generate an %_*sim.vhd in a ./tb sub-directory |
# it will look for a matching vbom in the parent directory |
%.ngc: ../%.vbom |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
(cd ./ise; vbomconv --xst_prj ../$< > $*.prj) |
(cd ./ise; touch $*.xcf) |
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi |
if [ -r ${RETROBASE}/vlib/${XFLOWOPT_SYN} ]; then \ |
cp ${RETROBASE}/vlib/${XFLOWOPT_SYN} ./ise; fi |
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi |
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj |
(cd ./ise; chmod -x *.* ) |
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi |
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi |
@ echo "===============================================================" |
@ echo "* Makefile.xflow: XST Diagnostic Summary *" |
@ echo "===============================================================" |
@ grep -i -A 1 ":.*:" $*_xst.log || true |
@ echo "===============================================================" |
# |
# Implement (map+par) |
# input: %.ngc |
# %.ucf constraint file (if available) |
# output: %.ncd |
# %.pcf |
# %_tra.log translate (ngdbuild) log file (renamed %.bld) |
# %_map.log map log file (renamed %_map.mrp) |
# %_par.log par log file (renamed %.par) |
# %_pad.log pad file (renamed %_pad.txt) |
# %_twr.log trce log file (renamed %.twr) |
# |
%.ncd %.pcf: %.ngc |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi |
if [ -r $*.ucf ]; then cp -p $*.ucf ./ise; fi |
if [ -r ${RETROBASE}/vlib/${XFLOWOPT_IMP} ]; then \ |
cp ${RETROBASE}/vlib/${XFLOWOPT_IMP} ./ise; fi |
if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi |
${XFLOW} -wd ise -implement ${XFLOWOPT_IMP} $< |
(cd ./ise; chmod -x *.* ) |
if [ -r ./ise/$*.ncd ]; then cp -p ./ise/$*.ncd .; fi |
if [ -r ./ise/$*.pcf ]; then cp -p ./ise/$*.pcf .; fi |
if [ -r ./ise/$*.bld ]; then cp -p ./ise/$*.bld ./$*_tra.log; fi |
if [ -r ./ise/$*_map.mrp ]; then cp -p ./ise/$*_map.mrp ./$*_map.log; fi |
if [ -r ./ise/$*.par ]; then cp -p ./ise/$*.par ./$*_par.log; fi |
if [ -r ./ise/$*_pad.txt ]; then cp -p ./ise/$*_pad.txt ./$*_pad.log; fi |
if [ -r ./ise/$*.twr ]; then cp -p ./ise/$*.twr ./$*_twr.log; fi |
# |
# Configure (bitgen) |
# input: %.ncd |
# output: %.bit |
# %.msk |
# %_bgn.log bitgen log file (renamed %.bgn) |
# |
%.bit: %.ncd |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
if [ -r $*.ncd ]; then cp -p $*.ncd ./ise; fi |
(cd ./ise; bitgen -l -w -m -g ReadBack -g UserId:${ISE_USERID} -intstyle xflow $*.ncd) |
(cd ./ise; chmod -x *.* ) |
if [ -r ./ise/$*.bit ]; then cp -p ./ise/$*.bit .; fi |
if [ -r ./ise/$*.msk ]; then cp -p ./ise/$*.msk .; fi |
if [ -r ./ise/$*.bgn ]; then cp -p ./ise/$*.bgn ./$*_bgn.log; fi |
# |
# Program FPGA with impact |
# input: %.bit |
# output: .phony |
# |
%.impact: %.bit |
impact_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} $*.bit |
|
# |
# Post-XST simulation model (netgen -sim; UNISIM based) |
# input: %.ngc |
# output: %_ssim.vhd |
# %_ngn_ssim.log netgen log file (renamed %.nlf) |
# |
%_ssim.vhd: %.ngc |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi |
(cd ise; netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngc) |
(cd ./ise; chmod -x *.* ) |
if [ -r ./ise/$*.vhd ]; then cp -p ./ise/$*.vhd ./$*_ssim.vhd; fi |
if [ -r ./ise/$*.nlf ]; then cp -p ./ise/$*.nlf ./$*_ngn_ssim.log; fi |
if [ -r $*_ssim.vhd ]; then xst_count_bels -xsts $*_ssim.vhd; fi |
# |
# Post-XST simulation model (netgen -sim; SIMPRIM based) |
# input: %.ngc |
# output: %_fsim.vhd |
# %_ngn_fsim.log netgen log file (renamed %.nlf) |
# |
%_fsim.vhd: %.ngc |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi |
(cd ise; ngdbuild -p ${ISE_PATH} -nt timestamp -intstyle xflow \ |
$*.ngc $*.ngd) |
(cd ise; netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngd) |
(cd ./ise; chmod -x *.* ) |
if [ -r ./ise/$*.vhd ]; then cp -p ./ise/$*.vhd ./$*_fsim.vhd; fi |
if [ -r ./ise/$*.nlf ]; then cp -p ./ise/$*.nlf ./$*_ngn_fsim.log; fi |
# |
# Post-par timing simulation model (netgen -sim) |
# input: %.ncd |
# output: %_tsim.vhd |
# %_ngn_tsim.log netgen log file (renamed time_sim.nlf) |
# |
#!! use netgen directly because xflow 8.1 goes mad when -tsim used a 2nd time |
#!! see blog_xilinx_webpack.txt 2007-06-10 |
# |
%_tsim.vhd %_tsim.sdf: %.ncd |
if [ ! -d ./ise ]; then mkdir ./ise; fi |
if [ -r $*.ncd ]; then cp -p $*.ncd ./ise; fi |
if [ -r $*.pcf ]; then cp -p $*.pcf ./ise; fi |
(cd ise; netgen -ofmt vhdl -sim -w -intstyle xflow -pcf \ |
$*.pcf $*.ncd $*_tsim.vhd ) |
(cd ./ise; chmod -x *.* ) |
if [ -r ./ise/$*_tsim.vhd ]; then cp -p ./ise/$*_tsim.vhd .; fi |
if [ -r ./ise/$*_tsim.sdf ]; then cp -p ./ise/$*_tsim.sdf .; fi |
if [ -r ./ise/$*_tsim.nlf ]; then cp -p ./ise/$*_tsim.nlf ./$*_ngn_tsim.log; fi |
if [ -r $*_tsim.vhd -a -r $*.tsim_xon_dat ]; then xilinx_tsim_xon $*; fi |
# |
# generate dep_xst files from vbom |
# |
%.dep_xst: %.vbom |
vbomconv --dep_xst $< > $@ |
# |
# generate cpp'ed ucf files from ucf_cpp |
# |
%.ucf : %.ucf_cpp |
cpp -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf |
# |
# generate nested dependency rules for cpp'ed ucf files from ucf_cpp |
# |
%.dep_ucf_cpp : %.ucf_cpp |
cpp -I${RETROBASE}/rtl -MM $*.ucf_cpp |\ |
sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp |
# |
.phony : ise_clean ise_tmp_clean |
# |
ise_clean: ise_tmp_clean |
rm -rf *.ngc |
rm -rf *.ncd |
rm -rf *.pcf |
rm -rf *.bit |
rm -rf *.msk |
rm -rf *_[sft]sim.vhd |
rm -rf *_tsim.sdf |
rm -rf *_xst.log |
rm -rf *_tra.log |
rm -rf *_map.log |
rm -rf *_par.log |
rm -rf *_pad.log |
rm -rf *_twr.log |
rm -rf *_bgn.log |
rm -rf *_ngn_[sft]sim.log |
rm -rf *_svn.log |
rm -rf *_sum.log |
# |
ise_tmp_clean: |
rm -rf ./ise |
# |
/rri/tb/tb_rri_serport.vhd
0,0 → 1,44
-- $Id: tb_rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tb_rri_serport |
-- Description: Configuration for tb_rri_serport for tb_rri. |
-- |
-- Dependencies: tbd_rri_gen |
-- |
-- To test: rri_serport |
-- rri_core |
-- |
-- Target Devices: generic |
-- |
-- Verified (with tb_rri_stim.dat): |
-- Date Rev Code ghdl ise Target Comment |
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (Test 15 fails) |
-- 2007-10-12 88 - 0.26 - - c:ok (Test 15 fails) |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2007-11-25 98 1.0.1 use entity rather arch name to switch core/serport |
-- 2007-07-08 65 1.0 Initial version |
------------------------------------------------------------------------------ |
|
configuration tb_rri_serport of tb_rri is |
|
for sim |
for all : tbd_rri_gen |
use entity work.tbd_rri_serport; |
end for; |
end for; |
|
end tb_rri_serport; |
/rri/tb/rritb_cpmon.vbom
0,0 → 1,7
# libs |
../../slvtypes.vhd |
../../simlib/simlib.vhd |
../rrilib.vhd |
# components |
# design |
rritb_cpmon.vhd |
/rri/tb/cext_rriext.c
0,0 → 1,215
/* $Id: cext_rriext.c 314 2010-07-09 17:38:41Z mueller $ |
* |
* Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
* |
* This program is free software; you may redistribute and/or modify it under |
* the terms of the GNU General Public License as published by the Free |
* Software Foundation, either version 2, or at your option any later version. |
* |
* This program is distributed in the hope that it will be useful, but |
* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
* for complete details. |
* |
* Revision History: |
* Date Rev Vers Comment |
* 2007-11-18 96 1.2 add 'read before write' logic to avoid deadlocks |
* under cygwin broken fifo (size=1 !) implementation |
* 2007-10-19 90 1.1 add trace option, controlled by setting an |
* the environment variable CEXT_RRIEXT_TRACE=1 |
* 2007-09-23 84 1.0 Initial version |
*/ |
|
#include <unistd.h> |
#include <errno.h> |
#include <sys/types.h> |
#include <sys/stat.h> |
#include <fcntl.h> |
#include <stdio.h> |
#include <sched.h> |
#include <stdlib.h> |
#include <string.h> |
|
#define CPREF 0x80 |
#define CESC (CPREF|0x0f) |
#define QRBUFSIZE 1024 |
|
static int fd_rx = -1; |
static int fd_tx = -1; |
|
static int io_trace = 0; |
|
static char qr_buf[QRBUFSIZE]; |
static int qr_pr = 0; |
static int qr_pw = 0; |
static int qr_nb = 0; |
static int qr_eof = 0; |
static int qr_err = EAGAIN; |
|
/* returns: |
* <0 if error |
* >=0 <=0xff normal data |
* == 0x100 idle |
* 0x1aahhll if side band message seen |
* |
*/ |
|
/* returns |
0 if EGAIN or |
*/ |
|
static void cext_dotrace(const char *text, int dat) |
{ |
int i; |
int mask = 0x80; |
printf("cext_rriext-I: %s ", text); |
for (i=0; i<8; i++) { |
printf("%c", (dat&mask)?'1':'0' ); |
mask >>= 1; |
} |
printf("\n"); |
} |
|
static void cext_doread() |
{ |
char buf[1]; |
ssize_t nbyte; |
nbyte = read(fd_rx, buf, 1); |
if (nbyte < 0) { |
qr_err = errno; |
} else if (nbyte == 0) { |
qr_err = EAGAIN; |
qr_eof = 1; |
} else { |
qr_err = EAGAIN; |
if (qr_nb < QRBUFSIZE) { |
if (io_trace) cext_dotrace("rcv8", (unsigned char) buf[0]); |
qr_buf[qr_pw++] = buf[0]; |
if (qr_pw >= QRBUFSIZE) qr_pw = 0; |
qr_nb += 1; |
} else { |
printf("Buffer overflow\n"); /* FIXME: better error handling */ |
} |
} |
} |
|
int cext_getbyte(int clk) |
{ |
char buf[1]; |
ssize_t nbyte; |
int irc; |
int tdat; |
char* env_val; |
|
static int odat; |
static int nidle = 0; |
static int ncesc = 0; |
static int nside = -1; |
|
if (fd_rx < 0) { /* fifo's not yet opened */ |
fd_rx = open("tb_rriext_fifo_rx", O_RDONLY|O_NONBLOCK); |
if (fd_rx <= 0) { |
perror("cext_rriext-E: failed to open tb_rriext_fifo_rx"); |
return -2; |
} |
printf("cext_rriext-I: connected to tb_rriext_fifo_rx\n"); |
fd_tx = open("tb_rriext_fifo_tx", O_WRONLY); |
if (fd_tx <= 0) { |
perror("cext_rriext-E: failed to open tb_rriext_fifo_tx"); |
return -2; |
} |
printf("cext_rriext-I: connected to tb_rriext_fifo_tx\n"); |
nidle = 0; |
ncesc = 0; |
nside = -1; |
|
io_trace = 0; |
env_val = getenv("CEXT_RRIEXT_TRACE"); |
if (env_val && strcmp(env_val, "1") == 0) { |
io_trace = 1; |
} |
|
} |
|
cext_doread(); |
|
if (qr_nb == 0) { /* no character to be processed */ |
if (qr_eof != 0) { /* EOF seen */ |
if (ncesc >= 2) { /* two+ CESC seen ? */ |
printf("cext_rriext-I: seen EOF, wait for reconnect\n"); |
close(fd_rx); |
close(fd_tx); |
fd_rx = -1; |
fd_tx = -1; |
usleep(500000); /* wait 0.5 sec */ |
return 0x100; /* return idle, will reconnect */ |
} |
|
printf("cext_rriext-I: seen EOF, schedule clock stop and exit\n"); |
return -1; /* signal EOF seen */ |
} else if (qr_err == EAGAIN) { /* nothing read, return idle */ |
if (nidle < 8 || (nidle%1024)==0) { |
irc = sched_yield(); |
if (irc < 0) perror("cext_rriext-W: sched_yield failed"); |
} |
nidle += 1; |
return 0x100; |
} else { /* must be a read error */ |
errno = qr_err; |
perror("cext_rriext-E: read error on tb_rriext_fifo_rx"); |
return -3; |
} |
} |
|
nidle = 0; |
tdat = (unsigned char) qr_buf[qr_pr++]; |
if (qr_pr >= QRBUFSIZE) qr_pr = 0; |
qr_nb -= 1; |
|
if (tdat == CESC) { |
ncesc += 1; |
if (ncesc == 2) nside = 0; |
} else { |
ncesc = 0; |
} |
|
switch (nside) { |
case -1: /* normal data */ |
return tdat; |
case 0: /* 2nd CESC, return it */ |
nside += 1; |
return tdat; |
case 1: /* get ADDR byte */ |
nside += 1; |
odat = 0x1000000 | (tdat<<16); |
return 0x100; |
case 2: /* get DL byte */ |
nside += 1; |
odat |= tdat; |
return 0x100; |
case 3: /* get DH byte */ |
nside = -1; |
odat |= tdat<<8; |
return odat; |
} |
} |
|
int cext_putbyte(int dat) |
{ |
char buf[1]; |
ssize_t nbyte; |
|
cext_doread(); |
|
if (io_trace) cext_dotrace("snd8", dat); |
|
buf[0] = (unsigned char) dat; |
nbyte = write(fd_tx, buf, 1); |
|
if (nbyte < 0) { |
perror("cext_rriext-E: write error on tb_rriext_fifo_tx"); |
return -3; |
} |
|
return 0; |
} |
/rri/tb/rritb_cpmon_sb.vhd
0,0 → 1,77
-- $Id: rritb_cpmon_sb.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rritb_cpmon_sb - sim |
-- Description: rritb: rri comm port monitor; simbus wrapper |
-- |
-- Dependencies: simbus |
-- Test bench: - |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-05-02 287 1.0.1 use sbcntl_sbf_cpmon def |
-- 2007-08-25 75 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.simbus.all; |
use work.rritblib.all; |
|
entity rritb_cpmon_sb is -- simbus wrap rri comm port monitor |
generic ( |
DWIDTH : positive := 9; -- data port width (8 or 9) |
ENAPIN : integer := sbcntl_sbf_cpmon); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
CP_DI : in slv(DWIDTH-1 downto 0); -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : in slbit; -- comm port: data busy |
CP_DO : in slv(DWIDTH-1 downto 0); -- comm port: data out |
CP_VAL : in slbit; -- comm port: data valid |
CP_HOLD : in slbit -- comm port: data hold |
); |
end rritb_cpmon_sb; |
|
|
architecture sim of rritb_cpmon_sb is |
|
signal ENA : slbit := '0'; |
|
begin |
|
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high |
report "assert(ENAPIN in SB_CNTL'range)" severity failure; |
|
ENA <= to_x01(SB_CNTL(ENAPIN)); |
|
CPMON : rritb_cpmon |
generic map ( |
DWIDTH => DWIDTH) |
port map ( |
CLK => CLK, |
CLK_CYCLE => SB_CLKCYCLE, |
ENA => ENA, |
CP_DI => CP_DI, |
CP_ENA => CP_ENA, |
CP_BUSY => CP_BUSY, |
CP_DO => CP_DO, |
CP_VAL => CP_VAL, |
CP_HOLD => CP_HOLD |
); |
|
end sim; |
/rri/tb/tb_rri_stim.dat
0,0 → 1,648
# $Id: tb_rri_stim.dat 311 2010-06-30 17:52:37Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2010-06-06 302 2.0 use sop/eop framing instead of soc+chaining |
# 2007-11-24 98 1.2 adapt to new internal init handling |
# 2007-11-04 95 1.1 add .iowt's in Test 15 to get serport timing right |
# 2007-06-17 58 1.0 Initial version |
# |
.wait 5 |
C some non frame data first |
.tx8 00000000 |
.wait 5 |
.tx8 00000001 |
.wait 5 |
.tx8 00000010 |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 1: wreg |
C wreg: tx: sop - cmd(10000,010) addr(0000) dl dh ccrc - eop |
C rx: sop - cmd(010) stat crc - eop |
# |
.rxsop |
.rxcs 10000010 00000000 |
.rxeop |
# |
.txsop |
.txcad 10000010 00000000 0011001111001100 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 2: rreg |
C rreg: tx: sop - cmd(10010,000) addr(0000) ccrc - eop |
C rx: sop - cmd(000) dl dh stat crc - eop |
# |
.rxsop |
.rxcds 10010000 0011001111001100 00000000 |
.rxeop |
# |
.txsop |
.txca 10010000 00000000 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 3: chained wreg - wreg - rreg |
C wreg: tx: sop - cmd(11001,010) addr(0001) dl dh ccrc |
C wreg: tx: - cmd(11011,010) addr(0010) dl dh ccrc |
C rreg: tx: - cmd(11100,000) addr(0001) ccrc |
C tx: - eop |
C rx: sop - cmd(010) stat crc |
C rx: - cmd(010) stat crc |
C rx: - cmd(000) dl dh stat crc |
C rx: - eop |
# |
.rxsop |
.rxcs 11001010 00000000 |
.rxcs 11001010 00000000 |
.rxcds 11100000 1111111100000001 00000000 |
.rxeop |
# |
.txsop |
.txcad 11001010 00000001 1111111100000001 |
.txcad 11001010 00000010 1111111100000010 |
.txca 11100000 00000001 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 4: wblk - rblk |
C wblk: rx: sop - cmd(10100,011) addr(10000000) cnt(8->111) ccrc dl dh .. dcrc |
C rx: - eop |
C rx: sop - cmd(011) stat crc |
C rx: - eop |
# |
.rxsop |
.rxcs 10100011 00000000 |
.rxeop |
# |
.txsop |
.txcac 10100011 10000000 00000111 |
.tx16 0000000001000000 |
.tx16 0000000001000001 |
.tx16 0000000001000010 |
.tx16 0000000001000011 |
.tx16 0000000001000100 |
.tx16 0000000001000101 |
.tx16 0000000001000110 |
.tx16 0000000001000111 |
.txcrc |
.txeop |
# |
.iowt 10 |
C |
C now check, that register 16 holds 8, clear it to prepare reread: |
C rreg: tx: sop - cmd(10011,000) addr(10000) ccrc |
C wreg: tx: - cmd(10000,010) addr(10000) dl dh ccrc |
C tx: - eop |
C rx: sop - cmd(000) dl dh stat crc |
C rx: - cmd(010) stat crc |
C rx: - eop |
# |
.rxsop |
.rxcds 10011000 0000000000001000 00000000 |
.rxcs 10000010 00000000 |
.rxeop |
# |
.txsop |
.txca 10011000 00010000 |
.txcad 10000010 00010000 00000000000000000 |
.txeop |
# |
.iowt 10 |
C rblk: rx: sop - cmd(10110,001) addr(10000000) cnt(8->111) ccrc - eop |
C rx: sop - cmd(001) cnt dl dh ... stat crc - eop |
# |
.rxsop |
.rx8 10110001 |
.rx8 00000111 |
.rx16 0000000001000000 |
.rx16 0000000001000001 |
.rx16 0000000001000010 |
.rx16 0000000001000011 |
.rx16 0000000001000100 |
.rx16 0000000001000101 |
.rx16 0000000001000110 |
.rx16 0000000001000111 |
.rx8 00000000 |
.rxcrc |
.rxeop |
# |
.txsop |
.txcac 10110001 10000000 00000111 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 5: stat (in non-error case) re-read last cmd twice, shouldn't change |
C wreg: tx: sop - cmd(00001,010) addr(0010) dl dh ccrc |
C wreg: tx: - cmd(00011,010) addr(0011) dl dh ccrc |
C rreg: tx: - cmd(00101,000) addr(0010) ccrc |
C rreg: tx: - cmd(00111,000) addr(0011) ccrc |
C stat: tx: - cmd(01001,100) ccrc |
C stat: tx: - cmd(01010,100) ccrc |
C tx: - eop |
C rx: sop - cmd(010) stat crc |
C rx: - cmd(010) stat crc |
C rx: - cmd(000) dl dh stat crc |
C rx: - cmd(000) dl dh stat crc |
C rx: - cmd(100) ccmd (000) dl dh stat crc |
C rx: - cmd(100) ccmd (000) dl dh stat crc |
C rx: - eop |
# |
.rxsop |
.rxcs 00001010 00000000 |
.rxcs 00011010 00000000 |
.rxcds 00101000 1000000000000010 00000000 |
.rxcds 00111000 1000000100000011 00000000 |
.rxccd 01001100 00111000 1000000100000011 00000000 |
.rxccd 01010100 00111000 1000000100000011 00000000 |
.rxeop |
# |
.txsop |
.txcad 00001010 00000010 1000000000000010 |
.txcad 00011010 00000011 1000000100000011 |
.txca 00101000 00000010 |
.txca 00111000 00000011 |
.txc 01001100 |
.txc 01010100 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 6: ccrc error abort |
C wreg: tx: sop - cmd(01001,010) addr(0010) dl dh ccrc |
C wreg: tx: - cmd(01011,010) addr(0011) dl dh ccrc |
C rreg: tx: - cmd(01101,000) addr(0010) ccrc |
C rreg: tx: - cmd(01110,000) addr(0011) *BAD CRC* |
C tx: - eop |
C rx: sop - cmd(010) stat crc |
C rx: - cmd(010) stat crc |
C rx: - cmd(000) dl dh stat crc |
C rx: - nak *ABORT* |
C rx: - eop |
# |
.rxsop |
.rxcs 01001010 00000000 |
.rxcs 01011010 00000000 |
.rxcds 01101000 1000000100001010 00000000 |
.rxnak |
.rxeop |
# |
.txsop |
.txcad 01001010 00000010 1000000100001010 |
.txcad 01011010 00000011 1000000100001011 |
.txca 01101000 00000010 |
.tx8 01110000 |
.tx8 00000011 |
.tx8 00000000 |
.txeop |
# |
.iowt 10 |
C |
C now check that stat reflects last successfull rreg; re-read ccrc=1 sticks ! |
C stat: tx: sop - cmd(10001,100) ccrc |
C stat: tx: - cmd(10010,100) ccrc |
C tx: - eop |
C rx: - cmd(100) ccmd (000) dl dh stat crc |
C rx: - cmd(100) ccmd (000) dl dh stat crc |
C rx: - eop |
C stat: stat(000),attn(0),ccrc(1),dcrc(0),ioto(0),ioerr(0) -> 00001000 |
.rxsop |
.rxccd 10001100 01101000 1000000100001010 00001000 |
.rxccd 10010100 01101000 1000000100001010 00001000 |
.rxeop |
# |
.txsop |
.txc 10001100 |
.txc 10010100 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 7: dcrc error condition |
C wreg: tx: sop - cmd(00001,010) addr(10000) dl dh ccrc |
C wblk: rx: - cmd(00011,011) addr(10000000) cnt(4->011) ccrc dl dh .. |
C *BAD CRC* |
C rx: - eop |
C rx: sop - cmd(010) stat crc |
C rx: - cmd(011) stat crc |
C rx: - eop |
C stat: stat(000),attn(0),ccrc(0),dcrc(1),ioto(0),ioerr(0) -> 00000100 |
# |
.rxsop |
.rxcs 00001010 00000000 |
.rxcs 00010011 00000100 |
.rxeop |
# |
.txsop |
.txcad 00001010 00010000 00000000000000000 |
.txcac 00010011 10000000 00000011 |
.tx16 0001000001000000 |
.tx16 0001000001000001 |
.tx16 0001000001000010 |
.tx16 0001000001000011 |
.tx8 00000000 |
.txeop |
# |
.iowt 10 |
C |
C now check that stat reflects bad dcrc: re-read dcrc=1 sticks ! |
C stat: tx: sop - cmd(00101,100) ccrc |
C stat: tx: - cmd(00110,100) ccrc |
C tx: - eop |
C rx: - cmd(100) ccmd (000) dl dh stat crc |
C rx: - cmd(100) ccmd (000) dl dh stat crc |
C rx: - eop |
C stat: stat(000),attn(0),ccrc(0),dcrc(1),ioto(0),ioerr(0) -> 00000100 |
C Note: dl,dh still the last read of Test 6 !! |
.rxsop |
.rxccd 00101100 00010011 1000000100001010 00000100 |
.rxccd 00110100 00010011 1000000100001010 00000100 |
.rxeop |
# |
.txsop |
.txc 00101100 |
.txc 00110100 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 8: err(bad address) condition; 11000000 is an address returning err=1 |
C rreg: tx: sop - cmd(00001,000) addr(00010000) ccrc |
C rreg: tx: - cmd(00011,000) addr(11000000) ccrc |
C wreg: tx: - cmd(00101,010) addr(00010000) dl dh ccrc |
C wreg: tx: - cmd(00110,010) addr(11000000) dl dh ccrc |
C tx: - eop |
C Note: the rreg(10000) will return 4, the prt after the last wblk ! |
C Note: tb returns 1010101010101010 for access to bad addresses |
C stat: stat(000),attn(0),ccrc(0),dcrc(0),ioto(0),ioerr(1) -> 00000001 |
# |
.rxsop |
.rxcds 00001000 0000000000000100 00000000 |
.rxcds 00011000 1010101010101010 00000001 |
.rxcs 00101010 00000000 |
.rxcs 00110010 00000001 |
.rxeop |
# |
.txsop |
.txca 00001000 00010000 |
.txca 00011000 11000000 |
.txcad 00101010 00010000 0000000000000000 |
.txcad 00110010 11000000 1000111110001111 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 9: to(time out) condition; 01bbbbbb addressed take n+1 hold states |
C wreg: tx: sop - cmd(00001,010) addr(01000000) dl dh ccrc (nh=1) |
C wreg: tx: - cmd(00011,010) addr(01001111) dl dh ccrc (nh=16) |
C wreg: tx: - cmd(00101,010) addr(01011101) dl dh ccrc (nh=30) |
C wreg: tx: - cmd(00111,010) addr(01011110) dl dh ccrc (nh=31) |
C wreg: tx: - cmd(01001,010) addr(01011111) dl dh ccrc (nh=32) TO |
C wreg: tx: - cmd(01011,010) addr(01100000) dl dh ccrc (nh=33) TO |
C wreg: tx: - cmd(01101,010) addr(01111111) dl dh ccrc (nh=64) TO |
C wreg: tx: - cmd(01110,010) addr(01000001) dl dh ccrc (nh=2) |
C tx: - eop |
C stat: stat(000),attn(0),ccrc(0),dcrc(0),ioto(1),ioerr(0) -> 00000010 |
# |
.rxsop |
.rxcs 00001010 00000000 |
.rxcs 00011010 00000000 |
.rxcs 00101010 00000000 |
.rxcs 00111010 00000000 |
.rxcs 01001010 00000010 |
.rxcs 01011010 00000010 |
.rxcs 01101010 00000010 |
.rxcs 01110010 00000000 |
.rxeop |
# |
.txsop |
.txcad 00001010 01000000 0000000001000000 |
.txcad 00011010 01001111 0000000001001111 |
.txcad 00101010 01011101 0000000001011101 |
.txcad 00111010 01011110 0000000001011110 |
.txcad 01001010 01011111 0000000001011111 |
.txcad 01011010 01100000 0000000001100000 |
.txcad 01101010 01111110 0000000001111111 |
.txcad 01110010 01000001 0000000001000001 |
.txeop |
.iowt 10 |
C |
C now same with rreg |
C rreg: tx: sop - cmd(00001,000) addr(01000000) ccrc (nh=1) |
C rreg: tx: - cmd(00011,000) addr(01001111) ccrc (nh=16) |
C rreg: tx: - cmd(00101,000) addr(01011101) ccrc (nh=30) |
C rreg: tx: - cmd(00111,000) addr(01011110) ccrc (nh=31) |
C rreg: tx: - cmd(01001,000) addr(01011111) ccrc (nh=32) TO |
C rreg: tx: - cmd(01011,000) addr(01100000) ccrc (nh=33) TO |
C rreg: tx: - cmd(01101,000) addr(01111111) ccrc (nh=64) TO |
C rreg: tx: - cmd(01110,000) addr(01000001) ccrc (nh=2) |
C tx: - eop |
C Note: tb returns 0101010101010101 for timeout |
# |
.rxsop |
.rxcds 00001000 0000000001000000 00000000 |
.rxcds 00011000 0000000001001111 00000000 |
.rxcds 00101000 0000000001011101 00000000 |
.rxcds 00111000 0000000001011110 00000000 |
.rxcds 01001000 0101010101010101 00000010 |
.rxcds 01011000 0101010101010101 00000010 |
.rxcds 01101000 0101010101010101 00000010 |
.rxcds 01110000 0000000001000001 00000000 |
.rxeop |
# |
.txsop |
.txca 00001000 01000000 |
.txca 00011000 01001111 |
.txca 00101000 01011101 |
.txca 00111000 01011110 |
.txca 01001000 01011111 |
.txca 01011000 01100000 |
.txca 01101000 01111110 |
.txca 01110000 01000001 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 10: external init command |
C rreg: tx: sop - cmd(00001,000) addr(00010010) ccrc |
C init: tx: - cmd(00011,110) addr(10000111) dl dh ccrc |
C rreg: tx: - cmd(00100,000) addr(00010010) ccrc |
C tx: - eop |
C rx: sop - cmd(000) dl dh stat crc |
C rx: - cmd(110) stat crc |
C rx: - cmd(000) dl dh stat crc |
C rx: - eop |
# |
.rxsop |
.rxcds 00001000 0000000000000000 00000000 |
.rxcs 00011110 00000000 |
.rxcds 00100000 0000000000000001 00000000 |
.rxeop |
# |
.txsop |
.txca 00001000 00010010 |
.txcad 00011110 10000111 0000111000111000 |
.txca 00100000 00010010 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 11: external status bit (RP_STAT) |
C Note: stat bits are not latched for stat command ! |
C stat <= "001" |
C rreg: tx: sop - cmd(00000,000) addr(00010010) ccrc - eop |
C rx: sop - cmd(000) dl dh stat crc - eop |
# |
.rxsop |
.rxcds 00000000 0000000000000001 00100000 |
.rxeop |
# |
.stat 001 |
.txsop |
.txca 00000000 00010010 |
.txeop |
# |
.iowt 10 |
C stat <= "010" |
C stat: tx: sop - cmd(00011,100) ccrc |
C rreg: tx: - cmd(00100,000) addr(00010010) ccrc |
C tx: - eop |
C rx: sop - cmd(100) ccmd (000) dl dh stat crc |
C rx: - cmd(000) dl dh stat crc |
C rx: - eop |
C Note: stat command returns old 001 status |
C rreg command returns new 010 status |
.rxsop |
.rxccd 00011100 00000000 0000000000000001 00100000 |
.rxcds 00010000 0000000000000001 01000000 |
.rxeop |
# |
.stat 010 |
.txsop |
.txc 00011100 |
.txca 00010000 00010010 |
.txeop |
# |
C stat <= "100" |
C rreg: tx: sop - cmd(00110,000) addr(00010010) ccrc - eop |
C rx: sop - cmd(000) dl dh stat crc - eop |
C stat <= '000' |
.iowt 10 |
# |
.rxsop |
.rxcds 00110000 0000000000000001 10000000 |
.rxeop |
# |
.stat 100 |
.txsop |
.txca 00110000 00010010 |
.txeop |
# |
.iowt 10 |
.stat 000 |
C ----------------------------------------------------------------------------- |
C Test 12: attention logic |
C attn <= "0000000000000100" (async case) |
C rreg: tx: sop - cmd(01001,000) addr(00010010) ccrc |
C attn: tx: - cmd(01011,101) ccrc |
C attn: tx: - cmd(01101,101) ccrc |
C rreg: tx: - cmd(01110,000) addr(00010010) ccrc |
C tx: - eop |
C Note: the rreg command returns attn=1 |
C the attn has attn=0, because stat is evaluated after read+clear !! |
C stat: stat(000),attn(1),ccrc(0),dcrc(0),ioto(0),ioerr(0) -> 00010000 |
# |
.rxsop |
.rxcds 01001000 0000000000000001 00010000 |
.rxcds 01011101 0000000000000100 00000000 |
.rxcds 01101101 0000000000000000 00000000 |
.rxcds 01110000 0000000000000001 00000000 |
.rxeop |
# |
.wait 5 |
.attn 00000100 |
.wait 5 |
.txsop |
.txca 01001000 00010010 |
.txc 01011101 |
.txc 01101101 |
.txca 01110000 00010010 |
.txeop |
# |
.iowt 10 |
C |
C now test sync case, the transaction causes the attention |
C a write to 10000010 causes AP_LAM(15 downto 8) be pinged with RP_DO data |
C wreg: tx: sob - cmd(10001,010) addr(10000010) dl dh ccrc |
C rreg: tx: - cmd(10011,000) addr(00010010) ccrc |
C attn: tx: - cmd(10101,101) ccrc |
C attn: tx: - cmd(10111,101) ccrc |
C rreg: tx: - cmd(11000,000) addr(00010010) ccrc |
C tx: - eop |
.rxsop |
.rxcs 10001010 00010000 |
.rxcds 10011000 0000000000000001 00010000 |
.rxcds 10101101 0000000100000000 00000000 |
.rxcds 10111101 0000000000000000 00000000 |
.rxcds 11000000 0000000000000001 00000000 |
.rxeop |
# |
.txsop |
.txcad 10001010 10000010 0000000100000000 |
.txca 10011000 00010010 |
.txc 10101101 |
.txc 10111101 |
.txca 11000000 00010010 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 13: verify that extra 'idle' commas are tolerated |
C do wreg+rreg, with "100000000" between bytes |
C use as data 1000000 and 10000001 to force escaping here |
C wreg: tx: sop - cmd(00001,010) addr(0000) dl dh ccrc |
C rreg: tx: sop - cmd(00010,000) addr(0000) ccrc |
C tx: - eop |
C rx: sop - cmd(010) stat crc |
C rx: sop - cmd(000) dl dh stat crc |
C rx: - eop |
# |
.rxsop |
.rxcs 00001010 00000000 |
.rxcds 00010000 1000000010000001 00000000 |
.rxeop |
# |
100000000 |
.txsop |
100000000 |
.tx8 00001010 |
100000000 |
.tx8 00000000 |
100000000 |
.tx8 10000001 |
100000000 |
100000000 |
.tx8 10000000 |
100000000 |
.txcrc |
100000000 |
.tx8 00010000 |
100000000 |
100000000 |
100000000 |
.tx8 00000000 |
100000000 |
.txcrc |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 14: enable and test asynchronous attn notification |
C init: tx: sob - cmd(00000,110) addr(00000001) dl dh ccrc - eop |
C init: anena(1), itoena(0), ito(0) -> 11111111,1000000000000000 |
# |
.rxsop |
.rxcs 00000110 00000000 |
.rxeop |
# |
.txsop |
.txcad 00000110 11111111 1000000000000000 |
.txeop |
.iowt 10 |
# |
C now ping an attention line, expect oob attn symbol |
.wait 50 |
.rxoob 100000100 |
.attn 00000001 |
.iowt 10 |
C finally read attn flags |
C attn: tx: - cmd(00010,101) ccrc - eop |
.rxsop |
.rxcds 00010101 0000000000000001 00000000 |
.rxeop |
# |
.txsop |
.txc 00010101 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 15: enable and test idle timeout |
C init: tx: sob - cmd(00100,110) addr(00000011) dl dh ccrc - eop |
C init: anena(1), itoena(1), ito(9) -> 11111111,1100000000001001 |
C ito=9 --> divider=10; ce_xsec div is 1:20 --> total every 200 cycles |
# |
.rxsop |
.rxcs 00100110 00000000 |
.rxeop |
.rxoob 100000000 |
.rxoob 100000000 |
.rxoob 100000100 |
.rxoob 100000100 |
.rxoob 100000100 |
# |
.txsop |
.txcad 00100110 11111111 1100000000001001 |
.txeop |
# |
.iowt 10 |
C total ito now 200 cycles; wait 500 cycles, see 2 idle symbols |
.wait 500 |
C ping an attention line, expect oob attn symbol |
.attn 00000010 |
.iowt 10 |
C wait 500 more cycles, see 2 attn symbols |
.wait 500 |
C finally read attn flags |
C attn: tx: - cmd(00110,101) ccrc - eop |
.rxsop |
.rxcds 00110101 0000000000000010 00000000 |
.rxeop |
# |
.txsop |
.txc 00110101 |
.txeop |
# |
.iowt 10 |
C wait 500 more cycles, see 2 idle symbols again |
.rxoob 100000000 |
.rxoob 100000000 |
.wait 500 |
C finally disable attn notification and idle timeout again |
C init: tx: sob - cmd(00000,110) addr(00000000) dl dh ccrc - eop |
C init: anena(0), itoena(0), ito(0) -> 11111111,0000000000000000 |
# |
.rxsop |
.rxcs 00000110 00000000 |
.rxeop |
# |
.txsop |
.txcad 00000110 11111111 0000000000000000 |
.txeop |
# |
.iowt 10 |
C ----------------------------------------------------------------------------- |
C Test 16: attn poll |
# |
C send 2 attn, expect two idles back |
.rxoob 100000000 |
.rxoob 100000000 |
100000100 |
100000100 |
.iowt 10 |
# |
C ping an attention line |
.attn 00000010 |
# |
C send 2 attn, expect two attn back |
.rxoob 100000100 |
.rxoob 100000100 |
100000100 |
100000100 |
.iowt 10 |
# |
/rri/tb/rritblib.vhd
0,0 → 1,152
-- $Id: rritblib.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: rritblib |
-- Description: Remote Register Interface test environment components |
-- |
-- Dependencies: - |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon |
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining |
-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon |
-- 2010-05-02 287 2.1.1 rename CE_XSEC->CE_INT,RP_STAT->RB_STAT |
-- drop RP_IINT signal from interfaces |
-- add sbcntl_sbf_(cp|rp)mon defs |
-- 2010-04-24 282 2.1 add rritb_core |
-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface |
-- 2008-03-24 129 1.1.5 CLK_CYCLE now 31 bits |
-- 2007-12-23 105 1.1.4 add AP_LAM for rritb_rpmon(_sb) |
-- 2007-11-24 98 1.1.3 add RP_IINT for rritb_rpmon(_sb) |
-- 2007-09-01 78 1.1.2 add rricp_rp |
-- 2007-08-25 75 1.1.1 add rritb_cpmon_sb, rritb_rpmon_sb |
-- 2007-08-16 74 1.1 remove rritb_tt* component; some interface changes |
-- 2007-08-03 71 1.0.2 use rrirp_acif; change generics for rritb_[cr]pmon |
-- 2007-07-22 68 1.0.1 add rritb_cpmon rritb_rpmon monitors |
-- 2007-07-15 66 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.rrilib.all; |
|
package rritblib is |
|
-- simbus sb_cntl field usage for rri |
constant sbcntl_sbf_cpmon : integer := 15; |
constant sbcntl_sbf_rbmon : integer := 14; |
|
|
component rritb_cpmon is -- rritb, rri comm port monitor |
generic ( |
DWIDTH : positive := 9); -- data port width (8 or 9) |
port ( |
CLK : in slbit; -- clock |
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number |
ENA : in slbit := '1'; -- enable monitor output |
CP_DI : in slv(DWIDTH-1 downto 0); -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : in slbit; -- comm port: data busy |
CP_DO : in slv(DWIDTH-1 downto 0); -- comm port: data out |
CP_VAL : in slbit; -- comm port: data valid |
CP_HOLD : in slbit -- comm port: data hold |
); |
end component; |
|
component rritb_cpmon_sb is -- simbus wrap for rri comm port monitor |
generic ( |
DWIDTH : positive := 9; -- data port width (8 or 9) |
ENAPIN : integer := sbcntl_sbf_cpmon); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
CP_DI : in slv(DWIDTH-1 downto 0); -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : in slbit; -- comm port: data busy |
CP_DO : in slv(DWIDTH-1 downto 0); -- comm port: data out |
CP_VAL : in slbit; -- comm port: data valid |
CP_HOLD : in slbit -- comm port: data hold |
); |
end component; |
|
component rritb_rbmon is -- rritb, rri rbus monitor |
generic ( |
DBASE : positive := 2); -- base for writing data values |
port ( |
CLK : in slbit; -- clock |
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number |
ENA : in slbit := '1'; -- enable monitor output |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv3 -- rbus: status flags |
); |
end component; |
|
component rritb_rbmon_sb is -- simbus wrap for rri rbus monitor |
generic ( |
DBASE : positive := 2; -- base for writing data values |
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv3 -- rbus: status flags |
); |
end component; |
|
component rritb_sres_or_mon is -- rribus result or monitor |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4 |
); |
end component; |
|
component rritb_core is -- core of rri/cext based test bench |
generic ( |
CLK_PERIOD : time := 20 ns; -- clock period |
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock) |
SETUP_TIME : time := 5 ns; -- setup time |
C2OUT_TIME : time := 10 ns); -- clock to output time |
port ( |
CLK : out slbit; -- main clock |
RX_DATA : out slv8; -- read data (data ext->tb) |
RX_VAL : out slbit; -- read data valid (data ext->tb) |
RX_HOLD : in slbit; -- read data hold (data ext->tb) |
TX_DATA : in slv8; -- write data (data tb->ext) |
TX_ENA : in slbit -- write data enable (data tb->ext) |
); |
end component; |
|
component rricp_rp is -- rri comm->reg port aif forwarder |
-- implements rricp_aif, uses rrirp_aif |
port ( |
CLK : in slbit; -- clock |
CE_INT : in slbit := '0'; -- rri ito time unit clock enable |
RESET : in slbit :='0'; -- reset |
CP_DI : in slv9; -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : out slbit; -- comm port: data busy |
CP_DO : out slv9; -- comm port: data out |
CP_VAL : out slbit; -- comm port: data valid |
CP_HOLD : in slbit := '0' -- comm port: data hold |
); |
end component; |
|
end rritblib; |
/rri/tb/rritb_sres_or_mon.vbom
0,0 → 1,5
# libs |
../../slvtypes.vhd |
../rrilib.vhd |
# design |
rritb_sres_or_mon.vhd |
/rri/tb/tb_rri_core.vbom
0,0 → 1,6
# configure tb_rri with tbd_rri_core wrapper |
# use vhdl configure file (tb_rri_core.vhd) at allow |
# that all configurations will co-exist in work library |
tbd_rri_gen = tbd_rri_core.vbom |
tb_rri.vbom |
tb_rri_core.vhd |
/rri/tb/rritb_core.vbom
0,0 → 1,12
# libs |
../../slvtypes.vhd |
../../simlib/simlib.vhd |
../../simlib/simbus.vhd |
rritblib.vhd |
vhpi_rriext.vhd |
# components |
../../simlib/simclk.vbom |
# vhpi |
cext_rriext.c |
# design |
rritb_core.vhd |
/rri/tb/rritb_cpmon.vhd
0,0 → 1,144
-- $Id: rritb_cpmon.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rritb_cpmon - sim |
-- Description: rritb: rri comm port monitor |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now |
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining |
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits |
-- 2007-09-09 81 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.rrilib.all; |
|
entity rritb_cpmon is -- rritb, rri comm port monitor |
generic ( |
DWIDTH : positive := 9); -- data port width (8 or 9) |
port ( |
CLK : in slbit; -- clock |
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number |
ENA : in slbit := '1'; -- enable monitor output |
CP_DI : in slv(DWIDTH-1 downto 0); -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : in slbit; -- comm port: data busy |
CP_DO : in slv(DWIDTH-1 downto 0); -- comm port: data out |
CP_VAL : in slbit; -- comm port: data valid |
CP_HOLD : in slbit -- comm port: data hold |
); |
end rritb_cpmon; |
|
|
architecture sim of rritb_cpmon is |
|
begin |
|
assert DWIDTH=8 or DWIDTH=9 |
report "assert(DWIDTH=8 or DWIDTH=9)" severity failure; |
|
proc_cpmoni: process |
variable oline : line; |
variable nbusy : integer := 0; |
variable nhold : integer := 0; |
|
procedure write_val(L: inout line; |
data: in slv(DWIDTH-1 downto 0); |
nwait: in integer; |
txt1: in string; |
txt2: in string) is |
variable data9 : slv9 := (others=>'0'); |
begin |
|
writetimestamp(L, CLK_CYCLE, txt1); |
|
if DWIDTH = 9 then |
write(L, data(data'left), right, 1); |
else |
write(L, string'(" ")); |
end if; |
|
write(L, data(7 downto 0), right, 9); |
if nwait > 0 then |
write(L, txt2); |
write(L, nwait); |
end if; |
|
if DWIDTH=9 and data(data'left)='1' then |
-- a copy to data9 needed to allow following case construct |
-- using data directly gives a 'subtype is not locally static' error |
data9 := (others=>'0'); |
data9(data'range) := data; |
write(L, string'(" comma")); |
case data9 is |
when c_rri_dat_idle => write(L, string'(" idle")); |
when c_rri_dat_sop => write(L, string'(" sop")); |
when c_rri_dat_eop => write(L, string'(" eop")); |
when c_rri_dat_nak => write(L, string'(" nak")); |
when c_rri_dat_attn => write(L, string'(" attn")); |
when others => null; |
end case; |
end if; |
|
writeline(output, L); |
end procedure write_val; |
|
begin |
|
loop |
|
if ENA='0' then -- if disabled |
wait until ENA='1'; -- stall process till enabled |
end if; |
|
wait until CLK'event and CLK='1'; -- check at end of clock cycle |
|
if CP_ENA = '1' then |
if CP_BUSY = '1' then |
nbusy := nbusy + 1; |
else |
write_val(oline, CP_DI, nbusy, ": cprx ", " nbusy="); |
nbusy := 0; |
end if; |
else |
nbusy := 0; |
end if; |
|
if CP_VAL = '1' then |
if CP_HOLD = '1' then |
nhold := nhold + 1; |
else |
write_val(oline, CP_DO, nhold, ": cptx ", " nhold="); |
nhold := 0; |
end if; |
else |
nhold := 0; |
end if; |
|
end loop; |
end process proc_cpmoni; |
|
end sim; |
/rri/tb/rritb_rbmon.vhd
0,0 → 1,146
-- $Id: rritb_rbmon.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rritb_rbmon - sim |
-- Description: rritb: rri rbus monitor |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon |
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext) |
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT signal from interfaces |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits |
-- 2007-12-23 105 1.2 added AP_LAM display |
-- 2007-11-24 98 1.1 added RP_IINT support |
-- 2007-08-27 76 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.rrilib.all; |
|
entity rritb_rbmon is -- rritb, rri rbus monitor |
generic ( |
DBASE : positive := 2); -- base for writing data values |
port ( |
CLK : in slbit; -- clock |
CLK_CYCLE : in slv31 := (others=>'0'); -- clock cycle number |
ENA : in slbit := '1'; -- enable monitor output |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv3 -- rbus: status flags |
); |
end rritb_rbmon; |
|
|
architecture sim of rritb_rbmon is |
|
begin |
|
proc_rbmoni: process |
variable oline : line; |
variable nhold : integer := 0; |
variable data : slv16 := (others=>'0'); |
variable tag : string(1 to 8) := (others=>' '); |
variable err : slbit := '0'; |
|
procedure write_data(L: inout line; |
tag: in string; |
data: in slv16; |
nhold: in integer := 0; |
cond: in boolean := false; |
ctxt: in string := " ") is |
begin |
writetimestamp(L, CLK_CYCLE, tag); |
write(L, RB_MREQ.addr, right, 10); |
write(L, string'(" ")); |
writegen(L, data, right, 0, DBASE); |
write(L, RB_STAT, right, 4); |
if nhold > 0 then |
write(L, string'(" nhold=")); |
write(L, nhold); |
end if; |
if cond then |
write(L, ctxt); |
end if; |
writeline(output, L); |
end procedure write_data; |
|
begin |
|
loop |
|
if ENA = '0' then -- if disabled |
wait until ENA='1'; -- stall process till enabled |
end if; |
|
wait until CLK'event and CLK='1'; -- check at end of clock cycle |
|
if RB_MREQ.req = '1' then |
if RB_SRES.err = '1' then |
err := '1'; |
end if; |
if RB_SRES.busy = '1' then |
nhold := nhold + 1; |
else |
if RB_MREQ.req = '1' then |
if RB_MREQ.we = '0' then |
data := RB_SRES.dout; |
tag := ": rbre "; |
else |
data := RB_MREQ.din; |
tag := ": rbwe "; |
end if; |
end if; |
|
write_data(oline, tag, data, nhold, err='1', " ERR='1'"); |
nhold := 0; |
end if; |
|
else |
if nhold > 0 then |
write_data(oline, tag, data, nhold, true, " TIMEOUT"); |
end if; |
nhold := 0; |
err := '0'; |
end if; |
|
if RB_MREQ.init = '1' then -- init |
if RB_MREQ.we = '1' then |
write_data(oline, ": rbini ", RB_MREQ.din); -- external |
else |
write_data(oline, ": rbint ", RB_MREQ.din); -- internal |
end if; |
end if; |
|
if unsigned(RB_LAM) /= 0 then |
write_data(oline, ": rblam ", RB_LAM, 0, true, " RB_LAM active"); |
end if; |
|
end loop; |
end process proc_rbmoni; |
|
end sim; |
/rri/tb/tb_rri.vhd
0,0 → 1,720
-- $Id: tb_rri.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tb_rri - sim |
-- Description: Test bench for rri_core |
-- |
-- Dependencies: simlib/simclk |
-- genlib/clkdivce |
-- tbd_rri_gen [UUT] |
-- |
-- To test: rri_core |
-- rri_serport |
-- |
-- Target Devices: generic |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining |
-- 2010-06-03 299 2.2.2 new init encoding (WE=0/1 int/ext);use sv_ prefix |
-- for shared variables |
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT signal from interfaces |
-- 2010-04-03 274 2.2 add CE_USEC in tbd_rri_gen interface |
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2008-03-24 129 1.1.2 CLK_CYCLE now 31 bits |
-- 2008-01-20 112 1.1.1 rename clkgen->clkdivce |
-- 2007-11-24 98 1.1 add RP_IINT support, add checkmiss_tx to test |
-- for missing responses |
-- 2007-10-26 92 1.0.2 add DONE timestamp at end of execution |
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned |
-- 2007-09-09 81 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.genlib.all; |
use work.comlib.all; |
use work.rrilib.all; |
use work.simlib.all; |
|
entity tb_rri is |
end tb_rri; |
|
architecture sim of tb_rri is |
|
signal CLK : slbit := '0'; |
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
signal RESET : slbit := '0'; |
signal CP_DI : slv9 := (others=>'0'); |
signal CP_ENA : slbit := '0'; |
signal CP_BUSY : slbit := '0'; |
signal CP_DO : slv9 := (others=>'0'); |
signal CP_VAL : slbit := '0'; |
signal CP_HOLD : slbit := '0'; |
signal RB_MREQ_req : slbit := '0'; |
signal RB_MREQ_we : slbit := '0'; |
signal RB_MREQ_initt: slbit := '0'; |
signal RB_MREQ_addr : slv8 := (others=>'0'); |
signal RB_MREQ_din : slv16 := (others=>'0'); |
signal RB_SRES_ack : slbit := '0'; |
signal RB_SRES_busy : slbit := '0'; |
signal RB_SRES_err : slbit := '0'; |
signal RB_SRES_dout : slv16 := (others=>'0'); |
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv3 := (others=>'0'); |
signal TXRXACT : slbit := '0'; |
|
signal CLK_STOP : slbit := '0'; |
signal CLK_CYCLE : slv31 := (others=>'0'); |
|
constant slv9_zero : slv9 := (others=>'0'); |
constant slv16_zero : slv16 := (others=>'0'); |
|
type slv9_array_type is array (0 to 255) of slv9; |
type slv16_array_type is array (0 to 255) of slv16; |
|
shared variable sv_rxlist : slv9_array_type := (others=>slv9_zero); |
shared variable sv_nrxlist : natural := 0; |
shared variable sv_rxind : natural := 0; |
|
constant clock_period : time := 20 ns; |
constant clock_offset : time := 200 ns; |
constant setup_time : time := 5 ns; |
constant c2out_time : time := 10 ns; |
|
component tbd_rri_gen is -- rri, generic tb design interface |
port ( |
CLK : in slbit; -- clock |
CE_INT : in slbit; -- rri ito time unit clock enable |
CE_USEC : in slbit; -- 1 usec clock enable |
RESET : in slbit; -- reset |
CP_DI : in slv9; -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : out slbit; -- comm port: data busy |
CP_DO : out slv9; -- comm port: data out |
CP_VAL : out slbit; -- comm port: data valid |
CP_HOLD : in slbit; -- comm port: data hold |
RB_MREQ_req : out slbit; -- rbus: request - req |
RB_MREQ_we : out slbit; -- rbus: request - we |
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll |
RB_MREQ_addr : out slv8; -- rbus: request - addr |
RB_MREQ_din : out slv16; -- rbus: request - din |
RB_SRES_ack : in slbit; -- rbus: response - ack |
RB_SRES_busy : in slbit; -- rbus: response - busy |
RB_SRES_err : in slbit; -- rbus: response - err |
RB_SRES_dout : in slv16; -- rbus: response - dout |
RB_LAM : in slv16; -- rbus: look at me |
RB_STAT : in slv3; -- rbus: status flags |
TXRXACT : out slbit -- txrx active flag |
); |
end component; |
|
begin |
|
SYSCLK : simclk |
generic map ( |
PERIOD => clock_period, |
OFFSET => clock_offset) |
port map ( |
CLK => CLK, |
CLK_CYCLE => CLK_CYCLE, |
CLK_STOP => CLK_STOP |
); |
|
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 6, |
USECDIV => 4, |
MSECDIV => 5 |
) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC |
); |
|
UUT : tbd_rri_gen |
port map ( |
CLK => CLK, |
CE_INT => CE_MSEC, |
CE_USEC => CE_USEC, |
RESET => RESET, |
CP_DI => CP_DI, |
CP_ENA => CP_ENA, |
CP_BUSY => CP_BUSY, |
CP_DO => CP_DO, |
CP_VAL => CP_VAL, |
CP_HOLD => CP_HOLD, |
RB_MREQ_req => RB_MREQ_req, |
RB_MREQ_we => RB_MREQ_we, |
RB_MREQ_initt=> RB_MREQ_initt, |
RB_MREQ_addr => RB_MREQ_addr, |
RB_MREQ_din => RB_MREQ_din, |
RB_SRES_ack => RB_SRES_ack, |
RB_SRES_busy => RB_SRES_busy, |
RB_SRES_err => RB_SRES_err, |
RB_SRES_dout => RB_SRES_dout, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT, |
TXRXACT => TXRXACT |
); |
|
|
proc_stim: process |
file fstim : text open read_mode is "tb_rri_stim"; |
variable iline : line; |
variable oline : line; |
variable icmd : slv8 := (others=>'0'); |
variable iaddr : slv8 := (others=>'0'); |
variable icnt : slv8 := (others=>'0'); |
variable istat : slv3 := (others=>'0'); |
variable iattn : slv8 := (others=>'0'); |
variable idata : slv16 := (others=>'0'); |
variable ioob : slv9 := (others=>'0'); |
variable ok : boolean; |
variable dname : string(1 to 6) := (others=>' '); |
variable idelta : integer := 0; |
variable iowait : integer := 0; |
variable txcrc,rxcrc : slv8 := (others=>'0'); |
variable txlist : slv9_array_type := (others=>slv9_zero); |
variable ntxlist : natural := 0; |
|
procedure do_tx8 (data : inout slv8) is |
begin |
txlist(ntxlist) := '0' & data; |
ntxlist := ntxlist + 1; |
crc8_update_tbl(txcrc, data); |
end procedure do_tx8; |
|
procedure do_tx16 (data : inout slv16) is |
begin |
do_tx8(data( 7 downto 0)); |
do_tx8(data(15 downto 8)); |
end procedure do_tx16; |
|
procedure do_rx8 (data : inout slv8) is |
begin |
sv_rxlist(sv_nrxlist) := '0' & data; |
sv_nrxlist := sv_nrxlist + 1; |
crc8_update_tbl(rxcrc, data); |
end procedure do_rx8; |
|
procedure do_rx16 (data : inout slv16) is |
begin |
do_rx8(data( 7 downto 0)); |
do_rx8(data(15 downto 8)); |
end procedure do_rx16; |
|
procedure checkmiss_rx is |
begin |
if sv_rxind < sv_nrxlist then |
for i in sv_rxind to sv_nrxlist-1 loop |
writetimestamp(oline, CLK_CYCLE, ": moni "); |
write(oline, string'(" FAIL MISSING DATA=")); |
write(oline, sv_rxlist(i)(8)); |
write(oline, string'(" ")); |
write(oline, sv_rxlist(i)(7 downto 0)); |
writeline(output, oline); |
end loop; |
|
end if; |
end procedure checkmiss_rx; |
|
begin |
|
wait for clock_offset - setup_time; |
|
file_loop: while not endfile(fstim) loop |
|
readline (fstim, iline); |
|
readcomment(iline, ok); |
next file_loop when ok; |
|
readcommand(iline, dname, ok); |
if ok then |
case dname is |
when ".reset" => -- .reset |
write(oline, string'(".reset")); |
writeline(output, oline); |
RESET <= '1'; |
wait for clock_period; |
RESET <= '0'; |
wait for 9*clock_period; |
|
when ".wait " => -- .wait |
read_ea(iline, idelta); |
wait for idelta*clock_period; |
|
when ".iowt " => -- .iowt |
read_ea(iline, iowait); |
idelta := iowait; |
while idelta > 0 loop -- until time has expired |
if TXRXACT = '1' then -- if any io activity |
idelta := iowait; -- restart timer |
else |
idelta := idelta - 1; -- otherwise count down time |
end if; |
wait for clock_period; |
end loop; |
|
when ".stat " => -- .stat |
read_ea(iline, istat); |
RB_STAT <= istat; -- set ext. status lines |
wait for clock_period; -- ensure some setling |
|
when ".attn " => -- .attn |
read_ea(iline, iattn); |
RB_LAM(7 downto 0) <= iattn; -- pulse lsb attn lines |
wait for clock_period; -- for 1 clock |
RB_LAM(7 downto 0) <= (others=>'0'); |
|
when ".txsop" => -- .txsop send sop |
txlist(0) := c_rri_dat_sop; |
ntxlist := 1; |
txcrc := (others=>'0'); |
when ".txeop" => -- .txeop send eop |
txlist(0) := c_rri_dat_eop; |
ntxlist := 1; |
txcrc := (others=>'0'); |
when ".txnak" => -- .txnak send nak |
txlist(0) := c_rri_dat_nak; |
ntxlist := 1; |
txcrc := (others=>'0'); |
when ".tx8 " => -- .tx8 send 8 bit value |
read_ea(iline, iaddr); |
ntxlist := 0; |
do_tx8(iaddr); |
when ".tx16 " => -- .tx16 send 16 bit value |
read_ea(iline, idata); |
ntxlist := 0; |
do_tx16(idata); |
when ".txcrc" => -- .txcrc send crc |
txlist(0) := '0' & txcrc; |
ntxlist := 1; |
|
when ".txc " => -- .txc send: cmd crc |
read_ea(iline, icmd); |
ntxlist := 0; |
do_tx8(icmd); |
txlist(ntxlist) := '0' & txcrc; |
ntxlist := ntxlist + 1; |
|
when ".txca " => -- .txc send: cmd addr crc |
read_ea(iline, icmd); |
read_ea(iline, iaddr); |
ntxlist := 0; |
do_tx8(icmd); |
do_tx8(iaddr); |
txlist(ntxlist) := '0' & txcrc; |
ntxlist := ntxlist + 1; |
|
when ".txcad" => -- .txc send: cmd addr data crc |
read_ea(iline, icmd); |
read_ea(iline, iaddr); |
read_ea(iline, idata); |
ntxlist := 0; |
do_tx8(icmd); |
do_tx8(iaddr); |
do_tx16(idata); |
txlist(ntxlist) := '0' & txcrc; |
ntxlist := ntxlist + 1; |
|
when ".txcac" => -- .txc send: cmd addr cnt crc |
read_ea(iline, icmd); |
read_ea(iline, iaddr); |
read_ea(iline, icnt); |
ntxlist := 0; |
do_tx8(icmd); |
do_tx8(iaddr); |
do_tx8(icnt); |
txlist(ntxlist) := '0' & txcrc; |
ntxlist := ntxlist + 1; |
|
when ".rxsop" => -- .rxsop expect sop |
checkmiss_rx; |
sv_rxlist(0) := c_rri_dat_sop; |
sv_nrxlist := 1; |
sv_rxind := 0; |
rxcrc := (others=>'0'); |
when ".rxeop" => -- .rxeop expect eop |
sv_rxlist(sv_nrxlist) := c_rri_dat_eop; |
sv_nrxlist := sv_nrxlist + 1; |
when ".rxnak" => -- .rxnak expect nak |
sv_rxlist(sv_nrxlist) := c_rri_dat_nak; |
sv_nrxlist := sv_nrxlist + 1; |
when ".rx8 " => -- .rx8 expect 8 bit value |
read_ea(iline, iaddr); |
do_rx8(iaddr); |
when ".rx16 " => -- .rx16 expect 16 bit value |
read_ea(iline, idata); |
do_rx16(idata); |
when ".rxcrc" => -- .rxcrc expect crc |
sv_rxlist(sv_nrxlist) := '0' & rxcrc; |
sv_nrxlist := sv_nrxlist+1; |
|
when ".rxcs " => -- .rxcs expect: cmd stat crc |
read_ea(iline, icmd); |
read_ea(iline, iaddr); |
do_rx8(icmd); |
do_rx8(iaddr); |
sv_rxlist(sv_nrxlist) := '0' & rxcrc; |
sv_nrxlist := sv_nrxlist + 1; |
|
when ".rxcds" => -- .rxcsd expect: cmd data stat crc |
read_ea(iline, icmd); |
read_ea(iline, idata); |
read_ea(iline, iaddr); |
do_rx8(icmd); |
do_rx16(idata); |
do_rx8(iaddr); |
sv_rxlist(sv_nrxlist) := '0' & rxcrc; |
sv_nrxlist := sv_nrxlist + 1; |
|
when ".rxccd" => -- .rxccd expect: cmd ccmd dat stat crc |
read_ea(iline, icmd); |
read_ea(iline, icnt); |
read_ea(iline, idata); |
read_ea(iline, iaddr); |
do_rx8(icmd); |
do_rx8(icnt); |
do_rx16(idata); |
do_rx8(iaddr); |
sv_rxlist(sv_nrxlist) := '0' & rxcrc; |
sv_nrxlist := sv_nrxlist + 1; |
|
when ".rxoob" => -- .rxoob expect: out-of-band symbol |
read_ea(iline, ioob); |
sv_rxlist(sv_nrxlist) := ioob; |
sv_nrxlist := sv_nrxlist + 1; |
|
when others => -- bad directive |
write(oline, string'("?? unknown directive: ")); |
write(oline, dname); |
writeline(output, oline); |
report "aborting" severity failure; |
end case; |
|
else |
read_ea(iline, txlist(0)); |
ntxlist := 1; |
|
end if; |
|
next file_loop when ntxlist=0; |
|
for i in 0 to ntxlist-1 loop |
|
CP_DI <= txlist(i); |
CP_ENA <= '1'; |
|
writetimestamp(oline, CLK_CYCLE, ": stim "); |
write(oline, txlist(i)(8), right, 3); |
write(oline, txlist(i)(7 downto 0), right, 9); |
if txlist(i)(8) = '1' then |
case txlist(i) is |
when c_rri_dat_idle => |
write(oline, string'(" (idle)")); |
when c_rri_dat_sop => |
write(oline, string'(" (sop) ")); |
when c_rri_dat_eop => |
write(oline, string'(" (eop) ")); |
when c_rri_dat_nak => |
write(oline, string'(" (nak) ")); |
when c_rri_dat_attn => |
write(oline, string'(" (attn)")); |
when others => |
write(oline, string'(" (????)")); |
end case; |
end if; |
writeline(output, oline); |
|
wait for clock_period; |
while CP_BUSY = '1' loop |
wait for clock_period; |
end loop; |
CP_ENA <= '0'; |
|
end loop; -- i |
|
ntxlist := 0; |
|
end loop; -- file fstim |
|
wait for 50*clock_period; |
|
checkmiss_rx; |
writetimestamp(oline, CLK_CYCLE, ": DONE "); |
writeline(output, oline); |
|
CLK_STOP <= '1'; |
|
wait; -- suspend proc_stim forever |
-- clock is stopped, sim will end |
|
end process proc_stim; |
|
|
proc_moni: process |
variable oline : line; |
begin |
|
loop |
wait until CLK'event and CLK='1'; |
wait for c2out_time; |
|
if CP_VAL = '1' then |
writetimestamp(oline, CLK_CYCLE, ": moni "); |
write(oline, CP_DO(8), right, 3); |
write(oline, CP_DO(7 downto 0), right, 9); |
if CP_DO(8) = '1' then |
case CP_DO is |
when c_rri_dat_idle => |
write(oline, string'(" (idle)")); |
when c_rri_dat_sop => |
write(oline, string'(" (sop) ")); |
when c_rri_dat_eop => |
write(oline, string'(" (eop) ")); |
when c_rri_dat_nak => |
write(oline, string'(" (nak) ")); |
when c_rri_dat_attn => |
write(oline, string'(" (attn)")); |
when others => |
write(oline, string'(" (????)")); |
end case; |
end if; |
if sv_nrxlist > 0 then |
write(oline, string'(" CHECK")); |
if sv_rxind < sv_nrxlist then |
if CP_DO = sv_rxlist(sv_rxind) then |
write(oline, string'(" OK")); |
else |
write(oline, string'(" FAIL, exp=")); |
write(oline, sv_rxlist(sv_rxind)(8), right, 2); |
write(oline, sv_rxlist(sv_rxind)(7 downto 0), right, 9); |
end if; |
sv_rxind := sv_rxind + 1; |
else |
write(oline, string'(" FAIL, UNEXPECTED")); |
end if; |
end if; |
writeline(output, oline); |
end if; |
|
end loop; |
|
end process proc_moni; |
|
|
-- simulated target: |
-- 00000000 ... 00111111: 64 registers, no wait states |
-- 00010000 : (16) pointer register for mem 0 |
-- 00010001 : (17) pointer register for mem 1 |
-- 00010010 : (18) counter for init's |
-- 01000000 ... 01111111: 64 registers, addr(5 downto 0)+1 wait states |
-- 10000000 : 256 word memory, addressed by reg(00010000) |
-- 10000001 : 256 word memory, addressed by reg(00010001) |
-- 10000010 : ping RB_LAM(15 downto 8) on WE access |
-- 11000000 : signal err, write noop, read 10101010 |
-- others : no ack |
-- |
|
proc_targ: process |
variable reg0 : slv16_array_type := (others=>slv16_zero); |
variable reg1 : slv16_array_type := (others=>slv16_zero); |
variable mem0 : slv16_array_type := (others=>slv16_zero); |
variable mem1 : slv16_array_type := (others=>slv16_zero); |
variable iack : slbit := '0'; |
variable ierr : slbit := '0'; |
variable nhold : integer := 0; |
variable addr : slv8 := (others=>'0'); |
variable idout : slv16 := (others=>'0'); |
variable ind : integer := 0; |
variable oline : line; |
|
constant c2out_setup : time := clock_period-c2out_time-setup_time; |
|
type acc_type is (acc_reg0, acc_reg1, acc_mem0, acc_mem1, acc_lam, |
acc_err, acc_bad); |
variable acc : acc_type := acc_bad; |
|
procedure write_data (pref : in string; |
data : in slv16; |
iack : in slbit; |
ierr : in slbit; |
nhold : in integer) is |
variable oline : line; |
begin |
writetimestamp(oline, CLK_CYCLE, pref); |
write(oline, RB_MREQ_addr, right, 10); |
write(oline, data, right, 18); |
if nhold > 0 then |
write(oline, string'(" nhold=")); |
write(oline, nhold, right, 2); |
end if; |
if iack = '0' then |
write(oline, string'(" ACK=0")); |
end if; |
if ierr = '1' then |
write(oline, string'(" ERR=1")); |
end if; |
writeline(output, oline); |
end procedure write_data; |
|
begin |
|
-- assert c2out_setup>0 report "assert(x>0)" severity FAILURE; |
|
wait until CLK'event and CLK='1'; |
wait for c2out_time; |
|
RB_SRES_ack <= '0'; |
RB_SRES_busy <= '0'; |
RB_SRES_err <= '0'; |
RB_SRES_dout <= (others=>'1'); |
|
addr := RB_MREQ_addr; |
idout := (others=>'0'); |
nhold := 0; |
|
acc := acc_bad; |
if unsigned(addr) <= 2#00111111# then |
acc := acc_reg0; |
elsif unsigned(addr) <= 2#01111111# then |
acc := acc_reg1; |
nhold := conv_integer(unsigned(addr and "00111111")) + 1; |
elsif unsigned(addr) = 2#10000000# then |
acc := acc_mem0; |
elsif unsigned(addr) = 2#10000001# then |
acc := acc_mem1; |
elsif unsigned(addr) = 2#10000010# then |
acc := acc_lam; |
elsif unsigned(addr) = 2#11000000# then |
acc := acc_err; |
end if; |
|
iack := '1'; |
ierr := '0'; |
|
if acc = acc_bad then -- if bad address |
iack := '0'; -- don't acknowledge |
end if; |
|
RB_SRES_ack <= iack; |
|
RB_LAM(15 downto 8) <= (others=>'0'); |
|
if RB_MREQ_req = '1' then |
|
-- handle WE transactions |
if RB_MREQ_we ='1' then |
case acc is |
when acc_reg0 => |
reg0(conv_integer(unsigned(addr))) := RB_MREQ_din; |
when acc_reg1 => |
reg1(conv_integer(unsigned(addr))) := RB_MREQ_din; |
when acc_mem0 => |
ind := conv_integer(unsigned(reg0(16) and X"00ff")); |
mem0(ind) := RB_MREQ_din; |
reg0(16) := unsigned(reg0(16)) + 1; |
when acc_mem1 => |
ind := conv_integer(unsigned(reg0(17) and X"00ff")); |
mem1(ind) := RB_MREQ_din; |
reg0(17) := unsigned(reg0(17)) + 1; |
when acc_lam => |
RB_LAM(15 downto 8) <= RB_MREQ_din(15 downto 8); |
writetimestamp(oline, CLK_CYCLE, |
": targ w ap_lam(15 downto 8) pinged"); |
writeline(output, oline); |
when acc_err => |
ierr := '1'; |
when others => null; |
end case; |
|
write_data(": targ w ", RB_MREQ_din, iack, ierr, nhold); |
|
while nhold>0 and RB_MREQ_req='1' loop |
RB_SRES_busy <= '1'; |
wait for clock_period; |
nhold := nhold - 1; |
end loop; |
RB_SRES_ack <= iack; |
RB_SRES_err <= ierr; |
RB_SRES_busy <= '0'; |
|
-- handle RE transactions |
else |
case acc is |
when acc_reg0 => |
idout := reg0(conv_integer(unsigned(addr))); |
when acc_reg1 => |
idout := reg1(conv_integer(unsigned(addr))); |
when acc_mem0 => |
ind := conv_integer(unsigned(reg0(16) and X"00ff")); |
idout := mem0(ind); |
reg0(16) := unsigned(reg0(16)) + 1; |
when acc_mem1 => |
ind := conv_integer(unsigned(reg0(17) and X"00ff")); |
idout := mem1(ind); |
reg0(17) := unsigned(reg0(17)) + 1; |
when acc_err => |
ierr := '1'; |
idout := "1010101010101010"; |
when acc_bad => |
idout := "1010101010101010"; |
when others => null; |
end case; |
|
write_data(": targ r ", idout, iack, ierr, nhold); |
|
RB_SRES_dout <= "0101010101010101"; |
wait for c2out_setup; |
|
while nhold>0 and RB_MREQ_req='1' loop |
RB_SRES_busy <= '1'; |
wait for clock_period; |
nhold := nhold - 1; |
end loop; |
RB_SRES_ack <= iack; |
RB_SRES_err <= ierr; |
RB_SRES_busy <= '0'; |
|
RB_SRES_dout <= idout; |
|
end if; |
end if; |
|
-- handle INIT transactions (ext and int) (just for monitoring...) |
|
if RB_MREQ_initt = '1' then |
if RB_MREQ_we = '1' then -- ext init |
write_data(": targ i ", RB_MREQ_din, '1', '0', 0); |
reg0(18) := unsigned(reg0(18)) + 1; |
else -- int init |
write_data(": iint ", RB_MREQ_din, '1', '0', 0); |
end if; |
end if; |
|
end process proc_targ; |
|
|
end sim; |
/rri/tb/tb_rri_serport.vbom
0,0 → 1,6
# configure tb_rri with tbd_rri_serport wrapper; |
# use vhdl configure file (tb_rri_serport.vhd) to allow |
# that all configurations will co-exist in work library |
tbd_rri_gen = tbd_rri_serport.vbom |
tb_rri.vbom |
tb_rri_serport.vhd |
/rri/tb/tbw.dat
0,0 → 1,12
# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $ |
# |
[tb_rri_core] |
tb_rri_stim = tb_rri_stim.dat |
[tb_rri_serport] |
tb_rri_stim = tb_rri_stim.dat |
[tb_rritba_ttcombo] |
tb_rritba_stim = tb_rritba_ttcombo_stim.dat |
[tb_rriext_ttcombo] |
tb_rriext_fifo_rx = <fifo> |
tb_rriext_fifo_tx = <fifo> |
tb_rriext_conf = <null> |
/rri/tb/rritb_core.vhd
0,0 → 1,264
-- $Id: rritb_core.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rritb_core - sim |
-- Description: Core for a rri and cext based test bench |
-- |
-- Dependencies: simlib/simclk |
-- |
-- To test: generic, any rri/cext based target |
-- |
-- Target Devices: generic |
-- Tool versions: xst 11.4; ghdl 0.26 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-05 301 1.1.2 renamed .rpmon -> .rbmon |
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit; |
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib; |
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup |
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.simbus.all; |
use work.rritblib.all; |
use work.vhpi_rriext.all; |
|
entity rritb_core is -- core of rri/cext based test bench |
generic ( |
CLK_PERIOD : time := 20 ns; -- clock period |
CLK_OFFSET : time := 200 ns; -- clock offset (time to start clock) |
SETUP_TIME : time := 5 ns; -- setup time |
C2OUT_TIME : time := 10 ns); -- clock to output time |
port ( |
CLK : out slbit; -- main clock |
RX_DATA : out slv8; -- read data (data ext->tb) |
RX_VAL : out slbit; -- read data valid (data ext->tb) |
RX_HOLD : in slbit; -- read data hold (data ext->tb) |
TX_DATA : in slv8; -- write data (data tb->ext) |
TX_ENA : in slbit -- write data enable (data tb->ext) |
); |
end rritb_core; |
|
architecture sim of rritb_core is |
|
signal CLK_L : slbit := '0'; |
signal CLK_STOP : slbit := '0'; |
|
begin |
|
SYSCLK : simclk |
generic map ( |
PERIOD => CLK_PERIOD, |
OFFSET => CLK_OFFSET) |
port map ( |
CLK => CLK_L, |
CLK_CYCLE => SB_CLKCYCLE, |
CLK_STOP => CLK_STOP |
); |
|
CLK <= CLK_L; |
|
proc_conf: process |
file fconf : text open read_mode is "tb_rriext_conf"; |
variable iline : line; |
variable oline : line; |
variable ok : boolean; |
variable dname : string(1 to 6) := (others=>' '); |
variable ien : slbit := '0'; |
variable ibit : integer := 0; |
variable iaddr : slv8 := (others=>'0'); |
variable idata : slv16 := (others=>'0'); |
begin |
|
SB_CNTL <= (others=>'L'); |
SB_VAL <= 'L'; |
SB_ADDR <= (others=>'L'); |
SB_DATA <= (others=>'L'); |
|
file_loop: while not endfile(fconf) loop |
|
readline (fconf, iline); |
readcomment(iline, ok); |
next file_loop when ok; |
readword(iline, dname, ok); |
|
if ok then |
case dname is |
|
when ".scntl" => -- .scntl |
read_ea(iline, ibit); |
read_ea(iline, ien); |
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high) |
report "assert bit number in range of SB_CNTL" |
severity failure; |
if ien = '1' then |
SB_CNTL(ibit) <= 'H'; |
else |
SB_CNTL(ibit) <= 'L'; |
end if; |
|
when ".cpmon" => -- .cpmon |
read_ea(iline, ien); |
if ien = '1' then |
SB_CNTL(sbcntl_sbf_cpmon) <= 'H'; |
else |
SB_CNTL(sbcntl_sbf_cpmon) <= 'L'; |
end if; |
|
when ".rbmon" => -- .rbmon |
read_ea(iline, ien); |
if ien = '1' then |
SB_CNTL(sbcntl_sbf_rbmon) <= 'H'; |
else |
SB_CNTL(sbcntl_sbf_rbmon) <= 'L'; |
end if; |
|
when ".sinit" => -- .sinit |
readgen_ea(iline, iaddr, 8); |
readgen_ea(iline, idata, 8); |
SB_ADDR <= iaddr; |
SB_DATA <= idata; |
SB_VAL <= 'H'; |
wait for 0 ns; |
SB_VAL <= 'L'; |
SB_ADDR <= (others=>'L'); |
SB_DATA <= (others=>'L'); |
wait for 0 ns; |
|
when others => -- bad command |
write(oline, string'("?? unknown command: ")); |
write(oline, dname); |
writeline(output, oline); |
report "aborting" severity failure; |
end case; |
else |
report "failed to find command" severity failure; |
end if; |
|
testempty_ea(iline); |
|
end loop; -- file_loop: |
|
wait; -- halt process here |
|
end process proc_conf; |
|
proc_stim: process |
variable icycle : integer := 0; |
variable irxint : integer := 0; |
variable irxslv : slv24 := (others=>'0'); |
variable ibit : integer := 0; |
variable oline : line; |
variable r_sb_cntl : slv16 := (others=>'Z'); |
variable iaddr : slv8 := (others=>'0'); |
variable idata : slv16 := (others=>'0'); |
begin |
|
wait for CLK_OFFSET; |
wait for 10*CLK_PERIOD; |
|
stim_loop: loop |
|
wait until CLK_L'event and CLK_L='1'; |
wait for CLK_PERIOD-SETUP_TIME; |
|
SB_ADDR <= (others=>'Z'); |
SB_DATA <= (others=>'Z'); |
|
icycle := conv_integer(unsigned(SB_CLKCYCLE)); |
RX_VAL <= '0'; |
|
if RX_HOLD = '0' then |
irxint := cext_getbyte(icycle); |
if irxint >= 0 then |
if irxint <= 16#ff# then -- normal data byte |
RX_DATA <= conv_std_logic_vector(irxint, 8); |
RX_VAL <= '1'; |
elsif irxint >= 16#1000000# then -- out-of-band message |
irxslv := conv_std_logic_vector(irxint, 24); |
iaddr := irxslv(23 downto 16); |
idata := irxslv(15 downto 0); |
writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG"); |
write(oline, irxslv(23 downto 16), right, 9); |
write(oline, irxslv(15 downto 8), right, 9); |
write(oline, irxslv( 7 downto 0), right, 9); |
write(oline, string'(" : ")); |
writeoct(oline, iaddr, right, 3); |
writeoct(oline, idata, right, 7); |
writeline(output, oline); |
if unsigned(iaddr) = 0 then |
ibit := conv_integer(unsigned(idata(15 downto 8))); |
r_sb_cntl(ibit) := idata(0); |
else |
SB_ADDR <= iaddr; |
SB_DATA <= idata; |
SB_VAL <= '1'; |
wait for 0 ns; |
SB_VAL <= 'Z'; |
wait for 0 ns; |
end if; |
end if; |
elsif irxint = -1 then -- end-of-file seen |
exit stim_loop; |
else |
report "cext_getbyte error: " & integer'image(-irxint) |
severity failure; |
end if; |
end if; |
|
SB_CNTL <= r_sb_cntl; |
|
end loop; |
|
wait for 50*CLK_PERIOD; |
CLK_STOP <= '1'; |
|
writetimestamp(oline, SB_CLKCYCLE, ": DONE "); |
writeline(output, oline); |
|
wait; -- suspend proc_stim forever |
-- clock is stopped, sim will end |
|
end process proc_stim; |
|
proc_moni: process |
variable itxdata : integer := 0; |
variable itxrc : integer := 0; |
variable oline : line; |
begin |
|
loop |
wait until CLK_L'event and CLK_L='1'; |
wait for C2OUT_TIME; |
if TX_ENA = '1' then |
itxdata := conv_integer(unsigned(TX_DATA)); |
itxrc := cext_putbyte(itxdata); |
assert itxrc=0 |
report "cext_putbyte error: " & integer'image(itxrc) |
severity failure; |
end if; |
|
end loop; |
|
end process proc_moni; |
|
end sim; |
/rri/tb/tbd_rri_core.vhd
0,0 → 1,126
-- $Id: tbd_rri_core.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tbd_rri_core - syn |
-- Description: Wrapper for rri_core to avoid records. It has a port |
-- interface which will not be modified by xst synthesis |
-- (no records, no generic port). |
-- |
-- Dependencies: rri_core |
-- |
-- To test: rri_core |
-- |
-- Target Devices: generic |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2007-11-24 92 8.1.03 I27 xc3s1000-4 143 309 0 166 s 7.64 |
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 148 320 0 - t 8.34 |
-- 2007-10-27 92 9.1 J30 xc3s1000-4 148 315 0 - t 8.34 |
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 302 0 162 s 7.65 |
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 138 306 0 - s 7.64 |
-- |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-05-02 287 2.2.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT signal from interfaces |
-- 2010-04-03 274 2.2 add CP_FLUSH for rri_core, add CE_USEC |
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch |
-- name to switch core/serport |
-- 2007-07-02 63 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
|
use work.slvtypes.all; |
use work.rrilib.all; |
|
entity tbd_rri_core is -- rri_core tb design |
-- generic: ATOWIDTH=5; ITOWIDTH=6 |
-- implements tbd_rri_gen |
port ( |
CLK : in slbit; -- clock |
CE_INT : in slbit; -- rri ito time unit clock enable |
CE_USEC : in slbit; -- 1 usec clock enable |
RESET : in slbit; -- reset |
CP_DI : in slv9; -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : out slbit; -- comm port: data busy |
CP_DO : out slv9; -- comm port: data out |
CP_VAL : out slbit; -- comm port: data valid |
CP_HOLD : in slbit; -- comm port: data hold |
RB_MREQ_req : out slbit; -- rbus: request - req |
RB_MREQ_we : out slbit; -- rbus: request - we |
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll |
RB_MREQ_addr : out slv8; -- rbus: request - addr |
RB_MREQ_din : out slv16; -- rbus: request - din |
RB_SRES_ack : in slbit; -- rbus: response - ack |
RB_SRES_busy : in slbit; -- rbus: response - busy |
RB_SRES_err : in slbit; -- rbus: response - err |
RB_SRES_dout : in slv16; -- rbus: response - dout |
RB_LAM : in slv16; -- rbus: look at me |
RB_STAT : in slv3; -- rbus: status flags |
TXRXACT : out slbit -- txrx active flag |
); |
end entity tbd_rri_core; |
|
|
architecture syn of tbd_rri_core is |
|
signal CP_FLUSH : slbit := '0'; |
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
|
begin |
|
RB_MREQ_req <= RB_MREQ.req; |
RB_MREQ_we <= RB_MREQ.we; |
RB_MREQ_initt<= RB_MREQ.init; |
RB_MREQ_addr <= RB_MREQ.addr; |
RB_MREQ_din <= RB_MREQ.din; |
|
RB_SRES.ack <= RB_SRES_ack; |
RB_SRES.busy <= RB_SRES_busy; |
RB_SRES.err <= RB_SRES_err; |
RB_SRES.dout <= RB_SRES_dout; |
|
UUT : rri_core |
generic map ( |
ATOWIDTH => 5, |
ITOWIDTH => 6) |
port map ( |
CLK => CLK, |
CE_INT => CE_INT, |
RESET => RESET, |
CP_DI => CP_DI, |
CP_ENA => CP_ENA, |
CP_BUSY => CP_BUSY, |
CP_DO => CP_DO, |
CP_VAL => CP_VAL, |
CP_HOLD => CP_HOLD, |
CP_FLUSH => CP_FLUSH, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT |
); |
|
TXRXACT <= '0'; |
|
end syn; |
/rri/tb/.cvsignore
0,0 → 1,19
tb_rri_stim |
tb_rri_core |
tb_rri_core_[sft]sim |
tb_rri_core_ISim |
tb_rri_core_ISim_[sft]sim |
tb_rri_serport |
tb_rri_serport_[sft]sim |
tb_rri_serport_ISim |
tb_rri_serport_ISim_[sft]sim |
tb_rritba_stim |
tb_rritba_ttcombo |
tb_rritba_ttcombo_[sft]sim |
tb_rritba_ttcombo_ISim |
tb_rritba_ttcombo_ISim_[sft]sim |
tb_rriext_ttcombo |
tb_rriext_ttcombo_[sft]sim |
tb_rriext_fifo_rx |
tb_rriext_fifo_tx |
tb_rriext_conf |
/rri/tb/Makefile
0,0 → 1,35
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2009-11-21 252 1.2 add ISim support |
# 2007-11-03 95 1.1.2 use .log rather .dat output in check_dsim |
# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl |
# 2007-06-29 61 1.1 add clean and all |
# 2007-06-10 51 1.0 Initial version |
# |
EXE_all = tb_rri_core tb_rri_serport \ |
tb_rritba_ttcombo tb_rriext_ttcombo |
# |
# |
.phony : all all_ssim all_tsim clean |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
all_tsim : $(EXE_all:=_tsim) |
# |
clean : ise_clean ghdl_clean isim_clean |
# |
#----- |
# |
include $(RETROBASE)/rtl/vlib/Makefile.ghdl |
include $(RETROBASE)/rtl/vlib/Makefile.isim |
include $(RETROBASE)/rtl/vlib/Makefile.xflow |
# |
VBOM_all = $(wildcard *.vbom) |
# |
include $(VBOM_all:.vbom=.dep_xst) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_isim) |
include $(wildcard *.o.dep_ghdl) |
# |
/rri/tb/rritb_rbmon.vbom
0,0 → 1,7
# libs |
../../slvtypes.vhd |
../../simlib/simlib.vhd |
../rrilib.vhd |
# components |
# design |
rritb_rbmon.vhd |
/rri/tb/rritb_rbmon_sb.vhd
0,0 → 1,80
-- $Id: rritb_rbmon_sb.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rritb_rbmon_sb - sim |
-- Description: rritb: rri reg port monitor; simbus wrapper |
-- |
-- Dependencies: simbus |
-- Test bench: - |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon |
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT signal from interfaces |
-- use sbcntl_sbf_cpmon def |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2007-12-23 105 1.2 added AP_LAM display |
-- 2007-11-24 98 1.1 added RP_IINT support |
-- 2007-08-27 76 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.simbus.all; |
use work.rrilib.all; |
use work.rritblib.all; |
|
entity rritb_rbmon_sb is -- simbus wrap for rri rbus monitor |
generic ( |
DBASE : positive := 2; -- base for writing data values |
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv3 -- rbus: status flags |
); |
end rritb_rbmon_sb; |
|
|
architecture sim of rritb_rbmon_sb is |
|
signal ENA : slbit := '0'; |
|
begin |
|
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high |
report "assert(ENAPIN in SB_CNTL'range)" severity failure; |
|
ENA <= to_x01(SB_CNTL(ENAPIN)); |
|
RBMON : rritb_rbmon |
generic map ( |
DBASE => DBASE) |
port map ( |
CLK => CLK, |
CLK_CYCLE => SB_CLKCYCLE, |
ENA => ENA, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT |
); |
|
end sim; |
/rri/tb/vhpi_rriext.vhd
0,0 → 1,55
-- $Id: vhpi_rriext.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: vhpi_rriext |
-- Description: VHDL procedural interface: VHDL declaration side |
-- |
-- Dependencies: - |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2007-08-26 76 1.0 Initial version |
------------------------------------------------------------------------------ |
|
package vhpi_rriext is |
|
impure function cext_getbyte ( |
clk : integer) -- clock cycle |
return integer; |
attribute foreign of cext_getbyte : function is "VHPIDIRECT cext_getbyte"; |
|
impure function cext_putbyte ( |
dat : integer) -- data byte |
return integer; |
attribute foreign of cext_putbyte : function is "VHPIDIRECT cext_putbyte"; |
|
end vhpi_rriext; |
|
package body vhpi_rriext is |
|
impure function cext_getbyte ( |
clk : integer) -- clock cycle |
return integer is |
begin |
report "cext_getbyte not vhpi'ed" severity failure; |
end cext_getbyte; |
|
impure function cext_putbyte ( |
dat : integer) -- data byte |
return integer is |
begin |
report "cext_getbyte not vhpi'ed" severity failure; |
end cext_putbyte; |
|
end vhpi_rriext; |
/rri/tb/tbd_rri_serport.vhd
0,0 → 1,246
-- $Id: tbd_rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tbd_rri_serport - syn |
-- Description: Wrapper for rri_core plus rri_serport with an interface |
-- compatible to the rri_core only module. |
-- NOTE: this implementation is a hack, should be redone |
-- using configurations. |
-- |
-- Dependencies: tbu_rri_serport [UUT] |
-- serport_uart_tx |
-- serport_uart_rx |
-- byte2cdata |
-- cdata2byte |
-- |
-- To test: rri_serport |
-- |
-- Target Devices: generic |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas) |
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT signal from interfaces |
-- 2010-04-24 281 2.2.1 use serport_uart_[tr]x directly again |
-- 2010-04-03 274 2.2 add CE_USEC |
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2007-11-25 98 1.1 added RP_IINT support; use entity rather arch |
-- name to switch core/serport; |
-- use serport_uart_[tr]x_tb to allow that UUT is a |
-- [sft]sim model compiled with keep hierarchy |
-- 2007-07-02 63 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
-- synthesis translate_off |
use ieee.std_logic_textio.all; |
use std.textio.all; |
-- synthesis translate_on |
|
use work.slvtypes.all; |
use work.rrilib.all; |
use work.comlib.all; |
use work.serport.all; |
|
entity tbd_rri_serport is -- rri_core+rri_serport tb design |
-- implements tbd_rri_gen |
port ( |
CLK : in slbit; -- clock |
CE_INT : in slbit; -- rri ito time unit clock enable |
CE_USEC : in slbit; -- 1 usec clock enable |
RESET : in slbit; -- reset |
CP_DI : in slv9; -- comm port: data in |
CP_ENA : in slbit; -- comm port: data enable |
CP_BUSY : out slbit; -- comm port: data busy |
CP_DO : out slv9; -- comm port: data out |
CP_VAL : out slbit; -- comm port: data valid |
CP_HOLD : in slbit; -- comm port: data hold |
RB_MREQ_req : out slbit; -- rbus: request - req |
RB_MREQ_we : out slbit; -- rbus: request - we |
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll |
RB_MREQ_addr : out slv8; -- rbus: request - addr |
RB_MREQ_din : out slv16; -- rbus: request - din |
RB_SRES_ack : in slbit; -- rbus: response - ack |
RB_SRES_busy : in slbit; -- rbus: response - busy |
RB_SRES_err : in slbit; -- rbus: response - err |
RB_SRES_dout : in slv16; -- rbus: response - dout |
RB_LAM : in slv16; -- rbus: look at me |
RB_STAT : in slv3; -- rbus: status flags |
TXRXACT : out slbit -- txrx active flag |
); |
end entity tbd_rri_serport; |
|
|
architecture syn of tbd_rri_serport is |
|
signal RRI_RXSD : slbit := '0'; |
signal RRI_TXSD : slbit := '0'; |
signal RXDATA : slv8 := (others=>'0'); |
signal RXVAL : slbit := '0'; |
signal RXACT : slbit := '0'; |
signal TXDATA : slv8 := (others=>'0'); |
signal TXENA : slbit := '0'; |
signal TXBUSY : slbit := '0'; |
signal CLKDIV : slv13 := conv_std_logic_vector(1,13); |
-- NOTE: change also CDINIT in tbu_rri_serport !! |
|
component tbu_rri_serport is -- rri core+serport combo |
port ( |
CLK : in slbit; -- clock |
CE_INT : in slbit; -- rri ito time unit clock enable |
CE_USEC : in slbit; -- 1 usec clock enable |
CE_MSEC : in slbit; -- 1 msec clock enable |
RESET : in slbit; -- reset |
RXSD : in slbit; -- receive serial data (uart view) |
TXSD : out slbit; -- transmit serial data (uart view) |
RB_MREQ_req : out slbit; -- rbus: request - req |
RB_MREQ_we : out slbit; -- rbus: request - we |
RB_MREQ_initt : out slbit; -- rbus: request - init; avoid name coll |
RB_MREQ_addr : out slv8; -- rbus: request - addr |
RB_MREQ_din : out slv16; -- rbus: request - din |
RB_SRES_ack : in slbit; -- rbus: response - ack |
RB_SRES_busy : in slbit; -- rbus: response - busy |
RB_SRES_err : in slbit; -- rbus: response - err |
RB_SRES_dout : in slv16; -- rbus: response - dout |
RB_LAM : in slv16; -- rbus: look at me |
RB_STAT : in slv3 -- rbus: status flags |
); |
end component; |
|
constant CPREF : slv4 := "1000"; |
constant NCOMM : positive := 4; |
|
begin |
|
UUT : tbu_rri_serport |
port map ( |
CLK => CLK, |
CE_INT => CE_INT, |
CE_USEC => CE_USEC, |
CE_MSEC => '1', |
RESET => RESET, |
RXSD => RRI_RXSD, |
TXSD => RRI_TXSD, |
RB_MREQ_req => RB_MREQ_req, |
RB_MREQ_we => RB_MREQ_we, |
RB_MREQ_initt=> RB_MREQ_initt, |
RB_MREQ_addr => RB_MREQ_addr, |
RB_MREQ_din => RB_MREQ_din, |
RB_SRES_ack => RB_SRES_ack, |
RB_SRES_busy => RB_SRES_busy, |
RB_SRES_err => RB_SRES_err, |
RB_SRES_dout => RB_SRES_dout, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT |
); |
|
UARTRX : serport_uart_rx |
generic map ( |
CDWIDTH => 13) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CLKDIV => CLKDIV, |
RXSD => RRI_TXSD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => open, |
RXACT => RXACT |
); |
|
UARTTX : serport_uart_tx |
generic map ( |
CDWIDTH => 13) |
port map ( |
CLK => CLK, |
RESET => RESET, |
CLKDIV => CLKDIV, |
TXSD => RRI_RXSD, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY |
); |
|
TXRXACT <= RXACT or TXBUSY; |
|
B2CD : byte2cdata -- byte stream -> 9bit comma,data |
generic map ( |
CPREF => CPREF, |
NCOMM => NCOMM) |
port map ( |
CLK => CLK, |
RESET => RESET, |
DI => RXDATA, |
ENA => RXVAL, |
BUSY => open, |
DO => CP_DO, |
VAL => CP_VAL, |
HOLD => CP_HOLD |
); |
|
CD2B : cdata2byte -- 9bit comma,data -> byte stream |
generic map ( |
CPREF => CPREF, |
NCOMM => NCOMM) |
port map ( |
CLK => CLK, |
RESET => RESET, |
DI => CP_DI, |
ENA => CP_ENA, |
BUSY => CP_BUSY, |
DO => TXDATA, |
VAL => TXENA, |
HOLD => TXBUSY |
); |
|
-- synthesis translate_off |
proc_moni: process |
variable oline : line; |
constant c2out_time : time := 10 ns; -- FIXME - this isn't modular !!! |
|
begin |
|
loop |
wait until CLK'event and CLK='1'; |
wait for c2out_time; |
|
if TXENA='1' and TXBUSY='0' then |
write(oline, now, right, 12); |
write(oline, string'(" ")); |
write(oline, string'(": tx ")); |
write(oline, string'(" ")); |
write(oline, TXDATA, right, 9); |
writeline(output, oline); |
end if; |
|
if RXVAL = '1' then |
write(oline, now, right, 12); |
write(oline, string'(" ")); |
write(oline, string'(": rx ")); |
write(oline, string'(" ")); |
write(oline, RXDATA, right, 9); |
writeline(output, oline); |
end if; |
|
end loop; |
|
end process proc_moni; |
-- synthesis translate_on |
|
|
end syn; |
/rri/tb/tb_rri.vbom
0,0 → 1,17
# Not meant for direct top level usage. Used with |
# tb_rri_(core|serport|...)[_ssim].vbom and config |
# lines to generate the different cases. |
# |
# libs |
../../slvtypes.vhd |
../../genlib/genlib.vhd |
../../comlib/comlib.vhd |
../rrilib.vhd |
../../simlib/simlib.vhd |
# components |
../../simlib/simclk.vbom |
../../genlib/clkdivce.vbom |
tbd_rri_gen : tbd_rri_core.vbom |
# design |
tb_rri.vhd |
@top:tb_rri |
/rri/tb/tbu_rri_serport.vbom
0,0 → 1,8
# libs |
../../slvtypes.vhd |
../rrilib.vhd |
# components |
../rri_core.vbom |
../rri_serport.vbom |
# design |
tbu_rri_serport.vhd |
/rri/tb/tbd_rri_core.vbom
0,0 → 1,7
# libs |
../../slvtypes.vhd |
../rrilib.vhd |
# components |
../rri_core.vbom |
# design |
tbd_rri_core.vhd |
/rri/tb/rritb_cpmon_sb.vbom
0,0 → 1,9
# libs |
../../slvtypes.vhd |
../../simlib/simlib.vhd |
../../simlib/simbus.vhd |
rritblib.vhd |
# components |
rritb_cpmon.vbom |
# design |
rritb_cpmon_sb.vhd |
/rri/tb/tbu_rri_serport.vhd
0,0 → 1,150
-- $Id: tbu_rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tbu_rri_serport - syn |
-- Description: Wrapper for rri_core plus rri_serport to avoid records. It |
-- has a port interface which will not be modified by xst |
-- synthesis (no records, no generic port). |
-- |
-- Dependencies: rri_core |
-- rri_serport |
-- |
-- To test: rri_serport |
-- |
-- Target Devices: generic |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-04-03 274 11.4 L68 xc3s1000-4 278 588 18 366 s 9.83 |
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 273 547 18 - t 9.65 |
-- 2007-10-27 92 9.1 J30 xc3s1000-4 273 545 18 - t 9.65 |
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 283 594 18 323 s 10.3 |
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 285 596 18 - s 9.32 |
-- |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-03 300 2.2.3 use default FAWIDTH for rri_core_serport |
-- 2010-05-02 287 2.2.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT from interfaces; drop RTSFLUSH generic |
-- 2010-04-18 279 2.2.1 drop RTSFBUF generic for rri_serport |
-- 2010-04-03 274 2.2 add CP_FLUSH, add rri_serport handshake logic |
-- 2009-03-14 197 2.1 remove records in interface to allow _ssim usage |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2007-11-24 98 1.1 added RP_IINT support |
-- 2007-07-02 63 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
|
use work.slvtypes.all; |
use work.rrilib.all; |
|
entity tbu_rri_serport is -- rri core+serport combo |
port ( |
CLK : in slbit; -- clock |
CE_INT : in slbit; -- rri ito time unit clock enable |
CE_USEC : in slbit; -- 1 usec clock enable |
CE_MSEC : in slbit; -- 1 msec clock enable |
RESET : in slbit; -- reset |
RXSD : in slbit; -- receive serial data (board view) |
TXSD : out slbit; -- transmit serial data (board view) |
RB_MREQ_req : out slbit; -- rbus: request - req |
RB_MREQ_we : out slbit; -- rbus: request - we |
RB_MREQ_initt: out slbit; -- rbus: request - init; avoid name coll |
RB_MREQ_addr : out slv8; -- rbus: request - addr |
RB_MREQ_din : out slv16; -- rbus: request - din |
RB_SRES_ack : in slbit; -- rbus: response - ack |
RB_SRES_busy : in slbit; -- rbus: response - busy |
RB_SRES_err : in slbit; -- rbus: response - err |
RB_SRES_dout : in slv16; -- rbus: response - dout |
RB_LAM : in slv16; -- rbus: look at me |
RB_STAT : in slv3 -- rbus: status flags |
); |
end entity tbu_rri_serport; |
|
|
architecture syn of tbu_rri_serport is |
|
signal RB_MREQ : rb_mreq_type := rb_mreq_init; |
signal RB_SRES : rb_sres_type := rb_sres_init; |
|
signal CTS_N : slbit := '0'; |
signal RTS_N : slbit := '0'; |
|
signal CP_DI : slv9 := (others=>'0'); |
signal CP_ENA : slbit := '0'; |
signal CP_BUSY : slbit := '0'; |
signal CP_DO : slv9 := (others=>'0'); |
signal CP_VAL : slbit := '0'; |
signal CP_HOLD : slbit := '0'; |
signal CP_FLUSH : slbit := '0'; |
|
begin |
|
RB_MREQ_req <= RB_MREQ.req; |
RB_MREQ_we <= RB_MREQ.we; |
RB_MREQ_initt<= RB_MREQ.init; |
RB_MREQ_addr <= RB_MREQ.addr; |
RB_MREQ_din <= RB_MREQ.din; |
|
RB_SRES.ack <= RB_SRES_ack; |
RB_SRES.busy <= RB_SRES_busy; |
RB_SRES.err <= RB_SRES_err; |
RB_SRES.dout <= RB_SRES_dout; |
|
CORE : rri_core |
port map ( |
CLK => CLK, |
CE_INT => CE_INT, |
RESET => RESET, |
CP_DI => CP_DI, |
CP_ENA => CP_ENA, |
CP_BUSY => CP_BUSY, |
CP_DO => CP_DO, |
CP_VAL => CP_VAL, |
CP_HOLD => CP_HOLD, |
CP_FLUSH => CP_FLUSH, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT |
); |
|
SERPORT : rri_serport |
generic map ( |
CPREF => "1000", |
CDWIDTH => 13, |
CDINIT => 1) -- NOTE: change also CLKDIV in tbd_rri_serport !! |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC, |
RESET => RESET, |
RXSD => RXSD, |
TXSD => TXSD, |
CTS_N => CTS_N, |
RTS_N => RTS_N, |
CP_DI => CP_DI, |
CP_ENA => CP_ENA, |
CP_BUSY => CP_BUSY, |
CP_DO => CP_DO, |
CP_VAL => CP_VAL, |
CP_HOLD => CP_HOLD, |
CP_FLUSH => CP_FLUSH |
); |
|
end syn; |
/rri/tb/tbd_rri_serport.vbom
0,0 → 1,13
# libs |
../../slvtypes.vhd |
../../comlib/comlib.vhd |
../../serport/serport.vhd |
../rrilib.vhd |
# components |
tbu_rri_serport : tbu_rri_serport.vbom |
../../serport/serport_uart_tx.vbom |
../../serport/serport_uart_rx.vbom |
../../comlib/byte2cdata.vbom |
../../comlib/cdata2byte.vbom |
# design |
tbd_rri_serport.vhd |
/rri/tb/rritb_rbmon_sb.vbom
0,0 → 1,10
# libs |
../../slvtypes.vhd |
../../simlib/simlib.vhd |
../../simlib/simbus.vhd |
../rrilib.vhd |
rritblib.vhd |
# components |
rritb_rbmon.vbom |
# design |
rritb_rbmon_sb.vhd |
/rri/tb/rritb_sres_or_mon.vhd
0,0 → 1,108
-- $Id: rritb_sres_or_mon.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rritb_sres_or_mon - sim |
-- Description: rribus result or monitor |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Tool versions: ghdl 0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-06-26 309 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.rrilib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity rritb_sres_or_mon is -- rribus result or monitor |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4 |
); |
end rritb_sres_or_mon; |
|
architecture sim of rritb_sres_or_mon is |
|
begin |
|
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, RB_SRES_4) |
constant dzero : slv16 := (others=>'0'); |
variable oline : line; |
variable nack : integer := 0; |
variable nbusy : integer := 0; |
variable nerr : integer := 0; |
variable ndout : integer := 0; |
begin |
|
nack := 0; |
nbusy := 0; |
nerr := 0; |
ndout := 0; |
|
if RB_SRES_1.ack /= '0' then nack := nack + 1; end if; |
if RB_SRES_2.ack /= '0' then nack := nack + 1; end if; |
if RB_SRES_3.ack /= '0' then nack := nack + 1; end if; |
if RB_SRES_4.ack /= '0' then nack := nack + 1; end if; |
|
if RB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if; |
if RB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if; |
if RB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if; |
if RB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if; |
|
if RB_SRES_1.err /= '0' then nerr := nerr + 1; end if; |
if RB_SRES_2.err /= '0' then nerr := nerr + 1; end if; |
if RB_SRES_3.err /= '0' then nerr := nerr + 1; end if; |
if RB_SRES_4.err /= '0' then nerr := nerr + 1; end if; |
|
if RB_SRES_1.dout /= dzero then ndout := ndout + 1; end if; |
if RB_SRES_2.dout /= dzero then ndout := ndout + 1; end if; |
if RB_SRES_3.dout /= dzero then ndout := ndout + 1; end if; |
if RB_SRES_4.dout /= dzero then ndout := ndout + 1; end if; |
|
if nack>1 or nbusy>1 or nerr>1 or ndout>1 then |
write(oline, now, right, 12); |
if nack > 1 then |
write(oline, string'(" #ack=")); |
write(oline, nack); |
end if; |
if nbusy > 1 then |
write(oline, string'(" #busy=")); |
write(oline, nbusy); |
end if; |
if nerr > 1 then |
write(oline, string'(" #err=")); |
write(oline, nerr); |
end if; |
if ndout > 1 then |
write(oline, string'(" #dout=")); |
write(oline, ndout); |
end if; |
write(oline, string'(" FAIL in ")); |
write(oline, rritb_sres_or_mon'path_name); |
writeline(output, oline); |
end if; |
|
end process proc_comb; |
|
end sim; |
/rri/tb/tb_rri_core.vhd
0,0 → 1,44
-- $Id: tb_rri_core.vhd 314 2010-07-09 17:38:41Z mueller $ |
-- |
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tb_rri_core |
-- Description: Configuration for tb_rri_core for tb_rri. |
-- |
-- Dependencies: tbd_rri_gen |
-- |
-- To test: rri_core |
-- |
-- Target Devices: generic |
-- |
-- Verified (with tb_rri_stim.dat): |
-- Date Rev Code ghdl ise Target Comment |
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok |
-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok |
-- 2007-10-12 88 - 0.26 - - c:ok |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2007-11-25 98 1.0.1 use entity rather arch name to switch core/serport |
-- 2007-07-08 65 1.0 Initial version |
------------------------------------------------------------------------------ |
|
configuration tb_rri_core of tb_rri is |
|
for sim |
for all : tbd_rri_gen |
use entity work.tbd_rri_core; |
end for; |
end for; |
|
end tb_rri_core; |
rri/tb
Property changes :
Added: svn:ignore
## -0,0 +1,51 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_rri_stim
+tb_rri_core
+tb_rri_core_[sft]sim
+tb_rri_core_ISim
+tb_rri_core_ISim_[sft]sim
+tb_rri_serport
+tb_rri_serport_[sft]sim
+tb_rri_serport_ISim
+tb_rri_serport_ISim_[sft]sim
+tb_rritba_stim
+tb_rritba_ttcombo
+tb_rritba_ttcombo_[sft]sim
+tb_rritba_ttcombo_ISim
+tb_rritba_ttcombo_ISim_[sft]sim
+tb_rriext_ttcombo
+tb_rriext_ttcombo_[sft]sim
+tb_rriext_fifo_rx
+tb_rriext_fifo_tx
+tb_rriext_conf
Index: rri/rb_sres_or_2.vhd
===================================================================
--- rri/rb_sres_or_2.vhd (nonexistent)
+++ rri/rb_sres_or_2.vhd (revision 7)
@@ -0,0 +1,76 @@
+-- $Id: rb_sres_or_2.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2008-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: rb_sres_or_2 - syn
+-- Description: rribus result or, 2 input
+--
+-- Dependencies: rritb_sres_or_mon [sim only]
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-26 309 1.1 add rritb_sres_or_mon
+-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
+-- 2008-01-20 113 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.rrilib.all;
+-- synthesis translate_off
+use work.rritblib.all;
+-- synthesis translate_on
+
+-- ----------------------------------------------------------------------------
+
+entity rb_sres_or_2 is -- rribus result or, 2 input
+ port (
+ RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
+ RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
+ RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
+ );
+end rb_sres_or_2;
+
+architecture syn of rb_sres_or_2 is
+
+begin
+
+ proc_comb : process (RB_SRES_1, RB_SRES_2)
+ begin
+
+ RB_SRES_OR.ack <= RB_SRES_1.ack or
+ RB_SRES_2.ack;
+ RB_SRES_OR.busy <= RB_SRES_1.busy or
+ RB_SRES_2.busy;
+ RB_SRES_OR.err <= RB_SRES_1.err or
+ RB_SRES_2.err;
+ RB_SRES_OR.dout <= RB_SRES_1.dout or
+ RB_SRES_2.dout;
+
+ end process proc_comb;
+
+-- synthesis translate_off
+ ORMON : rritb_sres_or_mon
+ port map (
+ RB_SRES_1 => RB_SRES_1,
+ RB_SRES_2 => RB_SRES_2,
+ RB_SRES_3 => rb_sres_init,
+ RB_SRES_4 => rb_sres_init
+ );
+-- synthesis translate_on
+
+end syn;
Index: rri/rb_sres_or_3.vhd
===================================================================
--- rri/rb_sres_or_3.vhd (nonexistent)
+++ rri/rb_sres_or_3.vhd (revision 7)
@@ -0,0 +1,81 @@
+-- $Id: rb_sres_or_3.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2008-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: rb_sres_or_3 - syn
+-- Description: rribus result or, 3 input
+--
+-- Dependencies: rritb_sres_or_mon [sim only]
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-26 309 1.1 add rritb_sres_or_mon
+-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
+-- 2008-01-20 113 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.rrilib.all;
+-- synthesis translate_off
+use work.rritblib.all;
+-- synthesis translate_on
+
+-- ----------------------------------------------------------------------------
+
+entity rb_sres_or_3 is -- rribus result or, 3 input
+ port (
+ RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
+ RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
+ RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
+ RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
+ );
+end rb_sres_or_3;
+
+architecture syn of rb_sres_or_3 is
+
+begin
+
+ proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3)
+ begin
+
+ RB_SRES_OR.ack <= RB_SRES_1.ack or
+ RB_SRES_2.ack or
+ RB_SRES_3.ack;
+ RB_SRES_OR.busy <= RB_SRES_1.busy or
+ RB_SRES_2.busy or
+ RB_SRES_3.busy;
+ RB_SRES_OR.err <= RB_SRES_1.err or
+ RB_SRES_2.err or
+ RB_SRES_3.err;
+ RB_SRES_OR.dout <= RB_SRES_1.dout or
+ RB_SRES_2.dout or
+ RB_SRES_3.dout;
+
+ end process proc_comb;
+
+-- synthesis translate_off
+ ORMON : rritb_sres_or_mon
+ port map (
+ RB_SRES_1 => RB_SRES_1,
+ RB_SRES_2 => RB_SRES_2,
+ RB_SRES_3 => RB_SRES_3,
+ RB_SRES_4 => rb_sres_init
+ );
+-- synthesis translate_on
+
+end syn;
Index: rri/rri_core_serport.vhd
===================================================================
--- rri/rri_core_serport.vhd (nonexistent)
+++ rri/rri_core_serport.vhd (revision 7)
@@ -0,0 +1,170 @@
+-- $Id: rri_core_serport.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: rri_core_serport - syn
+-- Description: rri: core + serport combo, with cpmon and rbmon
+--
+-- Dependencies: rri_serport
+-- rri_core
+-- rritb_cpmon_sb [sim only]
+-- rritb_rbmon_sb [sim only]
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 11.4; ghdl 0.26
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-04-03 275 11.4 L68 xc3s1000-4 280 600 18 375 s 9.8
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-05 301 1.2.2 renamed _rpmon -> _rbmon
+-- 2010-06-03 300 1.2.1 use FAWIDTH=5
+-- 2010-05-02 287 1.2 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
+-- drop RP_IINT from interfaces; drop RTSFLUSH generic
+-- 2010-04-18 279 1.1 drop RTSFBUF generic
+-- 2010-04-10 275 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.rrilib.all;
+-- synthesis translate_off
+use work.rritblib.all;
+-- synthesis translate_on
+
+entity rri_core_serport is -- rri, core+serport with cpmon+rbmon
+ generic (
+ ATOWIDTH : positive := 5; -- access timeout counter width
+ ITOWIDTH : positive := 6; -- idle timeout counter width
+ FAWIDTH : positive := 5; -- rx fifo address port width
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT : natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_USEC : in slbit; -- 1 usec clock enable
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ CE_INT : in slbit := '0'; -- rri ito time unit clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (board view)
+ TXSD : out slbit; -- transmit serial data (board view)
+ CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
+ RTS_N : out slbit; -- request to send (act.low, board view)
+ RB_MREQ : out rb_mreq_type; -- rbus: request
+ RB_SRES : in rb_sres_type; -- rbus: response
+ RB_LAM : in slv16; -- rbus: look at me
+ RB_STAT : in slv3 -- rbus: status flags
+ );
+end entity rri_core_serport;
+
+
+architecture syn of rri_core_serport is
+
+ signal CP_DI : slv9 := (others=>'0');
+ signal CP_ENA : slbit := '0';
+ signal CP_BUSY : slbit := '0';
+ signal CP_DO : slv9 := (others=>'0');
+ signal CP_VAL : slbit := '0';
+ signal CP_HOLD : slbit := '0';
+ signal CP_FLUSH : slbit := '0';
+
+ signal RB_MREQ_L : rb_mreq_type := rb_mreq_init; -- local, readable RB_MREQ
+
+begin
+
+ SER2RRI : rri_serport
+ generic map (
+ CPREF => "1000",
+ FAWIDTH => FAWIDTH,
+ CDWIDTH => CDWIDTH,
+ CDINIT => CDINIT)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ RESET => RESET,
+ RXSD => RXSD,
+ TXSD => TXSD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ CP_DI => CP_DI,
+ CP_ENA => CP_ENA,
+ CP_BUSY => CP_BUSY,
+ CP_DO => CP_DO,
+ CP_VAL => CP_VAL,
+ CP_HOLD => CP_HOLD,
+ CP_FLUSH => CP_FLUSH
+ );
+
+ RRI : rri_core
+ generic map (
+ ATOWIDTH => ATOWIDTH,
+ ITOWIDTH => ITOWIDTH)
+ port map (
+ CLK => CLK,
+ CE_INT => CE_INT,
+ RESET => RESET,
+ CP_DI => CP_DI,
+ CP_ENA => CP_ENA,
+ CP_BUSY => CP_BUSY,
+ CP_DO => CP_DO,
+ CP_VAL => CP_VAL,
+ CP_HOLD => CP_HOLD,
+ CP_FLUSH => CP_FLUSH,
+ RB_MREQ => RB_MREQ_L,
+ RB_SRES => RB_SRES,
+ RB_LAM => RB_LAM,
+ RB_STAT => RB_STAT
+ );
+
+ -- vhdl'93 unfortunately doesn't allow to read a signal bound to an out port
+ -- because RB_MREQ is read by the monitors, an extra internal
+ -- signal must be used. This will not be needed with vhdl'2000 anymore
+
+ RB_MREQ <= RB_MREQ_L;
+
+-- synthesis translate_off
+ CPMON : rritb_cpmon_sb
+ generic map (
+ DWIDTH => CP_DI'length,
+ ENAPIN => 15)
+ port map (
+ CLK => CLK,
+ CP_DI => CP_DI,
+ CP_ENA => CP_ENA,
+ CP_BUSY => CP_BUSY,
+ CP_DO => CP_DO,
+ CP_VAL => CP_VAL,
+ CP_HOLD => CP_HOLD
+ );
+
+ RBMON : rritb_rbmon_sb
+ generic map (
+ DBASE => 8,
+ ENAPIN => 14)
+ port map (
+ CLK => CLK,
+ RB_MREQ => RB_MREQ_L,
+ RB_SRES => RB_SRES,
+ RB_LAM => RB_LAM,
+ RB_STAT => RB_STAT
+ );
+-- synthesis translate_on
+
+end syn;
Index: rri/rb_sres_or_2.vbom
===================================================================
--- rri/rb_sres_or_2.vbom (nonexistent)
+++ rri/rb_sres_or_2.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../slvtypes.vhd
+rrilib.vhd
+[ghdl,isim]tb/rritblib.vhd
+# components
+[ghdl,isim]tb/rritb_sres_or_mon.vbom
+# design
+rb_sres_or_2.vhd
Index: rri/rb_sres_or_3.vbom
===================================================================
--- rri/rb_sres_or_3.vbom (nonexistent)
+++ rri/rb_sres_or_3.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../slvtypes.vhd
+rrilib.vhd
+[ghdl,isim]tb/rritblib.vhd
+# components
+[ghdl,isim]tb/rritb_sres_or_mon.vbom
+# design
+rb_sres_or_3.vhd
Index: rri/rrilib.vhd
===================================================================
--- rri/rrilib.vhd (nonexistent)
+++ rri/rrilib.vhd (revision 7)
@@ -0,0 +1,259 @@
+-- $Id: rrilib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: rrilib
+-- Description: Remote Register Interface components
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
+-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
+-- 2010-06-03 300 2.1.5 use FAWIDTH=5 for rri_serport
+-- 2010-05-02 287 2.1.4 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
+-- drop RP_IINT from interfaces; drop RTSFLUSH generic
+-- 2010-05-01 285 2.1.3 remove rri_rb_rpcompat, now obsolete
+-- 2010-04-18 279 2.1.2 rri_core_serport: drop RTSFBUF generic
+-- 2010-04-10 275 2.1.1 add rri_core_serport
+-- 2010-04-03 274 2.1 add CP_FLUSH for rri_core, rri_serport;
+-- CE_USEC, RTSFLUSH, CTS_N, RTS_N for rri_serport
+-- 2008-08-24 162 2.0 all with new rb_mreq/rb_sres interface
+-- 2008-08-22 161 1.3 renamed rri_rbres_ -> rb_sres_; drop rri_[24]rp
+-- 2008-02-16 116 1.2.1 added rri_wreg(rw|w|r)_3
+-- 2008-01-20 113 1.2 added rb_[mreq|sres]; _rbres_or_*; _rb_rpcompat
+-- 2007-11-24 98 1.1 added RP_IINT for rri_core.
+-- 2007-09-09 81 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package rrilib is
+
+constant c_rri_dat_idle : slv9 := "100000000";
+constant c_rri_dat_sop : slv9 := "100000001";
+constant c_rri_dat_eop : slv9 := "100000010";
+constant c_rri_dat_nak : slv9 := "100000011";
+constant c_rri_dat_attn : slv9 := "100000100";
+
+constant c_rri_cmd_rreg : slv3 := "000";
+constant c_rri_cmd_rblk : slv3 := "001";
+constant c_rri_cmd_wreg : slv3 := "010";
+constant c_rri_cmd_wblk : slv3 := "011";
+constant c_rri_cmd_stat : slv3 := "100";
+constant c_rri_cmd_attn : slv3 := "101";
+constant c_rri_cmd_init : slv3 := "110";
+
+constant c_rri_iint_rbf_anena: integer := 15; -- anena flag
+constant c_rri_iint_rbf_itoena: integer := 14; -- itoena flag
+subtype c_rri_iint_rbf_itoval is integer range 7 downto 0; -- command code
+
+subtype c_rri_cmd_rbf_seq is integer range 7 downto 3; -- sequence number
+subtype c_rri_cmd_rbf_code is integer range 2 downto 0; -- command code
+
+subtype c_rri_stat_rbf_stat is integer range 7 downto 5; -- ext status bits
+constant c_rri_stat_rbf_attn: integer := 4; -- attention flags set
+constant c_rri_stat_rbf_ccrc: integer := 3; -- command crc error
+constant c_rri_stat_rbf_dcrc: integer := 2; -- data crc error
+constant c_rri_stat_rbf_ioto: integer := 1; -- i/o time out
+constant c_rri_stat_rbf_ioerr: integer := 0; -- i/o error
+
+type rb_mreq_type is record -- rribus - master request
+ req : slbit; -- request
+ we : slbit; -- write enable
+ init : slbit; -- init
+ addr : slv8; -- address
+ din : slv16; -- data (input to slave)
+end record rb_mreq_type;
+
+constant rb_mreq_init : rb_mreq_type :=
+ ('0','0','0', -- req, we, init
+ (others=>'0'), -- addr
+ (others=>'0')); -- din
+
+type rb_sres_type is record -- rribus - slave response
+ ack : slbit; -- acknowledge
+ busy : slbit; -- busy
+ err : slbit; -- error
+ dout : slv16; -- data (output from slave)
+end record rb_sres_type;
+
+constant rb_sres_init : rb_sres_type :=
+ ('0','0','0', -- ack, busy, err
+ (others=>'0')); -- dout
+
+component rri_core is -- rri, core interface
+ generic (
+ ATOWIDTH : positive := 5; -- access timeout counter width
+ ITOWIDTH : positive := 6); -- idle timeout counter width
+ port (
+ CLK : in slbit; -- clock
+ CE_INT : in slbit := '0'; -- rri ito time unit clock enable
+ RESET : in slbit; -- reset
+ CP_DI : in slv9; -- comm port: data in
+ CP_ENA : in slbit; -- comm port: data enable
+ CP_BUSY : out slbit; -- comm port: data busy
+ CP_DO : out slv9; -- comm port: data out
+ CP_VAL : out slbit; -- comm port: data valid
+ CP_HOLD : in slbit; -- comm port: data hold
+ CP_FLUSH : out slbit; -- comm port: data flush
+ RB_MREQ : out rb_mreq_type; -- rbus: request
+ RB_SRES : in rb_sres_type; -- rbus: response
+ RB_LAM : in slv16; -- rbus: look at me
+ RB_STAT : in slv3 -- rbus: status flags
+ );
+end component;
+
+component rricp_aif is -- rri comm port, abstract interface
+ port (
+ CLK : in slbit; -- clock
+ CE_INT : in slbit := '0'; -- rri ito time unit clock enable
+ RESET : in slbit :='0'; -- reset
+ CP_DI : in slv9; -- comm port: data in
+ CP_ENA : in slbit; -- comm port: data enable
+ CP_BUSY : out slbit; -- comm port: data busy
+ CP_DO : out slv9; -- comm port: data out
+ CP_VAL : out slbit; -- comm port: data valid
+ CP_HOLD : in slbit := '0' -- comm port: data hold
+ );
+end component;
+
+component rrirp_aif is -- rri reg port, abstract interface
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- reset
+ RB_MREQ : in rb_mreq_type; -- rbus: request
+ RB_SRES : out rb_sres_type; -- rbus: response
+ RB_LAM : out slv16; -- rbus: look at me
+ RB_STAT : out slv3 -- rbus: status flags
+ );
+end component;
+
+component rri_serport is -- rri serport adapter
+ generic (
+ CPREF : slv4 := "1000"; -- comma prefix
+ FAWIDTH : positive := 5; -- rx fifo address port width
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT : natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_USEC : in slbit; -- 1 usec clock enable
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (board view)
+ TXSD : out slbit; -- transmit serial data (board view)
+ CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
+ RTS_N : out slbit; -- request to send (act.low, board view)
+ CP_DI : out slv9; -- comm port: data in
+ CP_ENA : out slbit; -- comm port: data enable
+ CP_BUSY : in slbit; -- comm port: data busy
+ CP_DO : in slv9; -- comm port: data out
+ CP_VAL : in slbit; -- comm port: data valid
+ CP_HOLD : out slbit; -- comm port: data hold
+ CP_FLUSH : in slbit := '0' -- comm port: data flush
+ );
+end component;
+
+component rri_core_serport is -- rri, core+serport with cpmon+rbmon
+ generic (
+ ATOWIDTH : positive := 5; -- access timeout counter width
+ ITOWIDTH : positive := 6; -- idle timeout counter width
+ FAWIDTH : positive := 5; -- rx fifo address port width
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT : natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_USEC : in slbit; -- 1 usec clock enable
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ CE_INT : in slbit := '0'; -- rri ito time unit clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (board view)
+ TXSD : out slbit; -- transmit serial data (board view)
+ CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
+ RTS_N : out slbit; -- request to send (act.low, board view)
+ RB_MREQ : out rb_mreq_type; -- rbus: request
+ RB_SRES : in rb_sres_type; -- rbus: response
+ RB_LAM : in slv16; -- rbus: look at me
+ RB_STAT : in slv3 -- rbus: status flags
+ );
+end component;
+
+component rb_sres_or_2 is -- rribus result or, 2 input
+ port (
+ RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
+ RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
+ RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
+ );
+end component;
+component rb_sres_or_3 is -- rribus result or, 3 input
+ port (
+ RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
+ RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
+ RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
+ RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
+ );
+end component;
+component rb_sres_or_4 is -- rribus result or, 4 input
+ port (
+ RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
+ RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
+ RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3
+ RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4
+ RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
+ );
+end component;
+
+component rri_wreg_rw_3 is -- rri: wide register r/w 3 bit select
+ generic (
+ DWIDTH : positive := 16);
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ FADDR : slv3; -- field address
+ SEL : slbit; -- select
+ DATA : out slv(DWIDTH-1 downto 0); -- data
+ RB_MREQ : in rb_mreq_type; -- rribus request
+ RB_SRES : out rb_sres_type -- rribus response
+ );
+end component;
+
+component rri_wreg_w_3 is -- rri: wide register w-o 3 bit select
+ generic (
+ DWIDTH : positive := 16);
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ FADDR : slv3; -- field address
+ SEL : slbit; -- select
+ DATA : out slv(DWIDTH-1 downto 0); -- data
+ RB_MREQ : in rb_mreq_type; -- rribus request
+ RB_SRES : out rb_sres_type -- rribus response
+ );
+end component;
+
+component rri_wreg_r_3 is -- rri: wide register r-o 3 bit select
+ generic (
+ DWIDTH : positive := 16);
+ port (
+ FADDR : slv3; -- field address
+ SEL : slbit; -- select
+ DATA : in slv(DWIDTH-1 downto 0); -- data
+ RB_SRES : out rb_sres_type -- rribus response
+ );
+end component;
+
+end rrilib;
Index: rri/rri_core_serport.vbom
===================================================================
--- rri/rri_core_serport.vbom (nonexistent)
+++ rri/rri_core_serport.vbom (revision 7)
@@ -0,0 +1,11 @@
+# libs
+../slvtypes.vhd
+rrilib.vhd
+[ghdl,isim]tb/rritblib.vhd
+# components
+rri_serport.vbom
+rri_core.vbom
+[ghdl,isim]tb/rritb_cpmon_sb.vbom
+[ghdl,isim]tb/rritb_rbmon_sb.vbom
+# design
+rri_core_serport.vhd
Index: rri/rri_core.vhd
===================================================================
--- rri/rri_core.vhd (nonexistent)
+++ rri/rri_core.vhd (revision 7)
@@ -0,0 +1,809 @@
+-- $Id: rri_core.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: rri_core - syn
+-- Description: rri: core interface
+--
+-- Dependencies: comlib/crc8
+--
+-- Test bench: tb/tb_rri_core
+-- tb/tb_rritba_ttcombo
+-- tb/tb_rriext_ttcombo
+--
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
+-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
+-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
+-- now nak on reserved cmd 111; use do_comma_abort();
+-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
+-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
+-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
+-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
+-- drop RP_IINT signal from interfaces
+-- 2010-04-03 274 2.1 add CP_FLUSH output
+-- 2009-07-12 233 2.0.1 remove snoopers
+-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
+-- 2008-03-02 121 1.1.1 comment out snoopers
+-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-09-15 82 1.0 Initial version, fully functional
+-- 2007-06-17 58 0.5 First preliminary version
+------------------------------------------------------------------------------
+--
+-- Overall protocol:
+-- _idle : expect
+-- sop -> _txsop (echo sop, , to _txsop, _rxcmd)
+-- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle)
+-- nak -> _txnak (silently ignore nak)
+-- attn -> _txito (send ito , to _idle)
+-- data -> _idle (silently ignore data)
+-- _error: expect
+-- sop -> _txnak (send nak , to _txnak, _error)
+-- eop -> _txeop (echo eop , to _txeop, _idle)
+-- nak -> _txnak (echo nak , to _txnak, _error)
+-- attn -> _txito (silently ignore attn)
+-- data -> _idle (silently ignore data)
+-- _rxcmd: expect
+-- sop -> _txnak (send nak , to _txnak, _error)
+-- eop -> _txeop (echo eop , to _txeop, _idle)
+-- nak -> _txnak (echo nak , to _txnak, _error)
+-- attn -> _txito (silently ignore attn)
+-- data -> _idle (decode command)
+-- _rx...: expect
+-- sop -> _txnak (send nak , to _txnak, _error)
+-- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle)
+-- nak -> _txnak (echo nak , to _txnak, _error)
+-- attn -> _txito (silently ignore attn)
+-- data -> _idle (decode data)
+--
+-- 7 supported commands:
+--
+-- 000 read reg (rreg):
+-- rx: cmd addr ccrc
+-- tx: cmd dl dh stat crc
+-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
+-- _rreg _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
+--
+-- 001 read blk (rblk):
+-- rx: cmd addr cnt ccrc
+-- tx: cmd cnt dl dh ... stat crc
+-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
+-- {_rreg _txdatl _txdath _blk}* _txstat _txcrc (_rxcmd|_idle)
+--
+-- 010 write reg (wreg):
+-- rx: cmd addr dl dh ccrc
+-- tx: cmd stat crc
+-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
+-- seq: _wreg _txstat _txcrc (_rxcmd|_idle)
+--
+-- 011 write blk (wblk):
+-- rx: cmd addr cnt ccrc dl dh ... dcrc
+-- tx: cmd stat crc
+-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
+-- {_rxdatl _rxdath _wreg _blk}* _rxdcrc _txstat _txcrc (_rxcmd|_idle)
+--
+-- 100 read stat (stat):
+-- rx: cmd ccrc
+-- tx: cmd ccmd dl dh stat crc
+-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
+-- _txccmd _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
+--
+-- 101 read attn (attn):
+-- rx: cmd ccrc
+-- tx: cmd dl dh stat crc
+-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
+-- _attn _txdatl _txdath _txstat _txcrc (_rxcmd|_idle)
+--
+-- 110 write init (init):
+-- rx: cmd addr dl dh ccrc
+-- tx: cmd stat crc
+-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
+-- seq: _txstat _txcrc (_rxcmd|_idle)
+-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
+--
+-- 111 is currently not a legal command and causes a nak
+-- seq: _txnak
+--
+-- The different rbus cycle types are encoded as:
+--
+-- init ack we
+-- 0 0 0 idle
+-- 0 0 1 idle
+-- 0 1 0 read
+-- 0 1 1 write
+-- 1 0 0 internal init
+-- 1 0 1 external init
+-- 1 1 0 not allowed
+-- 1 1 1 not allowed
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.comlib.all;
+use work.rrilib.all;
+
+entity rri_core is -- rri, core interface
+ generic (
+ ATOWIDTH : positive := 5; -- access timeout counter width
+ ITOWIDTH : positive := 6); -- idle timeout counter width
+ port (
+ CLK : in slbit; -- clock
+ CE_INT : in slbit := '0'; -- rri ito time unit clock enable
+ RESET : in slbit; -- reset
+ CP_DI : in slv9; -- comm port: data in
+ CP_ENA : in slbit; -- comm port: data enable
+ CP_BUSY : out slbit; -- comm port: data busy
+ CP_DO : out slv9; -- comm port: data out
+ CP_VAL : out slbit; -- comm port: data valid
+ CP_HOLD : in slbit; -- comm port: data hold
+ CP_FLUSH : out slbit; -- comm port: data flush
+ RB_MREQ : out rb_mreq_type; -- rbus: request
+ RB_SRES : in rb_sres_type; -- rbus: response
+ RB_LAM : in slv16; -- rbus: look at me
+ RB_STAT : in slv3 -- rbus: status flags
+ );
+end entity rri_core;
+
+
+architecture syn of rri_core is
+
+ type state_type is (
+ s_idle, -- s_idle: wait for sop
+ s_txito, -- s_txito: send timeout symbol
+ s_txsop, -- s_txsop: send sop
+ s_txnak, -- s_txnak: send nak
+ s_txeop, -- s_txeop: send eop
+ s_error, -- s_error: wait for eop
+ s_rxcmd, -- s_rxcmd: wait for cmd
+ s_rxaddr, -- s_rxaddr: wait for addr
+ s_rxdatl, -- s_rxdatl: wait for data low
+ s_rxdath, -- s_rxdath: wait for data high
+ s_rxcnt, -- s_rxcnt: wait for count
+ s_rxccrc, -- s_rxccrc: wait for command crc
+ s_txcmd, -- s_txcmd: send cmd
+ s_txcnt, -- s_txcnt: send cnt
+ s_rreg, -- s_rreg: reg or blk read
+ s_txdatl, -- s_txdatl: send data low
+ s_txdath, -- s_txdath: send data high
+ s_wreg, -- s_wreg: reg or blk write
+ s_blk, -- s_blk: block count handling
+ s_rxdcrc, -- s_rxdcrc: wait for data crc
+ s_attn, -- s_attn: handle attention flags
+ s_txccmd, -- s_txccmd: send last command
+ s_txstat, -- s_txstat: send status
+ s_txcrc -- s_txcrc: send crc
+ );
+
+ type regs_type is record
+ state : state_type; -- state
+ rcmd : slv8; -- received command
+ ccmd : slv8; -- current command
+ addr : slv8; -- register address
+ dil : slv8; -- input data, lsb
+ dih : slv8; -- input data, msb
+ dol : slv8; -- output data, lsb
+ doh : slv8; -- output data, msb
+ cnt : slv8; -- block transfer count
+ attn : slv16; -- attn mask
+ atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter
+ itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
+ itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
+ itoena : slbit; -- idle timeout enable flag
+ anena : slbit; -- attn notification enable flag
+ andone : slbit; -- attn notification done
+ ccrc : slbit; -- stat: command crc error
+ dcrc : slbit; -- stat: data crc error
+ ioto : slbit; -- stat: i/o time out
+ ioerr : slbit; -- stat: i/o time error
+ nakeop : slbit; -- send eop after nak
+ rbinit : slbit; -- rbus init signal
+ rbreq : slbit; -- rbus req signal
+ rbwe : slbit; -- rbus we signal
+ flush : slbit; -- flush pulse
+ stat : slv3; -- external status flags
+ end record regs_type;
+
+ constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
+ constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
+
+ constant c_idle : slv4 := "0000";
+ constant c_sop : slv4 := "0001";
+ constant c_eop : slv4 := "0010";
+ constant c_nak : slv4 := "0011";
+ constant c_attn : slv4 := "0100";
+
+ constant regs_init : regs_type := (
+ s_idle, --
+ (others=>'0'), -- rcmd
+ (others=>'0'), -- ccmd
+ (others=>'0'), -- addr
+ (others=>'0'), -- dil
+ (others=>'0'), -- dih
+ (others=>'0'), -- dol
+ (others=>'0'), -- doh
+ (others=>'0'), -- cnt
+ (others=>'0'), -- attn
+ atocnt_init, -- atocnt
+ itocnt_init, -- itocnt
+ itocnt_init, -- itoval
+ '0', -- itoena
+ '0','0', -- anena, andone
+ '0','0','0','0', -- stat flags
+ '0', -- nakeop
+ '0','0','0', -- rbinit,rbreq,rbwe
+ '0', -- flush
+ (others=>'0') -- stat
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ signal CRC_RESET : slbit := '0';
+ signal ICRC_ENA : slbit := '0';
+ signal OCRC_ENA : slbit := '0';
+ signal ICRC_OUT : slv8 := (others=>'0');
+ signal OCRC_OUT : slv8 := (others=>'0');
+ signal OCRC_IN : slv8 := (others=>'0');
+
+begin
+
+ assert ITOWIDTH<=8
+ report "assert(ITOWIDTH<=8): max byte size ITO counter supported"
+ severity failure;
+
+ ICRC : crc8 -- crc generator for input data
+ port map (
+ CLK => CLK,
+ RESET => CRC_RESET,
+ ENA => ICRC_ENA,
+ DI => CP_DI(7 downto 0),
+ CRC => ICRC_OUT
+ );
+
+ OCRC : crc8 -- crc generator for output data
+ port map (
+ CLK => CLK,
+ RESET => CRC_RESET,
+ ENA => OCRC_ENA,
+ DI => OCRC_IN,
+ CRC => OCRC_OUT
+ );
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, CE_INT, CP_DI, CP_ENA, CP_HOLD, RB_LAM,
+ RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable ival : slbit := '0';
+ variable ibusy : slbit := '0';
+ variable ido : slv9 := (others=>'0');
+ variable ato_go : slbit := '0';
+ variable ato_end : slbit := '0';
+ variable ito_go : slbit := '0';
+ variable ito_end : slbit := '0';
+ variable crcreset : slbit := '0';
+ variable icrcena : slbit := '0';
+ variable ocrcena : slbit := '0';
+ variable has_attn : slbit := '0';
+ variable idi8 : slv8 := (others=>'0');
+ variable is_comma : slbit := '0';
+ variable comma_typ : slv4 := "0000";
+
+ procedure do_comma_abort(nstate : inout state_type;
+ nnakeop : inout slbit;
+ comma_typ : in slv4) is
+ begin
+ if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then
+ if comma_typ = c_eop then
+ nnakeop := '1';
+ end if;
+ nstate := s_txnak; -- next: send nak
+ end if;
+ end procedure do_comma_abort;
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ idi8 := CP_DI(7 downto 0); -- get data part of CP_DI
+ is_comma := CP_DI(8); -- get comma marker
+ comma_typ := CP_DI(3 downto 0); -- get comma type
+
+ n.rbinit := '0'; -- clear rbinit,rbreq,rbwe by default
+ n.rbreq := '0'; -- they must always be set by the
+ n.rbwe := '0'; -- 'previous state'
+
+ n.flush := '0'; -- dito for flush
+
+ ibusy := '1'; -- default is to hold input
+ ival := '0';
+ ido := (others=>'0');
+
+ crcreset := '0';
+ icrcena := '0';
+ ocrcena := '0';
+
+ for i in RB_LAM'range loop -- handle attention "LAM's"
+ if RB_LAM(i) = '1' then -- if LAM bit set
+ n.attn(i) := '1'; -- set attention bit
+ end if;
+ end loop;
+
+ has_attn := '0';
+ if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
+ has_attn := '1';
+ end if;
+
+ ato_go := '0'; -- default: keep access timeout in reset
+ ato_end := '0';
+ if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
+ ato_end := '1'; -- signal expiration
+ end if;
+
+ ito_go := '0'; -- default: keep idle timeout in reset
+ ito_end := '0';
+ if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero
+ ito_end := '1'; -- signal expiration
+ end if;
+
+ case r.state is
+ when s_idle => -- s_idle: wait for sop --------------
+ ito_go := '1'; -- idle timeout active
+ if (r.anena='1' and -- if attn notification to send
+ has_attn='1' and r.andone='0') then
+ n.state := s_txito; -- next send ito byte
+ else
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then -- if input
+ if is_comma = '1' then -- if comma
+ case comma_typ is
+ when c_sop => -- if sop
+ crcreset := '1'; -- reset crc generators
+ n.state := s_txsop; -- next: echo it
+ when c_eop => -- if eop (unexpected)
+ n.nakeop := '1'; -- send nak,eop
+ n.state := s_txnak; -- next: send nak
+ when c_attn => -- if attn
+ n.state := s_txito; -- next: send ito byte
+ when others => null; -- other commas: silently ignore
+ end case;
+ else -- if normal data
+ n.state := s_idle; -- silently dropped
+ end if;
+ elsif (r.itoena='1' and -- if ito enable, expired and XSEC
+ ito_end='1' and CE_INT='1') then
+ n.state := s_txito; -- next: send ito byte
+ end if;
+ end if;
+
+ when s_txito => -- s_txito: send timeout symbol ------
+ if has_attn = '1' then
+ ido := c_rri_dat_attn; -- if attn pending: send attn symbol
+ n.andone := '1';
+ else
+ ido := c_rri_dat_idle; -- otherwise: send idle symbol
+ end if;
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ n.state := s_idle; -- next: wait for sop
+ end if;
+
+ when s_txsop => -- s_txsop: send sop -----------------
+ ido := c_rri_dat_sop; -- send sop character
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ n.state := s_rxcmd; -- next: read first command
+ end if;
+
+ when s_txnak => -- s_txnak: send nak -----------------
+ ido := c_rri_dat_nak; -- send nak character
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ n.nakeop := '0';
+ if r.nakeop = '1' then -- if eop after nak requested
+ n.state := s_txeop; -- next: send eop
+ else
+ n.state := s_error; -- next: error state, wait for eop
+ end if;
+ end if;
+
+ when s_txeop => -- s_txeop: send eop -----------------
+ ido := c_rri_dat_eop; -- send eop character
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ n.flush := '1'; -- send flush pulse
+ n.state := s_idle; -- next: idle state, wait for sop
+ end if;
+
+ when s_error => -- s_error: wait for eop -------------
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ case comma_typ is
+ when c_sop => -- if sop (unexpected)
+ n.state := s_txnak; -- next: send nak
+ when c_eop => -- if eop
+ n.state := s_txeop; -- next: echo eop
+ when c_nak => -- if nak
+ n.state := s_txnak; -- next: echo nak
+ when others => null; -- other commas: silently ignore
+ end case;
+ else -- if normal data
+ n.state := s_error; -- silently dropped
+ end if;
+ end if;
+
+ when s_rxcmd => -- s_rxcmd: wait for cmd -------------
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ case comma_typ is
+ when c_sop => -- if sop (unexpected)
+ n.state := s_txnak; -- next: send nak
+ when c_eop => -- if eop
+ n.state := s_txeop; -- next: echo eop
+ when c_nak => -- if nak
+ n.state := s_txnak; -- next: echo nak
+ when others => null; --other commas: silently ignore
+ end case;
+ else
+ icrcena := '1'; -- update input crc
+ n.rcmd := idi8; -- latch read command code
+ case CP_DI(c_rri_cmd_rbf_code) is
+ when c_rri_cmd_rreg | c_rri_cmd_rblk |
+ c_rri_cmd_wreg | c_rri_cmd_wblk |
+ c_rri_cmd_init => -- for commands needing addr(data)
+ n.state := s_rxaddr; -- next: read address
+ when c_rri_cmd_stat | c_rri_cmd_attn => -- stat and attn commands
+ n.state := s_rxccrc; -- next: read command crc
+ when others =>
+ n.state := s_idle; -- if bad command abort here
+ end case; -- rcmd,ccmd always hold good cmd
+ end if;
+ end if;
+
+ when s_rxaddr => -- s_rxaddr: wait for addr -----------
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ do_comma_abort(n.state, n.nakeop, comma_typ);
+ else
+ icrcena := '1'; -- update input crc
+ n.addr := idi8; -- latch read address
+ case r.rcmd(c_rri_cmd_rbf_code) is
+ when c_rri_cmd_rreg => -- for rreg command
+ n.state := s_rxccrc; -- next: read command crc
+ when c_rri_cmd_wreg | c_rri_cmd_init => -- for wreg, init command
+ n.state := s_rxdatl; -- next: read data lsb
+ when others => -- for rblk or wblk
+ n.state := s_rxcnt; -- next: read count
+ end case;
+ end if;
+ end if;
+
+ when s_rxdatl => -- s_rxdatl: wait for data low -------
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ do_comma_abort(n.state, n.nakeop, comma_typ);
+ else
+ icrcena := '1'; -- update input crc
+ n.dil := idi8; -- latch data lsb part
+ n.state := s_rxdath; -- next: read data msb
+ end if;
+ end if;
+
+ when s_rxdath => -- s_rxdath: wait for data high ------
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ do_comma_abort(n.state, n.nakeop, comma_typ);
+ else
+ icrcena := '1'; -- update input crc
+ n.dih := idi8; -- latch data msb part
+ if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk
+ n.rbreq := '1';
+ n.rbwe := '1';
+ n.state := s_wreg; -- next: write reg
+ else -- otherwise
+ n.state := s_rxccrc; -- next: read command crc
+ end if;
+ end if;
+ end if;
+
+ when s_rxcnt => -- s_rxcnt: wait for count -----------
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ do_comma_abort(n.state, n.nakeop, comma_typ);
+ else
+ icrcena := '1'; -- update input crc
+ n.cnt := idi8; -- latch count
+ n.state := s_rxccrc; -- next: read command crc
+ end if;
+ end if;
+
+ when s_rxccrc => -- s_rxccrc: wait for command crc ----
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ do_comma_abort(n.state, n.nakeop, comma_typ);
+ else
+ if idi8 /= ICRC_OUT then -- if crc error
+ n.ccrc := '1'; -- set command crc error flag
+ n.state := s_txnak; -- next: send nak
+ else -- if crc ok
+ n.state := s_txcmd; -- next: echo command
+ end if;
+ end if;
+ end if;
+
+ when s_txcmd => -- s_txcmd: send cmd -----------------
+ ido := '0' & r.rcmd; -- send read command
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ ocrcena := '1'; -- update output crc
+ if r.rcmd(c_rri_cmd_rbf_code) /= c_rri_cmd_stat then -- unless stat
+ n.ccmd := r.rcmd; -- latch read command in ccmd
+ n.stat := RB_STAT; -- latch external status bits
+ n.ccrc := '0';
+ n.dcrc := '0';
+ n.ioto := '0';
+ n.ioerr := '0';
+ end if;
+ case r.rcmd(c_rri_cmd_rbf_code) is -- main command dispatcher
+ when c_rri_cmd_rreg => -- rreg ----------------
+ n.rbreq := '1';
+ n.state := s_rreg;
+ when c_rri_cmd_rblk => -- rblk ----------------
+ n.state := s_txcnt;
+ when c_rri_cmd_wreg => -- wreg ----------------
+ n.rbreq := '1';
+ n.rbwe := '1';
+ n.state := s_wreg;
+ when c_rri_cmd_wblk => -- wblk ----------------
+ n.state := s_rxdatl;
+ when c_rri_cmd_stat => -- stat ----------------
+ n.state := s_txccmd;
+ when c_rri_cmd_attn => -- attn ----------------
+ n.state := s_attn;
+
+ when c_rri_cmd_init => -- init ----------------
+ n.rbinit := '1'; -- send init pulse
+ if r.addr(7 downto 3) = "11111" then -- is internal init
+ if r.addr(2 downto 0) = "111" then -- is rri init
+ n.anena := r.dih(c_rri_iint_rbf_anena - 8);
+ n.itoena := r.dih(c_rri_iint_rbf_itoena - 8);
+ n.itoval := r.dil(ITOWIDTH-1 downto 0);
+ -- note: itocnt will load in next
+ -- cycle because ito_go=0, so no
+ -- action required here
+
+ end if;
+ else -- is external init
+ n.rbwe := '1'; -- send init with we
+ end if;
+ n.state := s_txstat;
+
+ when others => -- '111' ---------------
+ n.state := s_txnak; -- send NAK on reserved command
+ end case;
+ end if;
+
+ when s_txcnt => -- s_txcnt: send cnt -----------------
+ ido := '0' & r.cnt; -- send cnt
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ ocrcena := '1'; -- update output crc
+ n.rbreq := '1';
+ n.state := s_rreg; -- next: first read reg
+ end if;
+
+ when s_rreg => -- s_rreg: reg or blk read -----------
+ -- this state handles all rbus reads. Expects that previous state
+ -- sets n.rbreq := '1' to start an rbus read cycle
+ ato_go := '1'; -- activate timeout counter
+ if RB_SRES.err = '1' then -- latch error flag
+ n.ioerr := '1';
+ end if;
+ n.doh := RB_SRES.dout(15 downto 8); -- latch data
+ n.dol := RB_SRES.dout( 7 downto 0);
+ n.stat := RB_STAT; -- latch external status bits
+ if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
+ if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
+ n.ioto := '1'; -- set timeout flag
+ elsif RB_SRES.ack = '0' then -- if non-busy and no ack
+ n.ioto := '1'; -- set timeout flag
+ end if;
+ n.state := s_txdatl; -- next: send data lsb
+ else -- otherwise rbus read continues
+ n.rbreq := '1'; -- extend req
+ end if;
+
+ when s_txdatl => -- s_txdatl: send data low -----------
+ ido := '0' & r.dol; -- send data
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ ocrcena := '1'; -- update output crc
+ n.state := s_txdath; -- next: send data msb
+ end if;
+
+ when s_txdath => -- s_txdath: send data high
+ ido := '0' & r.doh; -- send data
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ ocrcena := '1'; -- update output crc
+ if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
+ n.state := s_blk; -- next: block count handling
+ else -- otherwise
+ n.state := s_txstat; -- next: send stat
+ end if;
+ end if;
+
+ when s_wreg => -- s_wreg: reg or blk write ----------
+ -- this state handles all rbus writes. Expects that previous state
+ -- sets n.rbreq := '1' and n.rbwe := '1' to start an rbus write cycle
+ ato_go := '1'; -- activate timeout counter
+ if RB_SRES.err = '1' then -- latch error flag
+ n.ioerr := '1';
+ end if;
+ n.stat := RB_STAT; -- latch external status bits
+ if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
+ if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
+ n.ioto := '1'; -- set timeout flag
+ elsif RB_SRES.ack='0' then -- if non-busy and no ack
+ n.ioto := '1'; -- set timeout flag
+ end if;
+ if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_wblk then -- if wblk
+ n.state := s_blk; -- next: block count handling
+ else -- otherwise
+ n.state := s_txstat; -- next: send stat
+ end if;
+ else -- otherwise rbus write continues
+ n.rbreq := '1'; -- extend req
+ n.rbwe := '1'; -- extend we
+ end if;
+
+ when s_blk => -- s_blk: block count handling -------
+ n.cnt := unsigned(r.cnt) - 1; -- decrement transfer count
+ if unsigned(r.cnt) = 0 then -- if last transfer
+ if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
+ n.state := s_txstat; -- next: send stat
+ else -- otherwise
+ n.state := s_rxdcrc; -- next: read data crc
+ end if;
+
+ else -- otherwise more to transfer
+ if r.rcmd(c_rri_cmd_rbf_code) = c_rri_cmd_rblk then -- if rblk
+ n.rbreq := '1';
+ n.state := s_rreg; -- next: read blk
+ else -- otherwise
+ n.state := s_rxdatl; -- next: read data
+ end if;
+ end if;
+
+ when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
+ ibusy := '0'; -- accept input
+ if CP_ENA = '1' then
+ if is_comma = '1' then -- if comma
+ do_comma_abort(n.state, n.nakeop, comma_typ);
+ else
+ if idi8 /= ICRC_OUT then -- if crc error
+ n.dcrc := '1'; -- set data crc error flag
+ end if;
+ n.state := s_txstat; -- next: echo command
+ end if;
+ end if;
+
+ when s_attn => -- s_attn: handle attention flags ----
+ n.dol := r.attn(7 downto 0); -- move attention flags to do buffer
+ n.doh := r.attn(15 downto 8);
+ n.attn := RB_LAM; -- LAM in current cycle send next time
+ n.andone := '0'; -- reenable attn nofification
+ n.state := s_txdatl; -- next: send data lsb
+
+ when s_txccmd => -- s_txccmd: send last command
+ ido := '0' & r.ccmd; -- send last accepted command
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ ocrcena := '1'; -- update output crc
+ n.state := s_txdatl; -- next: send last data lsb
+ end if;
+
+ when s_txstat => -- s_txstat: send status -------------
+ ido := (others=>'0');
+ ido(c_rri_stat_rbf_stat) := r.stat;
+ ido(c_rri_stat_rbf_attn) := has_attn;
+ ido(c_rri_stat_rbf_ccrc) := r.ccrc;
+ ido(c_rri_stat_rbf_dcrc) := r.dcrc;
+ ido(c_rri_stat_rbf_ioto) := r.ioto;
+ ido(c_rri_stat_rbf_ioerr) := r.ioerr;
+ ival := '1';
+ if CP_HOLD ='0' then -- wait for accept
+ ocrcena := '1'; -- update output crc
+ n.state := s_txcrc; -- next: send crc
+ end if;
+
+ when s_txcrc => -- s_txcrc: send crc -----------------
+ ido := "0" & OCRC_OUT; -- send crc code
+ ival := '1';
+ if CP_HOLD = '0' then -- wait for accept
+ n.state := s_rxcmd; -- next: read command or eop
+ end if;
+
+ when others => null; -- <> --------------------------------
+ end case;
+
+ if ato_go = '0' then -- handle access timeout counter
+ n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
+ else
+ n.atocnt := unsigned(r.atocnt) - 1;-- otherwise count down
+ end if;
+
+ if ito_go = '0' then -- handle idle timeout counter
+ n.itocnt := r.itoval; -- if ito_go=0, keep at start value
+ else
+ if CE_INT = '1' then
+ n.itocnt := unsigned(r.itocnt) - 1;-- otherwise count down every CE_INT
+ end if;
+ end if;
+
+ N_REGS <= n;
+
+ CP_BUSY <= ibusy;
+ CP_DO <= ido;
+ CP_VAL <= ival;
+ CP_FLUSH <= r.flush;
+
+ RB_MREQ <= rb_mreq_init;
+ RB_MREQ.req <= r.rbreq;
+ RB_MREQ.we <= r.rbwe;
+ RB_MREQ.init <= r.rbinit;
+ RB_MREQ.addr <= r.addr;
+ RB_MREQ.din <= r.dih & r.dil;
+
+ CRC_RESET <= crcreset;
+ ICRC_ENA <= icrcena;
+ OCRC_ENA <= ocrcena;
+ OCRC_IN <= ido(7 downto 0);
+
+ end process proc_next;
+
+end syn;
Index: rri/rri_core.vbom
===================================================================
--- rri/rri_core.vbom (nonexistent)
+++ rri/rri_core.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../slvtypes.vhd
+../comlib/comlib.vhd
+rrilib.vhd
+# components
+../comlib/crc8.vbom
+# design
+rri_core.vhd
Index: rri/rri_serport.vhd
===================================================================
--- rri/rri_serport.vhd (nonexistent)
+++ rri/rri_serport.vhd (revision 7)
@@ -0,0 +1,201 @@
+-- $Id: rri_serport.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: rri_serport - syn
+-- Description: rri: serport adapter
+--
+-- Dependencies: serport/serport_uart_rxtx_ab
+-- comlib/byte2cdata
+-- comlib/cdata2byte
+-- memlib/fifo_1c_dram
+--
+-- Test bench: tb/tb_rri_serport
+--
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-06 301 2.3 use NCOMM=4 (new eop,nak commas)
+-- 2010-06-03 300 2.2.1 use FAWIDTH=5
+-- 2010-05-02 287 2.2 drop RTSFLUSH generic
+-- 2010-04-18 279 2.1 rewrite flow control, drop RTSFBUF generic
+-- 2010-04-03 274 2.0 flow control interfaces: RTSFLUSH, CTS_N, RTS_N
+-- 2007-06-24 60 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.genlib.all;
+use work.memlib.all;
+use work.comlib.all;
+use work.serport.all;
+use work.rrilib.all;
+
+entity rri_serport is -- rri serport adapter
+ generic (
+ CPREF : slv4 := "1000"; -- comma prefix
+ FAWIDTH : positive := 5; -- rx fifo address port width
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT : natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_USEC : in slbit; -- 1 usec clock enable
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (board view)
+ TXSD : out slbit; -- transmit serial data (board view)
+ CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
+ RTS_N : out slbit; -- request to send (act.low, board view)
+ CP_DI : out slv9; -- comm port: data in
+ CP_ENA : out slbit; -- comm port: data enable
+ CP_BUSY : in slbit; -- comm port: data busy
+ CP_DO : in slv9; -- comm port: data out
+ CP_VAL : in slbit; -- comm port: data valid
+ CP_HOLD : out slbit; -- comm port: data hold
+ CP_FLUSH : in slbit := '0' -- comm port: data flush
+ );
+end rri_serport;
+
+
+architecture syn of rri_serport is
+
+ signal LRESET : slbit := '0';
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+ signal ABACT : slbit := '0';
+ signal FIFO_DI : slv9 := (others=>'0');
+ signal FIFO_ENA : slbit := '0';
+ signal FIFO_BUSY : slbit := '0';
+ signal FIFO_SIZE : slv(FAWIDTH downto 0) := (others=>'0');
+ signal CD2B_HOLD : slbit := '0';
+
+ signal R_FIFOBLOCK : slbit := '0'; -- fifo block flag
+ signal FLUSH_PULSE : slbit := '0'; -- rri flush as 2-3 usec pulse
+
+ constant NCOMM : positive := 4;
+
+begin
+
+ UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
+ generic map (
+ CDWIDTH => CDWIDTH,
+ CDINIT => CDINIT)
+ port map (
+ CLK => CLK,
+ CE_MSEC => CE_MSEC,
+ RESET => RESET,
+ RXSD => RXSD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => open,
+ RXACT => open,
+ TXSD => TXSD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY,
+ ABACT => ABACT,
+ ABDONE => open
+ );
+
+ LRESET <= RESET or ABACT;
+
+ B2CD : byte2cdata -- byte stream -> 9bit comma,data
+ generic map (
+ CPREF => CPREF,
+ NCOMM => NCOMM)
+ port map (
+ CLK => CLK,
+ RESET => LRESET,
+ DI => RXDATA,
+ ENA => RXVAL,
+ BUSY => open,
+ DO => FIFO_DI,
+ VAL => FIFO_ENA,
+ HOLD => FIFO_BUSY
+ );
+
+ CD2B : cdata2byte -- 9bit comma,data -> byte stream
+ generic map (
+ CPREF => CPREF,
+ NCOMM => NCOMM)
+ port map (
+ CLK => CLK,
+ RESET => LRESET,
+ DI => CP_DO,
+ ENA => CP_VAL,
+ BUSY => CP_HOLD,
+ DO => TXDATA,
+ VAL => TXENA,
+ HOLD => CD2B_HOLD
+ );
+
+ FIFO : fifo_1c_dram -- fifo, 1 clock, dram based
+ generic map (
+ AWIDTH => FAWIDTH,
+ DWIDTH => 9)
+ port map (
+ CLK => CLK,
+ RESET => LRESET,
+ DI => FIFO_DI,
+ ENA => FIFO_ENA,
+ BUSY => FIFO_BUSY,
+ DO => CP_DI,
+ VAL => CP_ENA,
+ HOLD => CP_BUSY,
+ SIZE => FIFO_SIZE
+ );
+
+-- re-write later, use RB_MREQ internal init to set parameters which
+-- control the flush logic.
+--
+--DOFLUSH: if RTSFLUSH generate
+--
+-- PGEN : timer
+-- generic map (
+-- TWIDTH => 1,
+-- RETRIG => true)
+-- port map (
+-- CLK => CLK,
+-- CE => CE_USEC,
+-- DELAY => "1",
+-- START => CP_FLUSH,
+-- STOP => RESET,
+-- BUSY => FLUSH_PULSE
+-- );
+--end generate DOFLUSH;
+
+ proc_fifoblock: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if unsigned(FIFO_SIZE) >= 3*2**(FAWIDTH-2) then -- more than 3/4 full
+ R_FIFOBLOCK <= '1'; -- block
+ elsif unsigned(FIFO_SIZE) < 2**(FAWIDTH-1) then -- less than 1/2 full
+ R_FIFOBLOCK <= '0'; -- unblock
+ end if;
+ end if;
+
+ end process proc_fifoblock;
+
+ RTS_N <= R_FIFOBLOCK or FLUSH_PULSE;
+
+ CD2B_HOLD <= TXBUSY or CTS_N;
+
+end syn;
Index: rri/rri_serport.vbom
===================================================================
--- rri/rri_serport.vbom (nonexistent)
+++ rri/rri_serport.vbom (revision 7)
@@ -0,0 +1,14 @@
+# libs
+../slvtypes.vhd
+../genlib/genlib.vhd
+../memlib/memlib.vhd
+../comlib/comlib.vhd
+../serport/serport.vhd
+rrilib.vhd
+# components
+../serport/serport_uart_rxtx_ab.vbom
+../comlib/byte2cdata.vbom
+../comlib/cdata2byte.vbom
+../memlib/fifo_1c_dram.vbom
+# design
+rri_serport.vhd
Index: rri/Makefile
===================================================================
--- rri/Makefile (nonexistent)
+++ rri/Makefile (revision 7)
@@ -0,0 +1,22 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-12-09 100 1.0.1 drop ISE_p definition
+# 2007-07-06 64 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: rri
===================================================================
--- rri (nonexistent)
+++ rri (revision 7)
rri
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: simlib/simlib.vhd
===================================================================
--- simlib/simlib.vhd (nonexistent)
+++ simlib/simlib.vhd (revision 7)
@@ -0,0 +1,1063 @@
+-- $Id: simlib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2006-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: simlib - sim
+-- Description: Support routines for test benches
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
+-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
+-- 2007-12-27 106 1.3.3 added simclk2v
+-- 2007-12-15 101 1.3.2 add read_ea(time), readtagval[_ea](std_logic)
+-- 2007-10-12 88 1.3.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-08-28 76 1.3 added writehex and writegen
+-- 2007-08-10 72 1.2.2 remove entity simclk, put into separate source
+-- 2007-08-03 71 1.2.1 readgen, readtagval, readtagval2: add base arg
+-- 2007-07-29 70 1.2 readtagval2: add tag=- support; add readword_ea,
+-- readoptchar, writetimestamp
+-- 2007-07-28 69 1.1.1 rename readrest -> testempty; add readgen
+-- use readgen in readtagval() and readtagval2()
+-- 2007-07-22 68 1.1 add readrest, readtagval, readtagval2
+-- 2007-06-30 62 1.0.1 remove clock_period ect constant defs
+-- 2007-06-14 56 1.0 Initial version (renamed from pdp11_sim.vhd)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+
+package simlib is
+
+constant null_char : character := character'val(0); -- '\0'
+constant null_string : string(1 to 1) := (others=>null_char); -- "\0"
+
+procedure readwhite( -- read over white space
+ L: inout line); -- line
+
+procedure readoct( -- read slv in octal base (arb. length)
+ L: inout line; -- line
+ value: out std_logic_vector; -- value to be read
+ good: out boolean); -- success flag
+
+procedure readhex( -- read slv in hex base (arb. length)
+ L: inout line; -- line
+ value: out std_logic_vector; -- value to be read
+ good: out boolean); -- success flag
+
+procedure readgen( -- read slv generic base
+ L: inout line; -- line
+ value: out std_logic_vector; -- value to be read
+ good: out boolean; -- success flag
+ base: in integer:= 2); -- default base
+
+procedure readcomment(
+ L: inout line;
+ good: out boolean);
+
+procedure readcommand(
+ L: inout line;
+ name: out string;
+ good: out boolean);
+
+procedure readword(
+ L: inout line;
+ name: out string;
+ good: out boolean);
+
+procedure readoptchar(
+ L: inout line;
+ char: in character;
+ good: out boolean);
+
+procedure readempty(
+ L: inout line);
+
+procedure testempty(
+ L: inout line;
+ good: out boolean);
+
+procedure testempty_ea(
+ L: inout line);
+
+procedure read_ea(
+ L: inout line;
+ value: out integer);
+procedure read_ea(
+ L: inout line;
+ value: out time);
+
+procedure read_ea(
+ L: inout line;
+ value: out std_logic);
+procedure read_ea(
+ L: inout line;
+ value: out std_logic_vector);
+
+procedure readoct_ea(
+ L: inout line;
+ value: out std_logic_vector);
+
+procedure readhex_ea(
+ L: inout line;
+ value: out std_logic_vector);
+
+procedure readgen_ea(
+ L: inout line;
+ value: out std_logic_vector;
+ base: in integer:= 2);
+
+procedure readword_ea(
+ L: inout line;
+ name: out string);
+
+procedure readtagval(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic_vector;
+ good: out boolean;
+ base: in integer:= 2);
+procedure readtagval_ea(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic_vector;
+ base: in integer:= 2);
+
+procedure readtagval(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic;
+ good: out boolean);
+procedure readtagval_ea(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic);
+
+procedure readtagval2(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val1: out std_logic_vector;
+ val2: out std_logic_vector;
+ good: out boolean;
+ base: in integer:= 2);
+procedure readtagval2_ea(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val1: out std_logic_vector;
+ val2: out std_logic_vector;
+ base: in integer:= 2);
+
+procedure writeoct( -- write slv in octal base (arb. length)
+ L: inout line; -- line
+ value: in std_logic_vector; -- value to be written
+ justified: in side:=right; -- justification (left/right)
+ field: in width:=0); -- field width
+
+procedure writehex( -- write slv in hex base (arb. length)
+ L: inout line; -- line
+ value: in std_logic_vector; -- value to be written
+ justified: in side:=right; -- justification (left/right)
+ field: in width:=0); -- field width
+
+procedure writegen( -- write slv in generic base (arb. lth)
+ L: inout line; -- line
+ value: in std_logic_vector; -- value to be written
+ justified: in side:=right; -- justification (left/right)
+ field: in width:=0; -- field width
+ base: in integer:= 2); -- default base
+
+procedure writetimestamp(
+ L: inout line;
+ clkcyc: in slv31;
+ str : in string := null_string);
+
+-- ----------------------------------------------------------------------------
+
+component simclk is -- test bench clock generator
+ generic (
+ PERIOD : time := 20 ns; -- clock period
+ OFFSET : time := 200 ns); -- clock offset (first up transition)
+ port (
+ CLK : out slbit; -- clock
+ CLK_CYCLE : out slv31; -- clock cycle number
+ CLK_STOP : in slbit -- clock stop trigger
+ );
+end component;
+
+component simclkv is -- test bench clock generator
+ -- with variable periods
+ port (
+ CLK : out slbit; -- clock
+ CLK_CYCLE : out slv31; -- clock cycle number
+ CLK_PERIOD : in time; -- clock period
+ CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
+ CLK_STOP : in slbit -- clock stop trigger
+ );
+end component;
+
+end package simlib;
+
+-- ----------------------------------------------------------------------------
+
+package body simlib is
+
+procedure readwhite( -- read over white space
+ L: inout line) is -- line
+ variable ch : character;
+begin
+ while L'length>0 loop
+ ch := L(L'left);
+ exit when (ch/=' ' and ch/=HT);
+ read(L,ch);
+ end loop;
+
+end procedure readwhite;
+
+-- -------------------------------------
+
+procedure readoct( -- read slv in octal base (arb. length)
+ L: inout line; -- line
+ value: out std_logic_vector; -- value to be read
+ good: out boolean) is -- success flag
+
+ variable nibble : std_logic_vector(2 downto 0);
+ variable sum : std_logic_vector(31 downto 0);
+ variable ndig : integer; -- number of digits
+ variable ok : boolean;
+ variable ichar : character;
+
+begin
+
+ assert not value'ascending(1)
+ report "readoct called with ascending range"
+ severity failure;
+ assert value'length<=32
+ report "readoct called with value'length > 32"
+ severity failure;
+
+ readwhite(L);
+
+ ndig := 0;
+ sum := (others=>'U');
+
+ while L'length>0 loop
+ ok := true;
+ case L(L'left) is
+ when '0' => nibble := "000";
+ when '1' => nibble := "001";
+ when '2' => nibble := "010";
+ when '3' => nibble := "011";
+ when '4' => nibble := "100";
+ when '5' => nibble := "101";
+ when '6' => nibble := "110";
+ when '7' => nibble := "111";
+ when 'u'|'U' => nibble := "UUU";
+ when 'x'|'X' => nibble := "XXX";
+ when 'z'|'Z' => nibble := "ZZZ";
+ when '-' => nibble := "---";
+ when others => ok := false;
+ end case;
+
+ exit when not ok;
+ read(L,ichar);
+ ndig := ndig + 1;
+ sum(sum'left downto 3) := sum(sum'left-3 downto 0);
+ sum(2 downto 0) := nibble;
+ end loop;
+
+ ok := ndig>0;
+ value := sum(value'range);
+ good := ok;
+
+end procedure readoct;
+
+-- -------------------------------------
+
+procedure readhex( -- read slv in hex base (arb. length)
+ L: inout line; -- line
+ value: out std_logic_vector; -- value to be read
+ good: out boolean) is -- success flag
+
+ variable nibble : std_logic_vector(3 downto 0);
+ variable sum : std_logic_vector(31 downto 0);
+ variable ndig : integer; -- number of digits
+ variable ok : boolean;
+ variable ichar : character;
+
+begin
+
+ assert not value'ascending(1)
+ report "readhex called with ascending range"
+ severity failure;
+ assert value'length<=32
+ report "readhex called with value'length > 32"
+ severity failure;
+
+ readwhite(L);
+
+ ndig := 0;
+ sum := (others=>'U');
+
+ while L'length>0 loop
+ ok := true;
+ case L(L'left) is
+ when '0' => nibble := "0000";
+ when '1' => nibble := "0001";
+ when '2' => nibble := "0010";
+ when '3' => nibble := "0011";
+ when '4' => nibble := "0100";
+ when '5' => nibble := "0101";
+ when '6' => nibble := "0110";
+ when '7' => nibble := "0111";
+ when '8' => nibble := "1000";
+ when '9' => nibble := "1001";
+ when 'a'|'A' => nibble := "1010";
+ when 'b'|'B' => nibble := "1011";
+ when 'c'|'C' => nibble := "1100";
+ when 'd'|'D' => nibble := "1101";
+ when 'e'|'E' => nibble := "1110";
+ when 'f'|'F' => nibble := "1111";
+ when 'u'|'U' => nibble := "UUUU";
+ when 'x'|'X' => nibble := "XXXX";
+ when 'z'|'Z' => nibble := "ZZZZ";
+ when '-' => nibble := "----";
+ when others => ok := false;
+ end case;
+
+ exit when not ok;
+ read(L,ichar);
+ ndig := ndig + 1;
+ sum(sum'left downto 4) := sum(sum'left-4 downto 0);
+ sum(3 downto 0) := nibble;
+ end loop;
+
+ ok := ndig>0;
+ value := sum(value'range);
+ good := ok;
+
+end procedure readhex;
+
+-- -------------------------------------
+
+procedure readgen( -- read slv generic base
+ L: inout line; -- line
+ value: out std_logic_vector; -- value to be read
+ good: out boolean; -- success flag
+ base: in integer := 2) is -- default base
+
+ variable nibble : std_logic_vector(3 downto 0);
+ variable sum : std_logic_vector(31 downto 0);
+ variable lbase : integer; -- local base
+ variable cbase : integer; -- current base
+ variable ok : boolean;
+ variable ivalue : integer;
+ variable ichar : character;
+
+begin
+
+ assert not value'ascending(1)
+ report "readgen called with ascending range"
+ severity failure;
+ assert value'length<=32
+ report "readgen called with value'length > 32"
+ severity failure;
+ assert base=2 or base=8 or base=10 or base=16
+ report "readgen base not 2,8,10, or 16"
+ severity failure;
+
+ readwhite(L);
+
+ cbase := base;
+ lbase := 0;
+ ok := true;
+
+ if L'length >= 2 then
+ if L(L'left+1) = '"' then
+ case L(L'left) is
+ when 'b'|'B' => lbase := 2;
+ when 'o'|'O' => lbase := 8;
+ when 'd'|'D' => lbase := 10;
+ when 'x'|'X' => lbase := 16;
+ when others => ok := false;
+ end case;
+ end if;
+ if lbase /= 0 then
+ read(L, ichar);
+ read(L, ichar);
+ cbase := lbase;
+ end if;
+ end if;
+
+ if ok then
+ case cbase is
+ when 2 => read(L, value, ok);
+ when 8 => readoct(L, value, ok);
+ when 16 => readhex(L, value, ok);
+ when 10 =>
+ read(L, ivalue, ok);
+ value := conv_std_logic_vector(ivalue, value'length);
+ when others => null;
+ end case;
+ end if;
+
+ if ok and lbase/=0 then
+ if L'length>0 and L(L'left)='"' then
+ read(L, ichar);
+ else
+ ok := false;
+ end if;
+ end if;
+
+ good := ok;
+
+end procedure readgen;
+
+-- -------------------------------------
+
+procedure readcomment(
+ L: inout line;
+ good: out boolean) is
+ variable ichar : character;
+begin
+
+ readwhite(L);
+
+ good := true;
+ if L'length > 0 then
+ good := false;
+ if L(L'left) = '#' then
+ good := true;
+ elsif L(L'left) = 'C' then
+ good := true;
+ writeline(output, L);
+ end if;
+ end if;
+
+end procedure readcomment;
+
+-- -------------------------------------
+
+procedure readcommand(
+ L: inout line;
+ name: out string;
+ good: out boolean) is
+begin
+
+ for i in name'range loop
+ name(i) := ' ';
+ end loop;
+ good := false;
+
+ if L'length>0 and L(L'left)='.' then
+ readword(L, name, good);
+ end if;
+
+end procedure readcommand;
+
+-- -------------------------------------
+
+procedure readword(
+ L: inout line;
+ name: out string;
+ good: out boolean) is
+
+ variable ichar : character;
+ variable ind : integer;
+
+begin
+
+ assert name'ascending(1)
+ report "readword called with descending range for name"
+ severity failure;
+
+ readwhite(L);
+
+ for i in name'range loop
+ name(i) := ' ';
+ end loop;
+ ind := name'left;
+
+ while L'length>0 and ind<=name'right loop
+ ichar := L(L'left);
+ exit when ichar=' ' or ichar=',' or ichar='|';
+ read(L,ichar);
+ name(ind) := ichar;
+ ind := ind + 1;
+ end loop;
+
+ good := ind /= name'left; -- ok if one non-blank found
+
+end procedure readword;
+
+-- -------------------------------------
+
+procedure readoptchar(
+ L: inout line;
+ char: in character;
+ good: out boolean) is
+
+ variable ichar : character;
+
+begin
+
+ good := false;
+ if L'length > 0 then
+ if L(L'left) = char then
+ read(L, ichar);
+ good := true;
+ end if;
+ end if;
+
+end procedure readoptchar;
+
+-- -------------------------------------
+
+procedure readempty(
+ L: inout line) is
+
+ variable ch : character;
+
+begin
+
+ while L'length>0 loop -- anything left ?
+ read(L,ch); -- read and discard it
+ end loop;
+
+end procedure readempty;
+
+-- -------------------------------------
+
+procedure testempty(
+ L: inout line;
+ good: out boolean) is
+
+begin
+
+ readwhite(L); -- discard white space
+ good := true; -- good if now empty
+
+ if L'length > 0 then -- anything left ?
+ good := false; -- assume bad
+ if L'length >= 2 and -- check for "--"
+ L(L'left)='-' and L(L'left+1)='-' then
+ good := true; -- in that case comment -> good
+ end if;
+ end if;
+
+end procedure testempty;
+
+-- -------------------------------------
+
+procedure testempty_ea(
+ L: inout line) is
+
+ variable ok : boolean := false;
+
+begin
+
+ testempty(L, ok);
+ assert ok report "extra chars in """ & L.all & """" severity failure;
+
+end procedure testempty_ea;
+
+-- -------------------------------------
+
+procedure read_ea(
+ L: inout line;
+ value: out integer) is
+
+ variable ok : boolean := false;
+
+begin
+
+ read(L, value, ok);
+ assert ok report "read(integer) conversion error in """ &
+ L.all & """" severity failure;
+
+end procedure read_ea;
+
+-- -------------------------------------
+
+procedure read_ea(
+ L: inout line;
+ value: out time) is
+
+ variable ok : boolean := false;
+
+begin
+
+ read(L, value, ok);
+ assert ok report "read(time) conversion error in """ &
+ L.all & """" severity failure;
+
+end procedure read_ea;
+
+-- -------------------------------------
+
+procedure read_ea(
+ L: inout line;
+ value: out std_logic) is
+
+ variable ok : boolean := false;
+
+begin
+
+ read(L, value, ok);
+ assert ok report "read(std_logic) conversion error in """ &
+ L.all & """" severity failure;
+
+end procedure read_ea;
+
+-- -------------------------------------
+
+procedure read_ea(
+ L: inout line;
+ value: out std_logic_vector) is
+
+ variable ok : boolean := false;
+
+begin
+
+ read(L, value, ok);
+ assert ok report "read(std_logic_vector) conversion error in """ &
+ L.all & """" severity failure;
+
+end procedure read_ea;
+
+-- -------------------------------------
+
+procedure readoct_ea(
+ L: inout line;
+ value: out std_logic_vector) is
+
+ variable ok : boolean := false;
+
+begin
+
+ readoct(L, value, ok);
+ assert ok report "readoct() conversion error in """ &
+ L.all & """" severity failure;
+
+end procedure readoct_ea;
+
+-- -------------------------------------
+
+procedure readhex_ea(
+ L: inout line;
+ value: out std_logic_vector) is
+
+ variable ok : boolean := false;
+
+begin
+
+ readhex(L, value, ok);
+ assert ok report "readhex() conversion error in """ &
+ L.all & """" severity failure;
+
+end procedure readhex_ea;
+
+-- -------------------------------------
+
+procedure readgen_ea(
+ L: inout line;
+ value: out std_logic_vector;
+ base: in integer := 2) is
+
+ variable ok : boolean := false;
+
+begin
+
+ readgen(L, value, ok, base);
+ assert ok report "readgen() conversion error in """ &
+ L.all & """" severity failure;
+
+end procedure readgen_ea;
+
+-- -------------------------------------
+
+procedure readword_ea(
+ L: inout line;
+ name: out string) is
+
+ variable ok : boolean := false;
+
+begin
+
+ readword(L, name, ok);
+ assert ok report "readword() read error in """ &
+ L.all & """" severity failure;
+
+end procedure readword_ea;
+
+-- -------------------------------------
+
+procedure readtagval(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic_vector;
+ good: out boolean;
+ base: in integer:= 2) is
+
+ variable itag : string(tag'range);
+ variable ichar : character;
+ variable imatch : boolean;
+
+begin
+
+ readwhite(L);
+
+ for i in val'range loop
+ val(i) := '0';
+ end loop;
+ good := true;
+ imatch := false;
+
+ if L'length > tag'length then
+ imatch := L(L'left to L'left+tag'length-1) = tag and
+ L(L'left+tag'length) = '=';
+ if imatch then
+ read(L, itag);
+ read(L, ichar);
+ readgen(L, val, good, base);
+ end if;
+ end if;
+ match := imatch;
+
+end procedure readtagval;
+
+-- -------------------------------------
+
+procedure readtagval_ea(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic_vector;
+ base: in integer:= 2) is
+
+ variable ok : boolean := false;
+
+begin
+ readtagval(L, tag, match, val, ok, base);
+ assert ok report "readtagval(std_logic_vector) conversion error in """ &
+ L.all & """" severity failure;
+end procedure readtagval_ea;
+
+-- -------------------------------------
+
+procedure readtagval(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic;
+ good: out boolean) is
+
+ variable itag : string(tag'range);
+ variable ichar : character;
+ variable imatch : boolean;
+
+begin
+
+ readwhite(L);
+
+ val := '0';
+ good := true;
+ imatch := false;
+
+ if L'length > tag'length then
+ imatch := L(L'left to L'left+tag'length-1) = tag and
+ L(L'left+tag'length) = '=';
+ if imatch then
+ read(L, itag);
+ read(L, ichar);
+ read(L, val, good);
+ end if;
+ end if;
+ match := imatch;
+
+end procedure readtagval;
+
+-- -------------------------------------
+
+procedure readtagval_ea(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val: out std_logic) is
+
+ variable ok : boolean := false;
+
+begin
+ readtagval(L, tag, match, val, ok);
+ assert ok report "readtagval(std_logic) conversion error in """ &
+ L.all & """" severity failure;
+end procedure readtagval_ea;
+
+-- -------------------------------------
+
+procedure readtagval2(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val1: out std_logic_vector;
+ val2: out std_logic_vector;
+ good: out boolean;
+ base: in integer:= 2) is
+
+ variable itag : string(tag'range);
+ variable imatch : boolean;
+ variable igood : boolean;
+ variable ichar : character;
+ variable ok : boolean;
+
+begin
+
+ readwhite(L);
+
+ for i in val1'range loop -- zero val1
+ val1(i) := '0';
+ end loop;
+ for i in val2'range loop -- zero val2
+ val2(i) := '0';
+ end loop;
+ igood := true;
+ imatch := false;
+
+ if L'length > tag'length then -- check for tag
+ imatch := L(L'left to L'left+tag'length-1) = tag and
+ L(L'left+tag'length) = '=';
+
+ if imatch then -- if found
+ read(L, itag); -- remove tag
+ read(L, ichar); -- remove =
+
+ igood := false;
+ readoptchar(L, '-', ok); -- check for tag=-
+ if ok then
+ for i in val2'range loop -- set mask to all 1 (ignore)
+ val2(i) := '1';
+ end loop;
+ igood := true;
+ else -- here if tag=bit[,bit]
+ readgen(L, val1, igood, base); -- read val1
+ if igood then
+ readoptchar(L, ',', ok); -- check(and remove) ,
+ if ok then
+ readgen(L, val2, igood, base); -- and read val2
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+
+ match := imatch;
+ good := igood;
+
+end procedure readtagval2;
+
+-- -------------------------------------
+
+procedure readtagval2_ea(
+ L: inout line;
+ tag: in string;
+ match: out boolean;
+ val1: out std_logic_vector;
+ val2: out std_logic_vector;
+ base: in integer:= 2) is
+
+ variable ok : boolean := false;
+
+begin
+ readtagval2(L, tag, match, val1, val2, ok, base);
+ assert ok report "readtagval2() conversion error in """ &
+ L.all & """" severity failure;
+end procedure readtagval2_ea;
+
+-- -------------------------------------
+
+procedure writeoct( -- write slv in octal base (arb. length)
+ L: inout line; -- line
+ value: in std_logic_vector; -- value to be written
+ justified: in side:=right; -- justification (left/right)
+ field: in width:=0) is -- field width
+
+ variable nbit : integer; -- number of bits
+ variable ndig : integer; -- number of digits
+ variable iwidth : integer;
+ variable ioffset : integer;
+ variable nibble : std_logic_vector(2 downto 0);
+ variable ochar : character;
+
+begin
+
+ assert not value'ascending(1)
+ report "writeoct called with ascending range"
+ severity failure;
+
+ nbit := value'length(1);
+ ndig := (nbit+2)/3;
+ iwidth := nbit mod 3;
+ if iwidth = 0 then
+ iwidth := 3;
+ end if;
+ ioffset := value'left(1) - iwidth+1;
+ if justified=right and field>ndig then
+ for i in ndig+1 to field loop
+ write(L,' ');
+ end loop; -- i
+ end if;
+ for i in 0 to ndig-1 loop
+ nibble := "000";
+ nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
+ ochar := ' ';
+ for i in nibble'range loop
+ case nibble(i) is
+ when 'U' => ochar := 'U';
+ when 'X' => ochar := 'X';
+ when 'Z' => ochar := 'Z';
+ when '-' => ochar := '-';
+ when others => null;
+ end case;
+ end loop; -- i
+ if ochar = ' ' then
+ write(L,conv_integer(unsigned(nibble)));
+ else
+ write(L,ochar);
+ end if;
+ iwidth := 3;
+ ioffset := ioffset - 3;
+ end loop; -- i
+ if justified=left and field>ndig then
+ for i in ndig+1 to field loop
+ write(L,' ');
+ end loop; -- i
+ end if;
+end procedure writeoct;
+
+-- -------------------------------------
+
+procedure writehex( -- write slv in hex base (arb. length)
+ L: inout line; -- line
+ value: in std_logic_vector; -- value to be written
+ justified: in side:=right; -- justification (left/right)
+ field: in width:=0) is -- field width
+
+ variable nbit : integer; -- number of bits
+ variable ndig : integer; -- number of digits
+ variable iwidth : integer;
+ variable ioffset : integer;
+ variable nibble : std_logic_vector(3 downto 0);
+ variable ochar : character;
+ variable hextab : string(1 to 16) := "0123456789abcdef";
+
+begin
+
+ assert not value'ascending(1)
+ report "writehex called with ascending range"
+ severity failure;
+
+ nbit := value'length(1);
+ ndig := (nbit+3)/4;
+ iwidth := nbit mod 4;
+ if iwidth = 0 then
+ iwidth := 4;
+ end if;
+ ioffset := value'left(1) - iwidth+1;
+ if justified=right and field>ndig then
+ for i in ndig+1 to field loop
+ write(L,' ');
+ end loop; -- i
+ end if;
+ for i in 0 to ndig-1 loop
+ nibble := "0000";
+ nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset);
+ ochar := ' ';
+ for i in nibble'range loop
+ case nibble(i) is
+ when 'U' => ochar := 'U';
+ when 'X' => ochar := 'X';
+ when 'Z' => ochar := 'Z';
+ when '-' => ochar := '-';
+ when others => null;
+ end case;
+ end loop; -- i
+ if ochar = ' ' then
+ write(L,hextab(conv_integer(unsigned(nibble))+1));
+ else
+ write(L,ochar);
+ end if;
+ iwidth := 4;
+ ioffset := ioffset - 4;
+ end loop; -- i
+ if justified=left and field>ndig then
+ for i in ndig+1 to field loop
+ write(L,' ');
+ end loop; -- i
+ end if;
+end procedure writehex;
+
+-- -------------------------------------
+
+procedure writegen( -- write slv in generic base (arb. lth)
+ L: inout line; -- line
+ value: in std_logic_vector; -- value to be written
+ justified: in side:=right; -- justification (left/right)
+ field: in width:=0; -- field width
+ base: in integer:=2) is -- default base
+
+begin
+
+ case base is
+ when 2 => write(L, value, justified, field);
+ when 8 => writeoct(L, value, justified, field);
+ when 16 => writehex(L, value, justified, field);
+ when others => report "writegen base not 2,8, or 16"
+ severity failure;
+ end case;
+
+end procedure writegen;
+
+-- -------------------------------------
+
+procedure writetimestamp(
+ L: inout line;
+ clkcyc: in slv31;
+ str: in string := null_string) is
+
+begin
+
+ write(L, now, right, 12);
+ write(L, conv_integer(unsigned(clkcyc)), right, 7);
+ if str /= null_string then
+ write(L, str);
+ end if;
+
+end procedure writetimestamp;
+
+end package body simlib;
+
Index: simlib/simclk.vhd
===================================================================
--- simlib/simclk.vhd (nonexistent)
+++ simlib/simclk.vhd (revision 7)
@@ -0,0 +1,78 @@
+-- $Id: simclk.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: simclk - sim
+-- Description: Clock generator for test benches
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-08-10 72 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use work.slvtypes.all;
+
+entity simclk is -- test bench clock generator
+ generic (
+ PERIOD : time := 20 ns; -- clock period
+ OFFSET : time := 200 ns); -- clock offset (first up transition)
+ port (
+ CLK : out slbit; -- clock
+ CLK_CYCLE : out slv31; -- clock cycle number
+ CLK_STOP : in slbit -- clock stop trigger
+ );
+end entity simclk;
+
+architecture sim of simclk is
+begin
+
+ clk_proc: process
+ constant clock_halfperiod : time := PERIOD/2;
+ variable icycle : slv31 := (others=>'0');
+ begin
+
+ CLK <= '0';
+ CLK_CYCLE <= (others=>'0');
+ wait for OFFSET;
+
+ clk_loop: loop
+ CLK <= '1';
+ wait for 0 ns; -- make a delta cycle so that clock
+ icycle := unsigned(icycle) + 1; -- cycle number is updated after the
+ CLK_CYCLE <= icycle; -- clock transition. all edge triggered
+ -- proc's will thus read old value.
+ wait for clock_halfperiod;
+ CLK <= '0';
+ wait for clock_halfperiod;
+ exit clk_loop when CLK_STOP = '1';
+ end loop;
+
+ CLK <= '1'; -- final clock cycle for clk_sim
+ wait for clock_halfperiod;
+ CLK <= '0';
+ wait for clock_halfperiod;
+
+ wait; -- endless wait, simulator will stop
+
+ end process;
+
+end sim;
Index: simlib/simbus.vhd
===================================================================
--- simlib/simbus.vhd (nonexistent)
+++ simlib/simbus.vhd (revision 7)
@@ -0,0 +1,46 @@
+-- $Id: simbus.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: simbus
+-- Description: Global signals for support control in test benches
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
+-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
+-- 2007-08-27 76 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package simbus is
+
+ signal SB_CLKSTOP : slbit := '0'; -- global clock stop
+ signal SB_CLKCYCLE : slv31 := (others=>'0'); -- global clock cycle
+ signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
+ signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
+ signal SB_VAL : slbit := '0'; -- init bcast valid
+ signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
+ signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
+
+ -- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
+ -- strong ('0','1') drivers. Therefore always remove strenght before
+ -- using, e.g. with to_x01()
+
+end package simbus;
Index: simlib/simclk.vbom
===================================================================
--- simlib/simclk.vbom (nonexistent)
+++ simlib/simclk.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../slvtypes.vhd
+# components
+# design
+simclk.vhd
Index: simlib
===================================================================
--- simlib (nonexistent)
+++ simlib (revision 7)
simlib
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: genlib/debounce_gen.vbom
===================================================================
--- genlib/debounce_gen.vbom (nonexistent)
+++ genlib/debounce_gen.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+debounce_gen.vhd
Index: genlib/genlib.vhd
===================================================================
--- genlib/genlib.vhd (nonexistent)
+++ genlib/genlib.vhd (revision 7)
@@ -0,0 +1,156 @@
+-- $Id: genlib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: genlib
+-- Description: some general purpose components
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-17 277 1.0.7 timer: no default for START,DONE,BUSY; drop STOP
+-- 2010-04-02 273 1.0.6 add timer
+-- 2008-01-20 112 1.0.5 rename clkgen->clkdivce
+-- 2007-12-26 106 1.0.4 added gray_cnt_(4|5|n|gen) and gray2bin_gen
+-- 2007-12-25 105 1.0.3 RESET:='0' defaults
+-- 2007-06-17 58 1.0.2 added debounce_gen
+-- 2007-06-16 57 1.0.1 added cnt_array_dram, cnt_array_regs
+-- 2007-06-03 45 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package genlib is
+
+component clkdivce is -- generate usec/msec ce pulses
+ generic (
+ CDUWIDTH : positive := 6; -- usec clock divider width
+ USECDIV : positive := 50; -- divider ratio for usec pulse
+ MSECDIV : positive := 1000); -- divider ratio for msec pulse
+ port (
+ CLK : in slbit; -- input clock
+ CE_USEC : out slbit; -- usec pulse
+ CE_MSEC : out slbit -- msec pulse
+ );
+end component;
+
+component cnt_array_dram is -- counter array, dram based
+ generic (
+ AWIDTH : positive := 4; -- address width
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- clear counters
+ CE : in slv(2**AWIDTH-1 downto 0); -- count enables
+ ADDR : out slv(AWIDTH-1 downto 0); -- counter address
+ DATA : out slv(DWIDTH-1 downto 0); -- counter data
+ ACT : out slbit -- active (not reseting)
+ );
+end component;
+
+component cnt_array_regs is -- counter array, register based
+ generic (
+ AWIDTH : positive := 4; -- address width
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- clear counters
+ CE : in slv(2**AWIDTH-1 downto 0); -- count enables
+ ADDR : in slv(AWIDTH-1 downto 0); -- address
+ DATA : out slv(DWIDTH-1 downto 0) -- counter data
+ );
+end component;
+
+component debounce_gen is -- debounce, generic vector
+ generic (
+ CWIDTH : positive := 2; -- clock interval counter width
+ CEDIV : positive := 3; -- clock interval divider
+ DWIDTH : positive := 8); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- reset
+ CE_INT : in slbit; -- clock interval enable (usec or msec)
+ DI : in slv(DWIDTH-1 downto 0); -- data in
+ DO : out slv(DWIDTH-1 downto 0) -- data out
+ );
+end component;
+
+component gray_cnt_gen is -- gray code counter, generic vector
+ generic (
+ DWIDTH : positive := 4); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- reset
+ CE : in slbit := '1'; -- count enable
+ DATA : out slv(DWIDTH-1 downto 0) -- data out
+ );
+end component;
+
+component gray_cnt_4 is -- 4 bit gray code counter (ROM based)
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- reset
+ CE : in slbit := '1'; -- count enable
+ DATA : out slv4 -- data out
+ );
+end component;
+
+component gray_cnt_5 is -- 5 bit gray code counter (ROM based)
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- reset
+ CE : in slbit := '1'; -- count enable
+ DATA : out slv5 -- data out
+ );
+end component;
+
+component gray_cnt_n is -- n bit gray code counter
+ generic (
+ DWIDTH : positive := 8); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- reset
+ CE : in slbit := '1'; -- count enable
+ DATA : out slv(DWIDTH-1 downto 0) -- data out
+ );
+end component;
+
+component gray2bin_gen is -- gray->bin converter, generic vector
+ generic (
+ DWIDTH : positive := 4); -- data width
+ port (
+ DI : in slv(DWIDTH-1 downto 0); -- gray code input
+ DO : out slv(DWIDTH-1 downto 0) -- binary code output
+ );
+end component;
+
+component timer is -- retriggerable timer
+ generic (
+ TWIDTH : positive := 4; -- timer counter width
+ RETRIG : boolean := true); -- re-triggerable true/false
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DELAY : in slv(TWIDTH-1 downto 0) := (others=>'1'); -- timer delay
+ START : in slbit; -- start timer
+ STOP : in slbit := '0'; -- stop timer
+ DONE : out slbit; -- mark last delay cycle
+ BUSY : out slbit -- timer running
+ );
+end component;
+
+end genlib;
Index: genlib/clkdivce.vhd
===================================================================
--- genlib/clkdivce.vhd (nonexistent)
+++ genlib/clkdivce.vhd (revision 7)
@@ -0,0 +1,114 @@
+-- $Id: clkdivce.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: clkgen - syn
+-- Description: Generate usec and msec enable signals
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-30 62 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity clkdivce is -- generate usec/msec ce pulses
+ generic (
+ CDUWIDTH : positive := 6; -- usec clock divider width
+ USECDIV : positive := 50; -- divider ratio for usec pulse
+ MSECDIV : positive := 1000); -- divider ratio for msec pulse
+ port (
+ CLK : in slbit; -- input clock
+ CE_USEC : out slbit; -- usec pulse
+ CE_MSEC : out slbit -- msec pulse
+ );
+end clkdivce;
+
+
+architecture syn of clkdivce is
+
+ type regs_type is record
+ ucnt : slv(CDUWIDTH-1 downto 0); -- usec clock divider counter
+ mcnt : slv10; -- msec clock divider counter
+ usec : slbit; -- usec pulse
+ msec : slbit; -- msec pulse
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ conv_std_logic_vector(USECDIV-1,CDUWIDTH),
+ conv_std_logic_vector(MSECDIV-1,10),
+ '0','0'
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ assert USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024
+ report "assert(USECDIV <= 2**CDUWIDTH and MSECDIV <= 1024): " &
+ "USECDIV too large for given CDUWIDTH or MSECDIV>1024"
+ severity FAILURE;
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ R_REGS <= N_REGS;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ n.usec := '0';
+ n.msec := '0';
+
+ n.ucnt := unsigned(r.ucnt) - 1;
+ if unsigned(r.ucnt) = 0 then
+ n.usec := '1';
+ n.ucnt := conv_std_logic_vector(USECDIV-1,CDUWIDTH);
+ n.mcnt := unsigned(r.mcnt) - 1;
+ if unsigned(r.mcnt) = 0 then
+ n.msec := '1';
+ n.mcnt := conv_std_logic_vector(MSECDIV-1,10);
+ end if;
+ end if;
+
+ N_REGS <= n;
+
+ CE_USEC <= r.usec;
+ CE_MSEC <= r.msec;
+
+ end process proc_next;
+
+
+end syn;
Index: genlib/clkdivce.vbom
===================================================================
--- genlib/clkdivce.vbom (nonexistent)
+++ genlib/clkdivce.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+clkdivce.vhd
Index: genlib/debounce_gen.vhd
===================================================================
--- genlib/debounce_gen.vhd (nonexistent)
+++ genlib/debounce_gen.vhd (revision 7)
@@ -0,0 +1,132 @@
+-- $Id: debounce_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: debounce_gen - syn
+-- Description: Generic signal debouncer
+--
+-- Dependencies: -
+-- Test bench: tb/tb_debounce_gen
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-12-26 105 1.0.2 add default for RESET
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-29 61 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity debounce_gen is -- debounce, generic vector
+ generic (
+ CWIDTH : positive := 2; -- clock interval counter width
+ CEDIV : positive := 3; -- clock interval divider
+ DWIDTH : positive := 8); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit := '0'; -- reset
+ CE_INT : in slbit; -- clock interval enable (usec or msec)
+ DI : in slv(DWIDTH-1 downto 0); -- data in
+ DO : out slv(DWIDTH-1 downto 0) -- data out
+ );
+end entity debounce_gen;
+
+
+architecture syn of debounce_gen is
+
+ constant cntzero : slv(CWIDTH-1 downto 0) := (others=>'0');
+ constant datazero : slv(dWIDTH-1 downto 0) := (others=>'0');
+
+ type regs_type is record
+ cecnt : slv(CWIDTH-1 downto 0); -- clock interval counter
+ dref : slv(DWIDTH-1 downto 0); -- data reference
+ dchange : slv(DWIDTH-1 downto 0); -- data change flag
+ dout : slv(DWIDTH-1 downto 0); -- data output
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ cntzero,
+ datazero,
+ datazero,
+ datazero
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ assert CEDIV<=2**CWIDTH report "assert(CEDIV<=2**CWIDTH)" severity failure;
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS.cecnt <= cntzero;
+ R_REGS.dref <= DI;
+ R_REGS.dchange <= datazero;
+ R_REGS.dout <= DI;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, CE_INT, DI)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ for i in DI'range loop
+ if DI(i) /= r.dref(i) then
+ n.dchange(i) := '1';
+ end if;
+ end loop;
+
+ if CE_INT = '1' then
+ if unsigned(r.cecnt) = 0 then
+ n.cecnt := conv_std_logic_vector(CEDIV-1,CWIDTH);
+ n.dref := DI;
+ n.dchange := datazero;
+ for i in DI'range loop
+ if r.dchange(i) = '0' then
+ n.dout(i) := r.dref(i);
+ end if;
+ end loop;
+
+ else
+ n.cecnt := unsigned(r.cecnt) - 1;
+ end if;
+ end if;
+
+ N_REGS <= n;
+
+ DO <= r.dout;
+
+ end process proc_next;
+
+
+end syn;
+
Index: genlib/Makefile
===================================================================
--- genlib/Makefile (nonexistent)
+++ genlib/Makefile (revision 7)
@@ -0,0 +1,23 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-12-09 100 1.1.1 drop ISE_p definition
+# 2007-06-03 47 1.1 use Makefile.xflow
+# 2007-06-03 45 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: genlib
===================================================================
--- genlib (nonexistent)
+++ genlib (revision 7)
genlib
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: comlib/misc/gen_crc8_tbl_check.vhd
===================================================================
--- comlib/misc/gen_crc8_tbl_check.vhd (nonexistent)
+++ comlib/misc/gen_crc8_tbl_check.vhd (revision 7)
@@ -0,0 +1,100 @@
+-- $Id: gen_crc8_tbl_check.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: gen_crc8_tbl - sim
+-- Description: stand-alone program to test crc8 transition table
+--
+-- Dependencies: -
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-07-08 65 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+--use work.slvtypes.all;
+--use work.comlib.all;
+
+entity gen_crc8_tbl_check is
+end gen_crc8_tbl_check;
+
+architecture sim of gen_crc8_tbl_check is
+begin
+
+ process
+ type crc8_tbl_type is array (0 to 255) of integer;
+
+ variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
+ ( 0, 29, 58, 39, 116, 105, 78, 83,
+ 232, 245, 210, 207, 156, 129, 166, 187,
+ 205, 208, 247, 234, 185, 164, 131, 158,
+ 37, 56, 31, 2, 81, 76, 107, 118,
+ 135, 154, 189, 160, 243, 238, 201, 212,
+ 111, 114, 85, 72, 27, 6, 33, 60,
+ 74, 87, 112, 109, 62, 35, 4, 25,
+ 162, 191, 152, 133, 214, 203, 236, 241,
+ 19, 14, 41, 52, 103, 122, 93, 64,
+ 251, 230, 193, 220, 143, 146, 181, 168,
+ 222, 195, 228, 249, 170, 183, 144, 141,
+ 54, 43, 12, 17, 66, 95, 120, 101,
+ 148, 137, 174, 179, 224, 253, 218, 199,
+ 124, 97, 70, 91, 8, 21, 50, 47,
+ 89, 68, 99, 126, 45, 48, 23, 10,
+ 177, 172, 139, 150, 197, 216, 255, 226,
+ 38, 59, 28, 1, 82, 79, 104, 117,
+ 206, 211, 244, 233, 186, 167, 128, 157,
+ 235, 246, 209, 204, 159, 130, 165, 184,
+ 3, 30, 57, 36, 119, 106, 77, 80,
+ 161, 188, 155, 134, 213, 200, 239, 242,
+ 73, 84, 115, 110, 61, 32, 7, 26,
+ 108, 113, 86, 75, 24, 5, 34, 63,
+ 132, 153, 190, 163, 240, 237, 202, 215,
+ 53, 40, 15, 18, 65, 92, 123, 102,
+ 221, 192, 231, 250, 169, 180, 147, 142,
+ 248, 229, 194, 223, 140, 145, 182, 171,
+ 16, 13, 42, 55, 100, 121, 94, 67,
+ 178, 175, 136, 149, 198, 219, 252, 225,
+ 90, 71, 96, 125, 46, 51, 20, 9,
+ 127, 98, 69, 88, 11, 22, 49, 44,
+ 151, 138, 173, 176, 227, 254, 217, 196
+ );
+
+ variable crc : integer := 0;
+ variable oline : line;
+
+ begin
+
+ loop_i: for i in 0 to 255 loop
+ write(oline, i, right, 4);
+ write(oline, string'(": cycle length = "));
+ crc := i;
+ loop_n: for n in 1 to 256 loop
+ crc := crc8_tbl(crc);
+ if crc = i then
+ write(oline, n, right, 4);
+ writeline(output, oline);
+ exit loop_n;
+ end if;
+ end loop; -- n
+ end loop; -- i
+ wait;
+ end process;
+
+end sim;
Index: comlib/misc/gen_crc8_tbl_check.vbom
===================================================================
--- comlib/misc/gen_crc8_tbl_check.vbom (nonexistent)
+++ comlib/misc/gen_crc8_tbl_check.vbom (revision 7)
@@ -0,0 +1,6 @@
+#libs
+#../../slvtypes.vhd
+#../comlib.vhd
+#components
+#design
+gen_crc8_tbl_check.vhd
Index: comlib/misc/gen_crc8_tbl.vhd
===================================================================
--- comlib/misc/gen_crc8_tbl.vhd (nonexistent)
+++ comlib/misc/gen_crc8_tbl.vhd (revision 7)
@@ -0,0 +1,61 @@
+-- $Id: gen_crc8_tbl.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: gen_crc8_tbl - sim
+-- Description: stand-alone program to print crc8 transition table
+--
+-- Dependencies: comlib/crc8_update (procedure)
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-07-08 65 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.comlib.all;
+
+entity gen_crc8_tbl is
+end gen_crc8_tbl;
+
+architecture sim of gen_crc8_tbl is
+begin
+
+ process
+ variable crc : slv8 := (others=>'0');
+ variable dat : slv8 := (others=>'0');
+ variable oline : line;
+ begin
+ for i in 0 to 255 loop
+ crc := (others=>'0');
+ dat := conv_std_logic_vector(i,8);
+ crc8_update(crc, dat);
+ write(oline, conv_integer(unsigned(crc)), right, 4);
+ if i /= 255 then
+ write(oline, string'(","));
+ end if;
+ if (i mod 8) = 7 then
+ writeline(output, oline);
+ end if;
+ end loop; -- i
+ wait;
+ end process;
+
+end sim;
Index: comlib/misc/gen_crc8_tbl.vbom
===================================================================
--- comlib/misc/gen_crc8_tbl.vbom (nonexistent)
+++ comlib/misc/gen_crc8_tbl.vbom (revision 7)
@@ -0,0 +1,6 @@
+#libs
+../../slvtypes.vhd
+../comlib.vhd
+#components
+#design
+gen_crc8_tbl.vhd
Index: comlib/misc/Makefile
===================================================================
--- comlib/misc/Makefile (nonexistent)
+++ comlib/misc/Makefile (revision 7)
@@ -0,0 +1,25 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-11-26 98 1.0 Initial version
+#
+EXE_all = gen_crc8_tbl gen_crc8_tbl_check
+#
+#
+.phony : all clean
+#
+all : $(EXE_all)
+#
+clean : ghdl_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
+#-----
+#
Index: comlib/misc/.cvsignore
===================================================================
--- comlib/misc/.cvsignore (nonexistent)
+++ comlib/misc/.cvsignore (revision 7)
@@ -0,0 +1,2 @@
+gen_crc8_tbl
+gen_crc8_tbl_check
Index: comlib/misc
===================================================================
--- comlib/misc (nonexistent)
+++ comlib/misc (revision 7)
comlib/misc
Property changes :
Added: svn:ignore
## -0,0 +1,34 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+gen_crc8_tbl
+gen_crc8_tbl_check
Index: comlib/crc8.vhd
===================================================================
--- comlib/crc8.vhd (nonexistent)
+++ comlib/crc8.vhd (revision 7)
@@ -0,0 +1,101 @@
+-- $Id: crc8.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: crc8 - syn
+-- Description: 8bit CRC generator, use CRC-8-SAE J1850 polynomial.
+-- Based on CRC-8-SAE J1850 polynomial:
+-- x^8 + x^4 + x^3 + x^2 + 1 (0x1d)
+-- It is irreducible, and can be implemented with <= 54 xor's
+--
+-- Notes: # XST synthesis for a Spartan-3 gives:
+-- 1-bit xor2 : 11
+-- 1-bit xor4 : 5
+-- 1-bit xor5 : 1
+-- Number of 4 input LUTs: 20
+-- # Synthesis with crc8_update_tbl gives a lut-rom based table
+-- design. Even though a 256x8 bit ROM is behind, the optimizer
+-- gets it into 12 slices with 22 4 input LUTs, thus only
+-- little larger than with xor's.
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-07-08 65 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.comlib.all;
+
+entity crc8 is -- crc-8 generator, checker
+ generic (
+ INIT: slv8 := "00000000"); -- initial state of crc register
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ ENA : in slbit; -- update enable
+ DI : in slv8; -- input data
+ CRC : out slv8 -- crc code
+ );
+end crc8;
+
+
+architecture syn of crc8 is
+
+ signal R_CRC : slv8 := INIT; -- state registers
+ signal N_CRC : slv8 := INIT; -- next value state regs
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_CRC <= INIT;
+ else
+ R_CRC <= N_CRC;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_CRC, DI, ENA)
+
+ variable r : slv8 := INIT;
+ variable n : slv8 := INIT;
+
+ begin
+
+ r := R_CRC;
+ n := R_CRC;
+
+ if ENA = '1' then
+ crc8_update(n, DI);
+ end if;
+
+ N_CRC <= n;
+
+ CRC <= R_CRC;
+
+ end process proc_next;
+
+
+end syn;
Index: comlib/crc8.vbom
===================================================================
--- comlib/crc8.vbom (nonexistent)
+++ comlib/crc8.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../slvtypes.vhd
+comlib.vhd
+# design
+crc8.vhd
Index: comlib/cdata2byte.vhd
===================================================================
--- comlib/cdata2byte.vhd (nonexistent)
+++ comlib/cdata2byte.vhd (revision 7)
@@ -0,0 +1,168 @@
+-- $Id: cdata2byte.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: cdata2byte - syn
+-- Description: 9 bit comma,data to Byte stream converter
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-30 62 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity cdata2byte is -- 9bit comma,data -> byte stream
+ generic (
+ CPREF : slv4 := "1000"; -- comma prefix
+ NCOMM : positive := 4); -- number of comma chars
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ DI : in slv9; -- input data; bit 8 = komma flag
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv8; -- output data
+ VAL : out slbit; -- read valid
+ HOLD : in slbit -- read hold
+ );
+end cdata2byte;
+
+
+architecture syn of cdata2byte is
+
+ type state_type is (
+ s_idle,
+ s_data,
+ s_comma,
+ s_escape,
+ s_edata
+ );
+
+ type regs_type is record
+ data : slv8; -- current data
+ state : state_type; -- state
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ (others=>'0'),
+ s_idle
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ assert NCOMM <= 14
+ report "assert(NCOMM <= 14)"
+ severity FAILURE;
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, DI, ENA, HOLD)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable ido : slv8 := (others=>'0');
+ variable ival : slbit := '0';
+ variable ibusy : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ ido := r.data;
+ ival := '0';
+ ibusy := '1';
+
+ case r.state is
+
+ when s_idle =>
+ ibusy := '0';
+ if ENA = '1' then
+ n.data := DI(7 downto 0);
+ n.state := s_data;
+ if DI(8) = '1' then
+ n.state := s_comma;
+ else
+ if DI(7 downto 4)=CPREF and
+ (DI(3 downto 0)="1111" or
+ unsigned(DI(3 downto 0))<=NCOMM) then
+ n.state := s_escape;
+ end if;
+ end if;
+ end if;
+
+ when s_data =>
+ ival := '1';
+ if HOLD = '0' then
+ n.state := s_idle;
+ end if;
+
+ when s_comma =>
+ ido := CPREF & r.data(3 downto 0);
+ ival := '1';
+ if HOLD = '0' then
+ n.state := s_idle;
+ end if;
+
+ when s_escape =>
+ ido := CPREF & "1111";
+ ival := '1';
+ if HOLD = '0' then
+ n.state := s_edata;
+ end if;
+
+ when s_edata =>
+ ido := (not CPREF) & r.data(3 downto 0);
+ ival := '1';
+ if HOLD = '0' then
+ n.state := s_idle;
+ end if;
+
+ when others => null;
+ end case;
+
+ N_REGS <= n;
+
+ DO <= ido;
+ VAL <= ival;
+ BUSY <= ibusy;
+
+ end process proc_next;
+
+
+end syn;
Index: comlib/byte2cdata.vhd
===================================================================
--- comlib/byte2cdata.vhd (nonexistent)
+++ comlib/byte2cdata.vhd (revision 7)
@@ -0,0 +1,149 @@
+-- $Id: byte2cdata.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: byte2cdata - syn
+-- Description: Byte stream to 9 bit comma,data converter
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-08-27 76 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity byte2cdata is -- byte stream -> 9bit comma,data
+ generic (
+ CPREF : slv4 := "1000"; -- comma prefix
+ NCOMM : positive := 4); -- number of comma chars
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ DI : in slv8; -- input data
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv9; -- output data; bit 8 = komma flag
+ VAL : out slbit; -- read valid
+ HOLD : in slbit -- read hold
+ );
+end byte2cdata;
+
+
+architecture syn of byte2cdata is
+
+ type state_type is (
+ s_idle,
+ s_data,
+ s_escape
+ );
+
+ type regs_type is record
+ data : slv9; -- current data
+ state : state_type; -- state
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ (others=>'0'),
+ s_idle
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ assert NCOMM <= 14
+ report "assert(NCOMM <= 14)"
+ severity FAILURE;
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, DI, ENA, HOLD)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable ival : slbit := '0';
+ variable ibusy : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ ival := '0';
+ ibusy := '1';
+
+ case r.state is
+
+ when s_idle =>
+ ibusy := '0';
+ if ENA = '1' then
+ n.data := "0" & DI;
+ n.state := s_data;
+ if DI(7 downto 4) = CPREF then
+ if DI(3 downto 0) = "1111" then
+ n.state := s_escape;
+ elsif unsigned(DI(3 downto 0)) <= NCOMM then
+ n.data := "10000" & DI(3 downto 0);
+ n.state := s_data;
+ end if;
+ end if;
+ end if;
+
+ when s_data =>
+ ival := '1';
+ if HOLD = '0' then
+ n.state := s_idle;
+ end if;
+
+ when s_escape =>
+ ibusy := '0';
+ if ENA = '1' then
+ n.data := "0" & CPREF & DI(3 downto 0);
+ n.state := s_data;
+ end if;
+
+ when others => null;
+ end case;
+
+ N_REGS <= n;
+
+ DO <= r.data;
+ VAL <= ival;
+ BUSY <= ibusy;
+
+ end process proc_next;
+
+
+end syn;
Index: comlib/byte2cdata.vbom
===================================================================
--- comlib/byte2cdata.vbom (nonexistent)
+++ comlib/byte2cdata.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+byte2cdata.vhd
Index: comlib/cdata2byte.vbom
===================================================================
--- comlib/cdata2byte.vbom (nonexistent)
+++ comlib/cdata2byte.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+cdata2byte.vhd
Index: comlib/comlib.vhd
===================================================================
--- comlib/comlib.vhd (nonexistent)
+++ comlib/comlib.vhd (revision 7)
@@ -0,0 +1,155 @@
+-- $Id: comlib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: comlib
+-- Description: communication components
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-12 88 1.2.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-07-08 65 1.2 added procedure crc8_update_tbl
+-- 2007-06-29 61 1.1.1 rename for crc8 SALT->INIT
+-- 2007-06-17 58 1.1 add crc8
+-- 2007-06-03 45 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+package comlib is
+
+component cdata2byte is -- 9bit comma,data -> byte stream
+ generic (
+ CPREF : slv4 := "1000"; -- comma prefix
+ NCOMM : positive := 4); -- number of comma chars
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ DI : in slv9; -- input data; bit 8 = komma flag
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv8; -- output data
+ VAL : out slbit; -- read valid
+ HOLD : in slbit -- read hold
+ );
+end component;
+
+component byte2cdata is -- byte stream -> 9bit comma,data
+ generic (
+ CPREF : slv4 := "1000"; -- comma prefix
+ NCOMM : positive := 4); -- number of comma chars
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ DI : in slv8; -- input data
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv9; -- output data; bit 8 = komma flag
+ VAL : out slbit; -- read valid
+ HOLD : in slbit -- read hold
+ );
+end component;
+
+component crc8 is -- crc-8 generator, checker
+ generic (
+ INIT: slv8 := "00000000"); -- initial state of crc register
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ ENA : in slbit; -- update enable
+ DI : in slv8; -- input data
+ CRC : out slv8 -- crc code
+ );
+end component;
+
+ procedure crc8_update (crc : inout slv8;
+ data : in slv8);
+ procedure crc8_update_tbl (crc : inout slv8;
+ data : in slv8);
+
+end comlib;
+
+-- ----------------------------------------------------------------------------
+
+package body comlib is
+
+ procedure crc8_update (crc : inout slv8;
+ data : in slv8) is
+ variable t : slv8 := (others=>'0');
+ begin
+
+ t := data xor crc;
+ crc(0) := t(0) xor t(4) xor t(5) xor t(6);
+ crc(1) := t(1) xor t(5) xor t(6) xor t(7);
+ crc(2) := t(0) xor t(2) xor t(4) xor t(5) xor t(7);
+ crc(3) := t(0) xor t(1) xor t(3) xor t(4);
+ crc(4) := t(0) xor t(1) xor t(2) xor t(6);
+ crc(5) := t(1) xor t(2) xor t(3) xor t(7);
+ crc(6) := t(2) xor t(3) xor t(4);
+ crc(7) := t(3) xor t(4) xor t(5);
+
+ end procedure crc8_update;
+
+ procedure crc8_update_tbl (crc : inout slv8;
+ data : in slv8) is
+
+ type crc8_tbl_type is array (0 to 255) of integer;
+ variable crc8_tbl : crc8_tbl_type := -- generated with gen_crc8_tbl
+ ( 0, 29, 58, 39, 116, 105, 78, 83,
+ 232, 245, 210, 207, 156, 129, 166, 187,
+ 205, 208, 247, 234, 185, 164, 131, 158,
+ 37, 56, 31, 2, 81, 76, 107, 118,
+ 135, 154, 189, 160, 243, 238, 201, 212,
+ 111, 114, 85, 72, 27, 6, 33, 60,
+ 74, 87, 112, 109, 62, 35, 4, 25,
+ 162, 191, 152, 133, 214, 203, 236, 241,
+ 19, 14, 41, 52, 103, 122, 93, 64,
+ 251, 230, 193, 220, 143, 146, 181, 168,
+ 222, 195, 228, 249, 170, 183, 144, 141,
+ 54, 43, 12, 17, 66, 95, 120, 101,
+ 148, 137, 174, 179, 224, 253, 218, 199,
+ 124, 97, 70, 91, 8, 21, 50, 47,
+ 89, 68, 99, 126, 45, 48, 23, 10,
+ 177, 172, 139, 150, 197, 216, 255, 226,
+ 38, 59, 28, 1, 82, 79, 104, 117,
+ 206, 211, 244, 233, 186, 167, 128, 157,
+ 235, 246, 209, 204, 159, 130, 165, 184,
+ 3, 30, 57, 36, 119, 106, 77, 80,
+ 161, 188, 155, 134, 213, 200, 239, 242,
+ 73, 84, 115, 110, 61, 32, 7, 26,
+ 108, 113, 86, 75, 24, 5, 34, 63,
+ 132, 153, 190, 163, 240, 237, 202, 215,
+ 53, 40, 15, 18, 65, 92, 123, 102,
+ 221, 192, 231, 250, 169, 180, 147, 142,
+ 248, 229, 194, 223, 140, 145, 182, 171,
+ 16, 13, 42, 55, 100, 121, 94, 67,
+ 178, 175, 136, 149, 198, 219, 252, 225,
+ 90, 71, 96, 125, 46, 51, 20, 9,
+ 127, 98, 69, 88, 11, 22, 49, 44,
+ 151, 138, 173, 176, 227, 254, 217, 196
+ );
+
+ begin
+
+ crc := conv_std_logic_vector(
+ crc8_tbl(conv_integer(unsigned(data xor crc))), 8);
+
+ end procedure crc8_update_tbl;
+
+end package body comlib;
Index: comlib/Makefile
===================================================================
--- comlib/Makefile (nonexistent)
+++ comlib/Makefile (revision 7)
@@ -0,0 +1,22 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-07-06 64 1.1 use Makefile.xflow
+# 2007-06-03 45 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: comlib
===================================================================
--- comlib (nonexistent)
+++ comlib (revision 7)
comlib
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: memlib/ram_2swsr_rfirst_gen.vhd
===================================================================
--- memlib/ram_2swsr_rfirst_gen.vhd (nonexistent)
+++ memlib/ram_2swsr_rfirst_gen.vhd (revision 7)
@@ -0,0 +1,103 @@
+-- $Id: ram_2swsr_rfirst_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2006-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: ram_2swsr_rfirst_gen - syn
+-- Description: Dual-Port RAM with with two synchronous read/write ports
+-- and 'read-before-write' semantics (as block RAM).
+-- The code is inspired by Xilinx example rams_16.vhd. The
+-- 'ram_style' attribute is set to 'block', this will
+-- force in XST a synthesis as block RAM.
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
+-- 2008-03-08 123 1.0.2 use std_logic_arith, not _unsigned; use unsigned();
+-- now initialize DO to all '0' at start
+-- 2008-03-02 122 1.0.1 change generic default for BRAM models
+-- 2007-06-03 45 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
+ generic (
+ AWIDTH : positive := 11; -- address port width
+ DWIDTH : positive := 9); -- data port width
+ port(
+ CLKA : in slbit; -- clock port A
+ CLKB : in slbit; -- clock port B
+ ENA : in slbit; -- enable port A
+ ENB : in slbit; -- enable port B
+ WEA : in slbit; -- write enable port A
+ WEB : in slbit; -- write enable port B
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DIA : in slv(DWIDTH-1 downto 0); -- data in port A
+ DIB : in slv(DWIDTH-1 downto 0); -- data in port B
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end ram_2swsr_rfirst_gen;
+
+
+architecture syn of ram_2swsr_rfirst_gen is
+ constant memsize : positive := 2**AWIDTH;
+ constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
+ type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
+ shared variable sv_ram : ram_type := (others=>datzero);
+
+ attribute ram_style : string;
+ attribute ram_style of sv_ram : variable is "block";
+
+ signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
+ signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
+
+begin
+
+ proc_clka: process (CLKA)
+ begin
+ if CLKA'event and CLKA='1' then
+ if ENA = '1' then
+ R_DOA <= sv_ram(conv_integer(unsigned(ADDRA)));
+ if WEA = '1' then
+ sv_ram(conv_integer(unsigned(ADDRA))) := DIA;
+ end if;
+ end if;
+ end if;
+ end process proc_clka;
+
+ proc_clkb: process (CLKB)
+ begin
+ if CLKB'event and CLKB='1' then
+ if ENB = '1' then
+ R_DOB <= sv_ram(conv_integer(unsigned(ADDRB)));
+ if WEB = '1' then
+ sv_ram(conv_integer(unsigned(ADDRB))) := DIB;
+ end if;
+ end if;
+ end if;
+ end process proc_clkb;
+
+ DOA <= R_DOA;
+ DOB <= R_DOB;
+
+end syn;
Index: memlib/fifo_1c_dram_raw.vbom
===================================================================
--- memlib/fifo_1c_dram_raw.vbom (nonexistent)
+++ memlib/fifo_1c_dram_raw.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../slvtypes.vhd
+memlib.vhd
+# components
+[ghdl,isim]ram_1swar_1ar_gen.vbom
+[xst]ram_1swar_1ar_gen_unisim.vbom
+# design
+fifo_1c_dram_raw.vhd
Index: memlib/memlib.vhd
===================================================================
--- memlib/memlib.vhd (nonexistent)
+++ memlib/memlib.vhd (revision 7)
@@ -0,0 +1,238 @@
+-- $Id: memlib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2006-2007 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: memlib
+-- Description: Basic memory components: single/dual port synchronous and
+-- asynchronus rams; Fifo's.
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
+-- 2008-03-02 122 1.0.2 change generic default for BRAM models
+-- 2007-12-27 106 1.0.1 add fifo_2c_dram
+-- 2007-06-03 45 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package memlib is
+
+component ram_1swar_gen is -- RAM, 1 sync w asyn r port
+ generic (
+ AWIDTH : positive := 4; -- address port width
+ DWIDTH : positive := 16); -- data port width
+ port (
+ CLK : in slbit; -- clock
+ WE : in slbit; -- write enable
+ ADDR : in slv(AWIDTH-1 downto 0); -- address port
+ DI : in slv(DWIDTH-1 downto 0); -- data in port
+ DO : out slv(DWIDTH-1 downto 0) -- data out port
+ );
+end component;
+
+component ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
+ generic (
+ AWIDTH : positive := 4; -- address port width
+ DWIDTH : positive := 16); -- data port width
+ port (
+ CLK : in slbit; -- clock
+ WE : in slbit; -- write enable (port A)
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end component;
+
+component ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
+ generic (
+ AWIDTH : positive := 10; -- address port width
+ DWIDTH : positive := 16); -- data port width
+ port(
+ CLK : in slbit; -- clock
+ EN : in slbit; -- enable
+ WE : in slbit; -- write enable
+ ADDR : in slv(AWIDTH-1 downto 0); -- address port
+ DI : in slv(DWIDTH-1 downto 0); -- data in port
+ DO : out slv(DWIDTH-1 downto 0) -- data out port
+ );
+end component;
+
+component ram_1swsr_rfirst_gen is -- RAM, 1 sync r/w ports, read first
+ generic (
+ AWIDTH : positive := 11; -- address port width
+ DWIDTH : positive := 9); -- data port width
+ port(
+ CLK : in slbit; -- clock
+ EN : in slbit; -- enable
+ WE : in slbit; -- write enable
+ ADDR : in slv(AWIDTH-1 downto 0); -- address port
+ DI : in slv(DWIDTH-1 downto 0); -- data in port
+ DO : out slv(DWIDTH-1 downto 0) -- data out port
+ );
+end component;
+
+component ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
+ generic (
+ AWIDTH : positive := 11; -- address port width
+ DWIDTH : positive := 9); -- data port width
+ port(
+ CLKA : in slbit; -- clock port A
+ CLKB : in slbit; -- clock port B
+ ENA : in slbit; -- enable port A
+ ENB : in slbit; -- enable port B
+ WEA : in slbit; -- write enable port A
+ WEB : in slbit; -- write enable port B
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DIA : in slv(DWIDTH-1 downto 0); -- data in port A
+ DIB : in slv(DWIDTH-1 downto 0); -- data in port B
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end component;
+
+component ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
+ generic (
+ AWIDTH : positive := 11; -- address port width
+ DWIDTH : positive := 9); -- data port width
+ port(
+ CLKA : in slbit; -- clock port A
+ CLKB : in slbit; -- clock port B
+ ENA : in slbit; -- enable port A
+ ENB : in slbit; -- enable port B
+ WEA : in slbit; -- write enable port A
+ WEB : in slbit; -- write enable port B
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DIA : in slv(DWIDTH-1 downto 0); -- data in port A
+ DIB : in slv(DWIDTH-1 downto 0); -- data in port B
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end component;
+
+component ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w port
+ generic (
+ AWIDTH : positive := 11; -- address port width
+ DWIDTH : positive := 9; -- data port width
+ WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
+ port(
+ CLK : in slbit; -- clock
+ EN : in slbit; -- enable
+ WE : in slbit; -- write enable
+ ADDR : in slv(AWIDTH-1 downto 0); -- address
+ DI : in slv(DWIDTH-1 downto 0); -- data in
+ DO : out slv(DWIDTH-1 downto 0) -- data out
+ );
+end component;
+
+component ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
+ generic (
+ AWIDTH : positive := 11; -- address port width
+ DWIDTH : positive := 9; -- data port width
+ WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
+ port(
+ CLKA : in slbit; -- clock port A
+ CLKB : in slbit; -- clock port B
+ ENA : in slbit; -- enable port A
+ ENB : in slbit; -- enable port B
+ WEA : in slbit; -- write enable port A
+ WEB : in slbit; -- write enable port B
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DIA : in slv(DWIDTH-1 downto 0); -- data in port A
+ DIB : in slv(DWIDTH-1 downto 0); -- data in port B
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end component;
+
+component fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
+ generic (
+ AWIDTH : positive := 4; -- address width (sets size)
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ WE : in slbit; -- write enable
+ RE : in slbit; -- read enable
+ DI : in slv(DWIDTH-1 downto 0); -- input data
+ DO : out slv(DWIDTH-1 downto 0); -- output data
+ SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
+ EMPTY : out slbit; -- empty flag
+ FULL : out slbit -- full flag
+ );
+end component;
+
+component fifo_1c_dram is -- fifo, 1 clock, dram based
+ generic (
+ AWIDTH : positive := 4; -- address width (sets size)
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ DI : in slv(DWIDTH-1 downto 0); -- input data
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv(DWIDTH-1 downto 0); -- output data
+ VAL : out slbit; -- read valid
+ HOLD : in slbit; -- read hold
+ SIZE : out slv(AWIDTH downto 0) -- number of used slots
+ );
+end component;
+
+component fifo_1c_bubble is -- fifo, 1 clock, bubble regs
+ generic (
+ NSTAGE : positive := 4; -- number of stages
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ DI : in slv(DWIDTH-1 downto 0); -- input data
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv(DWIDTH-1 downto 0); -- output data
+ VAL : out slbit; -- read valid
+ HOLD : in slbit -- read hold
+ );
+end component;
+
+component fifo_2c_dram is -- fifo, 2 clock, dram based
+ generic (
+ AWIDTH : positive := 4; -- address width (sets size)
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLKW : in slbit; -- clock (write side)
+ CLKR : in slbit; -- clock (read side)
+ RESETW : in slbit; -- reset (synchronous with CLKW)
+ RESETR : in slbit; -- reset (synchronous with CLKR)
+ DI : in slv(DWIDTH-1 downto 0); -- input data
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv(DWIDTH-1 downto 0); -- output data
+ VAL : out slbit; -- read valid
+ HOLD : in slbit; -- read hold
+ SIZEW : out slv(AWIDTH-1 downto 0); -- number slots to write (synch w/ CLKW)
+ SIZER : out slv(AWIDTH-1 downto 0) -- number slots to read (synch w/ CLKR)
+ );
+end component;
+
+end memlib;
Index: memlib/ram_1swar_gen.vbom
===================================================================
--- memlib/ram_1swar_gen.vbom (nonexistent)
+++ memlib/ram_1swar_gen.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+ram_1swar_gen.vhd
Index: memlib/ram_2swsr_rfirst_gen_unisim.vbom
===================================================================
--- memlib/ram_2swsr_rfirst_gen_unisim.vbom (nonexistent)
+++ memlib/ram_2swsr_rfirst_gen_unisim.vbom (revision 7)
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+memlib.vhd
+# components
+ram_2swsr_xfirst_gen_unisim.vbom
+# design
+ram_2swsr_rfirst_gen_unisim.vhd
Index: memlib/ram_1swar_gen_unisim.vhd
===================================================================
--- memlib/ram_1swar_gen_unisim.vhd (nonexistent)
+++ memlib/ram_1swar_gen_unisim.vhd (revision 7)
@@ -0,0 +1,118 @@
+-- $Id: ram_1swar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2008- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: ram_1swar_gen_unisim - syn
+-- Description: Single-Port RAM with with one synchronous write and one
+-- asynchronius read port (as distributed RAM).
+-- Direct instantiation of Xilinx UNISIM primitives
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-03-08 123 1.0.1 use shorter label names
+-- 2008-03-02 122 1.0 Initial version
+--
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ALL;
+
+use work.slvtypes.all;
+
+entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
+ generic (
+ AWIDTH : positive := 4; -- address port width
+ DWIDTH : positive := 16); -- data port width
+ port (
+ CLK : in slbit; -- clock
+ WE : in slbit; -- write enable
+ ADDR : in slv(AWIDTH-1 downto 0); -- address port
+ DI : in slv(DWIDTH-1 downto 0); -- data in port
+ DO : out slv(DWIDTH-1 downto 0) -- data out port
+ );
+end ram_1swar_gen;
+
+
+architecture syn of ram_1swar_gen is
+
+begin
+
+ assert AWIDTH>=4 and AWIDTH<=6
+ report "assert(AWIDTH>=4 and AWIDTH<=6): only 4..6 bit AWIDTH supported"
+ severity failure;
+
+ AW_4: if AWIDTH = 4 generate
+ GL: for i in DWIDTH-1 downto 0 generate
+ MEM : RAM16X1S
+ generic map (
+ INIT => X"0000")
+ port map (
+ O => DO(i),
+ A0 => ADDR(0),
+ A1 => ADDR(1),
+ A2 => ADDR(2),
+ A3 => ADDR(3),
+ D => DI(i),
+ WCLK => CLK,
+ WE => WE
+ );
+ end generate GL;
+ end generate AW_4;
+
+ AW_5: if AWIDTH = 5 generate
+ GL: for i in DWIDTH-1 downto 0 generate
+ MEM : RAM32X1S
+ generic map (
+ INIT => X"00000000")
+ port map (
+ O => DO(i),
+ A0 => ADDR(0),
+ A1 => ADDR(1),
+ A2 => ADDR(2),
+ A3 => ADDR(3),
+ A4 => ADDR(4),
+ D => DI(i),
+ WCLK => CLK,
+ WE => WE
+ );
+ end generate GL;
+ end generate AW_5;
+
+ AW_6: if AWIDTH = 6 generate
+ GL: for i in DWIDTH-1 downto 0 generate
+ MEM : RAM64X1S
+ generic map (
+ INIT => X"0000000000000000")
+ port map (
+ O => DO(i),
+ A0 => ADDR(0),
+ A1 => ADDR(1),
+ A2 => ADDR(2),
+ A3 => ADDR(3),
+ A4 => ADDR(4),
+ A5 => ADDR(5),
+ D => DI(i),
+ WCLK => CLK,
+ WE => WE
+ );
+ end generate GL;
+ end generate AW_6;
+
+end syn;
Index: memlib/fifo_1c_dram.vhd
===================================================================
--- memlib/fifo_1c_dram.vhd (nonexistent)
+++ memlib/fifo_1c_dram.vhd (revision 7)
@@ -0,0 +1,95 @@
+-- $Id: fifo_1c_dram.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: fifo_1c_dram - syn
+-- Description: FIFO, single clock domain, distributed RAM based, with
+-- enable/busy/valid/hold interface.
+--
+-- Dependencies: fifo_1c_dram_raw
+--
+-- Test bench: tb/tb_fifo_1c_dram
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-06-06 49 1.0 Initial version
+--
+-- Some synthesis results:
+-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
+-- AWIDTH DWIDTH LUT.l LUT.m Flop clock(xst est.)
+-- 4 16 31 32 22 153MHz ( 16 words)
+-- 5 16 49 64 23 120MHz ( 32 words)
+-- 6 16 70 128 23 120MHz ( 64 words)
+-- 7 16 111 256 30 120MHz (128 words)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+
+entity fifo_1c_dram is -- fifo, 1 clock, dram based
+ generic (
+ AWIDTH : positive := 7; -- address width (sets size)
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ DI : in slv(DWIDTH-1 downto 0); -- input data
+ ENA : in slbit; -- write enable
+ BUSY : out slbit; -- write port hold
+ DO : out slv(DWIDTH-1 downto 0); -- output data
+ VAL : out slbit; -- read valid
+ HOLD : in slbit; -- read hold
+ SIZE : out slv(AWIDTH downto 0) -- number of used slots
+ );
+end fifo_1c_dram;
+
+
+architecture syn of fifo_1c_dram is
+
+ signal WE : slbit := '0';
+ signal RE : slbit := '0';
+ signal SIZE_L : slv(AWIDTH-1 downto 0) := (others=>'0');
+ signal EMPTY : slbit := '0';
+ signal FULL : slbit := '0';
+
+begin
+
+ FIFO : fifo_1c_dram_raw
+ generic map (
+ AWIDTH => AWIDTH,
+ DWIDTH => DWIDTH)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ WE => WE,
+ RE => RE,
+ DI => DI,
+ DO => DO,
+ SIZE => SIZE_L,
+ EMPTY => EMPTY,
+ FULL => FULL
+ );
+
+ WE <= ENA and (not FULL);
+ RE <= (not EMPTY) and (not HOLD);
+
+ BUSY <= FULL;
+ VAL <= not EMPTY;
+ SIZE <= FULL & SIZE_L;
+
+end syn;
Index: memlib/ram_1swar_1ar_gen.vbom
===================================================================
--- memlib/ram_1swar_1ar_gen.vbom (nonexistent)
+++ memlib/ram_1swar_1ar_gen.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+ram_1swar_1ar_gen.vhd
Index: memlib/ram_1swar_1ar_gen_unisim.vhd
===================================================================
--- memlib/ram_1swar_1ar_gen_unisim.vhd (nonexistent)
+++ memlib/ram_1swar_1ar_gen_unisim.vhd (revision 7)
@@ -0,0 +1,170 @@
+-- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2008-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: ram_1swar_1ar_gen - syn
+-- Description: Dual-Port RAM with with one synchronous write and two
+-- asynchronius read ports (as distributed RAM).
+-- Direct instantiation of Xilinx UNISIM primitives
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's
+-- 2008-03-08 123 1.0.1 use shorter label names
+-- 2008-03-02 122 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ALL;
+
+use work.slvtypes.all;
+
+entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
+ generic (
+ AWIDTH : positive := 4; -- address port width
+ DWIDTH : positive := 16); -- data port width
+ port (
+ CLK : in slbit; -- clock
+ WE : in slbit; -- write enable (port A)
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end ram_1swar_1ar_gen;
+
+
+architecture syn of ram_1swar_1ar_gen is
+
+begin
+
+ assert AWIDTH>=4 and AWIDTH<=5
+ report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported"
+ severity failure;
+
+ AW_4: if AWIDTH = 4 generate
+ GL: for i in DWIDTH-1 downto 0 generate
+ MEM : RAM16X1D
+ generic map (
+ INIT => X"0000")
+ port map (
+ DPO => DOB(i),
+ SPO => DOA(i),
+ A0 => ADDRA(0),
+ A1 => ADDRA(1),
+ A2 => ADDRA(2),
+ A3 => ADDRA(3),
+ D => DI(i),
+ DPRA0 => ADDRB(0),
+ DPRA1 => ADDRB(1),
+ DPRA2 => ADDRB(2),
+ DPRA3 => ADDRB(3),
+ WCLK => CLK,
+ WE => WE
+ );
+ end generate GL;
+ end generate AW_4;
+
+ -- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge..
+ AW_5: if AWIDTH = 5 generate
+ signal WE0 : slbit := '0';
+ signal WE1 : slbit := '0';
+ signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0');
+ signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0');
+ signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0');
+ signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0');
+ begin
+ WE0 <= WE and not ADDRA(4);
+ WE1 <= WE and ADDRA(4);
+ GL: for i in DWIDTH-1 downto 0 generate
+ MEM0 : RAM16X1D
+ generic map (
+ INIT => X"0000")
+ port map (
+ DPO => DOB0(i),
+ SPO => DOA0(i),
+ A0 => ADDRA(0),
+ A1 => ADDRA(1),
+ A2 => ADDRA(2),
+ A3 => ADDRA(3),
+ D => DI(i),
+ DPRA0 => ADDRB(0),
+ DPRA1 => ADDRB(1),
+ DPRA2 => ADDRB(2),
+ DPRA3 => ADDRB(3),
+ WCLK => CLK,
+ WE => WE0
+ );
+ MEM1 : RAM16X1D
+ generic map (
+ INIT => X"0000")
+ port map (
+ DPO => DOB1(i),
+ SPO => DOA1(i),
+ A0 => ADDRA(0),
+ A1 => ADDRA(1),
+ A2 => ADDRA(2),
+ A3 => ADDRA(3),
+ D => DI(i),
+ DPRA0 => ADDRB(0),
+ DPRA1 => ADDRB(1),
+ DPRA2 => ADDRB(2),
+ DPRA3 => ADDRB(3),
+ WCLK => CLK,
+ WE => WE1
+ );
+ DOA <= DOA0 when ADDRA(4)='0' else DOA1;
+ DOB <= DOB0 when ADDRB(4)='0' else DOB1;
+ end generate GL;
+ end generate AW_5;
+
+-- AW_6: if AWIDTH = 6 generate
+-- GL: for i in DWIDTH-1 downto 0 generate
+-- MEM : RAM64X1D
+-- generic map (
+-- INIT => X"0000000000000000")
+-- port map (
+-- DPO => DOB(i),
+-- SPO => DOA(i),
+-- A0 => ADDRA(0),
+-- A1 => ADDRA(1),
+-- A2 => ADDRA(2),
+-- A3 => ADDRA(3),
+-- A4 => ADDRA(4),
+-- A5 => ADDRA(5),
+-- D => DI(i),
+-- DPRA0 => ADDRB(0),
+-- DPRA1 => ADDRB(1),
+-- DPRA2 => ADDRB(2),
+-- DPRA3 => ADDRB(3),
+-- DPRA4 => ADDRB(4),
+-- DPRA5 => ADDRB(5),
+-- WCLK => CLK,
+-- WE => WE
+-- );
+-- end generate GL;
+-- end generate AW_6;
+
+end syn;
+
+-- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong.
+-- The annotation states that DPO is the port A output and SPO is port B
+-- output. The text before is correct, DPO is port B and SPO is port A.
Index: memlib/ram_2swsr_xfirst_gen_unisim.vbom
===================================================================
--- memlib/ram_2swsr_xfirst_gen_unisim.vbom (nonexistent)
+++ memlib/ram_2swsr_xfirst_gen_unisim.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../slvtypes.vhd
+@lib:unisim
+# design
+ram_2swsr_xfirst_gen_unisim.vhd
Index: memlib/fifo_1c_dram_raw.vhd
===================================================================
--- memlib/fifo_1c_dram_raw.vhd (nonexistent)
+++ memlib/fifo_1c_dram_raw.vhd (revision 7)
@@ -0,0 +1,160 @@
+-- $Id: fifo_1c_dram_raw.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: fifo_1c_dram_raw - syn
+-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
+-- interface exposing dram signals.
+--
+-- Dependencies: ram_1swar_1ar_gen
+--
+-- Test bench: tb/tb_fifo_1c_dram
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-03 47 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+
+entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
+ generic (
+ AWIDTH : positive := 4; -- address width (sets size)
+ DWIDTH : positive := 16); -- data width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ WE : in slbit; -- write enable
+ RE : in slbit; -- read enable
+ DI : in slv(DWIDTH-1 downto 0); -- input data
+ DO : out slv(DWIDTH-1 downto 0); -- output data
+ SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
+ EMPTY : out slbit; -- empty flag
+ FULL : out slbit -- full flag
+ );
+end fifo_1c_dram_raw;
+
+
+architecture syn of fifo_1c_dram_raw is
+
+ type regs_type is record
+ waddr : slv(AWIDTH-1 downto 0); -- write address
+ raddr : slv(AWIDTH-1 downto 0); -- read address
+ empty : slbit; -- empty flag
+ full : slbit; -- full flag
+ end record regs_type;
+
+ constant memsize : positive := 2**AWIDTH;
+ constant regs_init : regs_type := (
+ conv_std_logic_vector(0,AWIDTH),
+ conv_std_logic_vector(0,AWIDTH),
+ '1','0'
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ signal RAM_WE : slbit := '0';
+
+begin
+
+ RAM : ram_1swar_1ar_gen
+ generic map (
+ AWIDTH => AWIDTH,
+ DWIDTH => DWIDTH)
+ port map (
+ CLK => CLK,
+ WE => RAM_WE,
+ ADDRA => R_REGS.waddr,
+ ADDRB => R_REGS.raddr,
+ DI => DI,
+ DOA => open,
+ DOB => DO
+ );
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ R_REGS <= N_REGS;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, RESET, WE, RE)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
+
+ variable we_val : slbit := '0';
+ variable re_val : slbit := '0';
+ variable iram_we : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ re_val := RE and not r.empty;
+ we_val := WE and ((not r.full) or RE);
+ isize := unsigned(r.waddr) - unsigned(r.raddr);
+ iram_we := '0';
+
+ if RESET = '1' then
+ n := regs_init;
+
+ else
+
+ if we_val = '1' then
+ n.waddr := unsigned(r.waddr) + 1;
+ iram_we := '1';
+ if re_val = '0' then
+ n.empty := '0';
+ if unsigned(isize) = memsize-1 then
+ n.full := '1';
+ end if;
+ end if;
+ end if;
+
+ if re_val = '1' then
+ n.raddr := unsigned(r.raddr) + 1;
+ if we_val = '0' then
+ n.full := '0';
+ if unsigned(isize) = 1 then
+ n.empty := '1';
+ end if;
+ end if;
+ end if;
+
+ end if;
+
+ N_REGS <= n;
+
+ RAM_WE <= iram_we;
+
+ SIZE <= isize;
+ EMPTY <= r.empty;
+ FULL <= r.full;
+
+ end process proc_next;
+
+end syn;
Index: memlib/ram_2swsr_rfirst_gen.vbom
===================================================================
--- memlib/ram_2swsr_rfirst_gen.vbom (nonexistent)
+++ memlib/ram_2swsr_rfirst_gen.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+ram_2swsr_rfirst_gen.vhd
Index: memlib/ram_2swsr_rfirst_gen_unisim.vhd
===================================================================
--- memlib/ram_2swsr_rfirst_gen_unisim.vhd (nonexistent)
+++ memlib/ram_2swsr_rfirst_gen_unisim.vhd (revision 7)
@@ -0,0 +1,83 @@
+-- $Id: ram_2swsr_rfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2008- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: ram_2swsr_rfirst_gen - syn
+-- Description: Dual-Port RAM with with two synchronous read/write ports
+-- and 'read-before-write' semantics (as block RAM).
+-- Direct instantiation of Xilinx UNISIM primitives
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: Spartan-3, Virtex-2,-4
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
+-- 2008-03-02 122 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ALL;
+
+use work.slvtypes.all;
+use work.memlib.all;
+
+entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
+ generic (
+ AWIDTH : positive := 13; -- address port width 11/9 or 13/8
+ DWIDTH : positive := 8); -- data port width
+ port(
+ CLKA : in slbit; -- clock port A
+ CLKB : in slbit; -- clock port B
+ ENA : in slbit; -- enable port A
+ ENB : in slbit; -- enable port B
+ WEA : in slbit; -- write enable port A
+ WEB : in slbit; -- write enable port B
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DIA : in slv(DWIDTH-1 downto 0); -- data in port A
+ DIB : in slv(DWIDTH-1 downto 0); -- data in port B
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end ram_2swsr_rfirst_gen;
+
+
+architecture syn of ram_2swsr_rfirst_gen is
+begin
+
+ UMEM: ram_2swsr_xfirst_gen_unisim
+ generic map (
+ AWIDTH => AWIDTH,
+ DWIDTH => DWIDTH,
+ WRITE_MODE => "READ_FIRST")
+ port map (
+ CLKA => CLKA,
+ CLKB => CLKB,
+ ENA => ENA,
+ ENB => ENB,
+ WEA => WEA,
+ WEB => WEB,
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ DIA => DIA,
+ DIB => DIB,
+ DOA => DOA,
+ DOB => DOB
+ );
+
+end syn;
Index: memlib/ram_1swar_gen.vhd
===================================================================
--- memlib/ram_1swar_gen.vhd (nonexistent)
+++ memlib/ram_1swar_gen.vhd (revision 7)
@@ -0,0 +1,81 @@
+-- $Id: ram_1swar_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2006-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: ram_1swar_gen - syn
+-- Description: Single-Port RAM with with one synchronous write and one
+-- asynchronius read port (as distributed RAM).
+-- The code is inspired by Xilinx example rams_04.vhd. The
+-- 'ram_style' attribute is set to 'distributed', this will
+-- force in XST a synthesis as distributed RAM.
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-03-08 123 1.0.1 use std_logic_arith, not _unsigned; use unsigned()
+-- 2007-06-03 45 1.0 Initial version
+--
+-- Some synthesis results:
+-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
+-- AWIDTH DWIDTH LUTl LUTm Comments
+-- 4 16 - 16 16*RAM16X1S
+-- 5 16 - 32 16*RAM32X1S
+-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
+ generic (
+ AWIDTH : positive := 4; -- address port width
+ DWIDTH : positive := 16); -- data port width
+ port (
+ CLK : in slbit; -- clock
+ WE : in slbit; -- write enable
+ ADDR : in slv(AWIDTH-1 downto 0); -- address port
+ DI : in slv(DWIDTH-1 downto 0); -- data in port
+ DO : out slv(DWIDTH-1 downto 0) -- data out port
+ );
+end ram_1swar_gen;
+
+
+architecture syn of ram_1swar_gen is
+ constant memsize : positive := 2**AWIDTH;
+ constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
+ type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
+ signal RAM : ram_type := (others=>datzero);
+
+ attribute ram_style : string;
+ attribute ram_style of RAM : signal is "distributed";
+
+begin
+
+ proc_clk: process (CLK)
+ begin
+ if CLK'event and CLK='1' then
+ if WE = '1' then
+ RAM(conv_integer(unsigned(ADDR))) <= DI;
+ end if;
+ end if;
+ end process proc_clk;
+
+ DO <= RAM(conv_integer(unsigned(ADDR)));
+
+end syn;
Index: memlib/ram_1swar_1ar_gen.vhd
===================================================================
--- memlib/ram_1swar_1ar_gen.vhd (nonexistent)
+++ memlib/ram_1swar_1ar_gen.vhd (revision 7)
@@ -0,0 +1,88 @@
+-- $Id: ram_1swar_1ar_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2006-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: ram_1swar_1ar_gen - syn
+-- Description: Dual-Port RAM with with one synchronous write and two
+-- asynchronius read ports (as distributed RAM).
+-- The code is inspired by Xilinx example rams_09.vhd. The
+-- 'ram_style' attribute is set to 'distributed', this will
+-- force in XST a synthesis as distributed RAM.
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-03-08 123 1.0.1 use std_logic_arith, not _unsigned; use unsigned()
+-- 2007-06-03 45 1.0 Initial version
+--
+-- Some synthesis results:
+-- - 2010-06-03 ise 11.4 for xc3s1000-ft256-4:
+-- AWIDTH DWIDTH LUTl LUTm Comments
+-- 4 16 - 32 16*RAM16X1D
+-- 5 16 34 64 32*RAM16X1D
+-- 6 16 68 128 64*RAM16X1D, 32*MUXF5
+-- 7 16 136 256 128*RAM16X1D, 64*MUXF5, 32*MUXF6
+-- 8 16 292 512 256*RAM16X1D,144*MUXF5, 64*MUXF6, 32*MUXF7
+-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
+-- {same results as above for AW=4 and 6}
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
+ generic (
+ AWIDTH : positive := 4; -- address port width
+ DWIDTH : positive := 16); -- data port width
+ port (
+ CLK : in slbit; -- clock
+ WE : in slbit; -- write enable (port A)
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end ram_1swar_1ar_gen;
+
+
+architecture syn of ram_1swar_1ar_gen is
+ constant memsize : positive := 2**AWIDTH;
+ constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
+ type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
+ signal RAM : ram_type := (others=>datzero);
+
+ attribute ram_style : string;
+ attribute ram_style of RAM : signal is "distributed";
+
+begin
+
+ proc_clk: process (CLK)
+ begin
+ if CLK'event and CLK='1' then
+ if WE = '1' then
+ RAM(conv_integer(unsigned(ADDRA))) <= DI;
+ end if;
+ end if;
+ end process proc_clk;
+
+ DOA <= RAM(conv_integer(unsigned(ADDRA)));
+ DOB <= RAM(conv_integer(unsigned(ADDRB)));
+
+end syn;
Index: memlib/fifo_1c_dram.vbom
===================================================================
--- memlib/fifo_1c_dram.vbom (nonexistent)
+++ memlib/fifo_1c_dram.vbom (revision 7)
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+memlib.vhd
+# components
+fifo_1c_dram_raw.vbom
+# design
+fifo_1c_dram.vhd
Index: memlib/ram_2swsr_xfirst_gen_unisim.vhd
===================================================================
--- memlib/ram_2swsr_xfirst_gen_unisim.vhd (nonexistent)
+++ memlib/ram_2swsr_xfirst_gen_unisim.vhd (revision 7)
@@ -0,0 +1,435 @@
+-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2008- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
+-- Description: Dual-Port RAM with with two synchronous read/write ports
+-- Direct instantiation of Xilinx UNISIM primitives
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: Spartan-3, Virtex-2,-4
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
+-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ALL;
+
+use work.slvtypes.all;
+
+entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
+ generic (
+ AWIDTH : positive := 11; -- address port width
+ DWIDTH : positive := 9; -- data port width
+ WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
+ port(
+ CLKA : in slbit; -- clock port A
+ CLKB : in slbit; -- clock port B
+ ENA : in slbit; -- enable port A
+ ENB : in slbit; -- enable port B
+ WEA : in slbit; -- write enable port A
+ WEB : in slbit; -- write enable port B
+ ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
+ ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
+ DIA : in slv(DWIDTH-1 downto 0); -- data in port A
+ DIB : in slv(DWIDTH-1 downto 0); -- data in port B
+ DOA : out slv(DWIDTH-1 downto 0); -- data out port A
+ DOB : out slv(DWIDTH-1 downto 0) -- data out port B
+ );
+end ram_2swsr_xfirst_gen_unisim;
+
+
+architecture syn of ram_2swsr_xfirst_gen_unisim is
+
+ constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
+ ((DWIDTH+35)/36)=((DWIDTH+31)/32);
+ constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
+ ((DWIDTH+17)/18)=((DWIDTH+16)/16);
+ constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
+ ((DWIDTH+8)/9)=((DWIDTH+7)/8);
+
+begin
+
+ assert AWIDTH>=9 and AWIDTH<=14
+ report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
+ severity failure;
+
+ AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
+ constant dw_mem : positive := ((DWIDTH+35)/36)*36;
+ signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
+ begin
+
+ L_DIA(DIA'range) <= DIA;
+ L_DIB(DIB'range) <= DIB;
+
+ GL: for i in dw_mem/36-1 downto 0 generate
+ MEM : RAMB16_S36_S36
+ generic map (
+ INIT_A => O"000000000000",
+ INIT_B => O"000000000000",
+ SRVAL_A => O"000000000000",
+ SRVAL_B => O"000000000000",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => L_DOA(36*i+31 downto 36*i),
+ DOB => L_DOB(36*i+31 downto 36*i),
+ DOPA => L_DOA(36*i+35 downto 36*i+32),
+ DOPB => L_DOB(36*i+35 downto 36*i+32),
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => L_DIA(36*i+31 downto 36*i),
+ DIB => L_DIB(36*i+31 downto 36*i),
+ DIPA => L_DIA(36*i+35 downto 36*i+32),
+ DIPB => L_DIB(36*i+35 downto 36*i+32),
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+
+ DOA <= L_DOA(DOA'range);
+ DOB <= L_DOB(DOB'range);
+
+ end generate AW_09_S36;
+
+ AW_09_S32: if AWIDTH=9 and ok_mod32 generate
+ GL: for i in DWIDTH/32-1 downto 0 generate
+ MEM : RAMB16_S36_S36
+ generic map (
+ INIT_A => X"00000000",
+ INIT_B => X"00000000",
+ SRVAL_A => X"00000000",
+ SRVAL_B => X"00000000",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => DOA(32*i+31 downto 32*i),
+ DOB => DOB(32*i+31 downto 32*i),
+ DOPA => open,
+ DOPB => open,
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => DIA(32*i+31 downto 32*i),
+ DIB => DIB(32*i+31 downto 32*i),
+ DIPA => "0000",
+ DIPB => "0000",
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+ end generate AW_09_S32;
+
+ AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
+ constant dw_mem : positive := ((DWIDTH+17)/18)*18;
+ signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
+ begin
+
+ L_DIA(DIA'range) <= DIA;
+ L_DIB(DIB'range) <= DIB;
+
+ GL: for i in dw_mem/18-1 downto 0 generate
+ MEM : RAMB16_S18_S18
+ generic map (
+ INIT_A => O"000000",
+ INIT_B => O"000000",
+ SRVAL_A => O"000000",
+ SRVAL_B => O"000000",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => L_DOA(18*i+15 downto 18*i),
+ DOB => L_DOB(18*i+15 downto 18*i),
+ DOPA => L_DOA(18*i+17 downto 18*i+16),
+ DOPB => L_DOB(18*i+17 downto 18*i+16),
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => L_DIA(18*i+15 downto 18*i),
+ DIB => L_DIB(18*i+15 downto 18*i),
+ DIPA => L_DIA(18*i+17 downto 18*i+16),
+ DIPB => L_DIB(18*i+17 downto 18*i+16),
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+
+ DOA <= L_DOA(DOA'range);
+ DOB <= L_DOB(DOB'range);
+
+ end generate AW_10_S18;
+
+ AW_10_S16: if AWIDTH=10 and ok_mod16 generate
+ GL: for i in DWIDTH/16-1 downto 0 generate
+ MEM : RAMB16_S18_S18
+ generic map (
+ INIT_A => X"0000",
+ INIT_B => X"0000",
+ SRVAL_A => X"0000",
+ SRVAL_B => X"0000",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => DOA(16*i+15 downto 16*i),
+ DOB => DOB(16*i+15 downto 16*i),
+ DOPA => open,
+ DOPB => open,
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => DIA(16*i+15 downto 16*i),
+ DIB => DIB(16*i+15 downto 16*i),
+ DIPA => "00",
+ DIPB => "00",
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+ end generate AW_10_S16;
+
+ AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
+ constant dw_mem : positive := ((DWIDTH+8)/9)*9;
+ signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
+ begin
+
+ L_DIA(DIA'range) <= DIA;
+ L_DIB(DIB'range) <= DIB;
+
+ GL: for i in dw_mem/9-1 downto 0 generate
+ MEM : RAMB16_S9_S9
+ generic map (
+ INIT_A => O"000",
+ INIT_B => O"000",
+ SRVAL_A => O"000",
+ SRVAL_B => O"000",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => L_DOA(9*i+7 downto 9*i),
+ DOB => L_DOB(9*i+7 downto 9*i),
+ DOPA => L_DOA(9*i+8 downto 9*i+8),
+ DOPB => L_DOB(9*i+8 downto 9*i+8),
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => L_DIA(9*i+7 downto 9*i),
+ DIB => L_DIB(9*i+7 downto 9*i),
+ DIPA => L_DIA(9*i+8 downto 9*i+8),
+ DIPB => L_DIB(9*i+8 downto 9*i+8),
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+
+ DOA <= L_DOA(DOA'range);
+ DOB <= L_DOB(DOB'range);
+
+ end generate AW_11_S9;
+
+ AW_11_S8: if AWIDTH=11 and ok_mod08 generate
+ GL: for i in DWIDTH/8-1 downto 0 generate
+ MEM : RAMB16_S9_S9
+ generic map (
+ INIT_A => X"00",
+ INIT_B => X"00",
+ SRVAL_A => X"00",
+ SRVAL_B => X"00",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => DOA(8*i+7 downto 8*i),
+ DOB => DOB(8*i+7 downto 8*i),
+ DOPA => open,
+ DOPB => open,
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => DIA(8*i+7 downto 8*i),
+ DIB => DIB(8*i+7 downto 8*i),
+ DIPA => "0",
+ DIPB => "0",
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+ end generate AW_11_S8;
+
+ AW_12_S4: if AWIDTH = 12 generate
+ constant dw_mem : positive := ((DWIDTH+3)/4)*4;
+ signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
+ begin
+
+ L_DIA(DIA'range) <= DIA;
+ L_DIB(DIB'range) <= DIB;
+
+ GL: for i in dw_mem/4-1 downto 0 generate
+ MEM : RAMB16_S4_S4
+ generic map (
+ INIT_A => X"0",
+ INIT_B => X"0",
+ SRVAL_A => X"0",
+ SRVAL_B => X"0",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => L_DOA(4*i+3 downto 4*i),
+ DOB => L_DOB(4*i+3 downto 4*i),
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => L_DIA(4*i+3 downto 4*i),
+ DIB => L_DIB(4*i+3 downto 4*i),
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+
+ DOA <= L_DOA(DOA'range);
+ DOB <= L_DOB(DOB'range);
+
+ end generate AW_12_S4;
+
+ AW_13_S2: if AWIDTH = 13 generate
+ constant dw_mem : positive := ((DWIDTH+1)/2)*2;
+ signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
+ signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
+ begin
+
+ L_DIA(DIA'range) <= DIA;
+ L_DIB(DIB'range) <= DIB;
+
+ GL: for i in dw_mem/2-1 downto 0 generate
+ MEM : RAMB16_S2_S2
+ generic map (
+ INIT_A => "00",
+ INIT_B => "00",
+ SRVAL_A => "00",
+ SRVAL_B => "00",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => L_DOA(2*i+1 downto 2*i),
+ DOB => L_DOB(2*i+1 downto 2*i),
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => L_DIA(2*i+1 downto 2*i),
+ DIB => L_DIB(2*i+1 downto 2*i),
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+
+ DOA <= L_DOA(DOA'range);
+ DOB <= L_DOB(DOB'range);
+
+ end generate AW_13_S2;
+
+ AW_14_S1: if AWIDTH = 14 generate
+ GL: for i in DWIDTH-1 downto 0 generate
+ MEM : RAMB16_S1_S1
+ generic map (
+ INIT_A => "0",
+ INIT_B => "0",
+ SRVAL_A => "0",
+ SRVAL_B => "0",
+ WRITE_MODE_A => WRITE_MODE,
+ WRITE_MODE_B => WRITE_MODE)
+ port map (
+ DOA => DOA(i downto i),
+ DOB => DOB(i downto i),
+ ADDRA => ADDRA,
+ ADDRB => ADDRB,
+ CLKA => CLKA,
+ CLKB => CLKB,
+ DIA => DIA(i downto i),
+ DIB => DIB(i downto i),
+ ENA => ENA,
+ ENB => ENB,
+ SSRA => '0',
+ SSRB => '0',
+ WEA => WEA,
+ WEB => WEB
+ );
+ end generate GL;
+ end generate AW_14_S1;
+
+
+end syn;
+
+-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
+-- nonsense: INIT_A : bit_vector := X"000";
+-- This is a 12 bit value, while a 9 bit one is needed. Thus the
+-- explicit definition above.
Index: memlib/ram_1swar_gen_unisim.vbom
===================================================================
--- memlib/ram_1swar_gen_unisim.vbom (nonexistent)
+++ memlib/ram_1swar_gen_unisim.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../slvtypes.vhd
+@lib:unisim
+# design
+ram_1swar_gen_unisim.vhd
Index: memlib/Makefile
===================================================================
--- memlib/Makefile (nonexistent)
+++ memlib/Makefile (revision 7)
@@ -0,0 +1,22 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-12-09 100 1.0.1 drop ISE_p definition
+# 2007-06-03 45 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: memlib/ram_1swar_1ar_gen_unisim.vbom
===================================================================
--- memlib/ram_1swar_1ar_gen_unisim.vbom (nonexistent)
+++ memlib/ram_1swar_1ar_gen_unisim.vbom (revision 7)
@@ -0,0 +1,5 @@
+# libs
+../slvtypes.vhd
+@lib:unisim
+# design
+ram_1swar_1ar_gen_unisim.vhd
Index: memlib
===================================================================
--- memlib (nonexistent)
+++ memlib (revision 7)
memlib
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: serport/tb/tb_serport_uart_rxtx.vhd
===================================================================
--- serport/tb/tb_serport_uart_rxtx.vhd (nonexistent)
+++ serport/tb/tb_serport_uart_rxtx.vhd (revision 7)
@@ -0,0 +1,262 @@
+-- $Id: tb_serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_serport_uart_rxtx - sim
+-- Description: Test bench for serport_uart_rxtx
+--
+-- Dependencies: simlib/simclk
+-- tbd_serport_uart_rxtx [UUT]
+--
+-- To test: serport_uart_rxtx
+--
+-- Target Devices: generic
+--
+-- Verified (with tb_serport_uart_rxtx_stim.dat):
+-- Date Rev Code ghdl ise Target Comment
+-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
+-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
+-- 2007-10-21 91 - 0.26 - - c:ok
+-- 2007-10-14 89 - 0.26 - - c:ok
+-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
+-- 2007-10-12 88 - 0.26 - - c:ok
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
+-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
+-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-08-27 76 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.simlib.all;
+use work.serport.all;
+
+entity tb_serport_uart_rxtx is
+end tb_serport_uart_rxtx;
+
+architecture sim of tb_serport_uart_rxtx is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+ signal CLKDIV : slv13 := conv_std_logic_vector(15, 13);
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXERR : slbit := '0';
+ signal RXACT : slbit := '0';
+ signal TXSD : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal CLK_STOP : slbit := '0';
+ signal CLK_CYCLE : slv31 := (others=>'0');
+
+ signal N_MON_VAL : slbit := '0';
+ signal N_MON_DAT : slv8 := (others=>'0');
+ signal R_MON_VAL_1 : slbit := '0';
+ signal R_MON_DAT_1 : slv8 := (others=>'0');
+ signal R_MON_VAL_2 : slbit := '0';
+ signal R_MON_DAT_2 : slv8 := (others=>'0');
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant setup_time : time := 5 ns;
+ constant c2out_time : time := 10 ns;
+
+begin
+
+ SYSCLK : simclk
+ generic map (
+ PERIOD => clock_period,
+ OFFSET => clock_offset)
+ port map (
+ CLK => CLK,
+ CLK_CYCLE => CLK_CYCLE,
+ CLK_STOP => CLK_STOP
+ );
+
+ UUT : entity work.tbd_serport_uart_rxtx
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLKDIV => CLKDIV,
+ RXSD => TXSD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD => TXSD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+
+ proc_stim: process
+ file fstim : text open read_mode is "tb_serport_uart_rxtx_stim";
+ variable iline : line;
+ variable oline : line;
+ variable idelta : integer := 0;
+ variable itxdata : slv8 := (others=>'0');
+ variable ok : boolean;
+ variable dname : string(1 to 6) := (others=>' ');
+ variable irate : integer := 16;
+
+ begin
+
+ wait for clock_offset - setup_time;
+
+ file_loop: while not endfile(fstim) loop
+
+ readline (fstim, iline);
+
+ readcomment(iline, ok);
+ next file_loop when ok;
+
+ readword(iline, dname, ok);
+ if ok then
+ case dname is
+ when ".reset" => -- .reset
+ write(oline, string'(".reset"));
+ writeline(output, oline);
+ RESET <= '1';
+ wait for clock_period;
+ RESET <= '0';
+ wait for 9*clock_period;
+
+ when ".wait " => -- .wait
+ read_ea(iline, idelta);
+ wait for idelta*clock_period;
+
+ when ".rate " => -- .rate
+ read_ea(iline, irate);
+ CLKDIV <= conv_std_logic_vector(irate-1, 13);
+
+ when "send " => -- send
+ read_ea(iline, idelta);
+ read_ea(iline, itxdata);
+
+ while TXBUSY='1' loop
+ wait for clock_period;
+ end loop;
+
+ wait for idelta*clock_period;
+
+ writetimestamp(oline, CLK_CYCLE, ": send ");
+ write(oline, itxdata, right, 10);
+ writeline(output, oline);
+
+ TXDATA <= itxdata;
+ TXENA <= '1';
+ N_MON_VAL <= '1';
+ N_MON_DAT <= itxdata;
+
+ wait for clock_period;
+ TXENA <= '0';
+ N_MON_VAL <= '0';
+
+ when others => -- unknown command
+ write(oline, string'("?? unknown command: "));
+ write(oline, dname);
+ writeline(output, oline);
+ report "aborting" severity failure;
+ end case;
+
+ else
+ report "failed to find command" severity failure;
+
+ end if;
+
+ testempty_ea(iline);
+ end loop; -- file_loop
+
+ idelta := 0;
+ while TXBUSY='1' or RXACT='1' loop
+ wait for clock_period;
+ idelta := idelta + 1;
+ exit when idelta>3000;
+ end loop;
+
+ writetimestamp(oline, CLK_CYCLE, ": DONE ");
+ writeline(output, oline);
+
+ wait for 12*irate*clock_period;
+
+ CLK_STOP <= '1';
+
+ wait; -- suspend proc_stim forever
+ -- clock is stopped, sim will end
+
+ end process proc_stim;
+
+
+ proc_moni: process
+ variable oline : line;
+ begin
+
+ loop
+ wait until CLK'event and CLK='1';
+
+ if R_MON_VAL_1 = '1' then
+ if R_MON_VAL_2 = '1' then
+ writetimestamp(oline, CLK_CYCLE, ": moni ");
+ write(oline, string'(" FAIL MISSING DATA="));
+ write(oline, R_MON_DAT_2);
+ writeline(output, oline);
+ end if;
+ R_MON_VAL_2 <= R_MON_VAL_1;
+ R_MON_DAT_2 <= R_MON_DAT_1;
+ end if;
+
+ R_MON_VAL_1 <= N_MON_VAL;
+ R_MON_DAT_1 <= N_MON_DAT;
+
+ if RXVAL='1' or RXERR='1' then
+ writetimestamp(oline, CLK_CYCLE, ": moni ");
+ write(oline, RXDATA, right, 10);
+ if RXERR = '1' then
+ write(oline, string'(" RXERR=1"));
+ end if;
+
+ if R_MON_VAL_2 = '0' then
+ write(oline, string'(" FAIL UNEXPECTED"));
+ else
+ write(oline, string'(" CHECK"));
+ R_MON_VAL_2 <= '0';
+
+ if R_MON_DAT_2 = RXDATA and
+ RXERR='0' then
+ write(oline, string'(" OK"));
+ else
+ write(oline, string'(" FAIL"));
+ end if;
+
+ end if;
+
+ writeline(output, oline);
+ end if;
+
+ end loop;
+
+ end process proc_moni;
+
+end sim;
Index: serport/tb/tb_serport_uart_rx_ssim.vbom
===================================================================
--- serport/tb/tb_serport_uart_rx_ssim.vbom (nonexistent)
+++ serport/tb/tb_serport_uart_rx_ssim.vbom (revision 7)
@@ -0,0 +1,4 @@
+# configure for _*sim case
+tbd_serport_uart_rx = tbd_serport_uart_rx_ssim.vhd
+tb_serport_uart_rx.vbom
+@top:tb_serport_uart_rx
Index: serport/tb/tbd_serport_uart_rxtx.vhd
===================================================================
--- serport/tb/tbd_serport_uart_rxtx.vhd (nonexistent)
+++ serport/tb/tbd_serport_uart_rxtx.vhd (revision 7)
@@ -0,0 +1,87 @@
+-- $Id: tbd_serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tbd_serport_uart_rxtx - syn
+-- Description: Wrapper for serport_uart_rxtx to avoid records. It
+-- has a port interface which will not be modified by xst
+-- synthesis (no records, no generic port).
+--
+-- Dependencies: serport_uart_rxtx
+--
+-- To test: serport_uart_rxtx
+--
+-- Target Devices: generic
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 69 122 0 - t 9.13
+-- 2007-10-27 92 9.1 J30 xc3s1000-4 69 122 0 - t 9.13
+-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 73 152 0 81 s 9.30
+-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 73 125 0 - s 9.30
+--
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-21 91 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+
+entity tbd_serport_uart_rxtx is -- serial port uart [tb design]
+ -- generic: CDWIDTH=13
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv13; -- clock divider setting
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit; -- receiver active
+ TXSD : out slbit; -- transmit serial data (uart view)
+ TXDATA : in slv8; -- transmit data in
+ TXENA : in slbit; -- transmit data enable
+ TXBUSY : out slbit -- transmit busy
+ );
+end tbd_serport_uart_rxtx;
+
+
+architecture syn of tbd_serport_uart_rxtx is
+
+begin
+
+ UART : serport_uart_rxtx
+ generic map (
+ CDWIDTH => 13)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLKDIV => CLKDIV,
+ RXSD => RXSD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD => TXSD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+end syn;
Index: serport/tb/tb_serport_autobaud.vhd
===================================================================
--- serport/tb/tb_serport_autobaud.vhd (nonexistent)
+++ serport/tb/tb_serport_autobaud.vhd (revision 7)
@@ -0,0 +1,292 @@
+-- $Id: tb_serport_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_serport_autobaud - sim
+-- Description: Test bench for serport_autobaud
+--
+-- Dependencies: simlib/simclk
+-- tbd_serport_autobaud [UUT]
+--
+-- To test: serport_autobaud
+--
+-- Target Devices: generic
+--
+-- Verified (with tb_serport_autobaud_stim.dat):
+-- Date Rev Code ghdl ise Target Comment
+-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
+-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
+-- 2007-10-21 91 - 0.26 - - c:ok
+-- 2007-10-14 89 - 0.26 - - c:ok
+-- 2007-10-12 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
+-- 2007-10-12 88 - 0.26 - - c:ok
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-24 281 1.1.2 use direct instatiation for tbd_
+-- 2008-03-24 129 1.1.1 CLK_CYCLE now 31 bits
+-- 2007-10-21 91 1.1 now use 'send' command, self-checking (FAIL's)
+-- 2007-10-14 89 1.1 add extra stop bit for CLKDIV=0; drop c2out wait;
+-- add moni for autobauder
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-08-27 76 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.simlib.all;
+use work.serport.all;
+
+entity tb_serport_autobaud is
+end tb_serport_autobaud;
+
+architecture sim of tb_serport_autobaud is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+ signal RXSD : slbit := '0';
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+ signal CLKDIV : slv13 := (others=>'0');
+ signal ABACT : slbit := '0';
+ signal ABDONE : slbit := '0';
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXERR : slbit := '0';
+ signal RXACT : slbit := '0';
+ signal TXSD2 : slbit := '0';
+ signal RXDATA3 : slv8 := (others=>'0');
+ signal RXVAL3 : slbit := '0';
+ signal RXERR3 : slbit := '0';
+ signal RXACT3 : slbit := '0';
+
+ signal CLK_STOP : slbit := '0';
+ signal CLK_CYCLE : slv31 := (others=>'0');
+
+ signal N_MON_VAL : slbit := '0';
+ signal N_MON_DAT : slv8 := (others=>'0');
+ signal R_MON_VAL_1 : slbit := '0';
+ signal R_MON_DAT_1 : slv8 := (others=>'0');
+ signal R_MON_VAL_2 : slbit := '0';
+ signal R_MON_DAT_2 : slv8 := (others=>'0');
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant setup_time : time := 5 ns;
+ constant c2out_time : time := 10 ns;
+
+begin
+
+ SYSCLK : simclk
+ generic map (
+ PERIOD => clock_period,
+ OFFSET => clock_offset)
+ port map (
+ CLK => CLK,
+ CLK_CYCLE => CLK_CYCLE,
+ CLK_STOP => CLK_STOP
+ );
+
+ UUT : entity work.tbd_serport_autobaud
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ RXSD => RXSD,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC,
+ CLKDIV => CLKDIV,
+ ABACT => ABACT,
+ ABDONE => ABDONE,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD2 => TXSD2,
+ RXDATA3 => RXDATA3,
+ RXVAL3 => RXVAL3,
+ RXERR3 => RXERR3,
+ RXACT3 => RXACT3
+ );
+
+
+ proc_stim: process
+ file fstim : text open read_mode is "tb_serport_autobaud_stim";
+ variable iline : line;
+ variable oline : line;
+ variable ok : boolean;
+ variable dname : string(1 to 6) := (others=>' ');
+ variable idelta : integer := 0;
+ variable irate : integer := 16;
+ variable ival : slbit;
+ variable itxdata : slv8 := (others=>'0');
+
+ begin
+
+ RXSD <= '1';
+
+ wait for clock_offset - setup_time;
+
+ file_loop: while not endfile(fstim) loop
+
+ readline (fstim, iline);
+
+ readcomment(iline, ok);
+ next file_loop when ok;
+
+ readword(iline, dname, ok);
+ if ok then
+ case dname is
+ when ".reset" => -- .reset
+ write(oline, string'(".reset"));
+ writeline(output, oline);
+ RESET <= '1';
+ wait for clock_period;
+ RESET <= '0';
+ wait for 9*clock_period;
+
+ when ".break" => -- .break
+ read_ea(iline, idelta);
+ write(oline, string'(".break"));
+ writeline(output, oline);
+ RXSD <= '0';
+ wait for idelta*clock_period;
+ RXSD <= '1';
+
+ when ".wait " => -- .wait
+ read_ea(iline, idelta);
+ wait for idelta*clock_period;
+
+ when ".rate " => -- .rate
+ read_ea(iline, irate);
+
+ when "send " => -- send
+ read_ea(iline, ival);
+ read_ea(iline, itxdata);
+
+ writetimestamp(oline, CLK_CYCLE, ": send ");
+ write(oline, itxdata, right, 10);
+ writeline(output, oline);
+
+ RXSD <= '0'; -- start bit
+ N_MON_VAL <= ival;
+ N_MON_DAT <= itxdata;
+ wait for clock_period;
+ N_MON_VAL <= '0';
+ wait for (irate-1)*clock_period;
+ RXSD <= '1';
+
+ for i in itxdata'reverse_range loop -- transmit lsb first
+ RXSD <= itxdata(i); -- data bit
+ wait for irate*clock_period;
+ end loop;
+
+ RXSD <= '1'; -- stop bit (plus extra cycle)
+ wait for (irate+1)*clock_period;
+
+ when others => -- unknown command
+ write(oline, string'("?? unknown command: "));
+ write(oline, dname);
+ writeline(output, oline);
+ report "aborting" severity failure;
+ end case;
+
+ else
+ report "failed to find command" severity failure;
+
+ end if;
+
+ end loop;
+
+ writetimestamp(oline, CLK_CYCLE, ": DONE ");
+ writeline(output, oline);
+
+ wait for 25*irate*clock_period;
+
+ CLK_STOP <= '1';
+
+ wait; -- suspend proc_stim forever
+ -- clock is stopped, sim will end
+
+ end process proc_stim;
+
+
+ proc_moni: process
+ variable oline : line;
+ variable iabact : slbit := '0';
+ begin
+
+ loop
+ wait until CLK'event and CLK='1';
+
+ if R_MON_VAL_1 = '1' then
+ if R_MON_VAL_2 = '1' then
+ writetimestamp(oline, CLK_CYCLE, ": moni ");
+ write(oline, string'(" FAIL MISSING DATA="));
+ write(oline, R_MON_DAT_2);
+ writeline(output, oline);
+ end if;
+ R_MON_VAL_2 <= R_MON_VAL_1;
+ R_MON_DAT_2 <= R_MON_DAT_1;
+ end if;
+
+ R_MON_VAL_1 <= N_MON_VAL;
+ R_MON_DAT_1 <= N_MON_DAT;
+
+ if (ABACT xor iabact)='1' then
+ writetimestamp(oline, CLK_CYCLE, ": auto ABACT =");
+ write(oline, ABACT, right, 2);
+ iabact := ABACT;
+ writeline(output, oline);
+ end if;
+
+ if ABDONE = '1' then
+ writetimestamp(oline, CLK_CYCLE, ": auto CLKDIV =");
+ write(oline, conv_integer(unsigned(CLKDIV)), right, 3);
+ writeline(output, oline);
+ end if;
+
+ if RXVAL='1' or (ABACT='0' and RXERR='1' and unsigned(RXDATA)/=0) then
+ writetimestamp(oline, CLK_CYCLE, ": moni ");
+ write(oline, RXDATA, right, 10);
+ if RXERR = '1' then
+ write(oline, string'(" RXERR=1"));
+ end if;
+
+ if R_MON_VAL_2 = '0' then
+ write(oline, string'(" FAIL UNEXPECTED"));
+ else
+ write(oline, string'(" CHECK"));
+ R_MON_VAL_2 <= '0';
+
+ if R_MON_DAT_2 = RXDATA and
+ RXERR='0' then
+ write(oline, string'(" OK"));
+ else
+ write(oline, string'(" FAIL"));
+ end if;
+
+ end if;
+
+ writeline(output, oline);
+ end if;
+
+ end loop;
+
+ end process proc_moni;
+
+end sim;
Index: serport/tb/tb_serport_uart_rx.vbom
===================================================================
--- serport/tb/tb_serport_uart_rx.vbom (nonexistent)
+++ serport/tb/tb_serport_uart_rx.vbom (revision 7)
@@ -0,0 +1,9 @@
+# libs
+../../slvtypes.vhd
+../../simlib/simlib.vhd
+../serport.vhd
+# components
+../../simlib/simclk.vbom
+tbd_serport_uart_rx : tbd_serport_uart_rx.vbom
+# design
+tb_serport_uart_rx.vhd
Index: serport/tb/tb_serport_uart_rx_stim.dat
===================================================================
--- serport/tb/tb_serport_uart_rx_stim.dat (nonexistent)
+++ serport/tb/tb_serport_uart_rx_stim.dat (revision 7)
@@ -0,0 +1,529 @@
+# $Id: tb_serport_uart_rx_stim.dat 311 2010-06-30 17:52:37Z mueller $
+#
+#
+C setting rate=1 -> CLKDIV=0 ------------------------------------------------
+.wait 5
+.rate 1
+C test frame error (send 7,8,9,10 '0' bits, followed by 10 '1' bits)
+puls 1 0 11000000 0 7 1 10 -- VAL=1 ERR=0 DAT=11000000
+puls 1 0 10000000 0 8 1 10 -- VAL=1 ERR=0 DAT=10000000
+puls 1 0 00000000 0 9 1 10 -- VAL=1 ERR=0 DAT=00000000
+puls 1 1 00000000 0 10 1 10 -- VAL=1 ERR=1 DAT=00000000
+C test 1 stop bits
+puls 1 0 00000000 0 9 1 1 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 9 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 9 1 1 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 9 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
+C test 2 stop bits
+puls 1 0 00000000 0 9 1 2 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 10 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 9 1 2 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 10 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
+C test 3 stop bits
+puls 1 0 00000000 0 9 1 3 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 11 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 9 1 3 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 11 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
+C test 4 stop bits
+puls 1 0 00000000 0 9 1 4 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 12 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 9 1 4 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 1 1 12 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 00000001
+send 1 00000010
+send 1 00000100
+send 1 00001000
+send 1 00010000
+send 1 00100000
+send 1 01000000
+send 1 10000000
+send 1 11111110
+send 1 11111101
+send 1 11111011
+send 1 11110111
+send 1 11101111
+send 1 11011111
+send 1 10111111
+send 1 01111111
+send 1 00000000
+send 1 11111111
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
+C test data with 3 stop bits
+send 2 00000000
+send 2 00000001
+send 2 00000010
+send 2 00000100
+send 2 00001000
+send 2 00010000
+send 2 00100000
+send 2 01000000
+send 2 10000000
+send 2 11111110
+send 2 11111101
+send 2 11111011
+send 2 11110111
+send 2 11101111
+send 2 11011111
+send 2 10111111
+send 2 01111111
+send 2 00000000
+send 2 11111111
+send 2 00000011
+send 2 00001100
+send 2 00110000
+send 2 11000000
+#
+C setting rate=2 -> CLKDIV=1 ------------------------------------------------
+.wait 5
+.rate 2
+C test frame error (send 16,17,18,19,20 '0' bits, followed by 10 '1' bits)
+puls 1 0 10000000 0 16 1 10 -- VAL=1 ERR=0 DAT=10000000
+puls 1 0 10000000 0 17 1 10 -- VAL=1 ERR=0 DAT=10000000
+puls 1 0 00000000 0 18 1 10 -- VAL=1 ERR=0 DAT=00000000
+puls 1 0 00000000 0 19 1 10 -- VAL=1 ERR=0 DAT=00000000
+puls 1 1 00000000 0 20 1 10 -- VAL=1 ERR=1 DAT=00000000
+C test 1 stop bits
+puls 1 0 00000000 0 18 1 2 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 18 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 18 1 2 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 18 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
+C test 2 stop bits
+puls 1 0 00000000 0 18 1 4 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 20 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 18 1 4 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 20 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
+C test 3 stop bits
+puls 1 0 00000000 0 18 1 6 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 22 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 18 1 6 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 22 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
+C test 4 stop bits
+puls 1 0 00000000 0 18 1 8 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 24 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
+puls 1 0 00000000 0 18 1 8 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
+puls 1 0 11111111 0 2 1 24 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 00000001
+send 1 00000010
+send 1 00000100
+send 1 00001000
+send 1 00010000
+send 1 00100000
+send 1 01000000
+send 1 10000000
+send 1 11111110
+send 1 11111101
+send 1 11111011
+send 1 11110111
+send 1 11101111
+send 1 11011111
+send 1 10111111
+send 1 01111111
+send 1 00000000
+send 1 11111111
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
+C test data with 3 stop bits
+send 2 00000000
+send 2 00000001
+send 2 00000010
+send 2 00000100
+send 2 00001000
+send 2 00010000
+send 2 00100000
+send 2 01000000
+send 2 10000000
+send 2 11111110
+send 2 11111101
+send 2 11111011
+send 2 11110111
+send 2 11101111
+send 2 11011111
+send 2 10111111
+send 2 01111111
+send 2 00000000
+send 2 11111111
+send 2 00000011
+send 2 00001100
+send 2 00110000
+send 2 11000000
+#
+C setting rate=4 -> CLKDIV=3 ------------------------------------------------
+.wait 5
+.rate 4
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 00000001
+send 1 00000010
+send 1 00000100
+send 1 00001000
+send 1 00010000
+send 1 00100000
+send 1 01000000
+send 1 10000000
+send 1 11111110
+send 1 11111101
+send 1 11111011
+send 1 11110111
+send 1 11101111
+send 1 11011111
+send 1 10111111
+send 1 01111111
+send 1 00000000
+send 1 11111111
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
+#
+C setting rate=16 -> CLKDIV=15 -----------------------------------------------
+.wait 5
+.rate 16
+#
+C test resonse to start bit runts
+puls 0 0 00000000 0 1 1 20 -- will recover fast
+puls 0 0 00000000 0 2 1 20 -- "
+puls 0 0 00000000 0 3 1 20
+puls 0 0 00000000 0 4 1 20
+puls 0 0 00000000 0 6 1 20
+puls 1 0 11111111 0 10 1 200 -- will be taken as start bit
+#
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 11110000
+send 1 00001111
+send 1 11111111
+C test data with 3 stop bits
+send 2 00000000
+send 2 11110000
+send 2 00001111
+send 2 11111111
+C test data with 4 stop bits
+send 3 00000000
+send 3 11110000
+send 3 00001111
+send 3 11111111
+#
+C setting rate=32 -> CLKDIV=31 -----------------------------------------------
+.wait 5
+.rate 32
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 11110000
+send 1 00001111
+send 1 11111111
+C test data with 3 stop bits
+send 2 00000000
+send 2 11110000
+send 2 00001111
+send 2 11111111
+C test data with 4 stop bits
+send 3 00000000
+send 3 11110000
+send 3 00001111
+send 3 11111111
+#
+C setting rate=32 -> CLKDIV=31 ---- txrate = 31 !! ---------------------------
+.wait 5
+.rate 32
+.xrate 31
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 11110000
+send 1 00001111
+send 1 11111111
+C test data with 3 stop bits
+send 2 00000000
+send 2 11110000
+send 2 00001111
+send 2 11111111
+C test data with 4 stop bits
+send 3 00000000
+send 3 11110000
+send 3 00001111
+send 3 11111111
+#
+C setting rate=32 -> CLKDIV=31 ---- txrate = 33 !! ---------------------------
+.wait 5
+.rate 32
+.xrate 33
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 11110000
+send 1 00001111
+send 1 11111111
+C test data with 3 stop bits
+send 2 00000000
+send 2 11110000
+send 2 00001111
+send 2 11111111
+C test data with 4 stop bits
+send 3 00000000
+send 3 11110000
+send 3 00001111
+send 3 11111111
+#
+C setting rate=27 -> CLKDIV=25 ---- txrate = 26 !! ---------------------------
+.wait 5
+.rate 27
+.xrate 26
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 11110000
+send 1 00001111
+send 1 11111111
+C test data with 3 stop bits
+send 2 00000000
+send 2 11110000
+send 2 00001111
+send 2 11111111
+C test data with 4 stop bits
+send 3 00000000
+send 3 11110000
+send 3 00001111
+send 3 11111111
+#
+C setting rate=27 -> CLKDIV=27 ---- txrate = 28 !! ---------------------------
+.wait 5
+.rate 27
+.xrate 28
+C test back-to-back data
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 0 00001000
+send 0 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111110
+send 0 11111101
+send 0 11111011
+send 0 11110111
+send 0 11101111
+send 0 11011111
+send 0 10111111
+send 0 01111111
+send 0 00000000
+send 0 11111111
+send 0 00000011
+send 0 00001100
+send 0 00110000
+send 0 11000000
+C test data with 2 stop bits
+send 1 00000000
+send 1 11110000
+send 1 00001111
+send 1 11111111
+C test data with 3 stop bits
+send 2 00000000
+send 2 11110000
+send 2 00001111
+send 2 11111111
+C test data with 4 stop bits
+send 3 00000000
+send 3 11110000
+send 3 00001111
+send 3 11111111
+#
Index: serport/tb/tbd_serport_autobaud.vhd
===================================================================
--- serport/tb/tbd_serport_autobaud.vhd (nonexistent)
+++ serport/tb/tbd_serport_autobaud.vhd (revision 7)
@@ -0,0 +1,152 @@
+-- $Id: tbd_serport_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tbd_serport_autobaud - syn
+-- Description: Wrapper for serport_uart_autobaud and serport_uart_rxtx to
+-- avoid records. It has a port interface which will not be
+-- modified by xst synthesis (no records, no generic port).
+--
+-- Dependencies: clkdivce
+-- serport_uart_autobaud
+-- serport_uart_rxtx
+-- serport_uart_rx
+--
+-- To test: serport_uart_autobaud
+-- serport_uart_rxtx
+--
+-- Target Devices: generic
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 151 291 0 - t 9.23
+-- 2007-10-27 92 9.1 J30 xc3s1000-4 151 291 0 - t 9.23
+-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 153 338 0 178 s 9.45
+-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 152 293 0 - s 9.40
+--
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-01-20 112 1.0.1 rename clkgen->clkdivce
+-- 2007-06-24 60 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.genlib.all;
+use work.serport.all;
+
+entity tbd_serport_autobaud is -- serial port autobaud [tb design]
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (uart view)
+ CE_USEC : out slbit; -- usec pulse (here every 4 clocks)
+ CE_MSEC : out slbit; -- msec pulse (here every 20 clocks)
+ CLKDIV : out slv13; -- clock divider setting
+ ABACT : out slbit; -- autobaud active
+ ABDONE : out slbit; -- autobaud done
+ RXDATA : out slv8; -- receiver data out (1st rx)
+ RXVAL : out slbit; -- receiver data valid (1st rx)
+ RXERR : out slbit; -- receiver data error (1st rx)
+ RXACT : out slbit; -- receiver active (1st rx)
+ TXSD2 : out slbit; -- transmit serial data (2nd tx)
+ RXDATA3 : out slv8; -- receiver data out (3rd rx)
+ RXVAL3 : out slbit; -- receiver data valid (3rd rx)
+ RXERR3 : out slbit; -- receiver data error (3rd rx)
+ RXACT3 : out slbit -- receiver active (3rd rx)
+ );
+end tbd_serport_autobaud;
+
+
+architecture syn of tbd_serport_autobaud is
+
+ constant cdwidth : positive := 13;
+
+ signal LCE_MSEC : slbit := '0';
+ signal LCLKDIV : slv13 := (others=>'0');
+ signal LRXDATA : slv8 := (others=>'0');
+ signal LRXVAL : slbit := '0';
+ signal LTXSD2 : slbit := '0';
+ signal LABACT : slbit := '0';
+
+begin
+
+ CKLDIV : clkdivce
+ generic map (
+ CDUWIDTH => 6,
+ USECDIV => 4,
+ MSECDIV => 5)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => LCE_MSEC
+ );
+
+ AUTOBAUD : serport_uart_autobaud
+ generic map (
+ CDWIDTH => cdwidth,
+ CDINIT => 15)
+ port map (
+ CLK => CLK,
+ CE_MSEC => LCE_MSEC,
+ RESET => RESET,
+ RXSD => RXSD,
+ CLKDIV => LCLKDIV,
+ ACT => LABACT,
+ DONE => ABDONE
+ );
+
+ UART1 : serport_uart_rxtx
+ generic map (
+ CDWIDTH => cdwidth)
+ port map (
+ CLK => CLK,
+ RESET => LABACT,
+ CLKDIV => LCLKDIV,
+ RXSD => RXSD,
+ RXDATA => LRXDATA,
+ RXVAL => LRXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD => LTXSD2,
+ TXDATA => LRXDATA,
+ TXENA => LRXVAL,
+ TXBUSY => open
+ );
+
+ UART2 : serport_uart_rx
+ generic map (
+ CDWIDTH => cdwidth)
+ port map (
+ CLK => CLK,
+ RESET => LABACT,
+ CLKDIV => LCLKDIV,
+ RXSD => LTXSD2,
+ RXDATA => RXDATA3,
+ RXVAL => RXVAL3,
+ RXERR => RXERR3,
+ RXACT => RXACT3
+ );
+
+ CE_MSEC <= LCE_MSEC;
+ CLKDIV <= LCLKDIV;
+ ABACT <= LABACT;
+ RXDATA <= LRXDATA;
+ RXVAL <= LRXVAL;
+ TXSD2 <= LTXSD2;
+
+end syn;
Index: serport/tb/tbd_serport_uart_rx.vbom
===================================================================
--- serport/tb/tbd_serport_uart_rx.vbom (nonexistent)
+++ serport/tb/tbd_serport_uart_rx.vbom (revision 7)
@@ -0,0 +1,7 @@
+# libs
+../../slvtypes.vhd
+../serport.vhd
+# components
+../serport_uart_rx.vbom
+# design
+tbd_serport_uart_rx.vhd
Index: serport/tb/tb_serport_uart_rxtx_ssim.vbom
===================================================================
--- serport/tb/tb_serport_uart_rxtx_ssim.vbom (nonexistent)
+++ serport/tb/tb_serport_uart_rxtx_ssim.vbom (revision 7)
@@ -0,0 +1,4 @@
+# configure for _*sim case
+tbd_serport_uart_rxtx = tbd_serport_uart_rxtx_ssim.vhd
+tb_serport_uart_rxtx.vbom
+@top:tb_serport_uart_rxtx
Index: serport/tb/tb_serport_autobaud_ssim.vbom
===================================================================
--- serport/tb/tb_serport_autobaud_ssim.vbom (nonexistent)
+++ serport/tb/tb_serport_autobaud_ssim.vbom (revision 7)
@@ -0,0 +1,4 @@
+# configure for _*sim case
+tbd_serport_autobaud = tbd_serport_autobaud_ssim.vhd
+tb_serport_autobaud.vbom
+@top:tb_serport_autobaud
Index: serport/tb/tb_serport_uart_rxtx.vbom
===================================================================
--- serport/tb/tb_serport_uart_rxtx.vbom (nonexistent)
+++ serport/tb/tb_serport_uart_rxtx.vbom (revision 7)
@@ -0,0 +1,9 @@
+# libs
+../../slvtypes.vhd
+../../simlib/simlib.vhd
+../serport.vhd
+# components
+../../simlib/simclk.vbom
+tbd_serport_uart_rxtx : tbd_serport_uart_rxtx.vbom
+# design
+tb_serport_uart_rxtx.vhd
Index: serport/tb/tb_serport_uart_rxtx_stim.dat
===================================================================
--- serport/tb/tb_serport_uart_rxtx_stim.dat (nonexistent)
+++ serport/tb/tb_serport_uart_rxtx_stim.dat (revision 7)
@@ -0,0 +1,57 @@
+# $Id: tb_serport_uart_rxtx_stim.dat 311 2010-06-30 17:52:37Z mueller $
+#
+#
+C ----------------------------------------------------------------------------
+C with startup setting rate=16 -> CLKDIV=15
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 10 00001000
+send 50 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111111
+send 0 11001100
+send 0 00110011
+#
+C ----------------------------------------------------------------------------
+# wait >16*10 cycles
+.wait 200
+C now try rate=2 -> CLKDIV=1
+.rate 2
+.reset
+.wait 20
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 10 00001000
+send 50 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111111
+send 0 11001100
+send 0 00110011
+#
+C ----------------------------------------------------------------------------
+# wait >2*10 cycles
+.wait 30
+C now try rate=1 -> CLKDIV=0
+.rate 1
+.reset
+.wait 20
+send 0 00000000
+send 0 00000001
+send 0 00000010
+send 0 00000100
+send 10 00001000
+send 50 00010000
+send 0 00100000
+send 0 01000000
+send 0 10000000
+send 0 11111111
+send 0 11001100
+send 0 00110011
Index: serport/tb/tb_serport_uart_rx.vhd
===================================================================
--- serport/tb/tb_serport_uart_rx.vhd (nonexistent)
+++ serport/tb/tb_serport_uart_rx.vhd (revision 7)
@@ -0,0 +1,328 @@
+-- $Id: tb_serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_serport_uart_rx - sim
+-- Description: Test bench for serport_uart_rx
+--
+-- Dependencies: simlib/simclk
+-- tbd_serport_uart_rx [UUT]
+--
+-- To test: serport_uart_rx
+--
+-- Target Devices: generic
+--
+-- Verified (with tb_serport_uart_rx_stim.dat):
+-- Date Rev Code ghdl ise Target Comment
+-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
+-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (63488 cl 15.21s)
+-- 2007-10-21 91 - 0.26 - - c:ok (63488 cl 7.12s)
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
+-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
+-- 2007-10-21 91 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.simlib.all;
+use work.serport.all;
+
+entity tb_serport_uart_rx is
+end tb_serport_uart_rx;
+
+architecture sim of tb_serport_uart_rx is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+ signal CLKDIV : slv5 := conv_std_logic_vector(15, 5);
+ signal RXSD : slbit := '1';
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXERR : slbit := '0';
+ signal RXACT : slbit := '0';
+
+ signal CLK_STOP : slbit := '0';
+ signal CLK_CYCLE : slv31 := (others=>'0');
+
+ signal N_MON_VAL : slbit := '0';
+ signal N_MON_ERR : slbit := '0';
+ signal N_MON_DAT : slv8 := (others=>'0');
+ signal R_MON_VAL_1 : slbit := '0';
+ signal R_MON_ERR_1 : slbit := '0';
+ signal R_MON_DAT_1 : slv8 := (others=>'0');
+ signal R_MON_VAL_2 : slbit := '0';
+ signal R_MON_ERR_2 : slbit := '0';
+ signal R_MON_DAT_2 : slv8 := (others=>'0');
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant setup_time : time := 5 ns;
+ constant c2out_time : time := 10 ns;
+
+begin
+
+ SYSCLK : simclk
+ generic map (
+ PERIOD => clock_period,
+ OFFSET => clock_offset)
+ port map (
+ CLK => CLK,
+ CLK_CYCLE => CLK_CYCLE,
+ CLK_STOP => CLK_STOP
+ );
+
+ UUT : entity work.tbd_serport_uart_rx
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLKDIV => CLKDIV,
+ RXSD => RXSD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT
+ );
+
+
+ proc_stim: process
+ file fstim : text open read_mode is "tb_serport_uart_rx_stim";
+ variable iline : line;
+ variable oline : line;
+ variable idelta : integer := 0;
+ variable itxdata : slv8 := (others=>'0');
+ variable irxval : slbit := '0';
+ variable irxerr : slbit := '0';
+ variable irxdata : slv8 := (others=>'0');
+ variable ok : boolean;
+ variable dname : string(1 to 6) := (others=>' ');
+ variable irate : integer := 16;
+
+ type bit_10_array_type is array (0 to 9) of slbit;
+ type int_10_array_type is array (0 to 9) of integer;
+ variable valpuls : bit_10_array_type := (others=>'0');
+ variable delpuls : int_10_array_type := (others=>0);
+ variable npuls : integer := 0;
+
+ begin
+
+ wait for clock_offset - setup_time;
+
+ file_loop: while not endfile(fstim) loop
+
+ readline (fstim, iline);
+
+ readcomment(iline, ok);
+ next file_loop when ok;
+
+ readword(iline, dname, ok);
+ if ok then
+ case dname is
+ when ".reset" => -- .reset
+ write(oline, string'(".reset"));
+ writeline(output, oline);
+ RESET <= '1';
+ wait for clock_period;
+ RESET <= '0';
+ wait for 9*clock_period;
+
+ when ".wait " => -- .wait
+ read_ea(iline, idelta);
+ wait for idelta*clock_period;
+
+ when ".rate " => -- .rate
+ idelta := 0;
+ while RXACT='1' loop -- ensure that uart isn't active
+ wait for clock_period;
+ idelta := idelta + 1;
+ exit when idelta>3000;
+ end loop;
+ read_ea(iline, irate);
+ wait for 2*clock_period;
+ CLKDIV <= conv_std_logic_vector(irate-1, CLKDIV'length);
+ wait for 2*clock_period;
+
+ when ".xrate" => -- .xrate
+ read_ea(iline, irate);
+
+ when "puls " => -- puls
+ writetimestamp(oline, CLK_CYCLE, ": puls ");
+
+ read_ea(iline, irxval);
+ read_ea(iline, irxerr);
+ read_ea(iline, irxdata);
+
+ npuls := 0;
+ for i in valpuls'range loop
+ testempty(iline, ok);
+ if ok then
+ exit;
+ end if;
+ read_ea(iline, valpuls(i));
+ read_ea(iline, delpuls(i));
+ assert delpuls(i)>0
+ report "assert puls length > 0" severity failure;
+ npuls := npuls + 1;
+ write(oline, valpuls(i), right, 3);
+ write(oline, delpuls(i), right, 3);
+ end loop; -- i
+ writeline(output, oline);
+
+ if npuls > 0 then
+ N_MON_VAL <= irxval;
+ N_MON_ERR <= irxerr;
+ N_MON_DAT <= irxdata;
+ for i in 0 to npuls-1 loop
+ RXSD <= valpuls(i);
+ wait for clock_period;
+ N_MON_VAL <= '0';
+ wait for (delpuls(i)-1)*clock_period;
+ end loop; -- i
+ end if;
+
+ when "send " => -- send
+ read_ea(iline, idelta);
+ read_ea(iline, itxdata);
+
+ RXSD <= '1';
+ wait for idelta*clock_period;
+
+ writetimestamp(oline, CLK_CYCLE, ": send ");
+ write(oline, itxdata, right, 10);
+ writeline(output, oline);
+
+ N_MON_VAL <= '1';
+ N_MON_ERR <= '0';
+ N_MON_DAT <= itxdata;
+
+ RXSD <= '0'; -- start bit
+ wait for clock_period;
+ N_MON_VAL <= '0';
+ wait for (irate-1)*clock_period;
+ RXSD <= '1';
+
+ for i in itxdata'reverse_range loop -- transmit lsb first
+ RXSD <= itxdata(i); -- data bit
+ wait for irate*clock_period;
+ end loop;
+
+ RXSD <= '1'; -- stop bit
+ wait for irate*clock_period;
+
+ when others => -- unknown command
+ write(oline, string'("?? unknown command: "));
+ write(oline, dname);
+ writeline(output, oline);
+ report "aborting" severity failure;
+ end case;
+
+ else
+ report "failed to find command" severity failure;
+
+ end if;
+
+ testempty_ea(iline);
+ end loop; -- file_loop:
+
+ idelta := 0;
+ while RXACT='1' loop
+ wait for clock_period;
+ idelta := idelta + 1;
+ exit when idelta>3000;
+ end loop;
+
+ writetimestamp(oline, CLK_CYCLE, ": DONE ");
+ writeline(output, oline);
+
+ wait for 12*irate*clock_period;
+
+ CLK_STOP <= '1';
+
+ wait; -- suspend proc_stim forever
+ -- clock is stopped, sim will end
+
+ end process proc_stim;
+
+
+ proc_moni: process
+ variable oline : line;
+ begin
+
+ loop
+ wait until CLK'event and CLK='1';
+
+ if R_MON_VAL_1 = '1' then
+ if R_MON_VAL_2 = '1' then
+ writetimestamp(oline, CLK_CYCLE, ": moni ");
+ write(oline, string'(" FAIL MISSING ERR="));
+ write(oline, R_MON_ERR_2);
+ write(oline, string'(" DATA="));
+ write(oline, R_MON_DAT_2);
+ writeline(output, oline);
+ end if;
+ R_MON_VAL_2 <= R_MON_VAL_1;
+ R_MON_ERR_2 <= R_MON_ERR_1;
+ R_MON_DAT_2 <= R_MON_DAT_1;
+ end if;
+
+ R_MON_VAL_1 <= N_MON_VAL;
+ R_MON_ERR_1 <= N_MON_ERR;
+ R_MON_DAT_1 <= N_MON_DAT;
+
+ if RXVAL='1' or RXERR='1' then
+ writetimestamp(oline, CLK_CYCLE, ": moni ");
+ write(oline, RXDATA, right, 10);
+ if RXERR = '1' then
+ write(oline, string'(" RXERR=1"));
+ end if;
+
+ if R_MON_VAL_2 = '0' then
+ write(oline, string'(" FAIL UNEXPECTED"));
+ else
+ write(oline, string'(" CHECK"));
+ R_MON_VAL_2 <= '0';
+
+ if R_MON_ERR_2 = '0' then
+ if R_MON_DAT_2 = RXDATA and
+ RXERR='0' then
+ write(oline, string'(" OK"));
+ else
+ write(oline, string'(" FAIL"));
+ end if;
+
+ else
+ if RXERR = '1' then
+ write(oline, string'(" OK"));
+ else
+ write(oline, string'(" FAIL, RXERR=1 expected"));
+ end if;
+
+ end if;
+
+ end if;
+
+ writeline(output, oline);
+ end if;
+
+ end loop;
+
+ end process proc_moni;
+
+end sim;
Index: serport/tb/tbd_serport_uart_rxtx.vbom
===================================================================
--- serport/tb/tbd_serport_uart_rxtx.vbom (nonexistent)
+++ serport/tb/tbd_serport_uart_rxtx.vbom (revision 7)
@@ -0,0 +1,7 @@
+# libs
+../../slvtypes.vhd
+../serport.vhd
+# components
+../serport_uart_rxtx.vbom
+# design
+tbd_serport_uart_rxtx.vhd
Index: serport/tb/tb_serport_autobaud.vbom
===================================================================
--- serport/tb/tb_serport_autobaud.vbom (nonexistent)
+++ serport/tb/tb_serport_autobaud.vbom (revision 7)
@@ -0,0 +1,9 @@
+# libs
+../../slvtypes.vhd
+../../simlib/simlib.vhd
+../serport.vhd
+# components
+../../simlib/simclk.vbom
+tbd_serport_autobaud : tbd_serport_autobaud.vbom
+# design
+tb_serport_autobaud.vhd
Index: serport/tb/tb_serport_autobaud_stim.dat
===================================================================
--- serport/tb/tb_serport_autobaud_stim.dat (nonexistent)
+++ serport/tb/tb_serport_autobaud_stim.dat (revision 7)
@@ -0,0 +1,77 @@
+# $Id: tb_serport_autobaud_stim.dat 311 2010-06-30 17:52:37Z mueller $
+#
+#
+C ----------------------------------------------------------------------------
+C start without autobauding and default setup clock divisor of 16 (CLKDIV=15)
+.reset
+.rate 16
+.wait 5
+send 1 00000001
+send 1 10000000
+#
+C ----------------------------------------------------------------------------
+C now break + autobaud with clock divisor = 8 (CLKDIV=7)
+.break 3000
+.wait 20
+.rate 8
+send 0 10000000
+send 1 10000000
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
+#
+C ----------------------------------------------------------------------------
+C now break + autobaud with clock divisor = 4 (CLKDIV=3)
+.break 3000
+.wait 20
+.rate 4
+send 0 10000000
+send 1 10000000
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
+#
+C ----------------------------------------------------------------------------
+C now break + autobaud with clock divisor = 2 (CLKDIV=1)
+.break 3000
+.wait 20
+.rate 2
+send 0 10000000
+send 1 10000000
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
+#
+C ----------------------------------------------------------------------------
+C now break + autobaud with clock divisor = 1 (CLKDIV=0)
+.break 3000
+.wait 20
+.rate 1
+send 0 10000000
+send 1 10000000
+send 1 01000000
+send 1 00100000
+send 1 00010000
+send 1 00001000
+send 1 00000100
+send 1 00000010
+send 1 00000001
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
+#
+C ----------------------------------------------------------------------------
+C now break + autobaud with clock divisor = 32 (CLKDIV=31)
+.break 3000
+.wait 20
+.rate 32
+send 0 10000000
+send 1 10000000
+send 1 00000011
+send 1 00001100
+send 1 00110000
+send 1 11000000
Index: serport/tb/tbd_serport_uart_rx.vhd
===================================================================
--- serport/tb/tbd_serport_uart_rx.vhd (nonexistent)
+++ serport/tb/tbd_serport_uart_rx.vhd (revision 7)
@@ -0,0 +1,79 @@
+-- $Id: tbd_serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tbd_serport_uart_rx - syn
+-- Description: Wrapper for serport_uart_rx to avoid records. It
+-- has a port interface which will not be modified by xst
+-- synthesis (no records, no generic port).
+--
+-- Dependencies: serport_uart_rx
+--
+-- To test: serport_uart_rx
+--
+-- Target Devices: generic
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 26 67 0 - t 8.17
+-- 2007-10-27 92 9.1 J30 xc3s1000-4 26 67 0 - t 8.25
+-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 29 90 0 47 s 8.45
+-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 31 92 0 - s 8.25
+--
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-21 91 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+
+entity tbd_serport_uart_rx is -- serial port uart rx [tb design]
+ -- generic: CDWIDTH=5
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv5; -- clock divider setting
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit -- receiver active
+ );
+end tbd_serport_uart_rx;
+
+
+architecture syn of tbd_serport_uart_rx is
+
+begin
+
+ UART : serport_uart_rx
+ generic map (
+ CDWIDTH => 5)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLKDIV => CLKDIV,
+ RXSD => RXSD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT
+ );
+
+end syn;
Index: serport/tb/.cvsignore
===================================================================
--- serport/tb/.cvsignore (nonexistent)
+++ serport/tb/.cvsignore (revision 7)
@@ -0,0 +1,15 @@
+tb_serport_autobaud
+tb_serport_autobaud_stim
+tb_serport_autobaud_[sft]sim
+tb_serport_autobaud_ISim
+tb_serport_autobaud_ISim_[sft]sim
+tb_serport_uart_rx
+tb_serport_uart_rx_stim
+tb_serport_uart_rx_[sft]sim
+tb_serport_uart_rx_ISim
+tb_serport_uart_rx_ISim_[sft]sim
+tb_serport_uart_rxtx
+tb_serport_uart_rxtx_stim
+tb_serport_uart_rxtx_[sft]sim
+tb_serport_uart_rxtx_ISim
+tb_serport_uart_rxtx_ISim_[sft]sim
Index: serport/tb/Makefile
===================================================================
--- serport/tb/Makefile (nonexistent)
+++ serport/tb/Makefile (revision 7)
@@ -0,0 +1,30 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2009-11-21 252 1.2 add ISim support
+# 2007-11-26 98 1.1 use make includes
+# 2007-06-03 48 1.0 Initial version
+#
+EXE_all = tb_serport_uart_rx tb_serport_uart_rxtx tb_serport_autobaud
+#
+.phony : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean isim_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.ghdl
+include $(RETROBASE)/rtl/vlib/Makefile.isim
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(VBOM_all:.vbom=.dep_isim)
+#
Index: serport/tb/tbd_serport_autobaud.vbom
===================================================================
--- serport/tb/tbd_serport_autobaud.vbom (nonexistent)
+++ serport/tb/tbd_serport_autobaud.vbom (revision 7)
@@ -0,0 +1,11 @@
+# libs
+../../slvtypes.vhd
+../../genlib/genlib.vhd
+../serport.vhd
+# components
+../../genlib/clkdivce.vbom
+../serport_uart_autobaud.vbom
+../serport_uart_rxtx.vbom
+../serport_uart_rx.vbom
+# design
+tbd_serport_autobaud.vhd
Index: serport/tb
===================================================================
--- serport/tb (nonexistent)
+++ serport/tb (revision 7)
serport/tb
Property changes :
Added: svn:ignore
## -0,0 +1,47 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_serport_autobaud
+tb_serport_autobaud_stim
+tb_serport_autobaud_[sft]sim
+tb_serport_autobaud_ISim
+tb_serport_autobaud_ISim_[sft]sim
+tb_serport_uart_rx
+tb_serport_uart_rx_stim
+tb_serport_uart_rx_[sft]sim
+tb_serport_uart_rx_ISim
+tb_serport_uart_rx_ISim_[sft]sim
+tb_serport_uart_rxtx
+tb_serport_uart_rxtx_stim
+tb_serport_uart_rxtx_[sft]sim
+tb_serport_uart_rxtx_ISim
+tb_serport_uart_rxtx_ISim_[sft]sim
Index: serport/serport_uart_autobaud.vbom
===================================================================
--- serport/serport_uart_autobaud.vbom (nonexistent)
+++ serport/serport_uart_autobaud.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+serport_uart_autobaud.vhd
Index: serport/serport_uart_rxtx.vbom
===================================================================
--- serport/serport_uart_rxtx.vbom (nonexistent)
+++ serport/serport_uart_rxtx.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../slvtypes.vhd
+serport.vhd
+# components
+serport_uart_rx.vbom
+serport_uart_tx.vbom
+# design
+serport_uart_rxtx.vhd
Index: serport/serport_uart_rxtx_ab.vhd
===================================================================
--- serport/serport_uart_rxtx_ab.vhd (nonexistent)
+++ serport/serport_uart_rxtx_ab.vhd (revision 7)
@@ -0,0 +1,100 @@
+-- $Id: serport_uart_rxtx_ab.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: serport_uart_rxtx_ab - syn
+-- Description: serial port UART - transmitter-receiver + autobauder
+--
+-- Dependencies: serport_uart_autobaud
+-- serport_uart_rxtx
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-06-24 60 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+
+entity serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
+ generic (
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT: natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit; -- receiver active
+ TXSD : out slbit; -- transmit serial data (uart view)
+ TXDATA : in slv8; -- transmit data in
+ TXENA : in slbit; -- transmit data enable
+ TXBUSY : out slbit; -- transmit busy
+ ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
+ ABDONE : out slbit -- autobaud resync done
+ );
+end serport_uart_rxtx_ab;
+
+architecture syn of serport_uart_rxtx_ab is
+
+ signal CLKDIV : slv(CDWIDTH-1 downto 0) := conv_std_logic_vector(0, CDWIDTH);
+ signal ABACT_L : slbit := '0'; -- local readable copy of ABACT
+ signal UART_RESET : slbit := '0';
+
+begin
+
+ AB : serport_uart_autobaud
+ generic map (
+ CDWIDTH => CDWIDTH,
+ CDINIT => CDINIT)
+ port map (
+ CLK => CLK,
+ CE_MSEC => CE_MSEC,
+ RESET => RESET,
+ RXSD => RXSD,
+ CLKDIV => CLKDIV,
+ ACT => ABACT_L,
+ DONE => ABDONE
+ );
+
+ UART_RESET <= ABACT_L or RESET;
+ ABACT <= ABACT_L;
+
+ RXTX : serport_uart_rxtx
+ generic map (
+ CDWIDTH => CDWIDTH)
+ port map (
+ CLK => CLK,
+ RESET => UART_RESET,
+ CLKDIV => CLKDIV,
+ RXSD => RXSD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT,
+ TXSD => TXSD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+end syn;
Index: serport/serport_uart_rx.vhd
===================================================================
--- serport/serport_uart_rx.vhd (nonexistent)
+++ serport/serport_uart_rx.vhd (revision 7)
@@ -0,0 +1,312 @@
+-- $Id: serport_uart_rx.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2009 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+-- The uart expects CLKDIV+1 wide input bit symbols.
+-- This implementation counts the number of 1's in the first CLKDIV clock
+-- cycles, and checks in the last cycle of the symbol time whether the
+-- number of 1's was > CLKDIV/2. This supresses short glitches nicely,
+-- especially for larger clock dividers.
+--
+------------------------------------------------------------------------------
+-- Module Name: serport_uart_rx - syn
+-- Description: serial port UART - receiver
+--
+-- Dependencies: -
+-- Test bench: tb/tb_serport_uart_rxtx
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2009-07-12 233 2.0.2 remove snoopers
+-- 2008-03-02 121 2.0.1 comment out snoopers
+-- 2007-10-21 91 2.0 re-designed and -implemented with state machine.
+-- allow CLKDIV=0 with 1 stop bit; allow max. CLKDIV
+-- (all 1's); aborts bad start bit after 1/2 cell;
+-- accepts stop bit after 1/2 cell, permits tx clock
+-- be ~3 percent faster than rx clock.
+-- for 3s1000ft256: 50 -> 58 slices for CDWIDTH=13
+-- 2007-10-14 89 1.1 almost full rewrite, handles now CLKDIV=0 properly
+-- for 3s1000ft256: 43 -> 50 slices for CDWIDTH=13
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-30 62 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+-- synthesis translate_off
+use ieee.std_logic_textio.all;
+use std.textio.all;
+-- synthesis translate_on
+
+use work.slvtypes.all;
+
+entity serport_uart_rx is -- serial port uart: receive part
+ generic (
+ CDWIDTH : positive := 13); -- clk divider width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit -- receiver active
+ );
+end serport_uart_rx;
+
+
+architecture syn of serport_uart_rx is
+
+ type state_type is (
+ s_idle, -- s_idle: idle
+ s_colb0, -- s_colb0: collect b0 (start bit)
+ s_endb0, -- s_endb0: finish b0 (start bit)
+ s_colbx, -- s_colbx: collect bx
+ s_endbx, -- s_endbx: finish bx
+ s_colb9, -- s_colb9: collect bx (stop bit)
+ s_endb9 -- s_endb9: finish bx (stop bit)
+ );
+
+ type regs_type is record
+ state : state_type; -- state
+ ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
+ dcnt : slv(CDWIDTH downto 0); -- data '1' counter
+ bcnt : slv4; -- bit counter
+ sreg : slv8; -- input shift register
+ end record regs_type;
+
+ constant ccntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
+ constant dcntzero : slv(CDWIDTH downto 0) := (others=>'0');
+ constant regs_init : regs_type := (
+ s_idle,
+ ccntzero,
+ dcntzero,
+ (others=>'0'),
+ (others=>'0')
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ R_REGS <= N_REGS;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, RESET, CLKDIV, RXSD)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable dbit : slbit := '0';
+ variable ld_ccnt : slbit := '0';
+ variable tc_ccnt : slbit := '0';
+ variable tc_bcnt : slbit := '0';
+ variable ld_dcnt : slbit := '0';
+ variable ld_bcnt : slbit := '0';
+ variable ce_bcnt : slbit := '0';
+ variable iact : slbit := '0';
+ variable ival : slbit := '0';
+ variable ierr : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ dbit := '0';
+ ld_ccnt := '0';
+ tc_ccnt := '0';
+ tc_bcnt := '0';
+ ld_dcnt := '0';
+ ld_bcnt := '0';
+ ce_bcnt := '0';
+ iact := '1';
+ ival := '0';
+ ierr := '0';
+
+ if unsigned(r.ccnt) = 0 then
+ tc_ccnt := '1';
+ end if;
+ if unsigned(r.bcnt) = 9 then
+ tc_bcnt := '1';
+ end if;
+
+ if unsigned(r.dcnt) > unsigned("00" & CLKDIV(CDWIDTH-1 downto 1)) then
+ dbit := '1';
+ end if;
+
+ case r.state is
+
+ when s_idle => -- s_idle: idle ----------------------
+ iact := '0';
+ ld_dcnt := '1'; -- always keep dcnt in reset
+ if RXSD = '0' then -- if start bit seen
+ if tc_ccnt = '1' then
+ n.state := s_endb0; -- finish b0
+ ld_ccnt := '1'; -- start next bit
+ ce_bcnt := '1';
+ else
+ n.state := s_colb0; -- collect b0
+ end if;
+ else -- otherwise
+ ld_ccnt := '1'; -- keep all counters in reset
+ ld_bcnt := '1';
+ end if;
+
+ when s_colb0 => -- s_colb0: collect b0 (start bit) ---
+ if tc_ccnt = '1' then -- last cycle of b0 ?
+ n.state := s_endb0; -- finish b0
+ ld_ccnt := '1'; -- "
+ ce_bcnt := '1';
+ else -- continue in b0 ?
+ if dbit='1' and RXSD='1' then -- too many 1's ?
+ n.state := s_idle; -- abort to idle
+ ld_dcnt := '1'; -- put counters in reset
+ ld_ccnt := '1';
+ ld_bcnt := '1';
+ end if;
+ end if;
+
+ when s_endb0 => -- s_endb0: finish b0 (start bit) ---
+ ld_dcnt := '1'; -- start next bit
+ if dbit = '1' then -- was it a 1 ?
+ n.state := s_idle; -- abort to idle
+ ld_ccnt := '1'; -- put counters in reset
+ ld_bcnt := '1';
+ else
+ if tc_ccnt = '1' then -- last cycle of bx ?
+ n.state := s_endbx; -- finish bx
+ ld_ccnt := '1';
+ ce_bcnt := '1';
+ else -- continue in b0 ?
+ n.state := s_colbx; -- collect bx
+ end if;
+ end if;
+
+ when s_colbx => -- s_colbx: collect bx ---------------
+ if tc_ccnt = '1' then -- last cycle of bx ?
+ n.state := s_endbx; -- finish bx
+ ld_ccnt := '1';
+ ce_bcnt := '1';
+ end if;
+
+ when s_endbx => -- s_endbx: finish bx ---------------
+ ld_dcnt := '1'; -- start next bit
+ n.sreg := dbit & r.sreg(7 downto 1);
+ if tc_ccnt = '1' then -- last cycle of bx ?
+ if tc_bcnt = '1' then
+ n.state := s_endb9; -- finish b9
+ ld_bcnt := '1'; -- and wrap bcnt
+ else
+ n.state := s_endbx; -- finish bx
+ ce_bcnt := '1';
+ end if;
+ ld_ccnt := '1';
+ else -- continue in bx ?
+ if tc_bcnt = '1' then
+ n.state := s_colb9; -- collect b9
+ else
+ n.state := s_colbx; -- collect bx
+ end if;
+ end if;
+
+ when s_colb9 => -- s_colb9: collect bx (stop bit) ----
+ if tc_ccnt = '1' then -- last cycle of b9 ?
+ n.state := s_endb9; -- finish b9
+ ld_ccnt := '1'; -- "
+ ld_bcnt := '1'; -- and wrap bcnt
+ else -- continue in b9 ?
+ if dbit='1' and RXSD='1' then -- already enough 1's ?
+ n.state := s_idle; -- finish to idle
+ ld_dcnt := '1'; -- put counters in reset
+ ld_ccnt := '1';
+ ld_bcnt := '1';
+ ival := '1';
+ end if;
+ end if;
+
+ when s_endb9 => -- s_endb9: finish bx (stop bit) ----
+ ld_dcnt := '1'; -- start next bit
+ if dbit = '1' then -- was it a valid stop bit ?
+ ival := '1';
+ else
+ ierr := '1';
+ end if;
+ if RXSD = '1' then -- line in idle state ?
+ n.state := s_idle; -- finish to idle state
+ ld_ccnt := '1'; -- and put counters in reset
+ ld_bcnt := '1'; -- "
+ else
+ if tc_ccnt = '1' then -- last cycle of b9 ?
+ n.state := s_endb0; -- finish b0
+ ld_ccnt := '1'; -- "
+ ce_bcnt := '1';
+ else -- continue in b0 ?
+ n.state := s_colb0; -- collect bx
+ end if;
+ end if;
+
+ when others => null; -- -----------------------------------
+
+ end case;
+
+ if RESET = '1' then -- RESET seen
+ ld_ccnt := '1'; -- keep all counters in reset
+ ld_dcnt := '1';
+ ld_bcnt := '1';
+ n.state := s_idle;
+ end if;
+
+ if ld_ccnt = '1' then -- implement ccnt
+ n.ccnt := CLKDIV;
+ else
+ n.ccnt := unsigned(r.ccnt) - 1;
+ end if;
+
+ if ld_dcnt = '1' then -- implement dcnt
+ n.dcnt(CDWIDTH downto 1) := (others=>'0');
+ n.dcnt(0) := RXSD;
+ else
+ if RXSD = '1' then
+ n.dcnt := unsigned(r.dcnt) + 1;
+ end if;
+ end if;
+
+ if ld_bcnt = '1' then -- implement bcnt
+ n.bcnt := (others=>'0');
+ else
+ if ce_bcnt = '1' then
+ n.bcnt := unsigned(r.bcnt) + 1;
+ end if;
+ end if;
+
+ N_REGS <= n;
+
+ RXDATA <= r.sreg;
+ RXACT <= iact;
+ RXVAL <= ival;
+ RXERR <= ierr;
+
+ end process proc_next;
+
+end syn;
Index: serport/serport_uart_rxtx_ab.vbom
===================================================================
--- serport/serport_uart_rxtx_ab.vbom (nonexistent)
+++ serport/serport_uart_rxtx_ab.vbom (revision 7)
@@ -0,0 +1,8 @@
+# libs
+../slvtypes.vhd
+serport.vhd
+# components
+serport_uart_autobaud.vbom
+serport_uart_rxtx.vbom
+# design
+serport_uart_rxtx_ab.vhd
Index: serport/serport_uart_rx.vbom
===================================================================
--- serport/serport_uart_rx.vbom (nonexistent)
+++ serport/serport_uart_rx.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+serport_uart_rx.vhd
Index: serport/serport_uart_tx.vhd
===================================================================
--- serport/serport_uart_tx.vhd (nonexistent)
+++ serport/serport_uart_tx.vhd (revision 7)
@@ -0,0 +1,132 @@
+-- $Id: serport_uart_tx.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: serport_uart_tx - syn
+-- Description: serial port UART - transmitter
+--
+-- Dependencies: -
+-- Test bench: tb/tb_serport_uart_rxtx
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-21 91 1.0.3 use 1 stop bits (redesigned _rx allows this)
+-- 2007-10-19 90 1.0.2 use 2 stop bits (allow CLKDIV=0 operation in sim)
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-30 62 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity serport_uart_tx is -- serial port uart: transmit part
+ generic (
+ CDWIDTH : positive := 13); -- clk divider width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
+ TXSD : out slbit; -- transmit serial data (uart view)
+ TXDATA : in slv8; -- transmit data in
+ TXENA : in slbit; -- transmit data enable
+ TXBUSY : out slbit -- transmit busy
+ );
+end serport_uart_tx;
+
+
+architecture syn of serport_uart_tx is
+
+ type regs_type is record
+ ccnt : slv(CDWIDTH-1 downto 0); -- clock divider counter
+ bcnt : slv4; -- bit counter
+ sreg : slv9; -- output shift register
+ busy : slbit;
+ end record regs_type;
+
+ constant cntzero : slv(CDWIDTH-1 downto 0) := (others=>'0');
+ constant regs_init : regs_type := (
+ cntzero,
+ (others=>'0'),
+ (others=>'1'), -- sreg to all 1 !!
+ '0'
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ R_REGS <= N_REGS;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, RESET, CLKDIV, TXDATA, TXENA)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+ variable ld_ccnt : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+ ld_ccnt := '0';
+
+ if r.busy = '0' then
+ ld_ccnt := '1';
+ n.bcnt := (others=>'0');
+ if TXENA = '1' then
+ n.sreg := TXDATA & '0'; -- add start (0) bit
+ n.busy := '1';
+ end if;
+
+ else
+
+ if unsigned(r.ccnt) = 0 then
+ ld_ccnt := '1';
+ n.sreg := '1' & r.sreg(8 downto 1);
+ n.bcnt := unsigned(r.bcnt) + 1;
+ if unsigned(r.bcnt) = 9 then -- if 10 bits send
+ n.busy := '0'; -- declare all done
+ end if;
+ end if;
+ end if;
+
+ if RESET = '1' then
+ ld_ccnt := '1';
+ n.busy := '0';
+ end if;
+
+ if ld_ccnt = '1' then
+ n.ccnt := CLKDIV;
+ else
+ n.ccnt := unsigned(r.ccnt) - 1;
+ end if;
+
+ N_REGS <= n;
+
+ TXBUSY <= r.busy;
+ TXSD <= r.sreg(0);
+
+ end process proc_next;
+
+end syn;
Index: serport/serport_uart_tx.vbom
===================================================================
--- serport/serport_uart_tx.vbom (nonexistent)
+++ serport/serport_uart_tx.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+serport_uart_tx.vhd
Index: serport/serport_uart_autobaud.vhd
===================================================================
--- serport/serport_uart_autobaud.vhd (nonexistent)
+++ serport/serport_uart_autobaud.vhd (revision 7)
@@ -0,0 +1,173 @@
+-- $Id: serport_uart_autobaud.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: serport_uart_autobaud - syn
+-- Description: serial port UART - autobauder
+--
+-- Dependencies: -
+-- Test bench: tb/tb_serport_autobaud
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
+-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
+-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-30 62 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+
+entity serport_uart_autobaud is -- serial port uart: autobauder
+ generic (
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT: natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (uart view)
+ CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
+ ACT : out slbit; -- active; if 1 clkdiv is invalid
+ DONE : out slbit -- resync done
+ );
+end serport_uart_autobaud;
+
+
+architecture syn of serport_uart_autobaud is
+
+ type state_type is (
+ s_idle,
+ s_break,
+ s_wait,
+ s_sync
+ );
+
+ type regs_type is record
+ ccnt : slv(CDWIDTH-1+3 downto 0); -- clock divider counter
+ mcnt : slv7; -- msec counter
+ seen1 : slbit; -- seen a '1' in this msec
+ state : state_type; -- state
+ end record regs_type;
+
+ -- Note on initialization of ccnt:
+ -- - in the current logic ccnt is incremented n-1 times when n is number
+ -- clock cycles with a RXD of '0'. When running at 50 MBaud, ccnt will
+ -- be incremented 7 (not 8!) times.
+ -- - the three LSBs of ccnt should be at 100 under perfect conditions, this
+ -- gives the best rounded estimate of CLKDIV.
+ -- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
+ -- --> ccntinit = -3
+
+ constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
+ conv_std_logic_vector(2**(CDWIDTH+3)-3, CDWIDTH+3);
+ constant mcntzero : slv7 := (others=>'0');
+ constant mcntlast : slv7 := (others=>'1');
+ constant regs_init : regs_type := (
+ conv_std_logic_vector(CDINIT,CDWIDTH)&"000",
+ (others=>'0'),
+ '0',
+ s_idle
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ assert CDINIT <= 2**CDWIDTH-1
+ report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH"
+ severity FAILURE;
+
+ proc_regs: process (CLK)
+ begin
+
+ if CLK'event and CLK='1' then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, CE_MSEC, RESET, RXSD)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable iact : slbit := '0';
+ variable idone : slbit := '0';
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ iact := '1';
+ idone := '0';
+
+ case r.state is
+ when s_idle => -- s_idle: idle, detect break --------
+ iact := '0';
+ if CE_MSEC = '1' then -- if end of msec
+ if r.seen1 = '0' then -- if no '1' seen on RXD
+ n.mcnt := unsigned(r.mcnt) + 1; -- up break timer counter
+ if r.mcnt = mcntlast then -- after 127 msec
+ n.state := s_break; -- break detected !
+ end if;
+ else -- otherwise if '1' seen
+ n.mcnt := mcntzero; -- clear break timer again
+ end if;
+ n.seen1 := RXSD; -- latch current RXD value
+ else -- otherwise if not at end-of-msec
+ n.seen1 := r.seen1 or RXSD; -- remember whether RXS=1 seen
+ end if;
+
+ when s_break => -- s_break: detect end of break ------
+ if RXSD = '1' then -- if end of break seen
+ n.state := s_wait; -- to s_wait to wait for sync char
+ n.ccnt := ccntinit; -- and initialize ccnt
+ end if; -- otherwise stay in s_break
+
+ when s_wait => -- s_wait: wait for sync char --------
+ if RXSD = '0' then -- if start bit if sync char seen
+ n.state := s_sync; -- to s_sync to wait for end of '0'
+ end if; -- otherwise stay in s_wait
+
+ when s_sync => -- s_sync: wait for end of '0' bits --
+ if RXSD = '1' then -- if end of '0' bits seen
+ n.state := s_idle; -- to s_idle, autobauding done
+ idone := '1'; -- emit done pulse
+ else -- otherwise still in '0' of sync
+ n.ccnt := unsigned(n.ccnt) + 1; -- increment ccnt
+ end if;
+
+ when others => null; -- -----------------------------------
+ end case;
+
+ N_REGS <= n;
+
+ CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3);
+ ACT <= iact or RESET;
+ DONE <= idone;
+
+ end process proc_next;
+
+end syn;
Index: serport/Makefile
===================================================================
--- serport/Makefile (nonexistent)
+++ serport/Makefile (revision 7)
@@ -0,0 +1,22 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-12-09 100 1.0.1 drop ISE_p definition
+# 2007-07-03 45 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: serport/serport.vhd
===================================================================
--- serport/serport.vhd (nonexistent)
+++ serport/serport.vhd (revision 7)
@@ -0,0 +1,134 @@
+-- $Id: serport.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2010 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: serport
+-- Description: serial port interface components
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-04-10 276 1.2 add clock divider constant defs
+-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
+-- 2007-06-03 45 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package serport is
+
+-- clock divider constants assume 50 MHz clock
+
+ constant serport_clkdiv_009600 : integer := 5208-1; -- 50000000/ 9600=5208.33
+ constant serport_clkdiv_019200 : integer := 2604-1; -- 50000000/ 19200=2604.16
+ constant serport_clkdiv_038400 : integer := 1302-1; -- 50000000/ 38400=1302.08
+ constant serport_clkdiv_057600 : integer := 868-1; -- 50000000/ 57600= 868.05
+ constant serport_clkdiv_115200 : integer := 434-1; -- 50000000/115200= 434.02
+ constant serport_clkdiv_230400 : integer := 217-1; -- 50000000/230400= 217.01
+ constant serport_clkdiv_460800 : integer := 109-1; -- 50000000/460800= 108.51
+ constant serport_clkdiv_500000 : integer := 100-1; -- 50000000/500000= 100
+ constant serport_clkdiv_576000 : integer := 87-1; -- 50000000/576000= 86.80
+ constant serport_clkdiv_921600 : integer := 54-1; -- 50000000/921600= 54.25
+ constant serport_clkdiv_1M : integer := 50-1; -- 50000000/1M = 50
+ constant serport_clkdiv_2M : integer := 24-1; -- 50000000/2M = 25
+
+component serport_uart_rxtx is -- serial port uart: rx+tx combo
+ generic (
+ CDWIDTH : positive := 13); -- clk divider width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit; -- receiver active
+ TXSD : out slbit; -- transmit serial data (uart view)
+ TXDATA : in slv8; -- transmit data in
+ TXENA : in slbit; -- transmit data enable
+ TXBUSY : out slbit -- transmit busy
+ );
+end component;
+
+component serport_uart_rx is -- serial port uart: receive part
+ generic (
+ CDWIDTH : positive := 13); -- clk divider width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit -- receiver active
+ );
+end component;
+
+component serport_uart_tx is -- serial port uart: transmit part
+ generic (
+ CDWIDTH : positive := 13); -- clk divider width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
+ TXSD : out slbit; -- transmit serial data (uart view)
+ TXDATA : in slv8; -- transmit data in
+ TXENA : in slbit; -- transmit data enable
+ TXBUSY : out slbit -- transmit busy
+ );
+end component;
+
+component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
+ generic (
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT: natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit; -- receiver active
+ TXSD : out slbit; -- transmit serial data (uart view)
+ TXDATA : in slv8; -- transmit data in
+ TXENA : in slbit; -- transmit data enable
+ TXBUSY : out slbit; -- transmit busy
+ ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
+ ABDONE : out slbit -- autobaud resync done
+ );
+end component;
+
+component serport_uart_autobaud is -- serial port uart: autobauder
+ generic (
+ CDWIDTH : positive := 13; -- clk divider width
+ CDINIT: natural := 15); -- clk divider initial/reset setting
+ port (
+ CLK : in slbit; -- clock
+ CE_MSEC : in slbit; -- 1 msec clock enable
+ RESET : in slbit; -- reset
+ RXSD : in slbit; -- receive serial data (uart view)
+ CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
+ ACT : out slbit; -- active; if 1 clkdiv is invalid
+ DONE : out slbit -- resync done
+ );
+end component;
+
+end serport;
Index: serport/serport_uart_rxtx.vhd
===================================================================
--- serport/serport_uart_rxtx.vhd (nonexistent)
+++ serport/serport_uart_rxtx.vhd (revision 7)
@@ -0,0 +1,85 @@
+-- $Id: serport_uart_rxtx.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: serport_uart_rxtx - syn
+-- Description: serial port UART - transmitter + receiver
+--
+-- Dependencies: serport_uart_rx
+-- serport_uart_tx
+-- Test bench: tb/tb_serport_uart_rxtx
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-06-24 60 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.slvtypes.all;
+use work.serport.all;
+
+entity serport_uart_rxtx is -- serial port uart: rx+tx combo
+ generic (
+ CDWIDTH : positive := 13); -- clk divider width
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
+ RXSD : in slbit; -- receive serial data (uart view)
+ RXDATA : out slv8; -- receiver data out
+ RXVAL : out slbit; -- receiver data valid
+ RXERR : out slbit; -- receiver data error (frame error)
+ RXACT : out slbit; -- receiver active
+ TXSD : out slbit; -- transmit serial data (uart view)
+ TXDATA : in slv8; -- transmit data in
+ TXENA : in slbit; -- transmit data enable
+ TXBUSY : out slbit -- transmit busy
+ );
+end serport_uart_rxtx;
+
+architecture syn of serport_uart_rxtx is
+
+begin
+
+ RX : serport_uart_rx
+ generic map (
+ CDWIDTH => CDWIDTH)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLKDIV => CLKDIV,
+ RXSD => RXSD,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXERR => RXERR,
+ RXACT => RXACT
+ );
+
+ TX : serport_uart_tx
+ generic map (
+ CDWIDTH => CDWIDTH)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLKDIV => CLKDIV,
+ TXSD => TXSD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+end syn;
Index: serport
===================================================================
--- serport (nonexistent)
+++ serport (revision 7)
serport
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: xlib/iob_reg_o_gen.vbom
===================================================================
--- xlib/iob_reg_o_gen.vbom (nonexistent)
+++ xlib/iob_reg_o_gen.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+iob_reg_o_gen.vhd
Index: xlib/iob_keeper_gen.vbom
===================================================================
--- xlib/iob_keeper_gen.vbom (nonexistent)
+++ xlib/iob_keeper_gen.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+iob_keeper_gen.vhd
Index: xlib/iob_reg_i.vbom
===================================================================
--- xlib/iob_reg_i.vbom (nonexistent)
+++ xlib/iob_reg_i.vbom (revision 7)
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+xlib.vhd
+# components
+iob_reg_i_gen.vbom
+# design
+iob_reg_i.vhd
Index: xlib/iob_reg_o.vhd
===================================================================
--- xlib/iob_reg_o.vhd (nonexistent)
+++ xlib/iob_reg_o.vhd (revision 7)
@@ -0,0 +1,61 @@
+-- $Id: iob_reg_o.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: iob_reg_i - syn
+-- Description: Registered IOB, output only
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-12-16 101 1.0.1 add INIT generic port
+-- 2007-12-08 100 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity iob_reg_o is -- registered IOB, output
+ generic (
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DO : in slbit; -- output data
+ PAD : out slbit -- i/o pad
+ );
+end iob_reg_o;
+
+
+architecture syn of iob_reg_o is
+
+begin
+
+ IOB : iob_reg_o_gen
+ generic map (
+ DWIDTH => 1,
+ INIT => INIT)
+ port map (
+ CLK => CLK,
+ CE => CE,
+ DO(0) => DO,
+ PAD(0) => PAD
+ );
+
+end syn;
Index: xlib/iob_reg_o.vbom
===================================================================
--- xlib/iob_reg_o.vbom (nonexistent)
+++ xlib/iob_reg_o.vbom (revision 7)
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+xlib.vhd
+# components
+iob_reg_o_gen.vbom
+# design
+iob_reg_o.vhd
Index: xlib/iob_reg_io_gen.vhd
===================================================================
--- xlib/iob_reg_io_gen.vhd (nonexistent)
+++ xlib/iob_reg_io_gen.vhd (revision 7)
@@ -0,0 +1,123 @@
+-- $Id: iob_reg_io_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: iob_reg_io_gen - syn
+-- Description: Registered IOB, in/output, vector
+--
+-- Dependencies: iob_keeper_gen [sim only]
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-05-22 149 1.0.4 use internally TE to match OBUFT T polarity
+-- 2008-05-22 148 1.0.3 remove UNISIM prim's; PULL implemented only for sim
+-- 2008-05-18 147 1.0.2 add PULL generic, to enable PULL-UP,-DOWN or KEEPER
+-- 2007-12-16 101 1.0.1 add INIT generic ports
+-- 2007-12-08 100 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity iob_reg_io_gen is -- registered IOB, in/output, vector
+ generic (
+ DWIDTH : positive := 16; -- data port width
+ INITI : slbit := '0'; -- initial state ( in flop)
+ INITO : slbit := '0'; -- initial state (out flop)
+ INITE : slbit := '0'; -- initial state ( oe flop)
+ PULL : string := "NONE"); -- pull-up,-down or keeper
+ port (
+ CLK : in slbit; -- clock
+ CEI : in slbit := '1'; -- clock enable ( in flops)
+ CEO : in slbit := '1'; -- clock enable (out flops)
+ OE : in slbit; -- output enable
+ DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
+ DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
+ PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end iob_reg_io_gen;
+
+
+architecture syn of iob_reg_io_gen is
+
+ signal R_TE : slbit := not INITE;
+ signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INITI);
+ signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INITO);
+
+ constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
+ constant all_l : slv(DWIDTH-1 downto 0) := (others=>'L');
+ constant all_h : slv(DWIDTH-1 downto 0) := (others=>'H');
+
+ attribute iob : string;
+ attribute iob of R_TE : signal is "true";
+ attribute iob of R_DI : signal is "true";
+ attribute iob of R_DO : signal is "true";
+
+begin
+
+ assert PULL="NONE" or PULL="UP" or PULL="DOWN" or PULL="KEEP"
+ report "assert(PULL): only NONE, UP, DOWN, OR KEEP supported"
+ severity failure;
+
+ proc_regs: process (CLK)
+ begin
+ if CLK'event and CLK='1' then
+ R_TE <= not OE;
+ if CEI = '1' then
+ R_DI <= to_x01(PAD);
+ end if;
+ if CEO = '1' then
+ R_DO <= DO;
+ end if;
+ end if;
+ end process proc_regs;
+
+ proc_comb: process (R_TE, R_DO)
+ begin
+ if R_TE = '1' then
+ PAD <= all_z;
+ else
+ PAD <= R_DO;
+ end if;
+ end process proc_comb;
+
+ DI <= R_DI;
+
+-- Note: PULL (UP, DOWN or KEEP) is only implemented for simulation, not
+-- for inference in synthesis. Use pin attributes in UCF's or use
+-- iob_reg_io_gen_unisim
+--
+-- synthesis translate_off
+
+ PULL_UP: if PULL = "UP" generate
+ PAD <= all_h;
+ end generate PULL_UP;
+
+ PULL_DOWN: if PULL = "DOWN" generate
+ PAD <= all_l;
+ end generate PULL_DOWN;
+
+ PULL_KEEP: if PULL = "KEEP" generate
+ KEEPER : iob_keeper_gen
+ generic map (DWIDTH => DWIDTH)
+ port map (PAD => PAD);
+ end generate PULL_KEEP;
+
+-- synthesis translate_on
+
+end syn;
Index: xlib/iob_reg_i_gen.vhd
===================================================================
--- xlib/iob_reg_i_gen.vhd (nonexistent)
+++ xlib/iob_reg_i_gen.vhd (revision 7)
@@ -0,0 +1,67 @@
+-- $Id: iob_reg_i_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: iob_reg_i_gen - syn
+-- Description: Registered IOB, input only, vector
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-12-16 101 1.0.1 add INIT generic port
+-- 2007-12-08 100 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity iob_reg_i_gen is -- registered IOB, input, vector
+ generic (
+ DWIDTH : positive := 16; -- data port width
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DI : out slv(DWIDTH-1 downto 0); -- input data
+ PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end iob_reg_i_gen;
+
+
+architecture syn of iob_reg_i_gen is
+
+ signal R_DI : slv(DWIDTH-1 downto 0) := (others=>INIT);
+
+ attribute iob : string;
+ attribute iob of R_DI : signal is "true";
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+ if CLK'event and CLK='1' then
+ if CE = '1' then
+ R_DI <= PAD;
+ end if;
+ end if;
+ end process proc_regs;
+
+ DI <= R_DI;
+
+end syn;
Index: xlib/iob_reg_io_gen.vbom
===================================================================
--- xlib/iob_reg_io_gen.vbom (nonexistent)
+++ xlib/iob_reg_io_gen.vbom (revision 7)
@@ -0,0 +1,6 @@
+# libs
+../slvtypes.vhd
+# components
+[ghdl,isim]iob_keeper_gen.vbom
+# design
+iob_reg_io_gen.vhd
Index: xlib/iob_reg_i_gen.vbom
===================================================================
--- xlib/iob_reg_i_gen.vbom (nonexistent)
+++ xlib/iob_reg_i_gen.vbom (revision 7)
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+iob_reg_i_gen.vhd
Index: xlib/iob_reg_o_gen.vhd
===================================================================
--- xlib/iob_reg_o_gen.vhd (nonexistent)
+++ xlib/iob_reg_o_gen.vhd (revision 7)
@@ -0,0 +1,67 @@
+-- $Id: iob_reg_o_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: iob_reg_o_gen - syn
+-- Description: Registered IOB, output only, vector
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-12-16 101 1.0.1 add INIT generic port
+-- 2007-12-08 100 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity iob_reg_o_gen is -- registered IOB, output, vector
+ generic (
+ DWIDTH : positive := 16; -- data port width
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DO : in slv(DWIDTH-1 downto 0); -- output data
+ PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end iob_reg_o_gen;
+
+
+architecture syn of iob_reg_o_gen is
+
+ signal R_DO : slv(DWIDTH-1 downto 0) := (others=>INIT);
+
+ attribute iob : string;
+ attribute iob of R_DO : signal is "true";
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+ if CLK'event and CLK='1' then
+ if CE = '1' then
+ R_DO <= DO;
+ end if;
+ end if;
+ end process proc_regs;
+
+ PAD <= R_DO;
+
+end syn;
Index: xlib/iob_keeper_gen.vhd
===================================================================
--- xlib/iob_keeper_gen.vhd (nonexistent)
+++ xlib/iob_keeper_gen.vhd (revision 7)
@@ -0,0 +1,63 @@
+-- $Id: iob_keeper_gen.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2010- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: iob_keeper_gen - sim
+-- Description: keeper for IOB, vector
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-06-03 299 1.1 add explicit R_KEEP and driver
+-- 2008-05-22 148 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity iob_keeper_gen is -- keeper for IOB, vector
+ generic (
+ DWIDTH : positive := 16); -- data port width
+ port (
+ PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end iob_keeper_gen;
+
+-- Is't possible to directly use 'PAD<='H' in proc_pad. Introduced R_KEEP and
+-- the explicit driver 'PAD<=R_KEEP' to state the keeper function more clearly.
+
+architecture sim of iob_keeper_gen is
+ signal R_KEEP : slv(DWIDTH-1 downto 0) := (others=>'W');
+begin
+
+ proc_keep: process (PAD)
+ begin
+ for i in PAD'range loop
+ if PAD(i) = '1' then
+ R_KEEP(i) <= 'H';
+ elsif PAD(i) = '0' then
+ R_KEEP(i) <= 'L';
+ elsif PAD(i)='X' or PAD(i)='U' then
+ R_KEEP(i) <= 'W';
+ end if;
+ end loop;
+ PAD <= R_KEEP;
+ end process proc_keep;
+
+end sim;
Index: xlib/Makefile
===================================================================
--- xlib/Makefile (nonexistent)
+++ xlib/Makefile (revision 7)
@@ -0,0 +1,21 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version omment
+# 2007-12-08 100 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+.phony : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/vlib/Makefile.xflow
+#
+include $(VBOM_all:.vbom=.dep_xst)
+#
Index: xlib/xlib.vhd
===================================================================
--- xlib/xlib.vhd (nonexistent)
+++ xlib/xlib.vhd (revision 7)
@@ -0,0 +1,154 @@
+-- $Id: xlib.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: xlib
+-- Description: Xilinx specific components
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-05-23 149 1.0.4 add iob_io(_gen)
+-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);
+-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)
+-- 2007-12-16 101 1.0.1 add INIT generic ports
+-- 2007-12-08 100 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package xlib is
+
+component iob_reg_i is -- registered IOB, input
+ generic (
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DI : out slbit; -- input data
+ PAD : in slbit -- i/o pad
+ );
+end component;
+
+component iob_reg_i_gen is -- registered IOB, input, vector
+ generic (
+ DWIDTH : positive := 16; -- data port width
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DI : out slv(DWIDTH-1 downto 0); -- input data
+ PAD : in slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end component;
+
+component iob_reg_o is -- registered IOB, output
+ generic (
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DO : in slbit; -- output data
+ PAD : out slbit -- i/o pad
+ );
+end component;
+
+component iob_reg_o_gen is -- registered IOB, output, vector
+ generic (
+ DWIDTH : positive := 16; -- data port width
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DO : in slv(DWIDTH-1 downto 0); -- output data
+ PAD : out slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end component;
+
+component iob_reg_io is -- registered IOB, in/output
+ generic (
+ INITI : slbit := '0'; -- initial state ( in flop)
+ INITO : slbit := '0'; -- initial state (out flop)
+ INITE : slbit := '0'; -- initial state ( oe flop)
+ PULL : string := "NONE"); -- pull-up,-down or keeper
+ port (
+ CLK : in slbit; -- clock
+ CEI : in slbit := '1'; -- clock enable ( in flops)
+ CEO : in slbit := '1'; -- clock enable (out flops)
+ OE : in slbit; -- output enable
+ DI : out slbit; -- input data (read from pad)
+ DO : in slbit; -- output data (write to pad)
+ PAD : inout slbit -- i/o pad
+ );
+end component;
+
+component iob_reg_io_gen is -- registered IOB, in/output, vector
+ generic (
+ DWIDTH : positive := 16; -- data port width
+ INITI : slbit := '0'; -- initial state ( in flop)
+ INITO : slbit := '0'; -- initial state (out flop)
+ INITE : slbit := '0'; -- initial state ( oe flop)
+ PULL : string := "NONE"); -- pull-up,-down or keeper
+ port (
+ CLK : in slbit; -- clock
+ CEI : in slbit := '1'; -- clock enable ( in flops)
+ CEO : in slbit := '1'; -- clock enable (out flops)
+ OE : in slbit; -- output enable
+ DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
+ DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
+ PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end component;
+
+component iob_io is -- un-registered IOB, in/output
+ generic (
+ PULL : string := "NONE"); -- pull-up,-down or keeper
+ port (
+ OE : in slbit; -- output enable
+ DI : out slbit; -- input data (read from pad)
+ DO : in slbit; -- output data (write to pad)
+ PAD : inout slbit -- i/o pad
+ );
+end component;
+
+component iob_io_gen is -- un-registered IOB, in/output, vector
+ generic (
+ DWIDTH : positive := 16; -- data port width
+ PULL : string := "NONE"); -- pull-up,-down or keeper
+ port (
+ OE : in slbit; -- output enable
+ DI : out slv(DWIDTH-1 downto 0); -- input data (read from pad)
+ DO : in slv(DWIDTH-1 downto 0); -- output data (write to pad)
+ PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end component;
+
+component iob_keeper is -- keeper for IOB
+ port (
+ PAD : inout slbit -- i/o pad
+ );
+end component;
+
+component iob_keeper_gen is -- keeper for IOB, vector
+ generic (
+ DWIDTH : positive := 16); -- data port width
+ port (
+ PAD : inout slv(DWIDTH-1 downto 0) -- i/o pad
+ );
+end component;
+
+end xlib;
Index: xlib/iob_reg_i.vhd
===================================================================
--- xlib/iob_reg_i.vhd (nonexistent)
+++ xlib/iob_reg_i.vhd (revision 7)
@@ -0,0 +1,61 @@
+-- $Id: iob_reg_i.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: iob_reg_i - syn
+-- Description: Registered IOB, input only
+--
+-- Dependencies: -
+-- Test bench: -
+-- Target Devices: generic Spartan, Virtex
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-12-16 101 1.0.1 add INIT generic port
+-- 2007-12-08 100 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity iob_reg_i is -- registered IOB, input
+ generic (
+ INIT : slbit := '0'); -- initial state
+ port (
+ CLK : in slbit; -- clock
+ CE : in slbit := '1'; -- clock enable
+ DI : out slbit; -- input data
+ PAD : in slbit -- i/o pad
+ );
+end iob_reg_i;
+
+
+architecture syn of iob_reg_i is
+
+begin
+
+ IOB : iob_reg_i_gen
+ generic map (
+ DWIDTH => 1,
+ INIT => INIT)
+ port map (
+ CLK => CLK,
+ CE => CE,
+ DI(0) => DI,
+ PAD(0) => PAD
+ );
+
+end syn;
Index: xlib
===================================================================
--- xlib (nonexistent)
+++ xlib (revision 7)
xlib
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: slvtypes.vhd
===================================================================
--- slvtypes.vhd (nonexistent)
+++ slvtypes.vhd (revision 7)
@@ -0,0 +1,79 @@
+-- $Id: slvtypes.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: slvtypes
+-- Description: Short names for std_logic types.
+-- This package simply defines short hands for the std_logic
+-- types. slbit and slv are just aliases for std_logic and
+-- std_logic_vector. slv are subtype definitions for
+-- commonly used (n downto 0) vectors
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-08-24 162 1.0.4 add slv60 and 64
+-- 2008-08-22 161 1.0.3 add slvnn_m subtypes from pdp11 package
+-- 2008-03-24 129 1.0.2 add slv31
+-- 2007-12-08 100 1.0.1 add slv1
+-- 2007-06-02 44 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package slvtypes is
+
+ subtype slbit is std_logic; -- bit
+ subtype slv is std_logic_vector; -- vector
+
+ subtype slv1 is std_logic_vector( 0 downto 0); -- 1 bit word
+ subtype slv2 is std_logic_vector( 1 downto 0); -- 2 bit word
+ subtype slv3 is std_logic_vector( 2 downto 0); -- 3 bit word
+ subtype slv4 is std_logic_vector( 3 downto 0); -- 4 bit word
+ subtype slv5 is std_logic_vector( 4 downto 0); -- 5 bit word
+ subtype slv6 is std_logic_vector( 5 downto 0); -- 6 bit word
+ subtype slv7 is std_logic_vector( 6 downto 0); -- 7 bit word
+ subtype slv8 is std_logic_vector( 7 downto 0); -- 8 bit word
+ subtype slv9 is std_logic_vector( 8 downto 0); -- 9 bit word
+ subtype slv10 is std_logic_vector( 9 downto 0); -- 10 bit word
+ subtype slv11 is std_logic_vector(10 downto 0); -- 11 bit word
+ subtype slv12 is std_logic_vector(11 downto 0); -- 12 bit word
+ subtype slv13 is std_logic_vector(12 downto 0); -- 13 bit word
+ subtype slv14 is std_logic_vector(13 downto 0); -- 14 bit word
+ subtype slv15 is std_logic_vector(14 downto 0); -- 15 bit word
+ subtype slv16 is std_logic_vector(15 downto 0); -- 16 bit word
+
+ subtype slv17 is std_logic_vector(16 downto 0); -- 17 bit word
+ subtype slv18 is std_logic_vector(17 downto 0); -- 18 bit word
+ subtype slv19 is std_logic_vector(18 downto 0); -- 19 bit word
+ subtype slv20 is std_logic_vector(19 downto 0); -- 20 bit word
+ subtype slv21 is std_logic_vector(20 downto 0); -- 21 bit word
+ subtype slv22 is std_logic_vector(21 downto 0); -- 22 bit word
+ subtype slv23 is std_logic_vector(22 downto 0); -- 23 bit word
+ subtype slv24 is std_logic_vector(23 downto 0); -- 24 bit word
+ subtype slv31 is std_logic_vector(30 downto 0); -- 31 bit word
+ subtype slv32 is std_logic_vector(31 downto 0); -- 32 bit word
+
+ subtype slv60 is std_logic_vector(59 downto 0); -- 59 bit word
+ subtype slv64 is std_logic_vector(63 downto 0); -- 63 bit word
+
+ subtype slv8_1 is std_logic_vector(7 downto 1); -- 8 bit word, 1 lsb drop
+ subtype slv9_2 is std_logic_vector(8 downto 2); -- 9 bit word, 2 lsb drop
+ subtype slv13_1 is std_logic_vector(12 downto 1); -- 13 bit word, 1 lsb drop
+ subtype slv16_1 is std_logic_vector(15 downto 1); -- 16 bit word, 1 lsb drop
+ subtype slv18_1 is std_logic_vector(17 downto 1); -- 18 bit word, 1 lsb drop
+ subtype slv22_1 is std_logic_vector(21 downto 1); -- 22 bit word, 1 lsb drop
+
+end package slvtypes;
Index: balanced.opt
===================================================================
--- balanced.opt (nonexistent)
+++ balanced.opt (revision 7)
@@ -0,0 +1,95 @@
+FLOWTYPE = FPGA;
+###############################################################
+## Filename: balanced.opt
+##
+## Option File For Xilinx FPGA Implementation Flow
+##
+## Version: 8.1.1
+## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/virtex_fpga_balanced.opt,v 1.14 2004/10/01 22:29:20 rvklair Exp $
+###############################################################
+#
+# Options for Translator
+#
+# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
+#
+Program ngdbuild
+-p ; # Partname to use - picked from xflow commandline
+-nt timestamp; # NGO File generation. Regenerate only when
+ # source netlist is newer than existing
+ # NGO file (default)
+-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
+#-bm .bmm # Block RAM memory map file
+; # User design - pick from xflow command line
+.ngd; # Name of NGD file. Filebase same as design filebase
+End Program ngdbuild
+
+#
+# Options for Mapper
+#
+# Type "map -h " for a detailed list of map command line options
+#
+Program map
+-o _map.ncd; # Output Mapped ncd file
+-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
+# -fp .mfp; # Floorplan file
+# -gm incremental; # Guide mode
+# -timing; # Perform Timing-Driven Packing and Placement
+# -ol med; # Map Effort Levels. -ol [std|med|high]
+ # Note: If -timing is not specified, -ol switch is ignored.
+ # Device families supported: Virtex2, Virtex2P
+.ngd; # Input NGD file
+.pcf; # Physical constraints file
+END Program map
+
+#
+# Options for Post Map Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_map_trce
+-v 3; # Produce verbose timing report
+#-e 3; # Produce error report (limit 3 items/constraint)
+-xml _map.twx; # Output XML version of the timing report
+-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
+#-o _map.twr; # Output trace report file
+#-tsi _map.tsi; # Produce Timing Specification Interaction report
+#-fastpaths; # Report minimum paths in verbose mode
+#-nodatasheet; # Do not create the datasheet section of the report
+_map.ncd; # Input mapped ncd
+.pcf; # Physical constraints file
+END Program post_map_trce
+
+#
+# Options for Place and Route
+#
+# Type "par -h" for a detailed list of par command line options
+#
+Program par
+-w; # Overwrite existing placed and routed ncd
+-ol high; # Overall effort level
+-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
+# -gm incremental; # Guide mode
+_map.ncd; # Input mapped NCD file
+.ncd; # Output placed and routed NCD
+.pcf; # Input physical constraints file
+END Program par
+
+#
+# Options for Post Par Trace
+#
+# Type "trce -h" for a detailed list of trce command line options
+#
+Program post_par_trce
+-v 3; # Produce verbose timing report
+#-e 3; # Produce error report (limit 3 items/constraint)
+-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
+-xml .twx; # Output XML version of the timing report
+#-o .twr; # Output trace report file
+#-tsi .tsi; # Produce Timing Specification Interaction report
+#-fastpaths; # Report minimum paths in verbose mode
+#-nodatasheet; # Do not create the datasheet section of the report
+.ncd; # Input placed and routed ncd
+.pcf; # Physical constraints file
+END Program post_par_trce
+
+
Index: Makefile.ghdl
===================================================================
--- Makefile.ghdl (nonexistent)
+++ Makefile.ghdl (revision 7)
@@ -0,0 +1,47 @@
+# $Id: Makefile.ghdl 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2007-11-04 95 1.2.2 fix find statement in ghdl_tmp_clean
+# 2007-11-02 94 1.2.1 don't delete cext_*.o in ghdl_tmp_clean
+# 2007-07-08 65 1.2 support now autobuilding of _fsim and _tsim models
+# 2007-06-16 57 1.1 cleanup ghdl_clean handling
+# 2007-06-10 52 1.0 Initial version
+#
+GHDLIEEE = --ieee=synopsys
+GHDLUNISIM = -P$(XILINX)/ghdl/unisim
+GHDLSIMPRIM = -P$(XILINX)/ghdl/simprim
+GHDL = ghdl
+COMPILE.vhd = $(GHDL) -a $(GHDLIEEE)
+LINK.vhd = $(GHDL) -e $(GHDLIEEE)
+#
+% : %.vbom
+ vbomconv --ghdl_i $<
+ vbomconv --ghdl_m $<
+#
+# rules for _[ft]sim to use 'virtual' [ft]sim vbom's (derived from _ssim)
+#
+%_fsim : %_ssim.vbom
+ vbomconv --ghdl_i $*_fsim.vbom
+ vbomconv --ghdl_m $*_fsim.vbom
+#
+%_tsim : %_ssim.vbom
+ vbomconv --ghdl_i $*_tsim.vbom
+ vbomconv --ghdl_m $*_tsim.vbom
+#
+%.dep_ghdl: %.vbom
+ vbomconv --dep_ghdl $< > $@
+#
+.phony: ghdl_clean ghdl_tmp_clean
+#
+ghdl_clean: ghdl_tmp_clean
+ rm -f $(EXE_all)
+ rm -f $(EXE_all:%=%_[sft]sim)
+ rm -f $(EXE_all:%=%.exe)
+ rm -f $(EXE_all:%=%_[sft]sim.exe)
+ rm -f cext_*.o
+#
+ghdl_tmp_clean:
+ find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f
+ rm -f work-obj93.cf
+#
Index: xst_vhdl.opt
===================================================================
--- xst_vhdl.opt (nonexistent)
+++ xst_vhdl.opt (revision 7)
@@ -0,0 +1,63 @@
+FLOWTYPE = FPGA_SYNTHESIS;
+#########################################################
+## Filename: xst_vhdl.opt
+##
+## VHDL Option File for XST targeted for speed
+## This works for FPGA devices.
+##
+## Version: 8.1.1
+## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_vhdl_speed.opt,v 1.13 2004/10/01 22:29:20 rvklair Exp $
+#########################################################
+# Options for XST
+#
+#
+#
+Program xst
+-ifn _xst.scr; # input XST script file
+-ofn _xst.log; # output XST log file
+-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
+#
+# The options listed under ParamFile are the XST Properties that can be set by the
+# user. To turn on an option, uncomment by removing the '#' in front of the switch.
+#
+ParamFile: _xst.scr
+"run";
+#
+# Global Synthesis Options
+#
+"-ifn "; # Input/Project File Name
+"-ifmt VHDL"; # Input Format
+"-ofn "; # Output File Name
+"-ofmt ngc"; # Output File Format
+"-p "; # Target Device
+"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
+"-opt_level 2";
+"-uc .xcf"; # Constraint File name
+#"-case maintain"; # Specifies how to handle source name case
+ # upper, lower
+#"-keep_hierarchy NO"; # Prevents optimization across module boundaries
+ # CPLD default YES, FPGA default NO
+#"-write_timing_constraints NO"; # Write Timing Constraints
+ # YES, NO
+#"-cross_clock_analysis NO"; # Cross Clock Option
+ # YES, NO
+#"-iobuf YES"; # Add I/O Buffers to top level portS
+ # YES, NO
+#
+# The following are HDL Options
+#
+# The following are Xilinx FPGA specific options for Virtex, VirtexE, Virtex-II and Spartan2
+#
+#"-register_balancing NO"; # Register Balancing
+ # YES, NO, Forward, Backward
+#"-move_first_stage YES"; # Move First Flip-Flop Stage
+ # YES, NO
+#"-move_last_stage YES"; # Move Last Flip-Flop Stage
+ # YES, NO
+End ParamFile
+End Program xst
+#
+# See XST USER Guide Chapter 8 (Command Line Mode) for all XST options
+#
+
+
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 7)
@@ -0,0 +1,5 @@
+# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
+#
+#
+include Makefile.xflow
+#
Index: Makefile.xflow_cpld
===================================================================
--- Makefile.xflow_cpld (nonexistent)
+++ Makefile.xflow_cpld (revision 7)
@@ -0,0 +1,129 @@
+# $Id: Makefile.xflow_cpld 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-03-13 268 1.0 Initial version, cloned from .xflow Rev 252
+#---
+#
+# setup default device
+#
+ifndef ISE_PATH
+ISE_PATH = xc2c64a-7-vq44
+endif
+#
+# setup defaults for xflow option files for synthesis and implementation
+#
+ifndef XFLOWOPT_SYN
+XFLOWOPT_SYN = xst_vhdl.opt
+endif
+#
+ifndef XFLOWOPT_IMP
+XFLOWOPT_IMP = balanced.opt
+endif
+#
+XFLOW = xflow -p ${ISE_PATH}
+#
+# $@ first target
+# $< first dependency
+# $* stem in rule match
+#
+# when chaining, don't delete 'expensive' intermediate files:
+.SECONDARY :
+#
+# Synthesize (xst)
+# input: %.prj project file
+# output: %.ngc
+# %_xst.log xst log file
+#
+# Note: removed "cp ${RETROBASE}/vlib/${XFLOWOPT_SYN} ./ise" option
+#
+%.ngc: %.vbom
+ if [ ! -d ./ise ]; then mkdir ./ise; fi
+ (cd ./ise; vbomconv --xst_prj ../$< > $*.prj)
+ (cd ./ise; touch $*.xcf)
+ if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
+ if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
+ ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
+ (cd ./ise; chmod -x *.* )
+ if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
+ if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
+ @ echo "==============================================================="
+ @ echo "* Makefile.xflow: XST Diagnostic Summary *"
+ @ echo "==============================================================="
+ @ grep -i -A 1 ":.*:" $*_xst.log
+ @ echo "==============================================================="
+#
+# the following rule needed to generate an %_*sim.vhd in a ./tb sub-directory
+# it will look for a matching vbom in the parent directory
+%.ngc: ../%.vbom
+ if [ ! -d ./ise ]; then mkdir ./ise; fi
+ (cd ./ise; vbomconv --xst_prj ../$< > $*.prj)
+ (cd ./ise; touch $*.xcf)
+ if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
+ if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
+ ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
+ (cd ./ise; chmod -x *.* )
+ if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
+ if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
+ @ echo "==============================================================="
+ @ echo "* Makefile.xflow: XST Diagnostic Summary *"
+ @ echo "==============================================================="
+ @ grep -i -A 1 ":.*:" $*_xst.log
+ @ echo "==============================================================="
+#
+# Fit (map + cpldfit +
+# input: %.ngc project file
+# output: %.ncd
+# %.jed
+# %_tra.log translate (ngdbuild) log file (renamed %.bld)
+# %_fit.log cpldfit log file (renamed %.rpt)
+# %_tim.log timing analyser log file (renamed %.tim)
+# %_pad.log pad file (renamed %.pad)
+#
+# Note: removed "cp ${RETROBASE}/vlib/balanced.opt" option
+# currently ise 'density.opt' as steering file
+#
+%.ncd %.jed: %.ngc
+ if [ ! -d ./ise ]; then mkdir ./ise; fi
+ if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
+ if [ -r $*.ucf ]; then cp -p $*.ucf ./ise; fi
+ if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi
+ ${XFLOW} -wd ise -fit ${XFLOWOPT_IMP} $<
+ (cd ./ise; chmod -x *.* )
+ if [ -r ./ise/$*.ncd ]; then cp -p ./ise/$*.ncd .; fi
+ if [ -r ./ise/$*.jed ]; then cp -p ./ise/$*.jed .; fi
+ if [ -r ./ise/$*.bld ]; then cp -p ./ise/$*.bld ./$*_tra.log; fi
+ if [ -r ./ise/$*.rpt ]; then cp -p ./ise/$*.rpt ./$*_fit.log; fi
+ if [ -r ./ise/$*.tim ]; then cp -p ./ise/$*.tim ./$*_tim.log; fi
+ if [ -r ./ise/$*.pad ]; then cp -p ./ise/$*.pad ./$*_pad.log; fi
+#
+# generate dep_xst files from vbom
+#
+%.dep_xst: %.vbom
+ vbomconv --dep_xst $< > $@
+#
+# generate cpp'ed ucf files from ucf_cpp
+#
+%.ucf : %.ucf_cpp
+ cpp $*.ucf_cpp $*.ucf
+#
+# generate nested dependency rules for cpp'ed ucf files from ucf_cpp
+#
+%.dep_ucf_cpp : %.ucf_cpp
+ cpp -MM $*.ucf_cpp | sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp
+#
+.phony : ise_clean ise_tmp_clean
+#
+ise_clean: ise_tmp_clean
+ rm -rf *.ngc
+ rm -rf *.ncd
+ rm -rf *.jed
+ rm -rf *_xst.log
+ rm -rf *_tra.log
+ rm -rf *_fit.log
+ rm -rf *_tim.log
+ rm -rf *_pad.log
+#
+ise_tmp_clean:
+ rm -rf ./ise
+#
Index: Makefile.isim
===================================================================
--- Makefile.isim (nonexistent)
+++ Makefile.isim (revision 7)
@@ -0,0 +1,49 @@
+# $Id: Makefile.isim 311 2010-06-30 17:52:37Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2010-04-26 284 1.1 add _[sft]sim support
+# 2009-11-22 252 1.0 Initial version
+#
+FUSE = fuse
+#
+%_ISim : %.vbom
+ vbomconv -isim_prj $< > $*_isim.prj
+ $(FUSE) $* -prj $*_isim.prj -o $*_ISim
+ rm -rf $*_isim.prj
+#
+# rule for _ssim to call FUSE with right top level name
+#
+%_ISim_ssim : %_ssim.vbom
+ vbomconv -isim_prj $*_ssim.vbom > $*_isim_ssim.prj
+ $(FUSE) $* -prj $*_isim_ssim.prj -o $*_ISim_ssim
+ rm -rf $*_isim_ssim.prj
+#
+# rule for _[ft]sim to use 'virtual' _[ft]sim vbom's (derived from _ssim)
+#
+%_ISim_fsim : %_ssim.vbom
+ vbomconv -isim_prj $*_fsim.vbom > $*_isim_fsim.prj
+ $(FUSE) $* -prj $*_isim_fsim.prj -o $*_ISim_fsim
+ rm -rf $*_isim_fsim.prj
+#
+%_ISim_tsim : %_ssim.vbom
+ vbomconv -isim_prj $*_tsim.vbom > $*_isim_tsim.prj
+ $(FUSE) $* -prj $*_isim_tsim.prj -o $*_ISim_tsim
+ rm -rf $*_isim_tsim.prj
+#
+%.dep_isim: %.vbom
+ vbomconv --dep_isim $< > $@
+#
+.phony: isim_clean isim_tmp_clean
+#
+isim_clean: isim_tmp_clean
+ rm -f $(EXE_all:%=%_ISim)
+ rm -f $(EXE_all:%=%_ISim_ssim)
+ rm -f $(EXE_all:%=%_ISim_fsim)
+ rm -f $(EXE_all:%=%_ISim_tsim)
+#
+isim_tmp_clean:
+ rm -f isim.log isim.wdb
+ rm -f fuse.log
+ rm -rf isim
+#
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 7)
.
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log