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  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.6/rtl/bplib/atlys
    from Rev 22 to Rev 24
    ↔ Reverse comparison
  •

Rev 22 → Rev 24

/atlys_time_fx2_ic.ucf
0,0 → 1,18
## $Id: atlys_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-05 537 1.1 add VALID for hold time check
## 2013-01-05 471 1.0 Initial version (copied from nexys3)
##
## timing rules for a 30 MHz internal clock design:
## Period: 30 MHz
## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
## clk->out < 33.3-18.7 = 14.6 ns
## --> use 10 ns
##
 
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";
/atlys_pins_fx2.ucf
0,0 → 1,36
## $Id: atlys_pins_fx2.ucf 471 2013-01-05 19:46:38Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-01-05 471 1.0 Initial version
##
## Cypress EZ-USB FX2 Interface -- in Bank 0 ---------------------------------
##
##
NET "I_FX2_IFCLK" LOC = "c10" | IOSTANDARD=LVCMOS33;
##
NET "IO_FX2_DATA<0>" LOC = "a2" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<1>" LOC = "d6" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<2>" LOC = "c6" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<3>" LOC = "b3" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<4>" LOC = "a3" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<5>" LOC = "b4" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<6>" LOC = "a4" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<7>" LOC = "c5" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER;
##
NET "O_FX2_SLWR_N" LOC = "e13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLRD_N" LOC = "f13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLOE_N" LOC = "a15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_PKTEND_N" LOC = "c4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_FIFO<0>" LOC = "a14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_FIFO<1>" LOC = "b14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
## assume that PA.7 is used as FLAGD (and not as SLCS#)
NET "I_FX2_FLAG<0>" LOC = "b9" | IOSTANDARD=LVCMOS33; ## flag a (program)
NET "I_FX2_FLAG<1>" LOC = "a9" | IOSTANDARD=LVCMOS33; ## flag b (full)
NET "I_FX2_FLAG<2>" LOC = "c15" | IOSTANDARD=LVCMOS33; ## flag c (empty)
NET "I_FX2_FLAG<3>" LOC = "b2" | IOSTANDARD=LVCMOS33; ## flag d (slcs)
##
/atlys_pins_pmod.ucf
0,0 → 1,25
## $Id: atlys_pins_pmod.ucf 403 2011-08-06 17:36:22Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-08-06 403 1.0 Initial version
##
## Pmod connectors -----------------------------------------------------------
##
## front view (towards PCB edge):
##
## +-------------------------+
## | VCC GND P-4 P-3 P-2 P-1 |
## | VCC GND P10 P-9 P-8 P-7 |
## =============================
## < HDMI connector>
##
## Pmod A (top: 0-3; bot: 4-7; all 8 shared with HDMI Type D connector...)
NET "IO_PMODA<0>" LOC = "t3" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<1>" LOC = "r3" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<2>" LOC = "p6" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<3>" LOC = "n5" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<4>" LOC = "v9" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<5>" LOC = "t9" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<6>" LOC = "v4" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<7>" LOC = "t4" | IOSTANDARD=LVCMOS33;
/atlys_pins.ucf
0,0 → 1,61
## $Id: atlys_pins.ucf 414 2011-10-11 19:38:12Z mueller $
##
## Pin locks for Atlys core functionality
## - USB UART
## - human I/O (switches, buttons, leds)
##
## Revision History:
## Date Rev Version Comment
## 2011-10-10 413 1.0.2 new BTN sequence: clockwise(U-R-D-L) - mid - reset
## 2011-08-05 403 1.0.1 Fix IOSTANDARD typos; rename _GPIO_ to _HIO_
## 2011-08-04 402 1.0 Initial version
##
## Notes:
## - Bank 0+1 are 3V3; Bank 2 switchable 3V3 or 2V5; Bank 3 is 1V8 (DDR mem)
## - default is DRIVE=12 | SLEW=SLOW
## - pin names from Digilent master AtlysGeneralUCF.zip are given as comments
##
## clocks --------------------------------------------------------------------
## AtlysGeneralUCF: clk
##
NET "I_CLK100" LOC = "l15" | IOSTANDARD=LVCMOS25;
##
## USB UART interface --------------------------------------------------------
## AtlysGeneralUCF: UartRx, UartTx (crossed!)
##
NET "I_USB_RXD" LOC = "a16" | IOSTANDARD=LVCMOS33;
NET "O_USB_TXD" LOC = "b16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
##
## SWIs ----------------------------------------------------------------------
## AtlysGeneralUCF: sw<0:7>
##
NET "I_HIO_SWI<0>" LOC = "a10" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<1>" LOC = "d14" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<2>" LOC = "c14" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<3>" LOC = "p15" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<4>" LOC = "p12" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<5>" LOC = "r5" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<6>" LOC = "t5" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<7>" LOC = "e4" | IOSTANDARD=LVCMOS33;
##
## BTNs ----------------------------------------------------------------------
## AtlysGeneralUCF: btn<0:5>; clockwise(U-R-D-L) - middle - reset
##
NET "I_HIO_BTN<0>" LOC = "n4" | IOSTANDARD=LVCMOS18; # BTNU
NET "I_HIO_BTN<1>" LOC = "f6" | IOSTANDARD=LVCMOS18; # BTNR
NET "I_HIO_BTN<2>" LOC = "p3" | IOSTANDARD=LVCMOS18; # BTND
NET "I_HIO_BTN<3>" LOC = "p4" | IOSTANDARD=LVCMOS18; # BTNL
NET "I_HIO_BTN<4>" LOC = "f5" | IOSTANDARD=LVCMOS18; # BTNC
NET "I_HIO_BTN<5>" LOC = "t15" | IOSTANDARD=LVCMOS18; # RESET (act.low!!)
##
## LEDs ----------------------------------------------------------------------
## AtlysGeneralUCF: Led<0:7>
##
NET "O_HIO_LED<0>" LOC = "u18" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<1>" LOC = "m14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<2>" LOC = "n14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<3>" LOC = "l14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<4>" LOC = "m13" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<5>" LOC = "d4" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<6>" LOC = "p16" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<7>" LOC = "n12" | IOSTANDARD=LVCMOS33;
/atlys_pins_pma0_rs232.ucf
0,0 → 1,23
## $Id: atlys_pins_pma0_rs232.ucf 403 2011-08-06 17:36:22Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-08-06 403 1.0 Initial version
##
## Pmod connector A top / usage RS232 for FTDI USB serport -------------------
##
## front view (towards PCB edge):
##
## P-6 P-1
## | |
## +-------------------------+
## | VCC GND TXD RXD CTS RTS |
## | VCC GND ... ... ... ... |
## =============================
## < HDMI connector>
##
##
NET "O_FUSP_RTS_N" LOC = "t3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
NET "I_FUSP_CTS_N" LOC = "r3" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "I_FUSP_RXD" LOC = "p6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "O_FUSP_TXD" LOC = "n5" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
/.
. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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