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URL https://opencores.org/ocsvn/w11/w11/trunk

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  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.6/rtl/bplib/nexys3
    from Rev 22 to Rev 24
    ↔ Reverse comparison
  •

Rev 22 → Rev 24

/tb/tb_nexys3_fusp_cuff.vbom
0,0 → 1,26
# Not meant for direct top level usage. Used with
# tb_nexys3_fusp_cuff_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom}
# design
tb_nexys3_fusp_cuff.vhd
@top:tb_nexys3_fusp_cuff
/tb/tb_nexys3_fusp.vhd
0,0 → 1,264
-- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp - sim
-- Description: Test bench for nexys3 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
 
entity tb_nexys3_fusp is
end tb_nexys3_fusp;
 
architecture sim of tb_nexys3_fusp is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
 
signal RX_HOLD : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
 
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
 
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
 
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
 
signal R_PORTSEL : slbit := '0';
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
 
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
 
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
UUT : nexys3_fusp_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
 
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
 
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
 
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
 
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
 
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
 
end sim;
/tb/tb_nexys3_fusp.vbom
0,0 → 1,25
# Not meant for direct top level usage. Used with
# tb_nexys3_fusp_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}
# design
tb_nexys3_fusp.vhd
@top:tb_nexys3_fusp
/tb/tb_nexys3_fusp_cuff.vhd
0,0 → 1,336
-- $Id: tb_nexys3_fusp_cuff.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_fusp_cuff - sim
-- Description: Test bench for nexys3 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- fx2lib/tb/fx2_2fifo_core
-- nexys3_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
-- tb_nexys2_fusp_cuff)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
 
entity tb_nexys3_fusp_cuff is
end tb_nexys3_fusp_cuff;
 
architecture sim of tb_nexys3_fusp_cuff is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
 
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
 
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
 
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_PPCM_CE_N : slbit := '0';
signal O_PPCM_RST_N : slbit := '0';
 
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
 
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
 
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
 
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
 
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
SB_CLKSTOP <= CLK_STOP;
 
CLKGEN_COM : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
 
N3CORE : entity work.tb_nexys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
UUT : nexys3_fusp_cuff_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_PPCM_CE_N => O_PPCM_CE_N,
O_PPCM_RST_N => O_PPCM_RST_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
 
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXACT => UART_RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
 
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
 
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
 
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
 
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
 
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
 
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
 
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_FX2 <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
 
end sim;
/tb/.cvsignore
0,0 → 1,2
tb_nexys3_fusp_dummy
tb_nexys3_fusp_cuff_dummy
/tb/Makefile
0,0 → 1,34
# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 432 1.0 Initial version
#
EXE_all = tb_nexys3_fusp_dummy
EXE_all += tb_nexys3_fusp_cuff_dummy
#
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
endif
#
/tb/tb_nexys3_core.vhd
0,0 → 1,96
-- $Id: tb_nexys3_core.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys3_core - sim
-- Description: Test bench for nexys3 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys3 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
 
entity tb_nexys3_core is
port (
I_SWI : out slv8; -- n3 switches
I_BTN : out slv5; -- n3 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys3_core;
 
architecture sim of tb_nexys3_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
 
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
 
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
 
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
/tb/tb_nexys3_core.vbom
0,0 → 1,10
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
../../micron/mt45w8mw16b.vbom
# design
tb_nexys3_core.vhd
/tb
tb Property changes : Added: svn:ignore ## -0,0 +1,34 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nexys3_fusp_dummy +tb_nexys3_fusp_cuff_dummy Index: nexys3_pins_pmb0_rs232.ucf =================================================================== --- nexys3_pins_pmb0_rs232.ucf (nonexistent) +++ nexys3_pins_pmb0_rs232.ucf (revision 24) @@ -0,0 +1,13 @@ +## $Id: nexys3_pins_pmb0_rs232.ucf 534 2013-09-22 21:37:24Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-11-20 430 1.0 Initial version +## +## Pmod connector B top / usage RS232 for FTDI USB serport ------------------- +## +NET "O_FUSP_RTS_N" LOC = "k2" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "k1" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "l4" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "l3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +## Index: nexys3_time_fx2_ic.ucf =================================================================== --- nexys3_time_fx2_ic.ucf (nonexistent) +++ nexys3_time_fx2_ic.ucf (revision 24) @@ -0,0 +1,18 @@ +## $Id: nexys3_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-05 537 1.1 add VALID for hold time check +## 2012-01-01 448 1.0 Initial version +## +## timing rules for a 30 MHz internal clock design: +## Period: 30 MHz +## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns +## clk->out < 33.3-18.7 = 14.6 ns +## --> use 10 ns +## + +NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK"; +TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %; +OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK"; +OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK"; Index: nexys3lib.vhd =================================================================== --- nexys3lib.vhd (nonexistent) +++ nexys3lib.vhd (revision 24) @@ -0,0 +1,158 @@ +-- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nexys3lib +-- Description: Nexys 3 components +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif +-- 2011-11-25 432 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nexys3lib is + +component nexys3_aif is -- NEXYS 3, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit -- ppcm: ... + ); +end component; + +component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end component; + +component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +end package nexys3lib; Index: nexys3_pins_fx2.ucf =================================================================== --- nexys3_pins_fx2.ucf (nonexistent) +++ nexys3_pins_fx2.ucf (revision 24) @@ -0,0 +1,38 @@ +## $Id: nexys3_pins_fx2.ucf 455 2012-01-24 09:11:25Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2012-01-23 455 1.2 fix SLOE_N (h4->h6) +## 2012-01-01 448 1.1 use 12/FAST instead of 6/SLOW for _DATA<*> +## 2011-11-27 433 1.0 Initial version +## +## Cypress EZ-USB FX2 Interface -- in Bank 3 --------------------------------- +## +## +NET "I_FX2_IFCLK" LOC = "h2" | IOSTANDARD=LVCMOS33; +## +NET "IO_FX2_DATA<0>" LOC = "e1" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<1>" LOC = "f4" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<2>" LOC = "f3" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<3>" LOC = "d2" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<4>" LOC = "d1" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<5>" LOC = "h7" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<6>" LOC = "g6" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<7>" LOC = "e4" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER; +## +NET "O_FX2_SLWR_N" LOC = "c1" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLRD_N" LOC = "c2" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLOE_N" LOC = "h6" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_PKTEND_N" LOC = "d3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_FIFO<0>" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_FIFO<1>" LOC = "e3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +## assume that PA.7 is used as FLAGD (and not as SLCS#) +NET "I_FX2_FLAG<0>" LOC = "h1" | IOSTANDARD=LVCMOS33; ## flag a (program) +NET "I_FX2_FLAG<1>" LOC = "k4" | IOSTANDARD=LVCMOS33; ## flag b (full) +NET "I_FX2_FLAG<2>" LOC = "f5" | IOSTANDARD=LVCMOS33; ## flag c (empty) +NET "I_FX2_FLAG<3>" LOC = "f6" | IOSTANDARD=LVCMOS33; ## flag d (slcs) +## Index: nexys3_pins.ucf =================================================================== --- nexys3_pins.ucf (nonexistent) +++ nexys3_pins.ucf (revision 24) @@ -0,0 +1,135 @@ +## $Id: nexys3_pins.ucf 432 2011-11-25 20:16:28Z mueller $ +## +## Pin locks for Nexys 3 core functionality +## - USB UART +## - human I/O (switches, buttons, leds, display) +## - cram +## +## Revision History: +## Date Rev Version Comment +## 2011-11-23 432 1.0.2 add PPCM controls +## 2011-10-10 413 1.0.1 new BTN sequence: clockwise(U-R-D-L) - middle +## 2011-07-04 388 1.0 Initial version +## +## Note: default is DRIVE=12 | SLEW=SLOW +## +## Assume that VCCB0 is jumpered for 2.5 V (for VHDCI LVDS usage) +## +## clocks -- in bank 2 ------------------------------------------------------- +NET "I_CLK100" LOC = "v10" | IOSTANDARD=LVCMOS33; +## +## USB UART Interface -- in bank 1-------------------------------------------- +## I_RXD -> signal MCU_RX -> TXD pin of FT232R +## O_TXD -> signal MCU_TX -> RXD pin of FT232R +## I_CTS_N ?? signal RTS -> RTS pin of FT232R (only on J14) +## O_RTS_N ?? signal CTS -> CTS pin of FT232R (only on J14) +NET "I_RXD" LOC = "n17" | IOSTANDARD=LVCMOS33; +NET "O_TXD" LOC = "n18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## switches -- in bank 2 ----------------------------------------------------- +NET "I_SWI<0>" LOC = "t10" | IOSTANDARD=LVCMOS33; +NET "I_SWI<1>" LOC = "t9" | IOSTANDARD=LVCMOS33; +NET "I_SWI<2>" LOC = "v9" | IOSTANDARD=LVCMOS33; +NET "I_SWI<3>" LOC = "m8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<4>" LOC = "n8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<5>" LOC = "u8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<6>" LOC = "v8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<7>" LOC = "t5" | IOSTANDARD=LVCMOS33; +## +## buttons -- in bank 0------------------------------------------------------- +## sequence: clockwise(U-R-D-L) - middle +NET "I_BTN<0>" LOC = "a8" | IOSTANDARD=LVCMOS25; # BTNU +NET "I_BTN<1>" LOC = "d9" | IOSTANDARD=LVCMOS25; # BTNR +NET "I_BTN<2>" LOC = "c9" | IOSTANDARD=LVCMOS25; # BTND +NET "I_BTN<3>" LOC = "c4" | IOSTANDARD=LVCMOS25; # BTNL +NET "I_BTN<4>" LOC = "b8" | IOSTANDARD=LVCMOS25; # BTNS +## +## LEDs -- in bank 2 --------------------------------------------------------- +NET "O_LED<0>" LOC = "u16" | IOSTANDARD=LVCMOS33; +NET "O_LED<1>" LOC = "v16" | IOSTANDARD=LVCMOS33; +NET "O_LED<2>" LOC = "u15" | IOSTANDARD=LVCMOS33; +NET "O_LED<3>" LOC = "v15" | IOSTANDARD=LVCMOS33; +NET "O_LED<4>" LOC = "m11" | IOSTANDARD=LVCMOS33; +NET "O_LED<5>" LOC = "n11" | IOSTANDARD=LVCMOS33; +NET "O_LED<6>" LOC = "r11" | IOSTANDARD=LVCMOS33; +NET "O_LED<7>" LOC = "t11" | IOSTANDARD=LVCMOS33; +NET "O_LED<*>" DRIVE=12 | SLEW=SLOW; +## +## 7 segment display -- in bank 1 -------------------------------------------- +NET "O_ANO_N<0>" LOC = "n16" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<1>" LOC = "n15" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<2>" LOC = "p18" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<3>" LOC = "p17" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW; +## +NET "O_SEG_N<0>" LOC = "t17" | IOSTANDARD=LVCMOS33; # CA +NET "O_SEG_N<1>" LOC = "t18" | IOSTANDARD=LVCMOS33; # CB +NET "O_SEG_N<2>" LOC = "u17" | IOSTANDARD=LVCMOS33; # CC +NET "O_SEG_N<3>" LOC = "u18" | IOSTANDARD=LVCMOS33; # CD +NET "O_SEG_N<4>" LOC = "m14" | IOSTANDARD=LVCMOS33; # CE +NET "O_SEG_N<5>" LOC = "n14" | IOSTANDARD=LVCMOS33; # CF +NET "O_SEG_N<6>" LOC = "l14" | IOSTANDARD=LVCMOS33; # CG +NET "O_SEG_N<7>" LOC = "m13" | IOSTANDARD=LVCMOS33; # DP +NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW; +## +## CRAM -- in bank 2 (data) and 1 (addr) ------------------------------------- +NET "O_MEM_CE_N" LOC = "l15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_WE_N" LOC = "m16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_OE_N" LOC = "l18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_BE_N<0>" LOC = "k16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<1>" LOC = "k15" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_ADV_N" LOC = "h18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CLK" LOC = "r10" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CRE" LOC = "m18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "I_MEM_WAIT" LOC = "v4" | IOSTANDARD=LVCMOS33 | PULLDOWN; +## +NET "O_MEM_ADDR<0>" LOC = "k18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<1>" LOC = "k17" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<2>" LOC = "j18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<3>" LOC = "j16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<4>" LOC = "g18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<5>" LOC = "g16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<6>" LOC = "h16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<7>" LOC = "h15" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<8>" LOC = "h14" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<9>" LOC = "h13" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<10>" LOC = "f18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<11>" LOC = "f17" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<12>" LOC = "k13" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<13>" LOC = "k12" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<14>" LOC = "e18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<15>" LOC = "e16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<16>" LOC = "g13" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<17>" LOC = "h12" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<18>" LOC = "d18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<19>" LOC = "d17" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<20>" LOC = "g14" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<21>" LOC = "f14" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<22>" LOC = "c18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST; +## +NET "IO_MEM_DATA<0>" LOC = "r13" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<1>" LOC = "t14" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<2>" LOC = "v14" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<3>" LOC = "u5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<4>" LOC = "v5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<5>" LOC = "r3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<6>" LOC = "t3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<7>" LOC = "r5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<8>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<9>" LOC = "p6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<10>" LOC = "p12" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<11>" LOC = "u13" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<12>" LOC = "v13" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<13>" LOC = "u10" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<14>" LOC = "r8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<15>" LOC = "t8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## +## PPCM -- parallel PCM memory ----------------------------------------------- +NET "O_PPCM_CE_N" LOC = "l17" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW; +NET "O_PPCM_RST_N" LOC = "t4" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW; +## Index: . =================================================================== --- . (nonexistent) +++ . (revision 24)
. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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