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  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.6/rtl/bplib/nxcramlib/tb
    from Rev 19 to Rev 24
    ↔ Reverse comparison
  •

Rev 19 → Rev 24

/Makefile
0,0 → 1,33
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 433 1.0 Initial version (cloned)
#
EXE_all = tb_nx_cram_memctl_as
#
include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_isim.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
endif
#
/tb_nx_cram_memctl.vbom
0,0 → 1,15
# Not meant for direct top level usage. Used with
# tb_nx_cram_memctl_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simlib.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../micron/mt45w8mw16b.vbom
${uut := tbd_nx_cram_memctl_as.vbom}
# design
tb_nx_cram_memctl.vhd
@top:tb_nx_cram_memctl
/tb_nx_cram_memctl.vhd
0,0 → 1,376
-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nx_cram_memctl - sim
-- Description: Test bench for nx_cram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/micron/mt45w8mw16b
-- tbd_nx_cram_memctl [UUT, abstact]
--
-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as)
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.4 use new simclk/simclkcnt
-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl
-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage
-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl
-- 2010-05-23 293 1.0 Initial version (derived from tb_s3_sram_memctl)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
 
entity tb_nx_cram_memctl is
end tb_nx_cram_memctl;
 
architecture sim of tb_nx_cram_memctl is
component tbd_nx_cram_memctl is -- CRAM driver (abstract) [tb design]
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end component;
 
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv22 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slbit := '0';
signal O_MEM_BE_N : slv2 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADV_N : slbit := '0';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'0');
signal IO_MEM_DATA : slv16 := (others=>'0');
 
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv22 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv22 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv22 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 7.5 ns; -- compatible ucf for
constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as
 
begin
 
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
 
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
UUT : tbd_nx_cram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
proc_stim: process
file fstim : text open read_mode is "tb_nx_cram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv22 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
 
begin
wait for clock_offset - setup_time;
 
file_loop: while not endfile(fstim) loop
 
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
 
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
 
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
 
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 7, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
 
nbusy := 0;
while BUSY='1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
 
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
 
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
 
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 7, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
 
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
 
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
 
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
 
testempty_ea(iline);
 
end loop; -- file fstim
 
wait for 10*clock_period;
 
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
 
CLK_STOP <= '1';
 
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
 
end process proc_stim;
 
proc_moni: process
variable oline : line;
begin
 
loop
wait until rising_edge(CLK);
 
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
 
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
 
 
proc_memon: process
variable oline : line;
begin
 
loop
wait until rising_edge(CLK);
 
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 6, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 4, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
 
 
end sim;
/tb_nx_cram_memctl_as.vhd
0,0 → 1,39
-- $Id: tb_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nx_cram_memctl_as
-- Description: Configuration tb_nx_cram_memctl_as for tb_nx_cram_memctl
--
-- Dependencies: tbd_nx_cram_memctl_as
-- To test: nx_cram_memctl_as
--
-- Verified (with tb_nx_cram_memctl_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2010-05-30 297 - 0.26 11.4 L68 xc3s1200e ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1 renamed from tb_n2_cram_memctl_as
-- 2010-05-30 297 1.0 Initial version
------------------------------------------------------------------------------
 
configuration tb_nx_cram_memctl_as of tb_nx_cram_memctl is
 
for sim
for all :tbd_nx_cram_memctl
use entity work.tbd_nx_cram_memctl_as;
end for;
end for;
 
end tb_nx_cram_memctl_as;
/tb_nx_cram_memctl_stim.dat
0,0 → 1,212
# $Id: tb_nx_cram_memctl_stim.dat 433 2011-11-27 22:04:39Z mueller $
#
.memon 0
#
C write full word 16 cells
#
write 000000 1111 30201000
write 000001 1111 31211101
write 000002 1111 32221202
write 000003 1111 33231303
write 000004 1111 34241404
write 000005 1111 35251505
write 000006 1111 36261606
write 000007 1111 37271707
write 000008 1111 38281808
write 000009 1111 39291909
write 00000a 1111 3a2a1a0a
write 00000b 1111 3b2b1b0b
write 00000c 1111 3c2c1c0c
write 00000d 1111 3d2d1d0d
write 00000e 1111 3e2e1e0e
write 00000f 1111 3f2f1f0f
#
C read 16 cells
#
read 000000 30201000
read 000001 31211101
read 000002 32221202
read 000003 33231303
read 000004 34241404
read 000005 35251505
read 000006 36261606
read 000007 37271707
read 000008 38281808
read 000009 39291909
read 00000a 3a2a1a0a
read 00000b 3b2b1b0b
read 00000c 3c2c1c0c
read 00000d 3d2d1d0d
read 00000e 3e2e1e0e
read 00000f 3f2f1f0f
#
C write selected bytes in first 16 cells
#
write 000000 0000 70605040
write 000001 0001 71615141
write 000002 0010 72625242
write 000003 0011 73635343
write 000004 0100 74645444
write 000005 0101 75655545
write 000006 0110 76665646
write 000007 0111 77675747
write 000008 1000 78685848
write 000009 1001 79695949
write 00000a 1010 7a6a5a4a
write 00000b 1011 7b6b5b4b
write 00000c 1100 7c6c5c4c
write 00000d 1101 7d6d5d4d
write 00000e 1110 7e6e5e4e
write 00000f 1111 7f6f5f4f
#
C read back
#
read 000000 30201000
read 000001 31211141
read 000002 32225202
read 000003 33235343
read 000004 34641404
read 000005 35651545
read 000006 36665606
read 000007 37675747
read 000008 78281808
read 000009 79291949
read 00000a 7a2a5a0a
read 00000b 7b2b5b4b
read 00000c 7c6c1c0c
read 00000d 7d6d1d4d
read 00000e 7e6e5e0e
read 00000f 7f6f5f4f
#
C read and write with waits
#
.wait 12
write 000010 1111 30201000
.wait 11
write 000011 1111 31211101
.wait 10
write 000012 1111 32221202
.wait 9
write 000013 1111 33231303
.wait 8
write 000014 1111 34241404
.wait 7
write 000015 1111 35251505
.wait 6
write 000016 1111 36261606
.wait 5
write 000017 1111 37271707
.wait 4
write 000018 1111 38281808
.wait 3
write 000019 1111 39291909
.wait 2
write 00001a 1111 3a2a1a0a
.wait 1
write 00001b 1111 3b2b1b0b
write 00001c 1111 3b2b1b0b
#
.wait 12
read 000010 30201000
.wait 11
read 000011 31211101
.wait 10
read 000012 32221202
.wait 9
read 000013 33231303
.wait 8
read 000014 34241404
.wait 7
read 000015 35251505
.wait 6
read 000016 36261606
.wait 5
read 000017 37271707
.wait 4
read 000018 38281808
.wait 3
read 000019 39291909
.wait 2
read 00001a 3a2a1a0a
.wait 1
read 00000e 7e6e5e0e
read 00000f 7f6f5f4f
#
C read and write mixed, with waits
#
.wait 2
write 000014 1111 34241404
.wait 2
read 000012 32221202
.wait 2
write 000015 1111 35251505
.wait 2
read 000013 33231303
#
.wait 1
write 000016 1111 36261606
.wait 1
read 000014 34241404
.wait 1
write 000017 1111 37271707
.wait 1
read 000015 35251505
#
write 000018 1111 38281808
read 000016 36261606
write 000019 1111 39291909
read 000017 37271707
#
.wait 2
write 00001a 1111 3a2a1a0a
write 00001b 1111 3b2b1b0b
.wait 2
read 000018 38281808
read 000019 39291909
.wait 2
write 00001c 1111 3c2c1c0c
write 00001d 1111 3d2d1d0d
.wait 2
read 00001a 3a2a1a0a
read 00001b 3b2b1b0b
#
.wait 1
write 00001e 1111 3e2e1e0e
write 00001f 1111 3f2f1f0f
.wait 1
read 00001c 3c2c1c0c
read 00001d 3d2d1d0d
.wait 1
write 000014 0100 74645444
write 000015 0101 75655545
.wait 1
read 00001e 3e2e1e0e
read 00001f 3f2f1f0f
#
write 000016 0110 76665646
write 000017 0111 77675747
read 000010 30201000
read 000011 31211101
write 000018 1000 78685848
write 000019 1001 79695949
read 000012 32221202
read 000013 33231303
#
write 00001a 1010 7a6a5a4a
write 00001b 1011 7b6b5b4b
write 00001c 1100 7c6c5c4c
read 000014 34641404
read 000015 35651545
read 000016 36665606
write 00001d 1101 7d6d5d4d
write 00001e 1110 7e6e5e4e
write 00001f 1111 7f6f5f4f
read 000017 37675747
read 000018 78281808
read 000019 79291949
read 00001a 7a2a5a0a
read 00001b 7b2b5b4b
read 00001c 7c6c1c0c
read 00001d 7d6d1d4d
read 00001e 7e6e5e0e
read 00001f 7f6f5f4f
/tb_nx_cram_memctl_as.vbom
0,0 → 1,6
# configure tb_nx_cram_memctl with tbd_nx_cram_memctl_as target;
# use vhdl configure file (tb_nx_cram_memctl_as.vhd) to allow
# that all configurations will co-exist in work library
uut = tbd_nx_cram_memctl_as.vbom
tb_nx_cram_memctl.vbom
tb_nx_cram_memctl_as.vhd
/tbw.dat
0,0 → 1,4
# $Id: tbw.dat 433 2011-11-27 22:04:39Z mueller $
#
[tb_nx_cram_memctl_as]
tb_nx_cram_memctl_stim = tb_nx_cram_memctl_stim.dat
/tbd_nx_cram_memctl_as.vhd
0,0 → 1,121
-- $Id: tbd_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_nx_cram_memctl_as - syn
-- Description: Wrapper for nx_cram_memctl_as to avoid records & generics.
-- It has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: nx_cram_memctl_as
-- To test: nx_cram_memctl_as
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 122 0 107 t 11.4
-- 2010-05-30 297 11.4 L68 xc3s1200e-4 91 99 0 95 t 13.1
--
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_memctl
-- 2010-06-03 298 1.0.1 add hack to force IOB'FFs to O_MEM_ADDR
-- 2010-05-30 297 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.nxcramlib.all;
 
entity tbd_nx_cram_memctl_as is -- CRAM driver (async mode) [tb design]
-- generic: READ0=2;READ1=2;WRITE=3
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv22; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tbd_nx_cram_memctl_as;
 
 
architecture syn of tbd_nx_cram_memctl_as is
 
signal ADDR_X : slv22 := (others=>'0');
begin
 
-- Note: This is a HACk to ensure that the IOB flops are on the O_MEM_ADDR
-- pins. Without par might choose to use IFF's on ADDR, causing varying
-- routing delays to O_MEM_ADDR. Didn't find a better way, setting
-- iob "false" attributes in ADDR didn't help.
-- This logic doesn't hurt, and prevents that IFFs for ADDR compete with
-- OFF's for O_MEM_ADDR.
ADDR_X <= ADDR when RESET='0' else (others=>'0');
MEMCTL : nx_cram_memctl_as
generic map (
READ0DELAY => 2,
READ1DELAY => 2,
WRITEDELAY => 3)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR_X,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
end syn;
/tbd_nx_cram_memctl_as.vbom
0,0 → 1,7
# libs
../../../vlib/slvtypes.vhd
../nxcramlib.vhd
# components
../nx_cram_memctl_as.vbom
# design
tbd_nx_cram_memctl_as.vhd
/.cvsignore
0,0 → 1,5
tb_nx_cram_memctl_as
tb_nx_cram_memctl_as_[sft]sim
tb_nx_cram_memctl_as_ISim
tb_nx_cram_memctl_as_ISim_[sft]sim
tb_nx_cram_memctl_stim
/tb_nx_cram_memctl_as_ssim.vbom
0,0 → 1,5
# configure for _*sim case
#
uut = tbd_nx_cram_memctl_as_ssim.vhd
tb_nx_cram_memctl_as.vbom
@top:tb_nx_cram_memctl_as
/.
. Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nx_cram_memctl_as +tb_nx_cram_memctl_as_[sft]sim +tb_nx_cram_memctl_as_ISim +tb_nx_cram_memctl_as_ISim_[sft]sim +tb_nx_cram_memctl_stim

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