OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

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  • This comparison shows the changes necessary to convert path
    /w11/tags/w11a_V0.6/rtl/bplib
    from Rev 22 to Rev 24
    Reverse comparison

Rev 22 → Rev 24

/fx2rlink/rlink_sp1c_fx2.vhd
0,0 → 1,227
-- $Id: rlink_sp1c_fx2.vhd 525 2013-07-06 12:19:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_sp1c_fx2 - syn
-- Description: rlink_core8 + serport_1clock + fx2 combo
--
-- Dependencies: rlinklib/rlink_core8
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
 
entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end entity rlink_sp1c_fx2;
 
 
architecture syn of rlink_sp1c_fx2 is
 
signal RLB_DI : slv8 := (others=>'0');
signal RLB_ENA : slbit := '0';
signal RLB_BUSY : slbit := '0';
signal RLB_DO : slv8 := (others=>'0');
signal RLB_VAL : slbit := '0';
signal RLB_HOLD : slbit := '0';
 
signal SER_RXDATA : slv8 := (others=>'0');
signal SER_RXVAL : slbit := '0';
signal SER_RXHOLD : slbit := '0';
signal SER_TXDATA : slv8 := (others=>'0');
signal SER_TXENA : slbit := '0';
signal SER_TXBUSY : slbit := '0';
 
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
 
begin
CORE : rlink_core8
generic map (
ATOWIDTH => ATOWIDTH,
ITOWIDTH => ITOWIDTH,
CPREF => CPREF,
ENAPIN_RLMON => ENAPIN_RLMON,
ENAPIN_RBMON => ENAPIN_RBMON)
port map (
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
RXFAWIDTH => IFAWIDTH,
TXFAWIDTH => OFAWIDTH)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
TXDATA => SER_TXDATA,
TXENA => SER_TXENA,
TXBUSY => SER_TXBUSY,
MONI => SER_MONI,
RXSD => RXSD,
TXSD => TXSD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
RLB_DO => RLB_DO,
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
P0_RXDATA => SER_RXDATA,
P0_RXVAL => SER_RXVAL,
P0_RXHOLD => SER_RXHOLD,
P0_TXDATA => SER_TXDATA,
P0_TXENA => SER_TXENA,
P0_TXBUSY => SER_TXBUSY,
P1_RXDATA => FX2_RXDATA,
P1_RXVAL => FX2_RXVAL,
P1_RXHOLD => FX2_RXHOLD,
P1_TXDATA => FX2_TXDATA,
P1_TXENA => FX2_TXENA,
P1_TXBUSY => FX2_TXBUSY
);
 
FX2CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => PETOWIDTH,
CCWIDTH => CCWIDTH,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
 
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
end syn;
/fx2rlink/fx2rlinklib.vhd
0,0 → 1,100
-- $Id: fx2rlinklib.vhd 525 2013-07-06 12:19:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: fx2rlinklib
-- Description: Definitions for rlink + fx2 interface combos
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-20 509 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
 
package fx2rlinklib is
 
--
-- core + fx2 interface combo
--
 
component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6; -- idle timeout counter width
CPREF : slv4 := c_rlink_cpref; -- comma prefix
IFAWIDTH : natural := 5; -- ser input fifo addr width (0=none)
OFAWIDTH : natural := 5; -- ser output fifo addr width (0=none)
PETOWIDTH : positive := 10; -- fx2 packet end time-out counter width
CCWIDTH : positive := 5; -- fx2 chunk counter width
ENAPIN_RLMON : integer := sbcntl_sbf_rlmon; -- SB_CNTL for rlmon (-1=none)
ENAPIN_RBMON : integer := sbcntl_sbf_rbmon; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
CE_MSEC : in slbit; -- 1 msec clock enable
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
RTS_N : out slbit; -- request to send (act.low, board view)
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3; -- rbus: status flags
RL_MONI : out rl_moni_type; -- rlink_core: monitor port
RLB_MONI : out rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : out serport_moni_type; -- ser: monitor port
FX2_MONI : out fx2ctl_moni_type; -- fx2: monitor port
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
 
component ioleds_sp1c_fx2 -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end component;
 
end package fx2rlinklib;
/fx2rlink/Makefile
0,0 → 1,25
# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-04-20 509 1.0 Initial version (cloned..)
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
endif
#
/fx2rlink/ioleds_sp1c_fx2.vhd
0,0 → 1,115
-- $Id: ioleds_sp1c_fx2.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ioleds_sp1c_fx2 - syn
-- Description: io activity leds for rlink+serport_1clk+fx2_ic combo
--
-- Dependencies:
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.rblib.all;
use work.rlinklib.all;
use work.serportlib.all;
 
entity ioleds_sp1c_fx2 is -- io activity leds for rlink_sp1c_fx2
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
RESET : in slbit; -- reset
ENAFX2 : in slbit; -- enable fx2 usage
RB_SRES : in rb_sres_type; -- rbus: response
RLB_MONI : in rlb_moni_type; -- rlink 8b: monitor port
SER_MONI : in serport_moni_type; -- ser: monitor port
IOLEDS : out slv4 -- 4 bit IO monitor (e.g. for DSP_DP)
);
end entity ioleds_sp1c_fx2;
 
 
architecture syn of ioleds_sp1c_fx2 is
 
signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
signal R_LEDCE : slbit := '0'; -- ce every 64 usec
 
signal TXENA_LED : slbit := '0';
signal RXVAL_LED : slbit := '0';
 
begin
RXVAL_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.rxval,
POUT => RXVAL_LED
);
 
TXENA_PSTR : led_pulse_stretch
port map (
CLK => CLK,
CE_INT => R_LEDCE,
RESET => '0',
DIN => RLB_MONI.txena,
POUT => TXENA_LED
);
 
proc_leddiv: process (CLK)
begin
 
if rising_edge(CLK) then
R_LEDCE <= '0';
if CE_USEC = '1' then
R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
if unsigned(R_LEDDIV) = 0 then
R_LEDCE <= '1';
end if;
end if;
end if;
 
end process proc_leddiv;
 
proc_ledmux : process (ENAFX2, SER_MONI, RLB_MONI, RB_SRES,
TXENA_LED, RXVAL_LED)
begin
 
if ENAFX2 = '0' then
IOLEDS(3) <= not SER_MONI.txok;
IOLEDS(2) <= SER_MONI.txact;
IOLEDS(1) <= not SER_MONI.rxok;
IOLEDS(0) <= SER_MONI.rxact;
else
IOLEDS(3) <= RB_SRES.busy;
IOLEDS(2) <= RLB_MONI.txbusy;
IOLEDS(1) <= TXENA_LED;
IOLEDS(0) <= RXVAL_LED;
end if;
end process proc_ledmux;
 
end syn;
/fx2rlink/rlink_sp1c_fx2.vbom
0,0 → 1,13
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd
# components
../../vlib/rlink/rlink_core8.vbom
../../vlib/serport/serport_1clock.vbom
../../vlib/rlink/rlink_rlbmux.vbom
../fx2lib/fx2_2fifoctl_ic.vbom
# design
rlink_sp1c_fx2.vhd
/fx2rlink/ioleds_sp1c_fx2.vbom
0,0 → 1,10
# libs
../../vlib/slvtypes.vhd
../../vlib/genlib/genlib.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
# components
../../vlib/genlib/led_pulse_stretch.vbom
# design
ioleds_sp1c_fx2.vhd
/fx2rlink/fx2rlinklib.vbom
0,0 → 1,7
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rlink/rlinklib.vhd
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd
fx2rlinklib.vhd
fx2rlink Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: nexys2/nexys2_time_fx2_ic.ucf =================================================================== --- nexys2/nexys2_time_fx2_ic.ucf (nonexistent) +++ nexys2/nexys2_time_fx2_ic.ucf (revision 24) @@ -0,0 +1,27 @@ +## $Id: nexys2_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-05 537 1.1 add VALID for hold time check +## 2012-01-01 448 1.0 Initial version +## +## timing rules for a 30 MHz internal clock design: +## Period: 30 MHz +## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns +## clk->out < 33.3-18.7 = 14.6 ns +## --> use 10 ns +## + +## The nexys2 board has unfortunately the FX2 IFCLK *not* connected to a +## clock capable pin -> not ok when FX2 uses internal clock. So allow par +## to route from a 'normal' pin to a clock net. Not nice, compromizes the +## timing, but unavoidable on nexys2 (Note: nexys3 and atlys are ok). +## In practice IFCLK to pad times are quite similar on nexys2 and nexys3... + +NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE; + +## +NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK"; +TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %; +OFFSET = IN 2.5 ns VALID 33 ns BEFORE "I_FX2_IFCLK"; +OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK"; Index: nexys2/nexys2lib.vhd =================================================================== --- nexys2/nexys2lib.vhd (nonexistent) +++ nexys2/nexys2lib.vhd (revision 24) @@ -0,0 +1,162 @@ +-- $Id: nexys2lib.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2010-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nexys2lib +-- Description: Nexys 2 components +-- +-- Dependencies: - +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-01 467 1.4 add nexys2_cuff_aif, nexys2_fusp_cuff_aif +-- 2011-12-23 444 1.3 remove clksys output hack +-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram driver/dummy +-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock) +-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50 +-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy +-- 2010-05-23 294 1.0.2 add n2_cram_dummy; +-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl +-- 2010-05-21 292 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nexys2lib is + +component nexys2_aif is -- NEXYS 2, abstract iface, base + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit -- flash ce.. (act.low) + ); +end component; + +component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end component; + +component nexys2_cuff_aif is -- NEXYS 2, abstract iface, base+cuff + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +component nexys2_fusp_cuff_aif is -- NEXYS 2, abstract iface, +fusp+cuff + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +end package nexys2lib; Index: nexys2/tb/tb_nexys2_fusp_cuff.vhd =================================================================== --- nexys2/tb/tb_nexys2_fusp_cuff.vhd (nonexistent) +++ nexys2/tb/tb_nexys2_fusp_cuff.vhd (revision 24) @@ -0,0 +1,329 @@ +-- $Id: tb_nexys2_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys2_fusp_cuff - sim +-- Description: Test bench for nexys2 (base+fusp+cuff) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- xlib/dcm_sfs +-- rlink/tb/tbcore_rlink_dcm +-- tb_nexys2_core +-- serport/serport_uart_rxtx +-- fx2lib/tb/fx2_2fifo_core +-- nexys2_fusp_cuff_aif [UUT] +-- +-- To test: generic, any nexys2_fusp_cuff_aif target +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-03 469 1.1 add fx2 model and data path +-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.xlib.all; +use work.nexys2lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys2_fusp_cuff is +end tb_nexys2_fusp_cuff; + +architecture sim of tb_nexys2_fusp_cuff is + + signal CLKOSC : slbit := '0'; + signal CLKCOM : slbit := '0'; + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + + signal TBC_RXDATA : slv8 := (others=>'0'); + signal TBC_RXVAL : slbit := '0'; + signal TBC_RXHOLD : slbit := '0'; + signal TBC_TXDATA : slv8 := (others=>'0'); + signal TBC_TXENA : slbit := '0'; + + signal UART_RXDATA : slv8 := (others=>'0'); + signal UART_RXVAL : slbit := '0'; + signal UART_RXERR : slbit := '0'; + signal UART_RXACT : slbit := '0'; + signal UART_TXDATA : slv8 := (others=>'0'); + signal UART_TXENA : slbit := '0'; + signal UART_TXBUSY : slbit := '0'; + + signal FX2_RXDATA : slv8 := (others=>'0'); + signal FX2_RXENA : slbit := '0'; + signal FX2_RXBUSY : slbit := '0'; + signal FX2_TXDATA : slv8 := (others=>'0'); + signal FX2_TXVAL : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + signal O_LED : slv8 := (others=>'0'); + signal O_ANO_N : slv4 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + signal O_MEM_CE_N : slbit := '1'; + signal O_MEM_BE_N : slv2 := (others=>'1'); + signal O_MEM_WE_N : slbit := '1'; + signal O_MEM_OE_N : slbit := '1'; + signal O_MEM_ADV_N : slbit := '1'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'Z'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + signal O_FLA_CE_N : slbit := '0'; + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal I_FX2_IFCLK : slbit := '0'; + signal O_FX2_FIFO : slv2 := (others=>'0'); + signal I_FX2_FLAG : slv4 := (others=>'0'); + signal O_FX2_SLRD_N : slbit := '1'; + signal O_FX2_SLWR_N : slbit := '1'; + signal O_FX2_SLOE_N : slbit := '1'; + signal O_FX2_PKTEND_N : slbit := '1'; + signal IO_FX2_DATA : slv8 := (others=>'Z'); + + signal UART_RESET : slbit := '0'; + signal UART_RXD : slbit := '1'; + signal UART_TXD : slbit := '1'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport + signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2 + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + SB_CLKSTOP <= CLK_STOP; + + DCM_COM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TBC_RXDATA, + RX_VAL => TBC_RXVAL, + RX_HOLD => TBC_RXHOLD, + TX_DATA => TBC_TXDATA, + TX_ENA => TBC_TXENA + ); + + N2CORE : entity work.tb_nexys2_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + UUT : nexys2_fusp_cuff_aif + port map ( + I_CLK50 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA, + O_FLA_CE_N => O_FLA_CE_N, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + RXSD => UART_RXD, + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => UART_RXERR, + RXACT => UART_RXACT, + TXSD => UART_TXD, + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY + ); + + FX2 : entity work.fx2_2fifo_core + port map ( + CLK => CLKCOM, + RESET => '0', + RXDATA => FX2_RXDATA, + RXENA => FX2_RXENA, + RXBUSY => FX2_RXBUSY, + TXDATA => FX2_TXDATA, + TXVAL => FX2_TXVAL, + IFCLK => I_FX2_IFCLK, + FIFO => O_FX2_FIFO, + FLAG => I_FX2_FLAG, + SLRD_N => O_FX2_SLRD_N, + SLWR_N => O_FX2_SLWR_N, + SLOE_N => O_FX2_SLOE_N, + PKTEND_N => O_FX2_PKTEND_N, + DATA => IO_FX2_DATA + ); + + proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL, + UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL, + FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL + ) + begin + + if R_PORTSEL_FX2 = '0' then -- use serport + UART_TXDATA <= TBC_RXDATA; + UART_TXENA <= TBC_RXVAL; + TBC_RXHOLD <= UART_TXBUSY or RTS_N; + TBC_TXDATA <= UART_RXDATA; + TBC_TXENA <= UART_RXVAL; + else -- otherwise use fx2 + FX2_RXDATA <= TBC_RXDATA; + FX2_RXENA <= TBC_RXVAL; + TBC_RXHOLD <= FX2_RXBUSY; + TBC_TXDATA <= FX2_TXDATA; + TBC_TXENA <= FX2_TXVAL; + end if; + + end process proc_fx2_mux; + + proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, + O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) + begin + + if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl + I_RXD <= UART_TXD; -- write port 0 inputs + UART_RXD <= O_TXD; -- get port 0 outputs + RTS_N <= '0'; + I_FUSP_RXD <= '1'; -- port 1 inputs to idle state + I_FUSP_CTS_N <= '0'; + else -- otherwise use pmod1 rs232 + I_FUSP_RXD <= UART_TXD; -- write port 1 inputs + I_FUSP_CTS_N <= CTS_N; + UART_RXD <= O_FUSP_TXD; -- get port 1 outputs + RTS_N <= O_FUSP_RTS_N; + I_RXD <= '1'; -- port 0 inputs to idle state + end if; + + end process proc_ser_mux; + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if UART_RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_SER <= to_x01(SB_DATA(0)); + R_PORTSEL_FX2 <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim; Index: nexys2/tb/tb_nexys2_fusp_cuff.vbom =================================================================== --- nexys2/tb/tb_nexys2_fusp_cuff.vbom (nonexistent) +++ nexys2/tb/tb_nexys2_fusp_cuff.vbom (revision 24) @@ -0,0 +1,26 @@ +# Not meant for direct top level usage. Used with +# tb_nexys2_fusp_cuff_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/xlib/xlib.vhd +../nexys2lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/xlib/dcm_sfs_gsim.vbom +tb_nexys2_core.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom +${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom} +# design +tb_nexys2_fusp_cuff.vhd +@top:tb_nexys2_fusp_cuff Index: nexys2/tb/tb_nexys2_core.vhd =================================================================== --- nexys2/tb/tb_nexys2_core.vhd (nonexistent) +++ nexys2/tb/tb_nexys2_core.vhd (revision 24) @@ -0,0 +1,99 @@ +-- $Id: tb_nexys2_core.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys2_core - sim +-- Description: Test bench for nexys2 - core device handling +-- +-- Dependencies: vlib/parts/micron/mt45w8mw16b +-- +-- To test: generic, any nexys2 target +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core +-- 2011-11-21 432 1.1 update O_FLA_CE_N usage +-- 2011-11-19 427 1.0.1 now numeric_std clean +-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.simbus.all; + +entity tb_nexys2_core is + port ( + I_SWI : out slv8; -- n2 switches + I_BTN : out slv4; -- n2 buttons + O_MEM_CE_N : in slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : in slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : in slbit; -- cram: write enable (act.low) + O_MEM_OE_N : in slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : in slbit; -- cram: address valid (act.low) + O_MEM_CLK : in slbit; -- cram: clock + O_MEM_CRE : in slbit; -- cram: command register enable + I_MEM_WAIT : out slbit; -- cram: mem wait + O_MEM_ADDR : in slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end tb_nexys2_core; + +architecture sim of tb_nexys2_core is + + signal R_SWI : slv8 := (others=>'0'); + signal R_BTN : slv4 := (others=>'0'); + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + MEM : entity work.mt45w8mw16b + port map ( + CLK => O_MEM_CLK, + CE_N => O_MEM_CE_N, + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADV_N => O_MEM_ADV_N, + CRE => O_MEM_CRE, + MWAIT => I_MEM_WAIT, + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA + ); + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + +end sim; Index: nexys2/tb/tb_nexys2_core.vbom =================================================================== --- nexys2/tb/tb_nexys2_core.vbom (nonexistent) +++ nexys2/tb/tb_nexys2_core.vbom (revision 24) @@ -0,0 +1,10 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/simlib/simbus.vhd +# components +../../../vlib/serport/serport_uart_rx.vbom +../../../vlib/serport/serport_uart_tx.vbom +../../micron/mt45w8mw16b.vbom +# design +tb_nexys2_core.vhd Index: nexys2/tb/tb_nexys2_fusp.vhd =================================================================== --- nexys2/tb/tb_nexys2_fusp.vhd (nonexistent) +++ nexys2/tb/tb_nexys2_fusp.vhd (revision 24) @@ -0,0 +1,263 @@ +-- $Id: tb_nexys2_fusp.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys2_fusp - sim +-- Description: Test bench for nexys2 (base+fusp) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- xlib/dcm_sfs +-- rlink/tb/tbcore_rlink +-- tb_nexys2_core +-- serport/serport_uart_rxtx +-- nexys2_fusp_aif [UUT] +-- +-- To test: generic, any nexys2_fusp_aif target +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface +-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core +-- 2011-11-21 432 3.1 update O_FLA_CE_N usage +-- 2011-11-19 427 3.0.1 now numeric_std clean +-- 2010-12-29 351 3.0 use rlink/tb now +-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm +-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 +-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.xlib.all; +use work.nexys2lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys2_fusp is +end tb_nexys2_fusp; + +architecture sim of tb_nexys2_fusp is + + signal CLKOSC : slbit := '0'; + signal CLKCOM : slbit := '0'; + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal RX_HOLD : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + signal O_LED : slv8 := (others=>'0'); + signal O_ANO_N : slv4 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + signal O_MEM_CE_N : slbit := '1'; + signal O_MEM_BE_N : slv2 := (others=>'1'); + signal O_MEM_WE_N : slbit := '1'; + signal O_MEM_OE_N : slbit := '1'; + signal O_MEM_ADV_N : slbit := '1'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'Z'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + signal O_FLA_CE_N : slbit := '0'; + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal UART_RESET : slbit := '0'; + signal UART_RXD : slbit := '1'; + signal UART_TXD : slbit := '1'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal R_PORTSEL : slbit := '0'; + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + DCM_COM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => RX_HOLD, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb + + N2CORE : entity work.tb_nexys2_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + UUT : nexys2_fusp_aif + port map ( + I_CLK50 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA, + O_FLA_CE_N => O_FLA_CE_N, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + RXSD => UART_RXD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => UART_TXD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, + O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) + begin + + if R_PORTSEL = '0' then -- use main board rs232, no flow cntl + I_RXD <= UART_TXD; -- write port 0 inputs + UART_RXD <= O_TXD; -- get port 0 outputs + RTS_N <= '0'; + I_FUSP_RXD <= '1'; -- port 1 inputs to idle state + I_FUSP_CTS_N <= '0'; + else -- otherwise use pmod1 rs232 + I_FUSP_RXD <= UART_TXD; -- write port 1 inputs + I_FUSP_CTS_N <= CTS_N; + UART_RXD <= O_FUSP_TXD; -- get port 1 outputs + RTS_N <= O_FUSP_RTS_N; + I_RXD <= '1'; -- port 0 inputs to idle state + end if; + + end process proc_port_mux; + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL <= to_x01(SB_DATA(0)); + end if; + end if; + end process proc_simbus; + +end sim; Index: nexys2/tb/tb_nexys2_fusp.vbom =================================================================== --- nexys2/tb/tb_nexys2_fusp.vbom (nonexistent) +++ nexys2/tb/tb_nexys2_fusp.vbom (revision 24) @@ -0,0 +1,25 @@ +# Not meant for direct top level usage. Used with +# tb_nexys2_fusp_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/xlib/xlib.vhd +../nexys2lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/xlib/dcm_sfs_gsim.vbom +tb_nexys2_core.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +${nexys2_fusp_aif := nexys2_fusp_dummy.vbom} +# design +tb_nexys2_fusp.vhd +@top:tb_nexys2_fusp Index: nexys2/tb/Makefile =================================================================== --- nexys2/tb/Makefile (nonexistent) +++ nexys2/tb/Makefile (revision 24) @@ -0,0 +1,40 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-01-01 467 1.2.1 add tb_nexys2_fusp_cuff_dummy +# 2011-11-26 433 1.2 remove tb_n2_cram_memctl_as (moved to nxcramlib) +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now +# 2010-05-28 295 1.0.1 add tb_.._dummy's +# 2007-09-23 84 1.0 Initial version +# +EXE_all = tb_nexys2_dummy +EXE_all += tb_nexys2_fusp_dummy +EXE_all += tb_nexys2_fusp_cuff_dummy +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: nexys2/tb/.cvsignore =================================================================== --- nexys2/tb/.cvsignore (nonexistent) +++ nexys2/tb/.cvsignore (revision 24) @@ -0,0 +1,3 @@ +tb_nexys2_dummy +tb_nexys2_fusp_dummy +tb_nexys2_fusp_cuff_dummy Index: nexys2/tb/nexys2_fusp_dummy.vhd =================================================================== --- nexys2/tb/nexys2_fusp_dummy.vhd (nonexistent) +++ nexys2/tb/nexys2_fusp_dummy.vhd (revision 24) @@ -0,0 +1,92 @@ +-- $Id: nexys2_fusp_dummy.vhd 467 2013-01-02 19:49:05Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: nexys2_fusp_dummy - syn +-- Description: nexys2 minimal target (base; serport loopback) +-- +-- Dependencies: - +-- To test: tb_nexys2 +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.3 remove clksys output hack +-- 2011-11-26 433 1.2 use nxcramlib +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_dummy +-- 2010-11-13 338 1.0.2 add O_CLKSYS (for DCM derived system clock) +-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 +-- 2010-05-28 295 1.0 Initial version (derived from s3board_fusp_dummy) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +entity nexys2_fusp_dummy is -- NEXYS 2 dummy (base+fusp; loopback) + -- implements nexys2_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end nexys2_fusp_dummy; + +architecture syn of nexys2_fusp_dummy is + +begin + + O_TXD <= I_RXD; -- loop back + O_FUSP_TXD <= I_FUSP_RXD; + O_FUSP_RTS_N <= I_FUSP_CTS_N; + + CRAM : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: nexys2/tb/nexys2_fusp_dummy.vbom =================================================================== --- nexys2/tb/nexys2_fusp_dummy.vbom (nonexistent) +++ nexys2/tb/nexys2_fusp_dummy.vbom (revision 24) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../../nxcramlib/nxcramlib.vhd +# components +../../nxcramlib/nx_cram_dummy.vbom +# design +nexys2_fusp_dummy.vhd Index: nexys2/tb =================================================================== --- nexys2/tb (nonexistent) +++ nexys2/tb (revision 24)
nexys2/tb Property changes : Added: svn:ignore ## -0,0 +1,35 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nexys2_dummy +tb_nexys2_fusp_dummy +tb_nexys2_fusp_cuff_dummy Index: nexys2/Makefile =================================================================== --- nexys2/Makefile (nonexistent) +++ nexys2/Makefile (revision 24) @@ -0,0 +1,26 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-05-23 293 1.0 Initial version (cloned..) +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: nexys2/nexys2_pins_fx2.ucf =================================================================== --- nexys2/nexys2_pins_fx2.ucf (nonexistent) +++ nexys2/nexys2_pins_fx2.ucf (revision 24) @@ -0,0 +1,36 @@ +## $Id: nexys2_pins_fx2.ucf 397 2011-07-24 09:43:07Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-07-05 389 1.0 Initial version +## +## Cypress EZ-USB FX2 Interface ---------------------------------------------- +## +## +NET "I_FX2_IFCLK" LOC = "t15" | IOSTANDARD=LVCMOS33; +## +NET "IO_FX2_DATA<0>" LOC = "r14" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<1>" LOC = "r13" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<2>" LOC = "p13" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<3>" LOC = "t12" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<4>" LOC = "n11" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<5>" LOC = "r11" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<6>" LOC = "p10" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<7>" LOC = "r10" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## +NET "O_FX2_SLWR_N" LOC = "v9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLRD_N" LOC = "n9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLOE_N" LOC = "v15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_PKTEND_N" LOC = "v12" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_FIFO<0>" LOC = "t14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_FIFO<1>" LOC = "v13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +## assume that PA.7 is used a FLAGD (and not as SLCS#) +NET "I_FX2_FLAG<0>" LOC = "v14" | IOSTANDARD=LVCMOS33; ## flag a (program) +NET "I_FX2_FLAG<1>" LOC = "u14" | IOSTANDARD=LVCMOS33; ## flag b (full) +NET "I_FX2_FLAG<2>" LOC = "v16" | IOSTANDARD=LVCMOS33; ## flag c (empty) +NET "I_FX2_FLAG<3>" LOC = "t16" | IOSTANDARD=LVCMOS33; ## flag d (slcs) +## Index: nexys2/nexys2_pins.ucf =================================================================== --- nexys2/nexys2_pins.ucf (nonexistent) +++ nexys2/nexys2_pins.ucf (revision 24) @@ -0,0 +1,127 @@ +## $Id: nexys2_pins.ucf 444 2011-12-25 10:04:58Z mueller $ +## +## Pin locks for Nexys 2 core functionality (for 1200k FPGA) +## - internal RS232 +## - human I/O (switches, buttons, leds, display) +## - cram +## +## Revision History: +## Date Rev Version Comment +## 2011-11-23 444 1.1 remove clksys output hack +## 2010-11-13 338 1.0.3 add O_CLKSYS (for DCM derived system clock) +## 2010-11-06 336 1.0.2 Rename CLK -> I_CLK50 +## 2010-05-23 294 1.0.1 use ADV_N rather ADV +## 2010-05-16 291 1.0 Initial version +## +## Note: default is DRIVE=12 | SLEW=SLOW +## +## clocks -------------------------------------------------------------------- +NET "I_CLK50" LOC = "b8" | IOSTANDARD=LVCMOS33; +## +## RS232 interface ----------------------------------------------------------- +NET "I_RXD" LOC = "u6" | IOSTANDARD=LVCMOS33; +NET "O_TXD" LOC = "p9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## switches and buttons ------------------------------------------------------ +NET "I_SWI<0>" LOC = "g18" | IOSTANDARD=LVCMOS33; +NET "I_SWI<1>" LOC = "h18" | IOSTANDARD=LVCMOS33; +NET "I_SWI<2>" LOC = "k18" | IOSTANDARD=LVCMOS33; +NET "I_SWI<3>" LOC = "k17" | IOSTANDARD=LVCMOS33; +NET "I_SWI<4>" LOC = "l14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<5>" LOC = "l13" | IOSTANDARD=LVCMOS33; +NET "I_SWI<6>" LOC = "n17" | IOSTANDARD=LVCMOS33; +NET "I_SWI<7>" LOC = "r17" | IOSTANDARD=LVCMOS33; +## +NET "I_BTN<0>" LOC = "b18" | IOSTANDARD=LVCMOS33; +NET "I_BTN<1>" LOC = "d18" | IOSTANDARD=LVCMOS33; +NET "I_BTN<2>" LOC = "e18" | IOSTANDARD=LVCMOS33; +NET "I_BTN<3>" LOC = "h13" | IOSTANDARD=LVCMOS33; +## +## LEDs ---------------------------------------------------------------------- +NET "O_LED<0>" LOC = "j14" | IOSTANDARD=LVCMOS33; +NET "O_LED<1>" LOC = "j15" | IOSTANDARD=LVCMOS33; +NET "O_LED<2>" LOC = "k15" | IOSTANDARD=LVCMOS33; +NET "O_LED<3>" LOC = "k14" | IOSTANDARD=LVCMOS33; +NET "O_LED<4>" LOC = "e16" | IOSTANDARD=LVCMOS33; +NET "O_LED<5>" LOC = "p16" | IOSTANDARD=LVCMOS33; +NET "O_LED<6>" LOC = "e4" | IOSTANDARD=LVCMOS33; +NET "O_LED<7>" LOC = "p4" | IOSTANDARD=LVCMOS33; +NET "O_LED<*>" DRIVE=12 | SLEW=SLOW; +## +## 7 segment display --------------------------------------------------------- +NET "O_ANO_N<0>" LOC = "f17" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<1>" LOC = "h17" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<2>" LOC = "c18" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<3>" LOC = "f15" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW; +## +NET "O_SEG_N<0>" LOC = "l18" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<1>" LOC = "f18" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<2>" LOC = "d17" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<3>" LOC = "d16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<4>" LOC = "g14" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<5>" LOC = "j17" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<6>" LOC = "h14" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<7>" LOC = "c17" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW; +## +## CRAM ---------------------------------------------------------------------- +NET "O_MEM_CE_N" LOC = "r6" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_WE_N" LOC = "n7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_OE_N" LOC = "t2" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_BE_N<0>" LOC = "k5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<1>" LOC = "k4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_ADV_N" LOC = "j4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CLK" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CRE" LOC = "p7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "I_MEM_WAIT" LOC = "f5" | IOSTANDARD=LVCMOS33 | PULLDOWN; +## +NET "O_MEM_ADDR<0>" LOC = "j1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<1>" LOC = "j2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<2>" LOC = "h4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<3>" LOC = "h1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<4>" LOC = "h2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<5>" LOC = "j5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<6>" LOC = "h3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<7>" LOC = "h6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<8>" LOC = "f1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<9>" LOC = "g3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<10>" LOC = "g6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<11>" LOC = "g5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<12>" LOC = "g4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<13>" LOC = "f2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<14>" LOC = "e1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<15>" LOC = "m5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<16>" LOC = "e2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<17>" LOC = "c2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<18>" LOC = "c1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<19>" LOC = "d2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<20>" LOC = "k3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<21>" LOC = "d1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<22>" LOC = "k6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST; +## +NET "IO_MEM_DATA<0>" LOC = "l1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<1>" LOC = "l4" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<2>" LOC = "l6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<3>" LOC = "m4" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<4>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<5>" LOC = "p1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<6>" LOC = "p2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<7>" LOC = "r2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<8>" LOC = "l3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<9>" LOC = "l5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<10>" LOC = "m3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<11>" LOC = "m6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<12>" LOC = "l2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<13>" LOC = "n4" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<14>" LOC = "r3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<15>" LOC = "t1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## +## Flash --------------------------------------------------------------------- +NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW; +## Index: nexys2/nexys2_pins_pmb0_rs232.ucf =================================================================== --- nexys2/nexys2_pins_pmb0_rs232.ucf (nonexistent) +++ nexys2/nexys2_pins_pmb0_rs232.ucf (revision 24) @@ -0,0 +1,12 @@ +## $Id: nexys2_pins_pmb0_rs232.ucf 297 2010-05-30 20:10:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-05-28 295 1.0 Initial version +## +## Pmod connector B top / usage RS232 for FTDI USB serport ------------------- +## +NET "O_FUSP_RTS_N" LOC = "m13" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "r18" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "r15" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "t17" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; Index: nexys2 =================================================================== --- nexys2 (nonexistent) +++ nexys2 (revision 24)
nexys2 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: nexys3/tb/tb_nexys3_fusp_cuff.vbom =================================================================== --- nexys3/tb/tb_nexys3_fusp_cuff.vbom (nonexistent) +++ nexys3/tb/tb_nexys3_fusp_cuff.vbom (revision 24) @@ -0,0 +1,26 @@ +# Not meant for direct top level usage. Used with +# tb_nexys3_fusp_cuff_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/xlib/xlib.vhd +../nexys3lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +tb_nexys3_core.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom +${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom} +# design +tb_nexys3_fusp_cuff.vhd +@top:tb_nexys3_fusp_cuff Index: nexys3/tb/tb_nexys3_fusp.vhd =================================================================== --- nexys3/tb/tb_nexys3_fusp.vhd (nonexistent) +++ nexys3/tb/tb_nexys3_fusp.vhd (revision 24) @@ -0,0 +1,264 @@ +-- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys3_fusp - sim +-- Description: Test bench for nexys3 (base+fusp) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- xlib/s6_cmt_sfs +-- rlink/tb/tbcore_rlink +-- tb_nexys3_core +-- serport/serport_uart_rxtx +-- nexys3_fusp_aif [UUT] +-- +-- To test: generic, any nexys3_fusp_aif target +-- +-- Target Devices: generic +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect +-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface +-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.xlib.all; +use work.nexys3lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys3_fusp is +end tb_nexys3_fusp; + +architecture sim of tb_nexys3_fusp is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal RX_HOLD : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + signal O_LED : slv8 := (others=>'0'); + signal O_ANO_N : slv4 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + signal O_MEM_CE_N : slbit := '1'; + signal O_MEM_BE_N : slv2 := (others=>'1'); + signal O_MEM_WE_N : slbit := '1'; + signal O_MEM_OE_N : slbit := '1'; + signal O_MEM_ADV_N : slbit := '1'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'Z'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + signal O_PPCM_CE_N : slbit := '0'; + signal O_PPCM_RST_N : slbit := '0'; + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal UART_RESET : slbit := '0'; + signal UART_RXD : slbit := '1'; + signal UART_TXD : slbit := '1'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal R_PORTSEL : slbit := '0'; + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + CLKGEN_COM : s6_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => RX_HOLD, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb + + N3CORE : entity work.tb_nexys3_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + UUT : nexys3_fusp_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA, + O_PPCM_CE_N => O_PPCM_CE_N, + O_PPCM_RST_N => O_PPCM_RST_N, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + RXSD => UART_RXD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => UART_TXD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, + O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) + begin + + if R_PORTSEL = '0' then -- use main board rs232, no flow cntl + I_RXD <= UART_TXD; -- write port 0 inputs + UART_RXD <= O_TXD; -- get port 0 outputs + RTS_N <= '0'; + I_FUSP_RXD <= '1'; -- port 1 inputs to idle state + I_FUSP_CTS_N <= '0'; + else -- otherwise use pmod1 rs232 + I_FUSP_RXD <= UART_TXD; -- write port 1 inputs + I_FUSP_CTS_N <= CTS_N; + UART_RXD <= O_FUSP_TXD; -- get port 1 outputs + RTS_N <= O_FUSP_RTS_N; + I_RXD <= '1'; -- port 0 inputs to idle state + end if; + + end process proc_port_mux; + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL <= to_x01(SB_DATA(0)); + end if; + end if; + end process proc_simbus; + +end sim; Index: nexys3/tb/tb_nexys3_fusp.vbom =================================================================== --- nexys3/tb/tb_nexys3_fusp.vbom (nonexistent) +++ nexys3/tb/tb_nexys3_fusp.vbom (revision 24) @@ -0,0 +1,25 @@ +# Not meant for direct top level usage. Used with +# tb_nexys3_fusp_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/xlib/xlib.vhd +../nexys3lib.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +${sys_conf := sys_conf_sim.vhd} +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +tb_nexys3_core.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +${nexys3_fusp_aif := nexys3_fusp_dummy.vbom} +# design +tb_nexys3_fusp.vhd +@top:tb_nexys3_fusp Index: nexys3/tb/tb_nexys3_fusp_cuff.vhd =================================================================== --- nexys3/tb/tb_nexys3_fusp_cuff.vhd (nonexistent) +++ nexys3/tb/tb_nexys3_fusp_cuff.vhd (revision 24) @@ -0,0 +1,336 @@ +-- $Id: tb_nexys3_fusp_cuff.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys3_fusp_cuff - sim +-- Description: Test bench for nexys3 (base+fusp+cuff) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- xlib/s6_cmt_sfs +-- rlink/tb/tbcore_rlink +-- tb_nexys3_core +-- serport/serport_uart_rxtx +-- fx2lib/tb/fx2_2fifo_core +-- nexys3_fusp_cuff_aif [UUT] +-- +-- To test: generic, any nexys3_fusp_cuff_aif target +-- +-- Target Devices: generic +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and +-- tb_nexys2_fusp_cuff) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.xlib.all; +use work.nexys3lib.all; +use work.simlib.all; +use work.simbus.all; +use work.sys_conf.all; + +entity tb_nexys3_fusp_cuff is +end tb_nexys3_fusp_cuff; + +architecture sim of tb_nexys3_fusp_cuff is + + signal CLKOSC : slbit := '0'; -- board clock (100 Mhz) + signal CLKCOM : slbit := '0'; -- communication clock + + signal CLK_STOP : slbit := '0'; + signal CLKCOM_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + + signal TBC_RXDATA : slv8 := (others=>'0'); + signal TBC_RXVAL : slbit := '0'; + signal TBC_RXHOLD : slbit := '0'; + signal TBC_TXDATA : slv8 := (others=>'0'); + signal TBC_TXENA : slbit := '0'; + + signal UART_RXDATA : slv8 := (others=>'0'); + signal UART_RXVAL : slbit := '0'; + signal UART_RXERR : slbit := '0'; + signal UART_RXACT : slbit := '0'; + signal UART_TXDATA : slv8 := (others=>'0'); + signal UART_TXENA : slbit := '0'; + signal UART_TXBUSY : slbit := '0'; + + signal FX2_RXDATA : slv8 := (others=>'0'); + signal FX2_RXENA : slbit := '0'; + signal FX2_RXBUSY : slbit := '0'; + signal FX2_TXDATA : slv8 := (others=>'0'); + signal FX2_TXVAL : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + signal O_LED : slv8 := (others=>'0'); + signal O_ANO_N : slv4 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + signal O_MEM_CE_N : slbit := '1'; + signal O_MEM_BE_N : slv2 := (others=>'1'); + signal O_MEM_WE_N : slbit := '1'; + signal O_MEM_OE_N : slbit := '1'; + signal O_MEM_ADV_N : slbit := '1'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'Z'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + signal O_PPCM_CE_N : slbit := '0'; + signal O_PPCM_RST_N : slbit := '0'; + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal I_FX2_IFCLK : slbit := '0'; + signal O_FX2_FIFO : slv2 := (others=>'0'); + signal I_FX2_FLAG : slv4 := (others=>'0'); + signal O_FX2_SLRD_N : slbit := '1'; + signal O_FX2_SLWR_N : slbit := '1'; + signal O_FX2_SLOE_N : slbit := '1'; + signal O_FX2_PKTEND_N : slbit := '1'; + signal IO_FX2_DATA : slv8 := (others=>'Z'); + + signal UART_RESET : slbit := '0'; + signal UART_RXD : slbit := '1'; + signal UART_TXD : slbit := '1'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport + signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2 + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLKOSC, + CLK_STOP => CLK_STOP + ); + + SB_CLKSTOP <= CLK_STOP; + + CLKGEN_COM : s6_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => CLKOSC, + CLKFX => CLKCOM, + LOCKED => open + ); + + CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLKCOM, + CLK_STOP => CLK_STOP, + RX_DATA => TBC_RXDATA, + RX_VAL => TBC_RXVAL, + RX_HOLD => TBC_RXHOLD, + TX_DATA => TBC_TXDATA, + TX_ENA => TBC_TXENA + ); + + N3CORE : entity work.tb_nexys3_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + UUT : nexys3_fusp_cuff_aif + port map ( + I_CLK100 => CLKOSC, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA, + O_PPCM_CE_N => O_PPCM_CE_N, + O_PPCM_RST_N => O_PPCM_RST_N, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLKCOM, + RESET => UART_RESET, + CLKDIV => CLKDIV, + RXSD => UART_RXD, + RXDATA => UART_RXDATA, + RXVAL => UART_RXVAL, + RXERR => UART_RXERR, + RXACT => UART_RXACT, + TXSD => UART_TXD, + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY + ); + + FX2 : entity work.fx2_2fifo_core + port map ( + CLK => CLKCOM, + RESET => '0', + RXDATA => FX2_RXDATA, + RXENA => FX2_RXENA, + RXBUSY => FX2_RXBUSY, + TXDATA => FX2_TXDATA, + TXVAL => FX2_TXVAL, + IFCLK => I_FX2_IFCLK, + FIFO => O_FX2_FIFO, + FLAG => I_FX2_FLAG, + SLRD_N => O_FX2_SLRD_N, + SLWR_N => O_FX2_SLWR_N, + SLOE_N => O_FX2_SLOE_N, + PKTEND_N => O_FX2_PKTEND_N, + DATA => IO_FX2_DATA + ); + + proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL, + UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL, + FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL + ) + begin + + if R_PORTSEL_FX2 = '0' then -- use serport + UART_TXDATA <= TBC_RXDATA; + UART_TXENA <= TBC_RXVAL; + TBC_RXHOLD <= UART_TXBUSY or RTS_N; + TBC_TXDATA <= UART_RXDATA; + TBC_TXENA <= UART_RXVAL; + else -- otherwise use fx2 + FX2_RXDATA <= TBC_RXDATA; + FX2_RXENA <= TBC_RXVAL; + TBC_RXHOLD <= FX2_RXBUSY; + TBC_TXDATA <= FX2_TXDATA; + TBC_TXENA <= FX2_TXVAL; + end if; + + end process proc_fx2_mux; + + proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N, + O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) + begin + + if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl + I_RXD <= UART_TXD; -- write port 0 inputs + UART_RXD <= O_TXD; -- get port 0 outputs + RTS_N <= '0'; + I_FUSP_RXD <= '1'; -- port 1 inputs to idle state + I_FUSP_CTS_N <= '0'; + else -- otherwise use pmod1 rs232 + I_FUSP_RXD <= UART_TXD; -- write port 1 inputs + I_FUSP_CTS_N <= CTS_N; + UART_RXD <= O_FUSP_TXD; -- get port 1 outputs + RTS_N <= O_FUSP_RTS_N; + I_RXD <= '1'; -- port 0 inputs to idle state + end if; + + end process proc_ser_mux; + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLKCOM); + + if UART_RXERR = '1' then + writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL_SER <= to_x01(SB_DATA(0)); + R_PORTSEL_FX2 <= to_x01(SB_DATA(1)); + end if; + end if; + end process proc_simbus; + +end sim; Index: nexys3/tb/.cvsignore =================================================================== --- nexys3/tb/.cvsignore (nonexistent) +++ nexys3/tb/.cvsignore (revision 24) @@ -0,0 +1,2 @@ +tb_nexys3_fusp_dummy +tb_nexys3_fusp_cuff_dummy Index: nexys3/tb/Makefile =================================================================== --- nexys3/tb/Makefile (nonexistent) +++ nexys3/tb/Makefile (revision 24) @@ -0,0 +1,34 @@ +# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-26 432 1.0 Initial version +# +EXE_all = tb_nexys3_fusp_dummy +EXE_all += tb_nexys3_fusp_cuff_dummy +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: nexys3/tb/tb_nexys3_core.vhd =================================================================== --- nexys3/tb/tb_nexys3_core.vhd (nonexistent) +++ nexys3/tb/tb_nexys3_core.vhd (revision 24) @@ -0,0 +1,96 @@ +-- $Id: tb_nexys3_core.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nexys3_core - sim +-- Description: Test bench for nexys3 - core device handling +-- +-- Dependencies: vlib/parts/micron/mt45w8mw16b +-- +-- To test: generic, any nexys3 target +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_core) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.simbus.all; + +entity tb_nexys3_core is + port ( + I_SWI : out slv8; -- n3 switches + I_BTN : out slv5; -- n3 buttons + O_MEM_CE_N : in slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : in slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : in slbit; -- cram: write enable (act.low) + O_MEM_OE_N : in slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : in slbit; -- cram: address valid (act.low) + O_MEM_CLK : in slbit; -- cram: clock + O_MEM_CRE : in slbit; -- cram: command register enable + I_MEM_WAIT : out slbit; -- cram: mem wait + O_MEM_ADDR : in slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end tb_nexys3_core; + +architecture sim of tb_nexys3_core is + + signal R_SWI : slv8 := (others=>'0'); + signal R_BTN : slv5 := (others=>'0'); + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + MEM : entity work.mt45w8mw16b + port map ( + CLK => O_MEM_CLK, + CE_N => O_MEM_CE_N, + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADV_N => O_MEM_ADV_N, + CRE => O_MEM_CRE, + MWAIT => I_MEM_WAIT, + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA + ); + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + +end sim; Index: nexys3/tb/tb_nexys3_core.vbom =================================================================== --- nexys3/tb/tb_nexys3_core.vbom (nonexistent) +++ nexys3/tb/tb_nexys3_core.vbom (revision 24) @@ -0,0 +1,10 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/simlib/simbus.vhd +# components +../../../vlib/serport/serport_uart_rx.vbom +../../../vlib/serport/serport_uart_tx.vbom +../../micron/mt45w8mw16b.vbom +# design +tb_nexys3_core.vhd Index: nexys3/tb =================================================================== --- nexys3/tb (nonexistent) +++ nexys3/tb (revision 24)
nexys3/tb Property changes : Added: svn:ignore ## -0,0 +1,34 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nexys3_fusp_dummy +tb_nexys3_fusp_cuff_dummy Index: nexys3/nexys3_pins_pmb0_rs232.ucf =================================================================== --- nexys3/nexys3_pins_pmb0_rs232.ucf (nonexistent) +++ nexys3/nexys3_pins_pmb0_rs232.ucf (revision 24) @@ -0,0 +1,13 @@ +## $Id: nexys3_pins_pmb0_rs232.ucf 534 2013-09-22 21:37:24Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-11-20 430 1.0 Initial version +## +## Pmod connector B top / usage RS232 for FTDI USB serport ------------------- +## +NET "O_FUSP_RTS_N" LOC = "k2" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "k1" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "l4" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "l3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +## Index: nexys3/nexys3_time_fx2_ic.ucf =================================================================== --- nexys3/nexys3_time_fx2_ic.ucf (nonexistent) +++ nexys3/nexys3_time_fx2_ic.ucf (revision 24) @@ -0,0 +1,18 @@ +## $Id: nexys3_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-05 537 1.1 add VALID for hold time check +## 2012-01-01 448 1.0 Initial version +## +## timing rules for a 30 MHz internal clock design: +## Period: 30 MHz +## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns +## clk->out < 33.3-18.7 = 14.6 ns +## --> use 10 ns +## + +NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK"; +TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %; +OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK"; +OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK"; Index: nexys3/nexys3lib.vhd =================================================================== --- nexys3/nexys3lib.vhd (nonexistent) +++ nexys3/nexys3lib.vhd (revision 24) @@ -0,0 +1,158 @@ +-- $Id: nexys3lib.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nexys3lib +-- Description: Nexys 3 components +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-21 509 1.1 add nexys3_cuff_aif, nexys3_fusp_cuff_aif +-- 2011-11-25 432 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nexys3lib is + +component nexys3_aif is -- NEXYS 3, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit -- ppcm: ... + ); +end component; + +component nexys3_fusp_aif is -- NEXYS 3, abstract iface, base+fusp + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end component; + +component nexys3_cuff_aif is -- NEXYS 3, abstract iface, base+cuff + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +component nexys3_fusp_cuff_aif is -- NEXYS 3, abstract iface, +fusp+cuff + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +end package nexys3lib; Index: nexys3/nexys3_pins_fx2.ucf =================================================================== --- nexys3/nexys3_pins_fx2.ucf (nonexistent) +++ nexys3/nexys3_pins_fx2.ucf (revision 24) @@ -0,0 +1,38 @@ +## $Id: nexys3_pins_fx2.ucf 455 2012-01-24 09:11:25Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2012-01-23 455 1.2 fix SLOE_N (h4->h6) +## 2012-01-01 448 1.1 use 12/FAST instead of 6/SLOW for _DATA<*> +## 2011-11-27 433 1.0 Initial version +## +## Cypress EZ-USB FX2 Interface -- in Bank 3 --------------------------------- +## +## +NET "I_FX2_IFCLK" LOC = "h2" | IOSTANDARD=LVCMOS33; +## +NET "IO_FX2_DATA<0>" LOC = "e1" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<1>" LOC = "f4" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<2>" LOC = "f3" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<3>" LOC = "d2" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<4>" LOC = "d1" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<5>" LOC = "h7" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<6>" LOC = "g6" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<7>" LOC = "e4" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER; +## +NET "O_FX2_SLWR_N" LOC = "c1" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLRD_N" LOC = "c2" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLOE_N" LOC = "h6" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_PKTEND_N" LOC = "d3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_FIFO<0>" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_FIFO<1>" LOC = "e3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +## assume that PA.7 is used as FLAGD (and not as SLCS#) +NET "I_FX2_FLAG<0>" LOC = "h1" | IOSTANDARD=LVCMOS33; ## flag a (program) +NET "I_FX2_FLAG<1>" LOC = "k4" | IOSTANDARD=LVCMOS33; ## flag b (full) +NET "I_FX2_FLAG<2>" LOC = "f5" | IOSTANDARD=LVCMOS33; ## flag c (empty) +NET "I_FX2_FLAG<3>" LOC = "f6" | IOSTANDARD=LVCMOS33; ## flag d (slcs) +## Index: nexys3/nexys3_pins.ucf =================================================================== --- nexys3/nexys3_pins.ucf (nonexistent) +++ nexys3/nexys3_pins.ucf (revision 24) @@ -0,0 +1,135 @@ +## $Id: nexys3_pins.ucf 432 2011-11-25 20:16:28Z mueller $ +## +## Pin locks for Nexys 3 core functionality +## - USB UART +## - human I/O (switches, buttons, leds, display) +## - cram +## +## Revision History: +## Date Rev Version Comment +## 2011-11-23 432 1.0.2 add PPCM controls +## 2011-10-10 413 1.0.1 new BTN sequence: clockwise(U-R-D-L) - middle +## 2011-07-04 388 1.0 Initial version +## +## Note: default is DRIVE=12 | SLEW=SLOW +## +## Assume that VCCB0 is jumpered for 2.5 V (for VHDCI LVDS usage) +## +## clocks -- in bank 2 ------------------------------------------------------- +NET "I_CLK100" LOC = "v10" | IOSTANDARD=LVCMOS33; +## +## USB UART Interface -- in bank 1-------------------------------------------- +## I_RXD -> signal MCU_RX -> TXD pin of FT232R +## O_TXD -> signal MCU_TX -> RXD pin of FT232R +## I_CTS_N ?? signal RTS -> RTS pin of FT232R (only on J14) +## O_RTS_N ?? signal CTS -> CTS pin of FT232R (only on J14) +NET "I_RXD" LOC = "n17" | IOSTANDARD=LVCMOS33; +NET "O_TXD" LOC = "n18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## switches -- in bank 2 ----------------------------------------------------- +NET "I_SWI<0>" LOC = "t10" | IOSTANDARD=LVCMOS33; +NET "I_SWI<1>" LOC = "t9" | IOSTANDARD=LVCMOS33; +NET "I_SWI<2>" LOC = "v9" | IOSTANDARD=LVCMOS33; +NET "I_SWI<3>" LOC = "m8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<4>" LOC = "n8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<5>" LOC = "u8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<6>" LOC = "v8" | IOSTANDARD=LVCMOS33; +NET "I_SWI<7>" LOC = "t5" | IOSTANDARD=LVCMOS33; +## +## buttons -- in bank 0------------------------------------------------------- +## sequence: clockwise(U-R-D-L) - middle +NET "I_BTN<0>" LOC = "a8" | IOSTANDARD=LVCMOS25; # BTNU +NET "I_BTN<1>" LOC = "d9" | IOSTANDARD=LVCMOS25; # BTNR +NET "I_BTN<2>" LOC = "c9" | IOSTANDARD=LVCMOS25; # BTND +NET "I_BTN<3>" LOC = "c4" | IOSTANDARD=LVCMOS25; # BTNL +NET "I_BTN<4>" LOC = "b8" | IOSTANDARD=LVCMOS25; # BTNS +## +## LEDs -- in bank 2 --------------------------------------------------------- +NET "O_LED<0>" LOC = "u16" | IOSTANDARD=LVCMOS33; +NET "O_LED<1>" LOC = "v16" | IOSTANDARD=LVCMOS33; +NET "O_LED<2>" LOC = "u15" | IOSTANDARD=LVCMOS33; +NET "O_LED<3>" LOC = "v15" | IOSTANDARD=LVCMOS33; +NET "O_LED<4>" LOC = "m11" | IOSTANDARD=LVCMOS33; +NET "O_LED<5>" LOC = "n11" | IOSTANDARD=LVCMOS33; +NET "O_LED<6>" LOC = "r11" | IOSTANDARD=LVCMOS33; +NET "O_LED<7>" LOC = "t11" | IOSTANDARD=LVCMOS33; +NET "O_LED<*>" DRIVE=12 | SLEW=SLOW; +## +## 7 segment display -- in bank 1 -------------------------------------------- +NET "O_ANO_N<0>" LOC = "n16" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<1>" LOC = "n15" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<2>" LOC = "p18" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<3>" LOC = "p17" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW; +## +NET "O_SEG_N<0>" LOC = "t17" | IOSTANDARD=LVCMOS33; # CA +NET "O_SEG_N<1>" LOC = "t18" | IOSTANDARD=LVCMOS33; # CB +NET "O_SEG_N<2>" LOC = "u17" | IOSTANDARD=LVCMOS33; # CC +NET "O_SEG_N<3>" LOC = "u18" | IOSTANDARD=LVCMOS33; # CD +NET "O_SEG_N<4>" LOC = "m14" | IOSTANDARD=LVCMOS33; # CE +NET "O_SEG_N<5>" LOC = "n14" | IOSTANDARD=LVCMOS33; # CF +NET "O_SEG_N<6>" LOC = "l14" | IOSTANDARD=LVCMOS33; # CG +NET "O_SEG_N<7>" LOC = "m13" | IOSTANDARD=LVCMOS33; # DP +NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW; +## +## CRAM -- in bank 2 (data) and 1 (addr) ------------------------------------- +NET "O_MEM_CE_N" LOC = "l15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_WE_N" LOC = "m16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_OE_N" LOC = "l18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_BE_N<0>" LOC = "k16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<1>" LOC = "k15" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_ADV_N" LOC = "h18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CLK" LOC = "r10" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CRE" LOC = "m18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "I_MEM_WAIT" LOC = "v4" | IOSTANDARD=LVCMOS33 | PULLDOWN; +## +NET "O_MEM_ADDR<0>" LOC = "k18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<1>" LOC = "k17" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<2>" LOC = "j18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<3>" LOC = "j16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<4>" LOC = "g18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<5>" LOC = "g16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<6>" LOC = "h16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<7>" LOC = "h15" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<8>" LOC = "h14" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<9>" LOC = "h13" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<10>" LOC = "f18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<11>" LOC = "f17" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<12>" LOC = "k13" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<13>" LOC = "k12" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<14>" LOC = "e18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<15>" LOC = "e16" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<16>" LOC = "g13" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<17>" LOC = "h12" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<18>" LOC = "d18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<19>" LOC = "d17" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<20>" LOC = "g14" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<21>" LOC = "f14" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<22>" LOC = "c18" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST; +## +NET "IO_MEM_DATA<0>" LOC = "r13" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<1>" LOC = "t14" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<2>" LOC = "v14" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<3>" LOC = "u5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<4>" LOC = "v5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<5>" LOC = "r3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<6>" LOC = "t3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<7>" LOC = "r5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<8>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<9>" LOC = "p6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<10>" LOC = "p12" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<11>" LOC = "u13" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<12>" LOC = "v13" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<13>" LOC = "u10" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<14>" LOC = "r8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<15>" LOC = "t8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## +## PPCM -- parallel PCM memory ----------------------------------------------- +NET "O_PPCM_CE_N" LOC = "l17" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW; +NET "O_PPCM_RST_N" LOC = "t4" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW; +## Index: nexys3 =================================================================== --- nexys3 (nonexistent) +++ nexys3 (revision 24)
nexys3 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: bpgen/bpgenlib.vhd =================================================================== --- bpgen/bpgenlib.vhd (nonexistent) +++ bpgen/bpgenlib.vhd (revision 24) @@ -0,0 +1,178 @@ +-- $Id: bpgenlib.vhd 534 2013-09-22 21:37:24Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: bpgenlib +-- Description: Generic Board/Part components +-- +-- Dependencies: - +-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob +-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib +-- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus +-- 2011-11-16 426 1.0.6 now numeric_std clean +-- 2011-10-10 413 1.0.5 add sn_humanio_demu +-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob +-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob +-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib +-- 2011-07-08 390 1.0.1 move in sn_(4x7segctl|humanio*) from s3boardlib +-- 2011-07-01 386 1.0 Initial version (with rs232_iob's and bp_swibtnled) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +package bpgenlib is + +component bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD) + port ( + CLK : in slbit; -- clock + RXD : out slbit; -- receive data (board view) + TXD : in slbit; -- transmit data (board view) + I_RXD : in slbit; -- pad-i: receive data (board view) + O_TXD : out slbit -- pad-o: transmit data (board view) + ); +end component; + +component bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS) + port ( + CLK : in slbit; -- clock + RXD : out slbit; -- receive data (board view) + TXD : in slbit; -- transmit data (board view) + CTS_N : out slbit; -- clear to send (act. low) + RTS_N : in slbit; -- request to send (act. low) + I_RXD : in slbit; -- pad-i: receive data (board view) + O_TXD : out slbit; -- pad-o: transmit data (board view) + I_CTS_N : in slbit; -- pad-i: clear to send (act. low) + O_RTS_N : out slbit -- pad-o: request to send (act. low) + ); +end component; + +component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select + generic ( + RELAY : boolean := false); -- add a relay stage towards IOB's + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + SEL : in slbit; -- select, '0' for port 0 + RXD : out slbit; -- receive data (board view) + TXD : in slbit; -- transmit data (board view) + CTS_N : out slbit; -- clear to send (act. low) + RTS_N : in slbit; -- request to send (act. low) + I_RXD0 : in slbit; -- pad-i: p0: receive data (board view) + O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view) + I_RXD1 : in slbit; -- pad-i: p1: receive data (board view) + O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view) + I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low) + O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low) + ); +end component; + +component bp_rs232_4l4l_iob is -- iob's for dual 4l+4l rs232, w/ select + generic ( + RELAY : boolean := false); -- add a relay stage towards IOB's + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + SEL : in slbit; -- select, '0' for port 0 + RXD : out slbit; -- receive data (board view) + TXD : in slbit; -- transmit data (board view) + CTS_N : out slbit; -- clear to send (act. low) + RTS_N : in slbit; -- request to send (act. low) + I_RXD0 : in slbit; -- pad-i: p0: receive data (board view) + O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view) + I_CTS0_N : in slbit; -- pad-i: p0: clear to send (act. low) + O_RTS0_N : out slbit; -- pad-o: p0: request to send (act. low) + I_RXD1 : in slbit; -- pad-i: p1: receive data (board view) + O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view) + I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low) + O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low) + ); +end component; + +component bp_swibtnled is -- generic SWI, BTN and LED handling + generic ( + SWIDTH : positive := 4; -- SWI port width + BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 4; -- LED port width + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv(LWIDTH-1 downto 0); -- led data + I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches + I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons + O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds + ); +end component; + +component sn_4x7segctl is -- Quad 7 segment display controller + generic ( + CDWIDTH : positive := 6); -- clk divider width (must be >= 5) + port ( + CLK : in slbit; -- clock + DIN : in slv16; -- data + DP : in slv4; -- decimal points + ANO_N : out slv4; -- anodes (act.low) + SEG_N : out slv8 -- segements (act.low) + ); +end component; + +component sn_humanio is -- human i/o handling: swi,btn,led,dsp + generic ( + BWIDTH : positive := 4; -- BTN port width + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv8; -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons + O_LED : out slv8; -- pad-o: leds + O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + ); +end component; + +component sn_humanio_demu is -- human i/o handling: swi,btn,led only + generic ( + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv8; -- switch settings, debounced + BTN : out slv4; -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv6; -- pad-i: buttons + O_LED : out slv8 -- pad-o: leds + ); +end component; + +end package bpgenlib; Index: bpgen/bp_rs232_2l4l_iob.vhd =================================================================== --- bpgen/bp_rs232_2l4l_iob.vhd (nonexistent) +++ bpgen/bp_rs232_2l4l_iob.vhd (revision 24) @@ -0,0 +1,186 @@ +-- $Id: bp_rs232_2l4l_iob.vhd 534 2013-09-22 21:37:24Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: bp_rs232_2l4l_iob - syn +-- Description: iob's for internal(2line) + external(4line) rs232, with select +-- +-- Dependencies: bp_rs232_2line_iob +-- bp_rs232_4line_iob +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 12.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-08-14 406 1.2.2 fix mistake in tx and rts relay +-- 2011-08-07 404 1.2.1 add RELAY generic and a relay stage towards IOB's +-- 2011-08-06 403 1.2 add pipeline flops; add RESET signal +-- 2011-07-09 391 1.1 moved and renamed to bpgen +-- 2011-07-02 387 1.0.1 use bp_rs232_[24]line_iob now +-- 2010-04-17 278 1.0 Initial version +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select + generic ( + RELAY : boolean := false); -- add a relay stage towards IOB's + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + SEL : in slbit; -- select, '0' for port 0 + RXD : out slbit; -- receive data (board view) + TXD : in slbit; -- transmit data (board view) + CTS_N : out slbit; -- clear to send (act. low) + RTS_N : in slbit; -- request to send (act. low) + I_RXD0 : in slbit; -- pad-i: p0: receive data (board view) + O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view) + I_RXD1 : in slbit; -- pad-i: p1: receive data (board view) + O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view) + I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low) + O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low) + ); +end bp_rs232_2l4l_iob; + +architecture syn of bp_rs232_2l4l_iob is + + signal RXD0 : slbit := '0'; + signal RXD1 : slbit := '0'; + signal CTS1_N : slbit := '0'; + + signal R_RXD : slbit := '1'; + signal R_CTS_N : slbit := '0'; + signal R_TXD0 : slbit := '1'; + signal R_TXD1 : slbit := '1'; + signal R_RTS1_N : slbit := '0'; + + signal RR_RXD0 : slbit := '1'; + signal RR_TXD0 : slbit := '1'; + signal RR_RXD1 : slbit := '1'; + signal RR_TXD1 : slbit := '1'; + signal RR_CTS1_N : slbit := '0'; + signal RR_RTS1_N : slbit := '0'; + +begin + + -- On Digilent Atlys bords the IOBs for P0 and P1 are on diagonally opposide + -- corners of the die, which causes very long (7-8ns) routing delays to a LUT + -- in the middle. The RELAY generic allows to add 'relay flops' between IOB + -- flops and the mux implented in proc_regs_mux. + -- + -- The data flow is + -- iob-flop relay-flop if-flop port + -- RXD0 -> RR_RXD0 -> R_RXD -> RXD + -- TXD0 <- RR_TXD0 <- R_TXD0 <- TXD + -- RXD1 -> RR_RXD1 -> R_RXD -> RXD + -- TXD1 <- RR_TXD1 <- R_TXD1 <- TXD + -- CTS1_N -> RR_CTS1_N -> R_CTS_N -> CTS + -- RTS1_N <- RR_RTS1_N <- R_RTS1_N <- RTS + + P0 : bp_rs232_2line_iob + port map ( + CLK => CLK, + RXD => RXD0, + TXD => RR_TXD0, + I_RXD => I_RXD0, + O_TXD => O_TXD0 + ); + + P1 : bp_rs232_4line_iob + port map ( + CLK => CLK, + RXD => RXD1, + TXD => RR_TXD1, + CTS_N => CTS1_N, + RTS_N => RR_RTS1_N, + I_RXD => I_RXD1, + O_TXD => O_TXD1, + I_CTS_N => I_CTS1_N, + O_RTS_N => O_RTS1_N + ); + + DORELAY : if RELAY generate + proc_regs_pipe: process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + RR_RXD0 <= '1'; + RR_TXD0 <= '1'; + RR_RXD1 <= '1'; + RR_TXD1 <= '1'; + RR_CTS1_N <= '0'; + RR_RTS1_N <= '0'; + else + RR_RXD0 <= RXD0; + RR_TXD0 <= R_TXD0; + RR_RXD1 <= RXD1; + RR_TXD1 <= R_TXD1; + RR_CTS1_N <= CTS1_N; + RR_RTS1_N <= R_RTS1_N; + end if; + end if; + end process proc_regs_pipe; + end generate DORELAY; + + NORELAY : if not RELAY generate + RR_RXD0 <= RXD0; + RR_TXD0 <= R_TXD0; + RR_RXD1 <= RXD1; + RR_TXD1 <= R_TXD1; + RR_CTS1_N <= CTS1_N; + RR_RTS1_N <= R_RTS1_N; + end generate NORELAY; + + proc_regs_mux: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_RXD <= '1'; + R_CTS_N <= '0'; + R_TXD0 <= '1'; + R_TXD1 <= '1'; + R_RTS1_N <= '0'; + else + if SEL = '0' then -- use 2-line rs232, no flow cntl + R_RXD <= RR_RXD0; -- get port 0 inputs + R_CTS_N <= '0'; + R_TXD0 <= TXD; -- set port 0 output + R_TXD1 <= '1'; -- port 1 outputs to idle state + R_RTS1_N <= '0'; + else -- otherwise use 4-line rs232 + R_RXD <= RR_RXD1; -- get port 1 inputs + R_CTS_N <= RR_CTS1_N; + R_TXD0 <= '1'; -- port 0 output to idle state + R_TXD1 <= TXD; -- set port 1 outputs + R_RTS1_N <= RTS_N; + end if; + end if; + end if; + + end process proc_regs_mux; + + RXD <= R_RXD; + CTS_N <= R_CTS_N; + +end syn; Index: bpgen/bpgenrbuslib.vbom =================================================================== --- bpgen/bpgenrbuslib.vbom (nonexistent) +++ bpgen/bpgenrbuslib.vbom (revision 24) @@ -0,0 +1,4 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +bpgenrbuslib.vhd Index: bpgen/bpgenlib.vbom =================================================================== --- bpgen/bpgenlib.vbom (nonexistent) +++ bpgen/bpgenlib.vbom (revision 24) @@ -0,0 +1,3 @@ +# libs +../../vlib/slvtypes.vhd +bpgenlib.vhd Index: bpgen/bpgenrbuslib.vhd =================================================================== --- bpgen/bpgenrbuslib.vhd (nonexistent) +++ bpgen/bpgenrbuslib.vhd (revision 24) @@ -0,0 +1,101 @@ +-- $Id: bpgenrbuslib.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: bpgenrbuslib +-- Description: Generic Board/Part components using rbus +-- +-- Dependencies: - +-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; + +package bpgenrbuslib is + +component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept + generic ( + SWIDTH : positive := 4; -- SWI port width + BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 4; -- LED port width + DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv(LWIDTH-1 downto 0); -- led data + I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches + I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons + O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds + ); +end component; + +component sn_humanio_rbus is -- human i/o handling /w rbus intercept + generic ( + BWIDTH : positive := 4; -- BTN port width + DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SWI : out slv8; -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons + O_LED : out slv8; -- pad-o: leds + O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + ); +end component; + +component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus + generic ( + DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SWI : out slv8; -- switch settings, debounced + BTN : out slv4; -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv6; -- pad-i: buttons + O_LED : out slv8 -- pad-o: leds + ); +end component; + +end package bpgenrbuslib; Index: bpgen/Makefile =================================================================== --- bpgen/Makefile (nonexistent) +++ bpgen/Makefile (revision 24) @@ -0,0 +1,27 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2007-12-09 100 1.0.1 drop ISE_p definition +# 2007-09-16 83 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: bpgen/sn_humanio_demu_rbus.vhd =================================================================== --- bpgen/sn_humanio_demu_rbus.vhd (nonexistent) +++ bpgen/sn_humanio_demu_rbus.vhd (revision 24) @@ -0,0 +1,300 @@ +-- $Id: sn_humanio_demu_rbus.vhd 472 2013-01-06 14:39:10Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sn_humanio_demu_rbus - syn +-- Description: sn_humanio_demu with rbus interceptor +-- +-- Dependencies: bpgen/sn_humanio_demu +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2013-01-06 472 13.3 O76xd xc3s1000-4 160 136 0 124 s 6.1 ns +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-06 472 1.0 Initial version (cloned from sn_humanio_rbus +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- +-- Address Bits Name r/w/f Function +-- bbbbbb00 cntl r/w/- Control register and BTN access +-- x:08 btn r/w/- r: return hio BTN status +-- w: ored with hio BTN to drive BTN +-- 3 dsp_en r/w/- if 1 display data will be driven by rbus +-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus +-- 1 led_en r/w/- if 1 LED will be driven by rri +-- 0 swi_en r/w/- if 1 SWI will be driven by rri +-- +-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status +-- w: will drive SWI when swi_en=1 +-- +-- bbbbbb10 led r/w/- Interface to LED and DSP_DP +-- 15:12 dp r/w/- r: returns DSP_DP status +-- w: will drive display dp's when dp_en=1 +-- 7:00 led r/w/- r: returns LED status +-- w: will drive led's when led_en=1 +-- +-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status +-- w: will drive DSP_DAT when dsp_en=1 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus + generic ( + DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SWI : out slv8; -- switch settings, debounced + BTN : out slv4; -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv6; -- pad-i: buttons + O_LED : out slv8 -- pad-o: leds + ); +end sn_humanio_demu_rbus; + +architecture syn of sn_humanio_demu_rbus is + + type regs_type is record + rbsel : slbit; -- rbus select + swi : slv8; -- rbus swi + btn : slv4; -- rbus btn + led : slv8; -- rbus led + dsp_dat : slv16; -- rbus dsp_dat + dsp_dp : slv4; -- rbus dsp_dp + ledin : slv8; -- led from design + swieff : slv8; -- effective swi + btneff : slv4; -- effective btn + ledeff : slv8; -- effective led + dpeff : slv4; -- effective dsp_dp + dateff : slv16; -- effective dsp_dat + swi_en : slbit; -- enable: swi from rbus + led_en : slbit; -- enable: led from rbus + dsp_en : slbit; -- enable: dsp_dat from rbus + dp_en : slbit; -- enable: dsp_dp from rbus + end record regs_type; + + constant regs_init : regs_type := ( + '0', -- rbsel + (others=>'0'), -- swi + (others=>'0'), -- btn + (others=>'0'), -- led + (others=>'0'), -- dsp_dat + (others=>'0'), -- dsp_dp + (others=>'0'), -- ledin + (others=>'0'), -- swieff + (others=>'0'), -- btneff + (others=>'0'), -- ledeff + (others=>'0'), -- dpeff + (others=>'0'), -- dateff + '0','0','0','0' -- (swi|led|dsp|dp)_en + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + subtype cntl_rbf_btn is integer range 11 downto 8; + constant cntl_rbf_dsp_en: integer := 3; + constant cntl_rbf_dp_en: integer := 2; + constant cntl_rbf_led_en: integer := 1; + constant cntl_rbf_swi_en: integer := 0; + subtype led_rbf_dp is integer range 15 downto 12; + subtype led_rbf_led is integer range 7 downto 0; + + constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/- + constant rbaddr_swi: slv2 := "01"; -- 1 r/w/- + constant rbaddr_led: slv2 := "10"; -- 2 r/w/- + constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/- + + signal HIO_SWI : slv8 := (others=>'0'); + signal HIO_BTN : slv4 := (others=>'0'); + signal HIO_LED : slv8 := (others=>'0'); + signal HIO_DSP_DAT : slv16 := (others=>'0'); + signal HIO_DSP_DP : slv4 := (others=>'0'); + +begin + + HIO : sn_humanio_demu + generic map ( + DEBOUNCE => DEBOUNCE) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => HIO_SWI, + BTN => HIO_BTN, + LED => HIO_LED, + DSP_DAT => HIO_DSP_DAT, + DSP_DP => HIO_DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP, + HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irb_ack : slbit := '0'; + variable irb_busy : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + variable irbena : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + irb_ack := '0'; + irb_busy := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + + irbena := RB_MREQ.re or RB_MREQ.we; + + -- input register for LED signal + n.ledin := LED; + + -- rbus address decoder + n.rbsel := '0'; + if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then + n.rbsel := '1'; + end if; + + -- rbus transactions + if r.rbsel = '1' then + irb_ack := irbena; -- ack all accesses + + case RB_MREQ.addr(1 downto 0) is + + when rbaddr_cntl => + irb_dout(cntl_rbf_btn) := HIO_BTN; + irb_dout(cntl_rbf_dsp_en) := r.dsp_en; + irb_dout(cntl_rbf_dp_en) := r.dp_en; + irb_dout(cntl_rbf_led_en) := r.led_en; + irb_dout(cntl_rbf_swi_en) := r.swi_en; + if RB_MREQ.we = '1' then + n.btn := RB_MREQ.din(cntl_rbf_btn); + n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en); + n.dp_en := RB_MREQ.din(cntl_rbf_dp_en); + n.led_en := RB_MREQ.din(cntl_rbf_led_en); + n.swi_en := RB_MREQ.din(cntl_rbf_swi_en); + end if; + + when rbaddr_swi => + irb_dout(HIO_SWI'range) := HIO_SWI; + if RB_MREQ.we = '1' then + n.swi := RB_MREQ.din(n.swi'range); + end if; + + when rbaddr_led => + irb_dout(led_rbf_dp) := HIO_DSP_DP; + irb_dout(led_rbf_led) := r.ledin; + if RB_MREQ.we = '1' then + n.dsp_dp := RB_MREQ.din(led_rbf_dp); + n.led := RB_MREQ.din(led_rbf_led); + end if; + + when rbaddr_dsp => + irb_dout := HIO_DSP_DAT; + if RB_MREQ.we = '1' then + n.dsp_dat := RB_MREQ.din; + end if; + + when others => null; + end case; + + end if; + + n.btneff := HIO_BTN or r.btn; + + if r.swi_en = '0' then + n.swieff := HIO_SWI; + else + n.swieff := r.swi; + end if; + + if r.led_en = '0' then + n.ledeff := r.ledin; + else + n.ledeff := r.led; + end if; + + if r.dp_en = '0' then + n.dpeff := DSP_DP; + else + n.dpeff := r.dsp_dp; + end if; + + if r.dsp_en = '0' then + n.dateff := DSP_DAT; + else + n.dateff := r.dsp_dat; + end if; + + N_REGS <= n; + + BTN <= R_REGS.btneff; + SWI <= R_REGS.swieff; + HIO_LED <= R_REGS.ledeff; + HIO_DSP_DP <= R_REGS.dpeff; + HIO_DSP_DAT <= R_REGS.dateff; + + RB_SRES <= rb_sres_init; + RB_SRES.ack <= irb_ack; + RB_SRES.busy <= irb_busy; + RB_SRES.err <= irb_err; + RB_SRES.dout <= irb_dout; + + end process proc_next; + +end syn; Index: bpgen/sn_humanio_demu_rbus.vbom =================================================================== --- bpgen/sn_humanio_demu_rbus.vbom (nonexistent) +++ bpgen/sn_humanio_demu_rbus.vbom (revision 24) @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +bpgenlib.vbom +# components +sn_humanio_demu.vbom +# design +sn_humanio_demu_rbus.vhd Index: bpgen/bp_swibtnled.vbom =================================================================== --- bpgen/bp_swibtnled.vbom (nonexistent) +++ bpgen/bp_swibtnled.vbom (revision 24) @@ -0,0 +1,12 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/genlib/genlib.vhd +../../vlib/xlib/xlib.vhd +bpgenlib.vbom +## ${sys_conf := sys_conf.vhd} +# components +../../vlib/xlib/iob_reg_i_gen.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/genlib/debounce_gen.vbom +# design +bp_swibtnled.vhd Index: bpgen/sn_humanio.vhd =================================================================== --- bpgen/sn_humanio.vhd (nonexistent) +++ bpgen/sn_humanio.vhd (revision 24) @@ -0,0 +1,118 @@ +-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sn_humanio - syn +-- Description: All BTN, SWI, LED and DSP handling for s3board, nexys2/3 +-- +-- Dependencies: xlib/iob_reg_o_gen +-- bpgen/bp_swibtnled +-- bpgen/sn_4x7segctl +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns +-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns +-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-07-30 400 1.2.1 use CDWIDTH=7 for sn_4x7segctl (for 100 MHz) +-- 2011-07-08 390 1.2 renamed from s3_humanio, add BWIDTH generic +-- 2011-07-02 387 1.1.2 use bp_swibtnled +-- 2010-04-17 278 1.1.1 rename dispdrv -> s3_dispdrv +-- 2010-04-11 276 1.1 instantiate BTN/SWI debouncers via DEBOUNCE generic +-- 2010-04-10 275 1.0 Initial version +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity sn_humanio is -- human i/o handling: swi,btn,led,dsp + generic ( + BWIDTH : positive := 4; -- BTN port width + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv8; -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons + O_LED : out slv8; -- pad-o: leds + O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + ); +end sn_humanio; + +architecture syn of sn_humanio is + + signal N_ANO_N : slv4 := (others=>'0'); + signal N_SEG_N : slv8 := (others=>'0'); + +begin + + IOB_ANO_N : iob_reg_o_gen + generic map (DWIDTH => 4) + port map (CLK => CLK, CE => '1', DO => N_ANO_N, PAD => O_ANO_N); + + IOB_SEG_N : iob_reg_o_gen + generic map (DWIDTH => 8) + port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N); + + HIO : bp_swibtnled + generic map ( + SWIDTH => 8, + BWIDTH => BWIDTH, + LWIDTH => 8, + DEBOUNCE => DEBOUNCE) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED + ); + + DRV : sn_4x7segctl + generic map ( + CDWIDTH => 7) -- 7 good for 100 MHz on nexys2 + port map ( + CLK => CLK, + DIN => DSP_DAT, + DP => DSP_DP, + ANO_N => N_ANO_N, + SEG_N => N_SEG_N + ); + +end syn; Index: bpgen/sn_humanio_demu.vhd =================================================================== --- bpgen/sn_humanio_demu.vhd (nonexistent) +++ bpgen/sn_humanio_demu.vhd (revision 24) @@ -0,0 +1,195 @@ +-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sn_humanio_demu - syn +-- Description: All BTN, SWI, LED handling for atlys +-- +-- Dependencies: bpgen/bp_swibtnled +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low +-- 2011-10-10 413 1.0 Initial version +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity sn_humanio_demu is -- human i/o handling: swi,btn,led only + generic ( + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv8; -- switch settings, debounced + BTN : out slv4; -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv6; -- pad-i: buttons + O_LED : out slv8 -- pad-o: leds + ); +end sn_humanio_demu; + +architecture syn of sn_humanio_demu is + + constant c_mode_led : slv2 := "00"; + constant c_mode_dp : slv2 := "01"; + constant c_mode_datl : slv2 := "10"; + constant c_mode_dath : slv2 := "11"; + + type regs_type is record + mode : slv2; -- current mode + cnt : slv9; -- msec counter + up_1 : slbit; -- btn up last cycle + dn_1 : slbit; -- btn dn last cycle + led : slv8; -- led state + end record regs_type; + + constant regs_init : regs_type := ( + c_mode_led, -- mode + (others=>'0'), -- cnt + '0','0', -- up_1, dn_1 + (others=>'0') -- led + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal BTN_HW : slv6 := (others=>'0'); + signal LED_HW : slv8 := (others=>'0'); + +begin + + HIO : bp_swibtnled + generic map ( + SWIDTH => 8, + BWIDTH => 6, + LWIDTH => 8, + DEBOUNCE => DEBOUNCE) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN_HW, + LED => LED_HW, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable ibtn : slv4 := (others=>'0'); + variable iup : slbit := '0'; + variable idn : slbit := '0'; + variable ipuls : slbit := '0'; + + begin + r := R_REGS; + n := R_REGS; + + ibtn(0) := not BTN_HW(5); -- RESET button is act. low ! + ibtn(1) := BTN_HW(1); + ibtn(2) := BTN_HW(4); + ibtn(3) := BTN_HW(3); + iup := BTN_HW(0); + idn := BTN_HW(2); + + ipuls := '0'; + + + n.up_1 := iup; + n.dn_1 := idn; + + if iup='0' and idn='0' then + n.cnt := (others=>'0'); + else + if CE_MSEC = '1' then + n.cnt := slv(unsigned(r.cnt) + 1); + if r.cnt = "111111111" then + ipuls := '1'; + end if; + end if; + end if; + + if iup='1' or idn='1' then + n.led := (others=>'0'); + case r.mode is + when c_mode_led => n.led(0) := '1'; + when c_mode_dp => n.led(1) := '1'; + when c_mode_datl => n.led(2) := '1'; + when c_mode_dath => n.led(3) := '1'; + when others => null; + end case; + + if iup='1' and (r.up_1='0' or ipuls='1') then + n.mode := slv(unsigned(r.mode) + 1); + elsif idn='1' and (r.dn_1='0' or ipuls='1') then + n.mode := slv(unsigned(r.mode) - 1); + end if; + + else + case r.mode is + when c_mode_led => n.led := LED; + when c_mode_dp => n.led := "0000" & DSP_DP; + when c_mode_datl => n.led := DSP_DAT( 7 downto 0); + when c_mode_dath => n.led := DSP_DAT(15 downto 8); + when others => null; + end case; + end if; + + N_REGS <= n; + + BTN <= ibtn; + LED_HW <= r.led; + + end process proc_next; + +end syn; Index: bpgen/bp_swibtnled.vhd =================================================================== --- bpgen/bp_swibtnled.vhd (nonexistent) +++ bpgen/bp_swibtnled.vhd (revision 24) @@ -0,0 +1,116 @@ +-- $Id: bp_swibtnled.vhd 410 2011-09-18 11:23:09Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: bp_swibtnled - syn +-- Description: Generic SWI, BTN and LED handling +-- +-- Dependencies: xlib/iob_reg_i_gen +-- xlib/iob_reg_o_gen +-- genlib/debounce_gen +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-07-01 386 1.0 Initial version, extracted from s3_humanio +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity bp_swibtnled is -- generic SWI, BTN and LED handling + generic ( + SWIDTH : positive := 4; -- SWI port width + BWIDTH : positive := 4; -- BTN port width + LWIDTH : positive := 4; -- LED port width + DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv(LWIDTH-1 downto 0); -- led data + I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches + I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons + O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds + ); +end bp_swibtnled; + +architecture syn of bp_swibtnled is + + signal RI_SWI : slv(SWIDTH-1 downto 0) := (others=>'0'); + signal RI_BTN : slv(BWIDTH-1 downto 0) := (others=>'0'); + +begin + + IOB_SWI : iob_reg_i_gen + generic map (DWIDTH => SWIDTH) + port map (CLK => CLK, CE => '1', DI => RI_SWI, PAD => I_SWI); + + IOB_BTN : iob_reg_i_gen + generic map (DWIDTH => BWIDTH) + port map (CLK => CLK, CE => '1', DI => RI_BTN, PAD => I_BTN); + + IOB_LED : iob_reg_o_gen + generic map (DWIDTH => LWIDTH) + port map (CLK => CLK, CE => '1', DO => LED, PAD => O_LED); + + DEB: if DEBOUNCE generate + + DEB_SWI : debounce_gen + generic map ( + CWIDTH => 2, + CEDIV => 3, + DWIDTH => SWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CE_INT => CE_MSEC, + DI => RI_SWI, + DO => SWI + ); + + DEB_BTN : debounce_gen + generic map ( + CWIDTH => 2, + CEDIV => 3, + DWIDTH => BWIDTH) + port map ( + CLK => CLK, + RESET => RESET, + CE_INT => CE_MSEC, + DI => RI_BTN, + DO => BTN + ); + + end generate DEB; + + NODEB: if not DEBOUNCE generate + SWI <= RI_SWI; + BTN <= RI_BTN; + end generate NODEB; + +end syn; Index: bpgen/bp_rs232_2line_iob.vhd =================================================================== --- bpgen/bp_rs232_2line_iob.vhd (nonexistent) +++ bpgen/bp_rs232_2line_iob.vhd (revision 24) @@ -0,0 +1,62 @@ +-- $Id: bp_rs232_2line_iob.vhd 426 2011-11-18 18:14:08Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: bp_rs232_2line_iob - syn +-- Description: iob's for 2 line rs232 (RXD,TXD only) +-- +-- Dependencies: xlib/iob_reg_i +-- xlib/iob_reg_o +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-07-01 386 1.1 Moved and renamed to bpgen +-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_int) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; + +-- ---------------------------------------------------------------------------- + +entity bp_rs232_2line_iob is -- iob's for 2 line rs232 (RXD,TXD) + port ( + CLK : in slbit; -- clock + RXD : out slbit; -- receive data (board view) + TXD : in slbit; -- transmit data (board view) + I_RXD : in slbit; -- pad-i: receive data (board view) + O_TXD : out slbit -- pad-o: transmit data (board view) + ); +end bp_rs232_2line_iob; + +architecture syn of bp_rs232_2line_iob is +begin + + IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1 + generic map (INIT => '1') + port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD); + + IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1 + generic map (INIT => '1') + port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD); + +end syn; Index: bpgen/bp_rs232_4line_iob.vhd =================================================================== --- bpgen/bp_rs232_4line_iob.vhd (nonexistent) +++ bpgen/bp_rs232_4line_iob.vhd (revision 24) @@ -0,0 +1,72 @@ +-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: bp_rs232_4line_iob - syn +-- Description: iob's for 4 line rs232 (RXD,TXD and RTS,CTS) +-- +-- Dependencies: xlib/iob_reg_i +-- xlib/iob_reg_o +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-07-01 386 1.1 moved and renamed to bpgen +-- 2010-04-17 278 1.0 Initial version (as s3_rs232_iob_ext) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; + +-- ---------------------------------------------------------------------------- + +entity bp_rs232_4line_iob is -- iob's for 4 line rs232 (w/ RTS,CTS) + port ( + CLK : in slbit; -- clock + RXD : out slbit; -- receive data (board view) + TXD : in slbit; -- transmit data (board view) + CTS_N : out slbit; -- clear to send (act. low) + RTS_N : in slbit; -- request to send (act. low) + I_RXD : in slbit; -- pad-i: receive data (board view) + O_TXD : out slbit; -- pad-o: transmit data (board view) + I_CTS_N : in slbit; -- pad-i: clear to send (act. low) + O_RTS_N : out slbit -- pad-o: request to send (act. low) + ); +end bp_rs232_4line_iob; + +architecture syn of bp_rs232_4line_iob is +begin + + IOB_RXD : iob_reg_i -- line idle=1, so init sync flop =1 + generic map (INIT => '1') + port map (CLK => CLK, CE => '1', DI => RXD, PAD => I_RXD); + + IOB_TXD : iob_reg_o -- line idle=1, so init sync flop =1 + generic map (INIT => '1') + port map (CLK => CLK, CE => '1', DO => TXD, PAD => O_TXD); + + IOB_CTS : iob_reg_i + port map (CLK => CLK, CE => '1', DI => CTS_N, PAD => I_CTS_N); + + IOB_RTS : iob_reg_o + port map (CLK => CLK, CE => '1', DO => RTS_N, PAD => O_RTS_N); + +end syn; Index: bpgen/sn_humanio.vbom =================================================================== --- bpgen/sn_humanio.vbom (nonexistent) +++ bpgen/sn_humanio.vbom (revision 24) @@ -0,0 +1,10 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +bpgenlib.vbom +# components +../../vlib/xlib/iob_reg_o_gen.vbom +bp_swibtnled.vbom +sn_4x7segctl.vbom +# design +sn_humanio.vhd Index: bpgen/sn_4x7segctl.vhd =================================================================== --- bpgen/sn_4x7segctl.vhd (nonexistent) +++ bpgen/sn_4x7segctl.vhd (revision 24) @@ -0,0 +1,156 @@ +-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sn_4x7segctl - syn +-- Description: Quad 7 segment display controller (for s3board and nexys2/3) +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-09-17 410 1.2.1 now numeric_std clean +-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks) +-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv +-- 2010-04-17 278 1.1.1 renamed from dispdrv +-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off +-- delay and to avoid cross talk between digits +-- 2007-12-16 101 1.0.1 use _N for active low +-- 2007-09-16 83 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity sn_4x7segctl is -- Quad 7 segment display controller + generic ( + CDWIDTH : positive := 6); -- clk divider width (must be >= 5) + port ( + CLK : in slbit; -- clock + DIN : in slv16; -- data + DP : in slv4; -- decimal points + ANO_N : out slv4; -- anodes (act.low) + SEG_N : out slv8 -- segements (act.low) + ); +end sn_4x7segctl; + +architecture syn of sn_4x7segctl is + + type regs_type is record + cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter + dcnt : slv2; -- digit counter + end record regs_type; + + constant regs_init : regs_type := ( + slv(to_unsigned(0,CDWIDTH)), + (others=>'0') + ); + + type hex2segtbl_type is array (0 to 15) of slv7; + + constant hex2segtbl : hex2segtbl_type := + ("0111111", -- 0: "0000" + "0000110", -- 1: "0001" + "1011011", -- 2: "0010" + "1001111", -- 3: "0011" + "1100110", -- 4: "0100" + "1101101", -- 5: "0101" + "1111101", -- 6: "0110" + "0000111", -- 7: "0111" + "1111111", -- 8: "1000" + "1101111", -- 9: "1001" + "1110111", -- a: "1010" + "1111100", -- b: "1011" + "0111001", -- c: "1100" + "1011110", -- d: "1101" + "1111001", -- e: "1110" + "1110001" -- f: "1111" + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + assert CDWIDTH >= 5 + report "assert(CDWIDTH >= 5): CDWIDTH too small" + severity FAILURE; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + R_REGS <= N_REGS; + end if; + + end process proc_regs; + + + proc_next: process (R_REGS, DIN, DP) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable cano : slv4 := "0000"; + variable chex : slv4 := "0000"; + variable cdp : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + n.cdiv := slv(unsigned(r.cdiv) - 1); + if unsigned(r.cdiv) = 0 then + n.dcnt := slv(unsigned(r.dcnt) + 1); + end if; + + chex := "0000"; + cdp := '0'; + + case r.dcnt is + when "00" => chex := DIN( 3 downto 0); cdp := DP(0); + when "01" => chex := DIN( 7 downto 4); cdp := DP(1); + when "10" => chex := DIN(11 downto 8); cdp := DP(2); + when "11" => chex := DIN(15 downto 12); cdp := DP(3); + when others => chex := "----"; cdp := '-'; + end case; + + -- the logic below ensures that the anode PNP driver transistor is switched + -- off in the last quarter of the digit cycle.This prevents 'cross talk' + -- between digits due to transistor turn off delays. + -- For a nexys2 board at 50 MHz observed: + -- no or 4 cycles gap well visible cross talk + -- with 8 cycles still some weak cross talk + -- with 16 cycles none is visible. + -- --> The turn-off delay of the anode driver PNP's this therefore + -- larger 160 ns and below 320 ns. + -- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz. + + cano := "1111"; + if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then + cano(to_integer(unsigned(r.dcnt))) := '0'; + end if; + + N_REGS <= n; + + ANO_N <= cano; + SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex)))); + + end process proc_next; + +end syn; Index: bpgen/sn_humanio_rbus.vhd =================================================================== --- bpgen/sn_humanio_rbus.vhd (nonexistent) +++ bpgen/sn_humanio_rbus.vhd (revision 24) @@ -0,0 +1,317 @@ +-- $Id: sn_humanio_rbus.vhd 427 2011-11-19 21:04:11Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sn_humanio_rbus - syn +-- Description: sn_humanio with rbus interceptor +-- +-- Dependencies: bpgen/sn_humanio +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-08-14 406 12.1 M53d xc3s1000-4 142 156 0 123 s 5.1 ns +-- 2011-08-07 404 12.1 M53d xc3s1000-4 142 157 0 124 s 5.1 ns +-- 2010-12-29 351 12.1 M53d xc3s1000-4 93 138 0 111 s 6.8 ns +-- 2010-06-03 300 11.4 L68 xc3s1000-4 92 137 0 111 s 6.7 ns +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-19 427 1.2.1 now numeric_std clean +-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus +-- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff +-- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic +-- 2010-12-29 351 1.1 renamed from s3_humanio_rri; ported to rbv3 +-- 2010-06-18 306 1.0.1 rename rbus data fields to _rbf_ +-- 2010-06-03 300 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- rbus registers: +-- +-- Address Bits Name r/w/f Function +-- bbbbbb00 cntl r/w/- Control register and BTN access +-- x:08 btn r/w/- r: return hio BTN status +-- w: ored with hio BTN to drive BTN +-- 3 dsp_en r/w/- if 1 display data will be driven by rbus +-- 2 dp_en r/w/- if 1 display dp's will be driven by rbus +-- 1 led_en r/w/- if 1 LED will be driven by rri +-- 0 swi_en r/w/- if 1 SWI will be driven by rri +-- +-- bbbbbb01 7:00 swi r/w/- r: return hio SWI status +-- w: will drive SWI when swi_en=1 +-- +-- bbbbbb10 led r/w/- Interface to LED and DSP_DP +-- 15:12 dp r/w/- r: returns DSP_DP status +-- w: will drive display dp's when dp_en=1 +-- 7:00 led r/w/- r: returns LED status +-- w: will drive led's when led_en=1 +-- +-- bbbbbb11 15:00 dsp r/w/- r: return hio DSP_DAT status +-- w: will drive DSP_DAT when dsp_en=1 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.bpgenlib.all; + +-- ---------------------------------------------------------------------------- + +entity sn_humanio_rbus is -- human i/o handling /w rbus intercept + generic ( + BWIDTH : positive := 4; -- BTN port width + DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN + RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + CE_MSEC : in slbit; -- 1 ms clock enable + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + SWI : out slv8; -- switch settings, debounced + BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced + LED : in slv8; -- led data + DSP_DAT : in slv16; -- display data + DSP_DP : in slv4; -- display decimal points + I_SWI : in slv8; -- pad-i: switches + I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons + O_LED : out slv8; -- pad-o: leds + O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low) + O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low) + ); +end sn_humanio_rbus; + +architecture syn of sn_humanio_rbus is + + type regs_type is record + rbsel : slbit; -- rbus select + swi : slv8; -- rbus swi + btn : slv(BWIDTH-1 downto 0); -- rbus btn + led : slv8; -- rbus led + dsp_dat : slv16; -- rbus dsp_dat + dsp_dp : slv4; -- rbus dsp_dp + ledin : slv8; -- led from design + swieff : slv8; -- effective swi + btneff : slv(BWIDTH-1 downto 0); -- effective btn + ledeff : slv8; -- effective led + dpeff : slv4; -- effective dsp_dp + dateff : slv16; -- effective dsp_dat + swi_en : slbit; -- enable: swi from rbus + led_en : slbit; -- enable: led from rbus + dsp_en : slbit; -- enable: dsp_dat from rbus + dp_en : slbit; -- enable: dsp_dp from rbus + end record regs_type; + + constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + '0', -- rbsel + (others=>'0'), -- swi + btnzero, -- btn + (others=>'0'), -- led + (others=>'0'), -- dsp_dat + (others=>'0'), -- dsp_dp + (others=>'0'), -- ledin + (others=>'0'), -- swieff + btnzero, -- btneff + (others=>'0'), -- ledeff + (others=>'0'), -- dpeff + (others=>'0'), -- dateff + '0','0','0','0' -- (swi|led|dsp|dp)_en + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + subtype cntl_rbf_btn is integer range BWIDTH+8-1 downto 8; + constant cntl_rbf_dsp_en: integer := 3; + constant cntl_rbf_dp_en: integer := 2; + constant cntl_rbf_led_en: integer := 1; + constant cntl_rbf_swi_en: integer := 0; + subtype led_rbf_dp is integer range 15 downto 12; + subtype led_rbf_led is integer range 7 downto 0; + + constant rbaddr_cntl: slv2 := "00"; -- 0 r/w/- + constant rbaddr_swi: slv2 := "01"; -- 1 r/w/- + constant rbaddr_led: slv2 := "10"; -- 2 r/w/- + constant rbaddr_dsp: slv2 := "11"; -- 3 r/w/- + + signal HIO_SWI : slv8 := (others=>'0'); + signal HIO_BTN : slv(BWIDTH-1 downto 0) := (others=>'0'); + signal HIO_LED : slv8 := (others=>'0'); + signal HIO_DSP_DAT : slv16 := (others=>'0'); + signal HIO_DSP_DP : slv4 := (others=>'0'); + +begin + + HIO : sn_humanio + generic map ( + BWIDTH => BWIDTH, + DEBOUNCE => DEBOUNCE) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => HIO_SWI, + BTN => HIO_BTN, + LED => HIO_LED, + DSP_DAT => HIO_DSP_DAT, + DSP_DP => HIO_DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP, + HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irb_ack : slbit := '0'; + variable irb_busy : slbit := '0'; + variable irb_err : slbit := '0'; + variable irb_dout : slv16 := (others=>'0'); + variable irbena : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + irb_ack := '0'; + irb_busy := '0'; + irb_err := '0'; + irb_dout := (others=>'0'); + + irbena := RB_MREQ.re or RB_MREQ.we; + + -- input register for LED signal + n.ledin := LED; + + -- rbus address decoder + n.rbsel := '0'; + if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then + n.rbsel := '1'; + end if; + + -- rbus transactions + if r.rbsel = '1' then + irb_ack := irbena; -- ack all accesses + + case RB_MREQ.addr(1 downto 0) is + + when rbaddr_cntl => + irb_dout(cntl_rbf_btn) := HIO_BTN; + irb_dout(cntl_rbf_dsp_en) := r.dsp_en; + irb_dout(cntl_rbf_dp_en) := r.dp_en; + irb_dout(cntl_rbf_led_en) := r.led_en; + irb_dout(cntl_rbf_swi_en) := r.swi_en; + if RB_MREQ.we = '1' then + n.btn := RB_MREQ.din(cntl_rbf_btn); + n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en); + n.dp_en := RB_MREQ.din(cntl_rbf_dp_en); + n.led_en := RB_MREQ.din(cntl_rbf_led_en); + n.swi_en := RB_MREQ.din(cntl_rbf_swi_en); + end if; + + when rbaddr_swi => + irb_dout(HIO_SWI'range) := HIO_SWI; + if RB_MREQ.we = '1' then + n.swi := RB_MREQ.din(n.swi'range); + end if; + + when rbaddr_led => + irb_dout(led_rbf_dp) := HIO_DSP_DP; + irb_dout(led_rbf_led) := r.ledin; + if RB_MREQ.we = '1' then + n.dsp_dp := RB_MREQ.din(led_rbf_dp); + n.led := RB_MREQ.din(led_rbf_led); + end if; + + when rbaddr_dsp => + irb_dout := HIO_DSP_DAT; + if RB_MREQ.we = '1' then + n.dsp_dat := RB_MREQ.din; + end if; + + when others => null; + end case; + + end if; + + n.btneff := HIO_BTN or r.btn; + + if r.swi_en = '0' then + n.swieff := HIO_SWI; + else + n.swieff := r.swi; + end if; + + if r.led_en = '0' then + n.ledeff := r.ledin; + else + n.ledeff := r.led; + end if; + + if r.dp_en = '0' then + n.dpeff := DSP_DP; + else + n.dpeff := r.dsp_dp; + end if; + + if r.dsp_en = '0' then + n.dateff := DSP_DAT; + else + n.dateff := r.dsp_dat; + end if; + + N_REGS <= n; + + BTN <= R_REGS.btneff; + SWI <= R_REGS.swieff; + HIO_LED <= R_REGS.ledeff; + HIO_DSP_DP <= R_REGS.dpeff; + HIO_DSP_DAT <= R_REGS.dateff; + + RB_SRES <= rb_sres_init; + RB_SRES.ack <= irb_ack; + RB_SRES.busy <= irb_busy; + RB_SRES.err <= irb_err; + RB_SRES.dout <= irb_dout; + + end process proc_next; + +end syn; Index: bpgen/sn_humanio_demu.vbom =================================================================== --- bpgen/sn_humanio_demu.vbom (nonexistent) +++ bpgen/sn_humanio_demu.vbom (revision 24) @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +bpgenlib.vbom +# components +bp_swibtnled.vbom +# design +sn_humanio_demu.vhd Index: bpgen/bp_rs232_2line_iob.vbom =================================================================== --- bpgen/bp_rs232_2line_iob.vbom (nonexistent) +++ bpgen/bp_rs232_2line_iob.vbom (revision 24) @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_i.vbom +../../vlib/xlib/iob_reg_o.vbom +# design +bp_rs232_2line_iob.vhd Index: bpgen/bp_rs232_4line_iob.vbom =================================================================== --- bpgen/bp_rs232_4line_iob.vbom (nonexistent) +++ bpgen/bp_rs232_4line_iob.vbom (revision 24) @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_i.vbom +../../vlib/xlib/iob_reg_o.vbom +# design +bp_rs232_4line_iob.vhd Index: bpgen/bp_rs232_2l4l_iob.vbom =================================================================== --- bpgen/bp_rs232_2l4l_iob.vbom (nonexistent) +++ bpgen/bp_rs232_2l4l_iob.vbom (revision 24) @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +bpgenlib.vbom +# components +bp_rs232_2line_iob.vbom +bp_rs232_4line_iob.vbom +# design +bp_rs232_2l4l_iob.vhd Index: bpgen/sn_4x7segctl.vbom =================================================================== --- bpgen/sn_4x7segctl.vbom (nonexistent) +++ bpgen/sn_4x7segctl.vbom (revision 24) @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +sn_4x7segctl.vhd Index: bpgen/sn_humanio_rbus.vbom =================================================================== --- bpgen/sn_humanio_rbus.vbom (nonexistent) +++ bpgen/sn_humanio_rbus.vbom (revision 24) @@ -0,0 +1,8 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +bpgenlib.vbom +# components +sn_humanio.vbom +# design +sn_humanio_rbus.vhd Index: bpgen =================================================================== --- bpgen (nonexistent) +++ bpgen (revision 24)
bpgen Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: atlys/atlys_time_fx2_ic.ucf =================================================================== --- atlys/atlys_time_fx2_ic.ucf (nonexistent) +++ atlys/atlys_time_fx2_ic.ucf (revision 24) @@ -0,0 +1,18 @@ +## $Id: atlys_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-05 537 1.1 add VALID for hold time check +## 2013-01-05 471 1.0 Initial version (copied from nexys3) +## +## timing rules for a 30 MHz internal clock design: +## Period: 30 MHz +## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns +## clk->out < 33.3-18.7 = 14.6 ns +## --> use 10 ns +## + +NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK"; +TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %; +OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK"; +OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK"; Index: atlys/atlys_pins_fx2.ucf =================================================================== --- atlys/atlys_pins_fx2.ucf (nonexistent) +++ atlys/atlys_pins_fx2.ucf (revision 24) @@ -0,0 +1,36 @@ +## $Id: atlys_pins_fx2.ucf 471 2013-01-05 19:46:38Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-01-05 471 1.0 Initial version +## +## Cypress EZ-USB FX2 Interface -- in Bank 0 --------------------------------- +## +## +NET "I_FX2_IFCLK" LOC = "c10" | IOSTANDARD=LVCMOS33; +## +NET "IO_FX2_DATA<0>" LOC = "a2" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<1>" LOC = "d6" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<2>" LOC = "c6" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<3>" LOC = "b3" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<4>" LOC = "a3" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<5>" LOC = "b4" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<6>" LOC = "a4" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<7>" LOC = "c5" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER; +## +NET "O_FX2_SLWR_N" LOC = "e13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLRD_N" LOC = "f13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLOE_N" LOC = "a15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_PKTEND_N" LOC = "c4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_FIFO<0>" LOC = "a14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_FIFO<1>" LOC = "b14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +## assume that PA.7 is used as FLAGD (and not as SLCS#) +NET "I_FX2_FLAG<0>" LOC = "b9" | IOSTANDARD=LVCMOS33; ## flag a (program) +NET "I_FX2_FLAG<1>" LOC = "a9" | IOSTANDARD=LVCMOS33; ## flag b (full) +NET "I_FX2_FLAG<2>" LOC = "c15" | IOSTANDARD=LVCMOS33; ## flag c (empty) +NET "I_FX2_FLAG<3>" LOC = "b2" | IOSTANDARD=LVCMOS33; ## flag d (slcs) +## Index: atlys/atlys_pins_pmod.ucf =================================================================== --- atlys/atlys_pins_pmod.ucf (nonexistent) +++ atlys/atlys_pins_pmod.ucf (revision 24) @@ -0,0 +1,25 @@ +## $Id: atlys_pins_pmod.ucf 403 2011-08-06 17:36:22Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-08-06 403 1.0 Initial version +## +## Pmod connectors ----------------------------------------------------------- +## +## front view (towards PCB edge): +## +## +-------------------------+ +## | VCC GND P-4 P-3 P-2 P-1 | +## | VCC GND P10 P-9 P-8 P-7 | +## ============================= +## < HDMI connector> +## +## Pmod A (top: 0-3; bot: 4-7; all 8 shared with HDMI Type D connector...) +NET "IO_PMODA<0>" LOC = "t3" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<1>" LOC = "r3" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<2>" LOC = "p6" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<3>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<4>" LOC = "v9" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<5>" LOC = "t9" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<6>" LOC = "v4" | IOSTANDARD=LVCMOS33; +NET "IO_PMODA<7>" LOC = "t4" | IOSTANDARD=LVCMOS33; Index: atlys/atlys_pins.ucf =================================================================== --- atlys/atlys_pins.ucf (nonexistent) +++ atlys/atlys_pins.ucf (revision 24) @@ -0,0 +1,61 @@ +## $Id: atlys_pins.ucf 414 2011-10-11 19:38:12Z mueller $ +## +## Pin locks for Atlys core functionality +## - USB UART +## - human I/O (switches, buttons, leds) +## +## Revision History: +## Date Rev Version Comment +## 2011-10-10 413 1.0.2 new BTN sequence: clockwise(U-R-D-L) - mid - reset +## 2011-08-05 403 1.0.1 Fix IOSTANDARD typos; rename _GPIO_ to _HIO_ +## 2011-08-04 402 1.0 Initial version +## +## Notes: +## - Bank 0+1 are 3V3; Bank 2 switchable 3V3 or 2V5; Bank 3 is 1V8 (DDR mem) +## - default is DRIVE=12 | SLEW=SLOW +## - pin names from Digilent master AtlysGeneralUCF.zip are given as comments +## +## clocks -------------------------------------------------------------------- +## AtlysGeneralUCF: clk +## +NET "I_CLK100" LOC = "l15" | IOSTANDARD=LVCMOS25; +## +## USB UART interface -------------------------------------------------------- +## AtlysGeneralUCF: UartRx, UartTx (crossed!) +## +NET "I_USB_RXD" LOC = "a16" | IOSTANDARD=LVCMOS33; +NET "O_USB_TXD" LOC = "b16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## SWIs ---------------------------------------------------------------------- +## AtlysGeneralUCF: sw<0:7> +## +NET "I_HIO_SWI<0>" LOC = "a10" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<1>" LOC = "d14" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<2>" LOC = "c14" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<3>" LOC = "p15" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<4>" LOC = "p12" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<5>" LOC = "r5" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<6>" LOC = "t5" | IOSTANDARD=LVCMOS33; +NET "I_HIO_SWI<7>" LOC = "e4" | IOSTANDARD=LVCMOS33; +## +## BTNs ---------------------------------------------------------------------- +## AtlysGeneralUCF: btn<0:5>; clockwise(U-R-D-L) - middle - reset +## +NET "I_HIO_BTN<0>" LOC = "n4" | IOSTANDARD=LVCMOS18; # BTNU +NET "I_HIO_BTN<1>" LOC = "f6" | IOSTANDARD=LVCMOS18; # BTNR +NET "I_HIO_BTN<2>" LOC = "p3" | IOSTANDARD=LVCMOS18; # BTND +NET "I_HIO_BTN<3>" LOC = "p4" | IOSTANDARD=LVCMOS18; # BTNL +NET "I_HIO_BTN<4>" LOC = "f5" | IOSTANDARD=LVCMOS18; # BTNC +NET "I_HIO_BTN<5>" LOC = "t15" | IOSTANDARD=LVCMOS18; # RESET (act.low!!) +## +## LEDs ---------------------------------------------------------------------- +## AtlysGeneralUCF: Led<0:7> +## +NET "O_HIO_LED<0>" LOC = "u18" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<1>" LOC = "m14" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<2>" LOC = "n14" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<3>" LOC = "l14" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<4>" LOC = "m13" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<5>" LOC = "d4" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<6>" LOC = "p16" | IOSTANDARD=LVCMOS33; +NET "O_HIO_LED<7>" LOC = "n12" | IOSTANDARD=LVCMOS33; Index: atlys/atlys_pins_pma0_rs232.ucf =================================================================== --- atlys/atlys_pins_pma0_rs232.ucf (nonexistent) +++ atlys/atlys_pins_pma0_rs232.ucf (revision 24) @@ -0,0 +1,23 @@ +## $Id: atlys_pins_pma0_rs232.ucf 403 2011-08-06 17:36:22Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-08-06 403 1.0 Initial version +## +## Pmod connector A top / usage RS232 for FTDI USB serport ------------------- +## +## front view (towards PCB edge): +## +## P-6 P-1 +## | | +## +-------------------------+ +## | VCC GND TXD RXD CTS RTS | +## | VCC GND ... ... ... ... | +## ============================= +## < HDMI connector> +## +## +NET "O_FUSP_RTS_N" LOC = "t3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "r3" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "p6" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "n5" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; Index: atlys =================================================================== --- atlys (nonexistent) +++ atlys (revision 24)
atlys Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: nxcramlib/tb/Makefile =================================================================== --- nxcramlib/tb/Makefile (nonexistent) +++ nxcramlib/tb/Makefile (revision 24) @@ -0,0 +1,33 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-26 433 1.0 Initial version (cloned) +# +EXE_all = tb_nx_cram_memctl_as +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: nxcramlib/tb/tb_nx_cram_memctl.vbom =================================================================== --- nxcramlib/tb/tb_nx_cram_memctl.vbom (nonexistent) +++ nxcramlib/tb/tb_nx_cram_memctl.vbom (revision 24) @@ -0,0 +1,15 @@ +# Not meant for direct top level usage. Used with +# tb_nx_cram_memctl_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simlib.vhd +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../micron/mt45w8mw16b.vbom +${uut := tbd_nx_cram_memctl_as.vbom} +# design +tb_nx_cram_memctl.vhd +@top:tb_nx_cram_memctl Index: nxcramlib/tb/tb_nx_cram_memctl.vhd =================================================================== --- nxcramlib/tb/tb_nx_cram_memctl.vhd (nonexistent) +++ nxcramlib/tb/tb_nx_cram_memctl.vhd (revision 24) @@ -0,0 +1,376 @@ +-- $Id: tb_nx_cram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nx_cram_memctl - sim +-- Description: Test bench for nx_cram_memctl +-- +-- Dependencies: vlib/simlib/simclk +-- vlib/simlib/simclkcnt +-- bplib/micron/mt45w8mw16b +-- tbd_nx_cram_memctl [UUT, abstact] +-- +-- To test: nx_cram_memctl_as (via tbd_nx_cram_memctl_as) +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.4 use new simclk/simclkcnt +-- 2011-11-26 433 1.3 renamed from tb_n2_cram_memctl +-- 2011-11-21 432 1.2 now numeric_std clean; update O_FLA_CE_N usage +-- 2010-05-30 297 1.1 use abstact uut tbd_nx_cram_memctl +-- 2010-05-23 293 1.0 Initial version (derived from tb_s3_sram_memctl) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; + +entity tb_nx_cram_memctl is +end tb_nx_cram_memctl; + +architecture sim of tb_nx_cram_memctl is + +component tbd_nx_cram_memctl is -- CRAM driver (abstract) [tb design] + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv22; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end component; + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal REQ : slbit := '0'; + signal WE : slbit := '0'; + signal BUSY : slbit := '0'; + signal ACK_R : slbit := '0'; + signal ACK_W : slbit := '0'; + signal ACT_R : slbit := '0'; + signal ACT_W : slbit := '0'; + signal ADDR : slv22 := (others=>'0'); + signal BE : slv4 := (others=>'0'); + signal DI : slv32 := (others=>'0'); + signal DO : slv32 := (others=>'0'); + signal O_MEM_CE_N : slbit := '0'; + signal O_MEM_BE_N : slv2 := (others=>'0'); + signal O_MEM_WE_N : slbit := '0'; + signal O_MEM_OE_N : slbit := '0'; + signal O_MEM_ADV_N : slbit := '0'; + signal O_MEM_CLK : slbit := '0'; + signal O_MEM_CRE : slbit := '0'; + signal I_MEM_WAIT : slbit := '0'; + signal O_MEM_ADDR : slv23 := (others=>'0'); + signal IO_MEM_DATA : slv16 := (others=>'0'); + + signal R_MEMON : slbit := '0'; + signal N_CHK_DATA : slbit := '0'; + signal N_REF_DATA : slv32 := (others=>'0'); + signal N_REF_ADDR : slv22 := (others=>'0'); + signal R_CHK_DATA_AL : slbit := '0'; + signal R_REF_DATA_AL : slv32 := (others=>'0'); + signal R_REF_ADDR_AL : slv22 := (others=>'0'); + signal R_CHK_DATA_DL : slbit := '0'; + signal R_REF_DATA_DL : slv32 := (others=>'0'); + signal R_REF_ADDR_DL : slv22 := (others=>'0'); + + signal CLK_STOP : slbit := '0'; + signal CLK_CYCLE : integer := 0; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant setup_time : time := 7.5 ns; -- compatible ucf for + constant c2out_time : time := 12.0 ns; -- tbd_nx_cram_memctl_as + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK, + CLK_STOP => CLK_STOP + ); + + CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); + + MEM : entity work.mt45w8mw16b + port map ( + CLK => O_MEM_CLK, + CE_N => O_MEM_CE_N, + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADV_N => O_MEM_ADV_N, + CRE => O_MEM_CRE, + MWAIT => I_MEM_WAIT, + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA + ); + + UUT : tbd_nx_cram_memctl + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR, + BE => BE, + DI => DI, + DO => DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + proc_stim: process + file fstim : text open read_mode is "tb_nx_cram_memctl_stim"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable idelta : integer := 0; + variable iaddr : slv22 := (others=>'0'); + variable idata : slv32 := (others=>'0'); + variable ibe : slv4 := (others=>'0'); + variable ival : slbit := '0'; + variable nbusy : integer := 0; + + begin + + wait for clock_offset - setup_time; + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + if ok then + case dname is + when ".memon" => -- .memon + read_ea(iline, ival); + R_MEMON <= ival; + wait for 2*clock_period; + + when ".reset" => -- .reset + write(oline, string'(".reset")); + writeline(output, oline); + RESET <= '1'; + wait for clock_period; + RESET <= '0'; + wait for 9*clock_period; + + when ".wait " => -- .wait + read_ea(iline, idelta); + wait for idelta*clock_period; + + when "read " => -- read + readgen_ea(iline, iaddr, 16); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + REQ <= '1'; + WE <= '0'; + + writetimestamp(oline, CLK_CYCLE, ": stim read "); + writegen(oline, iaddr, right, 7, 16); + write(oline, string'(" ")); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY='1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + N_CHK_DATA <= '1', '0' after clock_period; + N_REF_DATA <= idata; + N_REF_ADDR <= iaddr; + + wait for clock_period; + REQ <= '0'; + + when "write " => -- write + readgen_ea(iline, iaddr, 16); + read_ea(iline, ibe); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + BE <= ibe; + DI <= idata; + REQ <= '1'; + WE <= '1'; + + writetimestamp(oline, CLK_CYCLE, ": stim write"); + writegen(oline, iaddr, right, 7, 16); + writegen(oline, ibe , right, 5, 2); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + wait for clock_period; + REQ <= '0'; + + when others => -- bad directive + write(oline, string'("?? unknown directive: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + else + report "failed to find command" severity failure; + + end if; + + testempty_ea(iline); + + end loop; -- file fstim + + wait for 10*clock_period; + + writetimestamp(oline, CLK_CYCLE, ": DONE "); + writeline(output, oline); + + CLK_STOP <= '1'; + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if ACK_R = '1' then + writetimestamp(oline, CLK_CYCLE, ": moni "); + writegen(oline, DO, right, 9, 16); + if R_CHK_DATA_DL = '1' then + write(oline, string'(" CHECK")); + if R_REF_DATA_DL = DO then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL, exp=")); + writegen(oline, R_REF_DATA_DL, right, 9, 16); + write(oline, string'(" for a=")); + writegen(oline, R_REF_ADDR_DL, right, 5, 16); + end if; + R_CHK_DATA_DL <= '0'; + end if; + writeline(output, oline); + end if; + + if R_CHK_DATA_AL = '1' then + R_CHK_DATA_DL <= R_CHK_DATA_AL; + R_REF_DATA_DL <= R_REF_DATA_AL; + R_REF_ADDR_DL <= R_REF_ADDR_AL; + R_CHK_DATA_AL <= '0'; + end if; + if N_CHK_DATA = '1' then + R_CHK_DATA_AL <= N_CHK_DATA; + R_REF_DATA_AL <= N_REF_DATA; + R_REF_ADDR_AL <= N_REF_ADDR; + end if; + + end loop; + + end process proc_moni; + + + proc_memon: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if R_MEMON = '1' then + writetimestamp(oline, CLK_CYCLE, ": mem "); + write(oline, string'(" ce=")); + write(oline, not O_MEM_CE_N, right, 2); + write(oline, string'(" be=")); + write(oline, not O_MEM_BE_N, right, 4); + write(oline, string'(" we=")); + write(oline, not O_MEM_WE_N, right); + write(oline, string'(" oe=")); + write(oline, not O_MEM_OE_N, right); + write(oline, string'(" a=")); + writegen(oline, O_MEM_ADDR, right, 6, 16); + write(oline, string'(" d=")); + writegen(oline, IO_MEM_DATA, right, 4, 16); + writeline(output, oline); + end if; + + end loop; + + end process proc_memon; + + +end sim; Index: nxcramlib/tb/tb_nx_cram_memctl_as.vhd =================================================================== --- nxcramlib/tb/tb_nx_cram_memctl_as.vhd (nonexistent) +++ nxcramlib/tb/tb_nx_cram_memctl_as.vhd (revision 24) @@ -0,0 +1,39 @@ +-- $Id: tb_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_nx_cram_memctl_as +-- Description: Configuration tb_nx_cram_memctl_as for tb_nx_cram_memctl +-- +-- Dependencies: tbd_nx_cram_memctl_as +-- To test: nx_cram_memctl_as +-- +-- Verified (with tb_nx_cram_memctl_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2010-05-30 297 - 0.26 11.4 L68 xc3s1200e ok +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.1 renamed from tb_n2_cram_memctl_as +-- 2010-05-30 297 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_nx_cram_memctl_as of tb_nx_cram_memctl is + + for sim + for all :tbd_nx_cram_memctl + use entity work.tbd_nx_cram_memctl_as; + end for; + end for; + +end tb_nx_cram_memctl_as; Index: nxcramlib/tb/tb_nx_cram_memctl_stim.dat =================================================================== --- nxcramlib/tb/tb_nx_cram_memctl_stim.dat (nonexistent) +++ nxcramlib/tb/tb_nx_cram_memctl_stim.dat (revision 24) @@ -0,0 +1,212 @@ +# $Id: tb_nx_cram_memctl_stim.dat 433 2011-11-27 22:04:39Z mueller $ +# +.memon 0 +# +C write full word 16 cells +# +write 000000 1111 30201000 +write 000001 1111 31211101 +write 000002 1111 32221202 +write 000003 1111 33231303 +write 000004 1111 34241404 +write 000005 1111 35251505 +write 000006 1111 36261606 +write 000007 1111 37271707 +write 000008 1111 38281808 +write 000009 1111 39291909 +write 00000a 1111 3a2a1a0a +write 00000b 1111 3b2b1b0b +write 00000c 1111 3c2c1c0c +write 00000d 1111 3d2d1d0d +write 00000e 1111 3e2e1e0e +write 00000f 1111 3f2f1f0f +# +C read 16 cells +# +read 000000 30201000 +read 000001 31211101 +read 000002 32221202 +read 000003 33231303 +read 000004 34241404 +read 000005 35251505 +read 000006 36261606 +read 000007 37271707 +read 000008 38281808 +read 000009 39291909 +read 00000a 3a2a1a0a +read 00000b 3b2b1b0b +read 00000c 3c2c1c0c +read 00000d 3d2d1d0d +read 00000e 3e2e1e0e +read 00000f 3f2f1f0f +# +C write selected bytes in first 16 cells +# +write 000000 0000 70605040 +write 000001 0001 71615141 +write 000002 0010 72625242 +write 000003 0011 73635343 +write 000004 0100 74645444 +write 000005 0101 75655545 +write 000006 0110 76665646 +write 000007 0111 77675747 +write 000008 1000 78685848 +write 000009 1001 79695949 +write 00000a 1010 7a6a5a4a +write 00000b 1011 7b6b5b4b +write 00000c 1100 7c6c5c4c +write 00000d 1101 7d6d5d4d +write 00000e 1110 7e6e5e4e +write 00000f 1111 7f6f5f4f +# +C read back +# +read 000000 30201000 +read 000001 31211141 +read 000002 32225202 +read 000003 33235343 +read 000004 34641404 +read 000005 35651545 +read 000006 36665606 +read 000007 37675747 +read 000008 78281808 +read 000009 79291949 +read 00000a 7a2a5a0a +read 00000b 7b2b5b4b +read 00000c 7c6c1c0c +read 00000d 7d6d1d4d +read 00000e 7e6e5e0e +read 00000f 7f6f5f4f +# +C read and write with waits +# +.wait 12 +write 000010 1111 30201000 +.wait 11 +write 000011 1111 31211101 +.wait 10 +write 000012 1111 32221202 +.wait 9 +write 000013 1111 33231303 +.wait 8 +write 000014 1111 34241404 +.wait 7 +write 000015 1111 35251505 +.wait 6 +write 000016 1111 36261606 +.wait 5 +write 000017 1111 37271707 +.wait 4 +write 000018 1111 38281808 +.wait 3 +write 000019 1111 39291909 +.wait 2 +write 00001a 1111 3a2a1a0a +.wait 1 +write 00001b 1111 3b2b1b0b +write 00001c 1111 3b2b1b0b +# +.wait 12 +read 000010 30201000 +.wait 11 +read 000011 31211101 +.wait 10 +read 000012 32221202 +.wait 9 +read 000013 33231303 +.wait 8 +read 000014 34241404 +.wait 7 +read 000015 35251505 +.wait 6 +read 000016 36261606 +.wait 5 +read 000017 37271707 +.wait 4 +read 000018 38281808 +.wait 3 +read 000019 39291909 +.wait 2 +read 00001a 3a2a1a0a +.wait 1 +read 00000e 7e6e5e0e +read 00000f 7f6f5f4f +# +C read and write mixed, with waits +# +.wait 2 +write 000014 1111 34241404 +.wait 2 +read 000012 32221202 +.wait 2 +write 000015 1111 35251505 +.wait 2 +read 000013 33231303 +# +.wait 1 +write 000016 1111 36261606 +.wait 1 +read 000014 34241404 +.wait 1 +write 000017 1111 37271707 +.wait 1 +read 000015 35251505 +# +write 000018 1111 38281808 +read 000016 36261606 +write 000019 1111 39291909 +read 000017 37271707 +# +.wait 2 +write 00001a 1111 3a2a1a0a +write 00001b 1111 3b2b1b0b +.wait 2 +read 000018 38281808 +read 000019 39291909 +.wait 2 +write 00001c 1111 3c2c1c0c +write 00001d 1111 3d2d1d0d +.wait 2 +read 00001a 3a2a1a0a +read 00001b 3b2b1b0b +# +.wait 1 +write 00001e 1111 3e2e1e0e +write 00001f 1111 3f2f1f0f +.wait 1 +read 00001c 3c2c1c0c +read 00001d 3d2d1d0d +.wait 1 +write 000014 0100 74645444 +write 000015 0101 75655545 +.wait 1 +read 00001e 3e2e1e0e +read 00001f 3f2f1f0f +# +write 000016 0110 76665646 +write 000017 0111 77675747 +read 000010 30201000 +read 000011 31211101 +write 000018 1000 78685848 +write 000019 1001 79695949 +read 000012 32221202 +read 000013 33231303 +# +write 00001a 1010 7a6a5a4a +write 00001b 1011 7b6b5b4b +write 00001c 1100 7c6c5c4c +read 000014 34641404 +read 000015 35651545 +read 000016 36665606 +write 00001d 1101 7d6d5d4d +write 00001e 1110 7e6e5e4e +write 00001f 1111 7f6f5f4f +read 000017 37675747 +read 000018 78281808 +read 000019 79291949 +read 00001a 7a2a5a0a +read 00001b 7b2b5b4b +read 00001c 7c6c1c0c +read 00001d 7d6d1d4d +read 00001e 7e6e5e0e +read 00001f 7f6f5f4f Index: nxcramlib/tb/tb_nx_cram_memctl_as.vbom =================================================================== --- nxcramlib/tb/tb_nx_cram_memctl_as.vbom (nonexistent) +++ nxcramlib/tb/tb_nx_cram_memctl_as.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure tb_nx_cram_memctl with tbd_nx_cram_memctl_as target; +# use vhdl configure file (tb_nx_cram_memctl_as.vhd) to allow +# that all configurations will co-exist in work library +uut = tbd_nx_cram_memctl_as.vbom +tb_nx_cram_memctl.vbom +tb_nx_cram_memctl_as.vhd Index: nxcramlib/tb/tbw.dat =================================================================== --- nxcramlib/tb/tbw.dat (nonexistent) +++ nxcramlib/tb/tbw.dat (revision 24) @@ -0,0 +1,4 @@ +# $Id: tbw.dat 433 2011-11-27 22:04:39Z mueller $ +# +[tb_nx_cram_memctl_as] +tb_nx_cram_memctl_stim = tb_nx_cram_memctl_stim.dat Index: nxcramlib/tb/tbd_nx_cram_memctl_as.vhd =================================================================== --- nxcramlib/tb/tbd_nx_cram_memctl_as.vhd (nonexistent) +++ nxcramlib/tb/tbd_nx_cram_memctl_as.vhd (revision 24) @@ -0,0 +1,121 @@ +-- $Id: tbd_nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tbd_nx_cram_memctl_as - syn +-- Description: Wrapper for nx_cram_memctl_as to avoid records & generics. +-- It has a port interface which will not be modified by xst +-- synthesis (no records, no generic port). +-- +-- Dependencies: nx_cram_memctl_as +-- To test: nx_cram_memctl_as +-- +-- Target Devices: generic +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 122 0 107 t 11.4 +-- 2010-05-30 297 11.4 L68 xc3s1200e-4 91 99 0 95 t 13.1 +-- +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.2 renamed from tbd_n2_cram_memctl_as +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port from n2_cram_memctl +-- 2010-06-03 298 1.0.1 add hack to force IOB'FFs to O_MEM_ADDR +-- 2010-05-30 297 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.nxcramlib.all; + +entity tbd_nx_cram_memctl_as is -- CRAM driver (async mode) [tb design] + -- generic: READ0=2;READ1=2;WRITE=3 + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv22; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end tbd_nx_cram_memctl_as; + + +architecture syn of tbd_nx_cram_memctl_as is + + signal ADDR_X : slv22 := (others=>'0'); + +begin + + -- Note: This is a HACk to ensure that the IOB flops are on the O_MEM_ADDR + -- pins. Without par might choose to use IFF's on ADDR, causing varying + -- routing delays to O_MEM_ADDR. Didn't find a better way, setting + -- iob "false" attributes in ADDR didn't help. + -- This logic doesn't hurt, and prevents that IFFs for ADDR compete with + -- OFF's for O_MEM_ADDR. + + ADDR_X <= ADDR when RESET='0' else (others=>'0'); + + MEMCTL : nx_cram_memctl_as + generic map ( + READ0DELAY => 2, + READ1DELAY => 2, + WRITEDELAY => 3) + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR_X, + BE => BE, + DI => DI, + DO => DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; Index: nxcramlib/tb/tbd_nx_cram_memctl_as.vbom =================================================================== --- nxcramlib/tb/tbd_nx_cram_memctl_as.vbom (nonexistent) +++ nxcramlib/tb/tbd_nx_cram_memctl_as.vbom (revision 24) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../nxcramlib.vhd +# components +../nx_cram_memctl_as.vbom +# design +tbd_nx_cram_memctl_as.vhd Index: nxcramlib/tb/.cvsignore =================================================================== --- nxcramlib/tb/.cvsignore (nonexistent) +++ nxcramlib/tb/.cvsignore (revision 24) @@ -0,0 +1,5 @@ +tb_nx_cram_memctl_as +tb_nx_cram_memctl_as_[sft]sim +tb_nx_cram_memctl_as_ISim +tb_nx_cram_memctl_as_ISim_[sft]sim +tb_nx_cram_memctl_stim Index: nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom =================================================================== --- nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom (nonexistent) +++ nxcramlib/tb/tb_nx_cram_memctl_as_ssim.vbom (revision 24) @@ -0,0 +1,5 @@ +# configure for _*sim case +# +uut = tbd_nx_cram_memctl_as_ssim.vhd +tb_nx_cram_memctl_as.vbom +@top:tb_nx_cram_memctl_as Index: nxcramlib/tb =================================================================== --- nxcramlib/tb (nonexistent) +++ nxcramlib/tb (revision 24)
nxcramlib/tb Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nx_cram_memctl_as +tb_nx_cram_memctl_as_[sft]sim +tb_nx_cram_memctl_as_ISim +tb_nx_cram_memctl_as_ISim_[sft]sim +tb_nx_cram_memctl_stim Index: nxcramlib/Makefile =================================================================== --- nxcramlib/Makefile (nonexistent) +++ nxcramlib/Makefile (revision 24) @@ -0,0 +1,25 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-26 433 1.0 Initial version (cloned..) +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: nxcramlib/nxcramlib.vhd =================================================================== --- nxcramlib/nxcramlib.vhd (nonexistent) +++ nxcramlib/nxcramlib.vhd (revision 24) @@ -0,0 +1,80 @@ +-- $Id: nxcramlib.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nxcramlib +-- Description: Nexys 2/3 CRAM drivers +-- +-- Dependencies: - +-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.0 Initial version (extracted from nexys2lib) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nxcramlib is + +component nx_cram_dummy is -- CRAM protection dummy + port ( + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end component; + +component nx_cram_memctl_as is -- CRAM driver (async+page mode) + generic ( + READ0DELAY : positive := 2; -- read word 0 delay in clock cycles + READ1DELAY : positive := 2; -- read word 1 delay in clock cycles + WRITEDELAY : positive := 3); -- write delay in clock cycles + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv22; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end component; + +end package nxcramlib; Index: nxcramlib/nx_cram_dummy.vhd =================================================================== --- nxcramlib/nx_cram_dummy.vhd (nonexistent) +++ nxcramlib/nx_cram_dummy.vhd (revision 24) @@ -0,0 +1,64 @@ +-- $Id: nx_cram_dummy.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: nx_cram_dummy - syn +-- Description: nexys2/3: CRAM protection dummy +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.2 renamed from n2_cram_dummy +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port +-- 2010-05-28 295 1.0.1 use _ADV_N +-- 2010-05-21 292 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity nx_cram_dummy is -- CRAM protection dummy + port ( + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end nx_cram_dummy; + + +architecture syn of nx_cram_dummy is +begin + + O_MEM_CE_N <= '1'; -- disable cram chip + O_MEM_BE_N <= "11"; + O_MEM_WE_N <= '1'; + O_MEM_OE_N <= '1'; + O_MEM_ADV_N <= '1'; + O_MEM_CLK <= '0'; + O_MEM_CRE <= '0'; + O_MEM_ADDR <= (others=>'0'); + IO_MEM_DATA <= (others=>'0'); + +end syn; Index: nxcramlib/nx_cram_dummy.vbom =================================================================== --- nxcramlib/nx_cram_dummy.vbom (nonexistent) +++ nxcramlib/nx_cram_dummy.vbom (revision 24) @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +nx_cram_dummy.vhd Index: nxcramlib/nx_cram_memctl_as.vhd =================================================================== --- nxcramlib/nx_cram_memctl_as.vhd (nonexistent) +++ nxcramlib/nx_cram_memctl_as.vhd (revision 24) @@ -0,0 +1,587 @@ +-- $Id: nx_cram_memctl_as.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: nx_cram_memctl_as - syn +-- Description: nexys2/3: CRAM driver - async and page mode +-- +-- Dependencies: vlib/xlib/iob_reg_o +-- vlib/xlib/iob_reg_o_gen +-- vlib/xlib/iob_reg_io_gen +-- Test bench: tb/tb_nx_cram_memctl_as +-- sys_gen/tst_sram/nexys2/tb/tb_tst_sram_n2 +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-06-03 299 11.4 L68 xc3s1200e-4 91 100 0 96 s 6.7 +-- 2010-05-24 294 11.4 L68 xc3s1200e-4 91 99 0 95 s 6.7 +-- 2010-05-23 293 11.4 L68 xc3s1200e-4 91 139 0 99 s 6.7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.2 renamed from n2_cram_memctl_as +-- 2011-11-19 432 1.1 remove O_FLA_CE_N port +-- 2011-11-19 427 1.0.5 now numeric_std clean +-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics +-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read +-- cycle; +-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic +-- 2010-05-24 294 1.0.1 more compact n.memdi logic; extra wait in s_rdwait1 +-- 2010-05-23 293 1.0 Initial version +-- +-- Notes: +-- 1. READ1DELAY of 2 is needed even though the timing of the memory suggests +-- that 1 cycle is enough (T_apa is 20 ns, so 40 ns round trip is ok). A +-- short READ1 delay works in sim, but not on fpga where the data od the +-- ADDR(0)=0 cycle is re-read (see notes_tst_sram_n2.txt). +-- tb_n2_cram_memctl_as_ISim_tsim works with full sdf even when T_apa is +-- 40ns or 50 ns, only T_apa 60 ns fails ! +-- Unclear what is wrong here, the timing of the memory model seems ok. +-- 2. There is no 'bus-turn-around' cycle needed for a write->read change +-- FPGA_OE goes 1->0 and MEM_OE goes 0->1 on the s_wrput1->s_rdinit +-- transition simultaneously. The FPGA will go high-Z quickly, the memory +-- low-Z delay by the IOB and internal memory delays. No clash. +-- 3. There is a hidden 'bus-turn-around' cycle for a read->write change. +-- MEM_OE goes 1->0 on s_rdget1->s_wrinit and the memory will go high-z with +-- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0. +-- Again no clash due to the 1 cycle delay. +-- +-- Nominal timings: +-- READ0/1 = N_rd_cycle - 2 +-- WRITE = N_wr_cycle - 1 +-- +-- from notes_nexys2.txt (Rev 339): +-- clksys RD WR < use for > Test case +-- MHz div mul +-- <51.20 2 3 <-- 50 50 1 1 +-- 51.20- 54.80 3 3 <-- 52,54 54 25 27 +-- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32 +-- 64.10- 68.50 4 4 <-- 65 65 10 13 +-- 68.50- 76.92 4 5 <-- 70,75 75 2 3 +-- 76.92- 82.19 5 5 <-- 80 80 5 8 +-- 82.19- 89.74 5 6 <-- 85 85 10 17 +-- 89.74- 95.89 6 6 <-- 90,95 95 10 19 +-- 95.89-102.56 6 7 <-- 100 100 1 2 +-- +-- Timing of some signals: +-- +-- single read request: +-- +-- state |_idle |_rdinit|_rdwt0 |_rdwt0 |_rdget0|_rdwt1 |_rdget1| +-- 0 20 40 60 80 100 120 +-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___| +-- +-- REQ _______|^^^^^|_____________________________________________ +-- WE ___________________________________________________________ +-- +-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_ +-- IOB_OE _________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_ +-- +-- DO oooooooooooooooooooooooooooooooooooooooooo|lllllll|lllllll|h +-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|________________ +-- ACK_R ___________________________________________________________|^^^^^^^|_ +-- +-- single write request: +-- +-- state |_idle |_wrinit|_wrwt0 |_wrwt0 |_wrwt0 |_wrput0|_idle | +-- 0 20 40 60 80 100 120 +-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___|^^^|___| +-- +-- REQ _______|^^^^^|______________________________________ +-- WE _______|^^^^^|______________________________________ +-- +-- IOB_CE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_ +-- IOB_BE __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_ +-- IOB_OE ____________________________________________________ +-- IOB_WE ______________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_____ +-- +-- BUSY __________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^|_________ +-- ACK_W __________________________________________|^^^^^^^|_ +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; + +entity nx_cram_memctl_as is -- CRAM driver (async+page mode) + generic ( + READ0DELAY : positive := 2; -- read word 0 delay in clock cycles + READ1DELAY : positive := 2; -- read word 1 delay in clock cycles + WRITEDELAY : positive := 3); -- write delay in clock cycles + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv22; -- address (32 bit word address) + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end nx_cram_memctl_as; + + +architecture syn of nx_cram_memctl_as is + + type state_type is ( + s_idle, -- s_idle: wait for req + s_rdinit, -- s_rdinit: read init cycle + s_rdwait0, -- s_rdwait0: read wait low word + s_rdget0, -- s_rdget0: read get low word + s_rdwait1, -- s_rdwait1: read wait high word + s_rdget1, -- s_rdget1: read get high word + s_wrinit, -- s_wrinit: write init cycle + s_wrwait0, -- s_rdwait0: write wait 1st word + s_wrput0, -- s_rdput0: write put 1st word + s_wrini1, -- s_wrini1: write init 2nd word + s_wrwait1, -- s_wrwait1: write wait 2nd word + s_wrput1 -- s_wrput1: write put 2nd word + ); + + type regs_type is record + state : state_type; -- state + ackr : slbit; -- signal ack_r + addr0 : slbit; -- current addr0 + be2nd : slv2; -- be's of 2nd write cycle + cntdly : slv3; -- wait delay counter + cntce : slv7; -- ce counter + fidle : slbit; -- force idle flag + memdo0 : slv16; -- mem data out, low word + memdi : slv32; -- mem data in + end record regs_type; + + constant regs_init : regs_type := ( + s_idle, -- + '0', -- ackr + '0', -- addr0 + "00", -- be2nd + (others=>'0'), -- cntdly + (others=>'0'), -- cntce + '0', -- fidle + (others=>'0'), -- memdo0 + (others=>'0') -- memdi + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal CLK_180 : slbit := '0'; + signal MEM_CE_N : slbit := '1'; + signal MEM_BE_N : slv2 := "11"; + signal MEM_WE_N : slbit := '1'; + signal MEM_OE_N : slbit := '1'; + signal BE_CE : slbit := '0'; + signal ADDRH_CE : slbit := '0'; + signal ADDR0_CE : slbit := '0'; + signal ADDR0 : slbit := '0'; + signal DATA_CEI : slbit := '0'; + signal DATA_CEO : slbit := '0'; + signal DATA_OE : slbit := '0'; + signal MEM_DO : slv16 := (others=>'0'); + signal MEM_DI : slv16 := (others=>'0'); + +-- these attributes aren't accepted by ghdl 0.26 +-- attribute s : string; +-- attribute s of I_MEM_WAIT : signal is "true"; + +begin + + assert READ0DELAY<=2**R_REGS.cntdly'length and + READ1DELAY<=2**R_REGS.cntdly'length and + WRITEDELAY<=2**R_REGS.cntdly'length + report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)" + severity failure; + + CLK_180 <= not CLK; + + IOB_MEM_CE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_CE_N, + PAD => O_MEM_CE_N + ); + + IOB_MEM_BE : iob_reg_o_gen + generic map ( + DWIDTH => 2, + INIT => '1') + port map ( + CLK => CLK, + CE => BE_CE, + DO => MEM_BE_N, + PAD => O_MEM_BE_N + ); + + IOB_MEM_WE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK_180, + CE => '1', + DO => MEM_WE_N, + PAD => O_MEM_WE_N + ); + + IOB_MEM_OE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_OE_N, + PAD => O_MEM_OE_N + ); + + IOB_MEM_ADDRH : iob_reg_o_gen + generic map ( + DWIDTH => 22) + port map ( + CLK => CLK, + CE => ADDRH_CE, + DO => ADDR, + PAD => O_MEM_ADDR(22 downto 1) + ); + + IOB_MEM_ADDR0 : iob_reg_o + port map ( + CLK => CLK, + CE => ADDR0_CE, + DO => ADDR0, + PAD => O_MEM_ADDR(0) + ); + + IOB_MEM_DATA : iob_reg_io_gen + generic map ( + DWIDTH => 16, + PULL => "KEEP") + port map ( + CLK => CLK, + CEI => DATA_CEI, + CEO => DATA_CEO, + OE => DATA_OE, + DI => MEM_DO, + DO => MEM_DI, + PAD => IO_MEM_DATA + ); + + O_MEM_ADV_N <= '0'; + O_MEM_CLK <= '0'; + O_MEM_CRE <= '0'; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, REQ, WE, BE, DI, MEM_DO) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibusy : slbit := '0'; + variable iackw : slbit := '0'; + variable iactr : slbit := '0'; + variable iactw : slbit := '0'; + variable imem_ce : slbit := '0'; + variable imem_be : slv2 := "00"; + variable imem_we : slbit := '0'; + variable imem_oe : slbit := '0'; + variable ibe_ce : slbit := '0'; + variable iaddrh_ce : slbit := '0'; + variable iaddr0_ce : slbit := '0'; + variable iaddr0 : slbit := '0'; + variable idata_cei : slbit := '0'; + variable idata_ceo : slbit := '0'; + variable idata_oe : slbit := '0'; + + procedure do_dispatch(nstate : out state_type; + iaddrh_ce : out slbit; + iaddr0_ce : out slbit; + iaddr0 : out slbit; + ibe_ce : out slbit; + imem_be : out slv2; + imem_ce : out slbit; + imem_oe : out slbit; + nbe2nd : out slv2) is + begin + iaddrh_ce := '1'; -- latch address (high part) + iaddr0_ce := '1'; -- latch address 0 bit + ibe_ce := '1'; -- latch be's + imem_ce := '1'; -- ce CRAM next cycle + nbe2nd := "00"; -- assume no 2nd write cycle + if WE = '0' then -- if READ requested + iaddr0 := '0'; -- go first for low word + imem_be := "11"; -- on read always on + imem_oe := '1'; -- oe CRAM next cycle + nstate := s_rdinit; -- next: read init part + else -- if WRITE requested + if BE(1 downto 0) /= "00" then -- low word write + iaddr0 := '0'; -- access word 0 + imem_be := BE(1 downto 0); -- set be's for 1st cycle + nbe2nd := BE(3 downto 2); -- keep be's for 2nd cycle + else -- high word write + iaddr0 := '1'; -- access word 1 + imem_be := BE(3 downto 2); -- set be's for 1st cycle + end if; + nstate := s_wrinit; -- next: write init part + end if; + end procedure do_dispatch; + + begin + + r := R_REGS; + n := R_REGS; + n.ackr := '0'; + + ibusy := '0'; + iackw := '0'; + iactr := '0'; + iactw := '0'; + + imem_ce := '0'; + imem_be := "11"; + imem_we := '0'; + imem_oe := '0'; + ibe_ce := '0'; + iaddrh_ce := '0'; + iaddr0_ce := '0'; + iaddr0 := '0'; + idata_cei := '0'; + idata_ceo := '0'; + idata_oe := '0'; + + if unsigned(r.cntdly) /= 0 then + n.cntdly := slv(unsigned(r.cntdly) - 1); + end if; + + case r.state is + when s_idle => -- s_idle: wait for req + if REQ = '1' then -- if IO requested + do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0, + ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd); + end if; + + when s_rdinit => -- s_rdinit: read init cycle + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := '1'; -- ce CRAM next cycle + imem_oe := '1'; -- oe CRAM next cycle + n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length)); + n.state := s_rdwait0; -- next: wait + + when s_rdwait0 => -- s_rdwait0: read wait low word + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := '1'; -- ce CRAM next cycle + imem_oe := '1'; -- oe CRAM next cycle + if unsigned(r.cntdly) = 0 then -- wait expired ? + n.state := s_rdget0; -- next: get low word + end if; + + when s_rdget0 => -- s_rdget0: read get low word + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := '1'; -- ce CRAM next cycle + imem_oe := '1'; -- oe CRAM next cycle + idata_cei := '1'; -- latch input data + iaddr0_ce := '1'; -- latch address 0 bit + iaddr0 := '1'; -- now go for high word + n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length)); + n.state := s_rdwait1; -- next: wait high word + + when s_rdwait1 => -- s_rdwait1: read wait high word + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := '1'; -- ce CRAM next cycle + imem_oe := '1'; -- oe CRAM next cycle + if unsigned(r.cntdly) = 0 then -- wait expired ? + n.state := s_rdget1; -- next: get low word + end if; -- + + when s_rdget1 => -- s_rdget1: read get high word + iactr := '1'; -- signal mem read + n.memdo0:= MEM_DO; -- save low word data + idata_cei := '1'; -- latch input data + n.ackr := '1'; -- ACK_R next cycle + n.state := s_idle; -- next: wait next request + if r.fidle = '1' then -- forced idle cycle + ibusy := '1'; -- signal busy, unable to handle req + else + if REQ = '1' then -- if IO requested + do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0, + ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd); + end if; + end if; + + when s_wrinit => -- s_wrinit: write init cycle + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + iackw := '1'; -- signal write done (all latched) + idata_ceo:= '1'; -- latch output data + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := '1'; -- ce CRAM next cycle + imem_we := '1'; -- we CRAM in half cycle + n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length)); + n.state := s_wrwait0; -- next: wait + + when s_wrwait0 => -- s_rdput0: write wait 1st word + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := '1'; -- ce CRAM next cycle + imem_we := '1'; -- we CRAM next cycle + if unsigned(r.cntdly) = 0 then -- wait expired ? + n.state := s_wrput0; -- next: put 1st word + end if; + + when s_wrput0 => -- s_rdput0: write put 1st word + iactw := '1'; -- signal mem write + imem_we := '0'; -- deassert we CRAM in half cycle + if r.be2nd /= "00" then + ibusy := '1'; -- signal busy, unable to handle req + imem_ce := '1'; -- ce CRAM next cycle + iaddr0_ce := '1'; -- latch address 0 bit + iaddr0 := '1'; -- now go for high word + ibe_ce := '1'; -- latch be's + imem_be := r.be2nd; -- now be's of high word + n.state := s_wrini1; -- next: start 2nd write + else + n.state := s_idle; -- next: wait next request + if r.fidle = '1' then -- forced idle cycle + ibusy := '1'; -- signal busy + else + if REQ = '1' then -- if IO requested + do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0, + ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd); + end if; + end if; + end if; + + when s_wrini1 => -- s_wrini1: write init 2nd word + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + idata_ceo:= '1'; -- latch output data + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := '1'; -- ce CRAM next cycle + imem_we := '1'; -- we CRAM in half cycle + n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length)); + n.state := s_wrwait1; -- next: wait + + when s_wrwait1 => -- s_wrwait1: write wait 2nd word + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := '1'; -- ce CRAM next cycle + imem_we := '1'; -- we CRAM next cycle + if unsigned(r.cntdly) = 0 then -- wait expired ? + n.state := s_wrput1; -- next: put 2nd word + end if; + + when s_wrput1 => -- s_wrput1: write put 2nd word + iactw := '1'; -- signal mem write + imem_we := '0'; -- deassert we CRAM in half cycle + n.state := s_idle; -- next: wait next request + if r.fidle = '1' then -- forced idle cycle + ibusy := '1'; -- signal busy, unable to handle req + else + if REQ = '1' then -- if IO requested + do_dispatch(n.state, iaddrh_ce, iaddr0_ce, iaddr0, + ibe_ce, imem_be, imem_ce, imem_oe, n.be2nd); + end if; + end if; + + when others => null; + end case; + + if imem_ce = '0' then -- if cmem not active + n.cntce := (others=>'0'); -- clear counter + n.fidle := '0'; -- clear force idle flag + else -- if cmem active + if unsigned(r.cntce) >= 127 then -- if max ce count expired + n.fidle := '1'; -- set forced idle flag + else -- if max ce count not yet reached + n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter + end if; + end if; + + if iaddrh_ce = '1' then -- if addresses are latched + n.memdi := DI; -- latch data too... + end if; + + if iaddr0_ce = '1' then -- if address bit 0 changed + n.addr0 := iaddr0; -- mirror it in state regs + end if; + + N_REGS <= n; + + MEM_CE_N <= not imem_ce; + MEM_WE_N <= not imem_we; + MEM_BE_N <= not imem_be; + MEM_OE_N <= not imem_oe; + + if r.addr0 = '0' then + MEM_DI <= r.memdi(15 downto 0); + else + MEM_DI <= r.memdi(31 downto 16); + end if; + + BE_CE <= ibe_ce; + ADDRH_CE <= iaddrh_ce; + ADDR0_CE <= iaddr0_ce; + ADDR0 <= iaddr0; + DATA_CEI <= idata_cei; + DATA_CEO <= idata_ceo; + DATA_OE <= idata_oe; + + BUSY <= ibusy; + ACK_R <= r.ackr; + ACK_W <= iackw; + ACT_R <= iactr; + ACT_W <= iactw; + + DO <= MEM_DO & r.memdo0; + + end process proc_next; + +end syn; Index: nxcramlib/nx_cram_memctl_as.vbom =================================================================== --- nxcramlib/nx_cram_memctl_as.vbom (nonexistent) +++ nxcramlib/nx_cram_memctl_as.vbom (revision 24) @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_o.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/xlib/iob_reg_io_gen.vbom +# design +nx_cram_memctl_as.vhd Index: nxcramlib =================================================================== --- nxcramlib (nonexistent) +++ nxcramlib (revision 24)
nxcramlib Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: fx2lib/Makefile =================================================================== --- fx2lib/Makefile (nonexistent) +++ fx2lib/Makefile (revision 24) @@ -0,0 +1,26 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-05-23 293 1.0 Initial version (cloned..) +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: fx2lib/fx2_2fifoctl_ic.vhd =================================================================== --- fx2lib/fx2_2fifoctl_ic.vhd (nonexistent) +++ fx2lib/fx2_2fifoctl_ic.vhd (revision 24) @@ -0,0 +1,566 @@ +-- $Id: fx2_2fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $ +-- +-- Copyright 2012-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: fx2_2fifoctl_ic - syn +-- Description: Cypress EZ-USB FX2 driver (2 fifo; int clk) +-- +-- Dependencies: vlib/xlib/iob_reg_o +-- vlib/xlib/iob_reg_i_gen +-- vlib/xlib/iob_reg_o_gen +-- vlib/xlib/iob_reg_io_gen +-- memlib/fifo_2c_dram +-- +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2013-01-04 469 13.3 O76x xc3s1200e-4 112 172 64 169 s 7.4/7.4 +-- 2012-01-14 453 13.3 O76x xc3s1200e-4 101? 173 64 159 s 8.3/7.4 +-- 2012-01-08 451 13.3 O76x xc3s1200e-4 110 166 64 163 s 7.5 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-04 469 1.2 BUGFIX: redo rx logic, now properly pipelined +-- 2012-01-15 453 1.1 use aempty/afull logic; collapse tx and pe flows +-- 2012-01-09 451 1.0 Initial version +-- 2012-01-01 448 0.5 First draft +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.memlib.all; +use work.fx2lib.all; + +entity fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk) + generic ( + RXFAWIDTH : positive := 5; -- receive fifo address width + TXFAWIDTH : positive := 5; -- transmit fifo address width + PETOWIDTH : positive := 7; -- packet end time-out counter width + CCWIDTH : positive := 5; -- chunk counter width + RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag + TXAFULL_THRES : natural := 1); -- threshold for tx afull flag + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RXDATA : out slv8; -- receive data out + RXVAL : out slbit; -- receive data valid + RXHOLD : in slbit; -- receive data hold + RXAEMPTY : out slbit; -- receive almost empty flag + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit data busy + TXAFULL : out slbit; -- transmit almost full flag + MONI : out fx2ctl_moni_type; -- monitor port data + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end fx2_2fifoctl_ic; + + +architecture syn of fx2_2fifoctl_ic is + + constant c_rxfifo : slv2 := c_fifo_ep4; + constant c_txfifo : slv2 := c_fifo_ep6; + + constant c_flag_prog : integer := 0; + constant c_flag_tx_ff : integer := 1; + constant c_flag_rx_ef : integer := 2; + constant c_flag_tx2_ff : integer := 3; + + type state_type is ( + s_idle, -- s_idle: idle state + s_rxprep0, -- s_rxprep0: switch to rx-fifo + s_rxprep1, -- s_rxprep1: fifo addr setup + s_rxprep2, -- s_rxprep2: wait for flags + s_rxdisp, -- s_rxdisp: read, dispatch + s_rxpipe, -- s_rxpipe: read, pipe wait + s_txprep0, -- s_txprep0: switch to tx-fifo + s_txprep1, -- s_txprep1: fifo addr setup + s_txprep2, -- s_txprep2: wait for flags + s_txdisp -- s_txdisp: write, dispatch + ); + + type regs_type is record + state : state_type; -- state + petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter + pepend : slbit; -- pktend pending + rxpipe1 : slbit; -- read pipe 1: iob capture stage + rxpipe2 : slbit; -- read pipe 2: fifo write stage + ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter + moni_ep4_sel : slbit; -- ep4 (rx) select + moni_ep6_sel : slbit; -- ep6 (tx) select + moni_ep4_pf : slbit; -- ep4 (rx) prog flag + moni_ep6_pf : slbit; -- ep6 (tx) prog flag + end record regs_type; + + constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0'); + constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + s_idle, -- state + petocnt_init, -- petocnt + '0', -- pepend + '0','0', -- rxpipe1, rxpipe2 + ccnt_init, -- ccnt + '0','0', -- moni_ep(4|6)_sel + '0','0' -- moni_ep(4|6)_pf + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal FX2_FIFO : slv2 := (others=>'0'); + signal FX2_FIFO_CE : slbit := '0'; + signal FX2_FLAG_N : slv4 := (others=>'0'); + signal FX2_SLRD_N : slbit := '1'; + signal FX2_SLWR_N : slbit := '1'; + signal FX2_SLOE_N : slbit := '1'; + signal FX2_PKTEND_N : slbit := '1'; + signal FX2_DATA_CEI : slbit := '0'; + signal FX2_DATA_CEO : slbit := '0'; + signal FX2_DATA_OE : slbit := '0'; + + signal RXFIFO_DI : slv8 := (others=>'0'); + signal RXFIFO_ENA : slbit := '0'; + signal RXFIFO_BUSY : slbit := '0'; + signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0'); + signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0'); + signal TXFIFO_DO : slv8 := (others=>'0'); + signal TXFIFO_VAL : slbit := '0'; + signal TXFIFO_HOLD : slbit := '0'; + signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0'); + signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0'); + + signal TXBUSY_L : slbit := '0'; + + signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init; + signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init; + +begin + + assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and + TXAFULL_THRES<=2**TXFAWIDTH-1 + report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1" + severity failure; + + + IOB_FX2_FIFO : iob_reg_o_gen + generic map ( + DWIDTH => 2, + INIT => '0') + port map ( + CLK => I_FX2_IFCLK, + CE => FX2_FIFO_CE, + DO => FX2_FIFO, + PAD => O_FX2_FIFO + ); + + IOB_FX2_FLAG : iob_reg_i_gen + generic map ( + DWIDTH => 4, + INIT => '0') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DI => FX2_FLAG_N, + PAD => I_FX2_FLAG + ); + + IOB_FX2_SLRD : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_SLRD_N, + PAD => O_FX2_SLRD_N + ); + + IOB_FX2_SLWR : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_SLWR_N, + PAD => O_FX2_SLWR_N + ); + + IOB_FX2_SLOE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_SLOE_N, + PAD => O_FX2_SLOE_N + ); + + IOB_FX2_PKTEND : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_PKTEND_N, + PAD => O_FX2_PKTEND_N + ); + + IOB_FX2_DATA : iob_reg_io_gen + generic map ( + DWIDTH => 8, + PULL => "KEEP") + port map ( + CLK => I_FX2_IFCLK, + CEI => FX2_DATA_CEI, + CEO => FX2_DATA_CEO, + OE => FX2_DATA_OE, + DI => RXFIFO_DI, -- input data (read from pad) + DO => TXFIFO_DO, -- output data (write to pad) + PAD => IO_FX2_DATA + ); + + RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based + generic map ( + AWIDTH => RXFAWIDTH, + DWIDTH => 8) + port map ( + CLKW => I_FX2_IFCLK, + CLKR => CLK, + RESETW => '0', + RESETR => RESET, + DI => RXFIFO_DI, + ENA => RXFIFO_ENA, + BUSY => RXFIFO_BUSY, + DO => RXDATA, + VAL => RXVAL, + HOLD => RXHOLD, + SIZEW => RXSIZE_FX2, + SIZER => RXSIZE_USR + ); + + TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based + generic map ( + AWIDTH => TXFAWIDTH, + DWIDTH => 8) + port map ( + CLKW => CLK, + CLKR => I_FX2_IFCLK, + RESETW => RESET, + RESETR => '0', + DI => TXDATA, + ENA => TXENA, + BUSY => TXBUSY_L, + DO => TXFIFO_DO, + VAL => TXFIFO_VAL, + HOLD => TXFIFO_HOLD, + SIZEW => TXSIZE_USR, + SIZER => TXSIZE_FX2 + ); + + proc_regs: process (I_FX2_IFCLK) + begin + + if rising_edge(I_FX2_IFCLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, + FX2_FLAG_N, TXFIFO_VAL, RXSIZE_FX2, + RXFIFO_BUSY, TXBUSY_L) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable ififo_ce : slbit := '0'; + variable ififo : slv2 := "00"; + + variable irxfifo_ena : slbit := '0'; + variable itxfifo_hold : slbit := '0'; + + variable islrd : slbit := '0'; + variable islwr : slbit := '0'; + variable isloe : slbit := '0'; + variable ipktend : slbit := '0'; + + variable idata_cei : slbit := '0'; + variable idata_ceo : slbit := '0'; + variable idata_oe : slbit := '0'; + + variable slrxok : slbit := '0'; + variable sltxok : slbit := '0'; + variable pipeok : slbit := '0'; + + variable cc_clr : slbit := '0'; + variable cc_cnt : slbit := '0'; + variable cc_done : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + ififo_ce := '0'; + ififo := "00"; + + irxfifo_ena := '0'; + itxfifo_hold := '1'; + + islrd := '0'; + islwr := '0'; + isloe := '0'; + ipktend := '0'; + + idata_cei := '0'; + idata_ceo := '0'; + idata_oe := '0'; + + slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low! + sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low! + pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low! + + cc_clr := '0'; + cc_cnt := '0'; + if unsigned(r.ccnt) = 0 then + cc_done := '1'; + else + cc_done := '0'; + end if; + + n.rxpipe1 := '0'; + + case r.state is + when s_idle => -- s_idle: + if slrxok='1' and RXFIFO_BUSY='0' then + ififo_ce := '1'; + ififo := c_rxfifo; + n.state := s_rxprep1; + elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then + ififo_ce := '1'; + ififo := c_txfifo; + n.state := s_txprep1; + end if; + + when s_rxprep0 => -- s_rxprep0: switch to rx-fifo + ififo_ce := '1'; + ififo := c_rxfifo; + n.state := s_rxprep1; + + when s_rxprep1 => -- s_rxprep1: fifo addr setup + cc_clr := '1'; + n.state := s_rxprep2; + + when s_rxprep2 => -- s_rxprep2: wait for flags + isloe := '1'; + n.state := s_rxdisp; + + when s_rxdisp => -- s_rxdisp: read, dispatch + isloe := '1'; + -- if chunk done and tx or pe pending and possible + if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then + if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ? + n.state := s_rxdisp; -- wait + else + n.state := s_txprep0; -- otherwise switch to tx flow + end if; + -- if more rx to do and possible + elsif slrxok='1' and unsigned(RXSIZE_FX2)>3 then -- !thres must be >3! + islrd := '1'; + cc_cnt := '1'; + n.rxpipe1 := '1'; + if pipeok='1' then + n.state := s_rxdisp; -- 1 cycle read + --n.state := s_rxprep2; -- 2 cycle read + else + n.state := s_rxpipe; + end if; + -- otherwise back to idle + else + if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ? + n.state := s_rxdisp; -- wait + else + n.state := s_idle; -- to idle + end if; + end if; + + when s_rxpipe => -- s_rxpipe: read, pipe wait + isloe := '1'; + n.state := s_rxprep2; + + when s_txprep0 => -- s_txprep0: switch to tx-fifo + ififo_ce := '1'; + ififo := c_txfifo; + n.state := s_txprep1; + + when s_txprep1 => -- s_txprep1: fifo addr setup + cc_clr := '1'; + n.state := s_txprep2; + + when s_txprep2 => -- s_txprep2: wait for flags + n.state := s_txdisp; + + when s_txdisp => -- s_txdisp: write, dispatch + -- if chunk done and rx pending and possible + if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then + n.state := s_rxprep0; + -- if pktend to do and possible + elsif sltxok = '1' and r.pepend = '1' then + ipktend := '1'; + n.pepend := '0'; + n.state := s_idle; + -- if more tx to do and possible + elsif sltxok = '1' and TXFIFO_VAL = '1' then + cc_cnt := '1'; -- inc chunk count + n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe) + itxfifo_hold := '0'; + idata_ceo := '1'; + idata_oe := '1'; + islwr := '1'; + if pipeok = '1' then -- if not almost full + n.state := s_txdisp; -- stream + else + n.state := s_txprep1; -- wait for full flag + end if; + -- otherwise back to idle + else + n.state := s_idle; + end if; + + when others => null; + end case; + + -- rx pipe handling + idata_cei := r.rxpipe1; + n.rxpipe2 := r.rxpipe1; + irxfifo_ena := r.rxpipe2; + + -- chunk counter handling + if cc_clr = '1' then + n.ccnt := (others=>'1'); + elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then + n.ccnt := slv(unsigned(r.ccnt) - 1); + end if; + + -- pktend time-out handling: + -- if tx fifo is non-empty, set counter to max + -- if tx fifo is empty, count down every usec + -- on 1->0 transition queue pktend request + if TXFIFO_VAL = '1' then + n.petocnt := (others=>'1'); + else + if unsigned(r.petocnt) /= 0 then + n.petocnt := slv(unsigned(r.petocnt) - 1); + if unsigned(r.petocnt) = 1 then + n.pepend := '1'; + end if; + end if; + end if; + + n.moni_ep4_sel := '0'; + n.moni_ep6_sel := '0'; + if r.state = s_rxdisp or r.state = s_rxpipe then + n.moni_ep4_sel := '1'; + n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog); + elsif r.state = s_txdisp then + n.moni_ep6_sel := '1'; + n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog); + end if; + + N_REGS <= n; + + FX2_FIFO_CE <= ififo_ce; + FX2_FIFO <= ififo; + + FX2_SLRD_N <= not islrd; + FX2_SLWR_N <= not islwr; + FX2_SLOE_N <= not isloe; + FX2_PKTEND_N <= not ipktend; + + FX2_DATA_CEI <= idata_cei; + FX2_DATA_CEO <= idata_ceo; + FX2_DATA_OE <= idata_oe; + + RXFIFO_ENA <= irxfifo_ena; + TXFIFO_HOLD <= itxfifo_hold; + + end process proc_next; + + proc_moni: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_MONI_C <= fx2ctl_moni_init; + R_MONI_S <= fx2ctl_moni_init; + else + R_MONI_C <= fx2ctl_moni_init; + R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel; + R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel; + R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef); + R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf; + R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff); + R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf; + R_MONI_C.slrd <= not FX2_SLRD_N; + R_MONI_C.slwr <= not FX2_SLWR_N; + R_MONI_C.pktend <= not FX2_PKTEND_N; + R_MONI_S <= R_MONI_C; + end if; + end if; + + end process proc_moni; + + proc_almost: process (RXSIZE_USR, TXSIZE_USR) + begin + + -- rxsize_usr is the number of bytes to read + -- txsize_usr is the number of bytes to write + + if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then + RXAEMPTY <= '1'; + else + RXAEMPTY <= '0'; + end if; + + if unsigned(TXSIZE_USR) <= TXAFULL_THRES then + TXAFULL <= '1'; + else + TXAFULL <= '0'; + end if; + + end process proc_almost; + + TXBUSY <= TXBUSY_L; + + MONI <= R_MONI_S; + +end syn; Index: fx2lib/fx2_3fifoctl_ic.vhd =================================================================== --- fx2lib/fx2_3fifoctl_ic.vhd (nonexistent) +++ fx2lib/fx2_3fifoctl_ic.vhd (revision 24) @@ -0,0 +1,699 @@ +-- $Id: fx2_3fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $ +-- +-- Copyright 2012-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: fx2_3fifoctl_ic - syn +-- Description: Cypress EZ-USB FX2 driver (3 fifo; int clk) +-- +-- Dependencies: vlib/xlib/iob_reg_o +-- vlib/xlib/iob_reg_i_gen +-- vlib/xlib/iob_reg_o_gen +-- vlib/xlib/iob_reg_io_gen +-- memlib/fifo_2c_dram +-- +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2012-01-15 453 13.3 O76x xc3s1200e-4 157 265 96 243 s 7.7/7.4 +-- 2012-01-15 453 13.3 O76x xc3s1200e-4 156 259 96 238 s 7.9/7.5 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-04 469 1.1 BUGFIX: redo rx logic, now properly pipelined +-- 2012-01-09 453 1.0 Initial version (derived from 2fifo_ic) +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.memlib.all; +use work.fx2lib.all; + +entity fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk) + generic ( + RXFAWIDTH : positive := 5; -- receive fifo address width + TXFAWIDTH : positive := 5; -- transmit fifo address width + PETOWIDTH : positive := 7; -- packet end time-out counter width + CCWIDTH : positive := 5; -- chunk counter width + RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag + TXAFULL_THRES : natural := 1; -- threshold for tx afull flag + TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RXDATA : out slv8; -- receive data out + RXVAL : out slbit; -- receive data valid + RXHOLD : in slbit; -- receive data hold + RXAEMPTY : out slbit; -- receive almost empty flag + TXDATA : in slv8; -- transmit 1 data in + TXENA : in slbit; -- transmit 1 data enable + TXBUSY : out slbit; -- transmit 1 data busy + TXAFULL : out slbit; -- transmit 1 almost full flag + TX2DATA : in slv8; -- transmit 2 data in + TX2ENA : in slbit; -- transmit 2 data enable + TX2BUSY : out slbit; -- transmit 2 data busy + TX2AFULL : out slbit; -- transmit 2 almost full flag + MONI : out fx2ctl_moni_type; -- monitor port data + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end fx2_3fifoctl_ic; + + +architecture syn of fx2_3fifoctl_ic is + + constant c_rxfifo : slv2 := c_fifo_ep4; + constant c_txfifo : slv2 := c_fifo_ep6; + constant c_tx2fifo: slv2 := c_fifo_ep8; + + constant c_flag_prog : integer := 0; + constant c_flag_tx_ff : integer := 1; + constant c_flag_rx_ef : integer := 2; + constant c_flag_tx2_ff : integer := 3; + + type state_type is ( + s_idle, -- s_idle: idle state + s_rxprep0, -- s_rxprep0: switch to rx-fifo + s_rxprep1, -- s_rxprep1: fifo addr setup + s_rxprep2, -- s_rxprep2: wait for flags + s_rxdisp, -- s_rxdisp: read, dispatch + s_rxpipe, -- s_rxpipe: read, pipe wait + s_txprep0, -- s_txprep0: switch to tx-fifo + s_txprep1, -- s_txprep1: fifo addr setup + s_txprep2, -- s_txprep2: wait for flags + s_txdisp, -- s_txdisp: write, dispatch + s_tx2prep0, -- s_tx2prep0: switch to tx2-fifo + s_tx2prep1, -- s_tx2prep1: fifo addr setup + s_tx2prep2, -- s_tx2prep2: wait for flags + s_tx2disp -- s_tx2disp: write, dispatch + ); + + type regs_type is record + state : state_type; -- state + petocnt : slv(PETOWIDTH-1 downto 0); -- pktend 1 time out counter + pe2tocnt : slv(PETOWIDTH-1 downto 0); -- pktend 2 time out counter + pepend : slbit; -- pktend 1 pending + pe2pend : slbit; -- pktend 2 pending + rxpipe1 : slbit; -- read pipe 1: iob capture stage + rxpipe2 : slbit; -- read pipe 2: fifo write stage + ccnt : slv(CCWIDTH-1 downto 0); -- chunk counter + moni_ep4_sel : slbit; -- ep4 (rx) select + moni_ep6_sel : slbit; -- ep6 (tx) select + moni_ep8_sel : slbit; -- ep8 (tx2) select + moni_ep4_pf : slbit; -- ep4 (rx) prog flag + moni_ep6_pf : slbit; -- ep6 (tx) prog flag + moni_ep8_pf : slbit; -- ep8 (tx2) prog flag + end record regs_type; + + constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0'); + constant ccnt_init : slv(CCWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + s_idle, -- state + petocnt_init, -- petocnt + petocnt_init, -- pe2tocnt + '0','0', -- pepend,pe2pend + '0','0', -- rxpipe1, rxpipe2 + ccnt_init, -- ccnt + '0','0','0', -- moni_ep(4|6|8)_sel + '0','0','0' -- moni_ep(4|6|8)_pf + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal FX2_FIFO : slv2 := (others=>'0'); + signal FX2_FIFO_CE : slbit := '0'; + signal FX2_FLAG_N : slv4 := (others=>'0'); + signal FX2_SLRD_N : slbit := '1'; + signal FX2_SLWR_N : slbit := '1'; + signal FX2_SLOE_N : slbit := '1'; + signal FX2_PKTEND_N : slbit := '1'; + signal FX2_DATA_CEI : slbit := '0'; + signal FX2_DATA_CEO : slbit := '0'; + signal FX2_DATA_OE : slbit := '0'; + signal FX2_DATA_DO : slv8 := (others=>'0'); + + signal RXFIFO_DI : slv8 := (others=>'0'); + signal RXFIFO_ENA : slbit := '0'; + signal RXFIFO_BUSY : slbit := '0'; + signal RXSIZE_FX2 : slv(RXFAWIDTH-1 downto 0) := (others=>'0'); + signal RXSIZE_USR : slv(RXFAWIDTH-1 downto 0) := (others=>'0'); + signal TXFIFO_DO : slv8 := (others=>'0'); + signal TXFIFO_VAL : slbit := '0'; + signal TXFIFO_HOLD : slbit := '0'; + signal TXSIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0'); + signal TXSIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0'); + signal TX2FIFO_DO : slv8 := (others=>'0'); + signal TX2FIFO_VAL : slbit := '0'; + signal TX2FIFO_HOLD : slbit := '0'; + signal TX2SIZE_FX2 : slv(TXFAWIDTH-1 downto 0) := (others=>'0'); + signal TX2SIZE_USR : slv(TXFAWIDTH-1 downto 0) := (others=>'0'); + + signal TXBUSY_L : slbit := '0'; + signal TX2BUSY_L : slbit := '0'; + + signal R_MONI_C : fx2ctl_moni_type := fx2ctl_moni_init; + signal R_MONI_S : fx2ctl_moni_type := fx2ctl_moni_init; + +begin + + assert RXAEMPTY_THRES<=2**RXFAWIDTH-1 and + TXAFULL_THRES<=2**TXFAWIDTH-1 and + TX2AFULL_THRES<=2**TXFAWIDTH-1 + report "assert((RXAEMPTY|TXAFULL|TX2AFULL)_THRES <= 2**(RX|TX)FAWIDTH)-1" + severity failure; + + + IOB_FX2_FIFO : iob_reg_o_gen + generic map ( + DWIDTH => 2, + INIT => '0') + port map ( + CLK => I_FX2_IFCLK, + CE => FX2_FIFO_CE, + DO => FX2_FIFO, + PAD => O_FX2_FIFO + ); + + IOB_FX2_FLAG : iob_reg_i_gen + generic map ( + DWIDTH => 4, + INIT => '0') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DI => FX2_FLAG_N, + PAD => I_FX2_FLAG + ); + + IOB_FX2_SLRD : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_SLRD_N, + PAD => O_FX2_SLRD_N + ); + + IOB_FX2_SLWR : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_SLWR_N, + PAD => O_FX2_SLWR_N + ); + + IOB_FX2_SLOE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_SLOE_N, + PAD => O_FX2_SLOE_N + ); + + IOB_FX2_PKTEND : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => I_FX2_IFCLK, + CE => '1', + DO => FX2_PKTEND_N, + PAD => O_FX2_PKTEND_N + ); + + IOB_FX2_DATA : iob_reg_io_gen + generic map ( + DWIDTH => 8, + PULL => "KEEP") + port map ( + CLK => I_FX2_IFCLK, + CEI => FX2_DATA_CEI, + CEO => FX2_DATA_CEO, + OE => FX2_DATA_OE, + DI => RXFIFO_DI, -- input data (read from pad) + DO => FX2_DATA_DO, -- output data (write to pad) + PAD => IO_FX2_DATA + ); + + RXFIFO : fifo_2c_dram -- input fifo, 2 clock, dram based + generic map ( + AWIDTH => RXFAWIDTH, + DWIDTH => 8) + port map ( + CLKW => I_FX2_IFCLK, + CLKR => CLK, + RESETW => '0', + RESETR => RESET, + DI => RXFIFO_DI, + ENA => RXFIFO_ENA, + BUSY => RXFIFO_BUSY, + DO => RXDATA, + VAL => RXVAL, + HOLD => RXHOLD, + SIZEW => RXSIZE_FX2, + SIZER => RXSIZE_USR + ); + + TXFIFO : fifo_2c_dram -- output fifo, 2 clock, dram based + generic map ( + AWIDTH => TXFAWIDTH, + DWIDTH => 8) + port map ( + CLKW => CLK, + CLKR => I_FX2_IFCLK, + RESETW => RESET, + RESETR => '0', + DI => TXDATA, + ENA => TXENA, + BUSY => TXBUSY_L, + DO => TXFIFO_DO, + VAL => TXFIFO_VAL, + HOLD => TXFIFO_HOLD, + SIZEW => TXSIZE_USR, + SIZER => TXSIZE_FX2 + ); + + TX2FIFO : fifo_2c_dram -- output 2 fifo, 2 clock, dram based + generic map ( + AWIDTH => TXFAWIDTH, + DWIDTH => 8) + port map ( + CLKW => CLK, + CLKR => I_FX2_IFCLK, + RESETW => RESET, + RESETR => '0', + DI => TX2DATA, + ENA => TX2ENA, + BUSY => TX2BUSY_L, + DO => TX2FIFO_DO, + VAL => TX2FIFO_VAL, + HOLD => TX2FIFO_HOLD, + SIZEW => TX2SIZE_USR, + SIZER => TX2SIZE_FX2 + ); + + proc_regs: process (I_FX2_IFCLK) + begin + + if rising_edge(I_FX2_IFCLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, + FX2_FLAG_N, TXFIFO_VAL, TX2FIFO_VAL, + TXFIFO_DO, TX2FIFO_DO, + RXSIZE_FX2, RXFIFO_BUSY, TXBUSY_L, TX2BUSY_L) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable ififo_ce : slbit := '0'; + variable ififo : slv2 := "00"; + + variable irxfifo_ena : slbit := '0'; + variable itxfifo_hold : slbit := '0'; + variable itx2fifo_hold : slbit := '0'; + + variable islrd : slbit := '0'; + variable islwr : slbit := '0'; + variable isloe : slbit := '0'; + variable ipktend : slbit := '0'; + + variable idata_cei : slbit := '0'; + variable idata_ceo : slbit := '0'; + variable idata_oe : slbit := '0'; + variable idata_do : slv8 := (others=>'0'); + + variable slrxok : slbit := '0'; + variable sltxok : slbit := '0'; + variable sltx2ok : slbit := '0'; + variable pipeok : slbit := '0'; + + variable cc_clr : slbit := '0'; + variable cc_cnt : slbit := '0'; + variable cc_done : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + + ififo_ce := '0'; + ififo := "00"; + + irxfifo_ena := '0'; + itxfifo_hold := '1'; + itx2fifo_hold := '1'; + + islrd := '0'; + islwr := '0'; + isloe := '0'; + ipktend := '0'; + + idata_cei := '0'; + idata_ceo := '0'; + idata_oe := '0'; + idata_do := TXFIFO_DO; + + slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low! + sltxok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low! + sltx2ok := FX2_FLAG_N(c_flag_tx2_ff); -- full flag is act.low! + pipeok := FX2_FLAG_N(c_flag_prog); -- almost flag is act.low! + + cc_clr := '0'; + cc_cnt := '0'; + if unsigned(r.ccnt) = 0 then + cc_done := '1'; + else + cc_done := '0'; + end if; + + n.rxpipe1 := '0'; + + case r.state is + when s_idle => -- s_idle: + if slrxok='1' and RXFIFO_BUSY='0' then + ififo_ce := '1'; + ififo := c_rxfifo; + n.state := s_rxprep1; + elsif sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1')then + ififo_ce := '1'; + ififo := c_txfifo; + n.state := s_txprep1; + elsif sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')then + ififo_ce := '1'; + ififo := c_tx2fifo; + n.state := s_tx2prep1; + end if; + + when s_rxprep0 => -- s_rxprep0: switch to rx-fifo + ififo_ce := '1'; + ififo := c_rxfifo; + n.state := s_rxprep1; + + when s_rxprep1 => -- s_rxprep1: fifo addr setup + cc_clr := '1'; + n.state := s_rxprep2; + + when s_rxprep2 => -- s_rxprep2: wait for flags + isloe := '1'; + n.state := s_rxdisp; + + when s_rxdisp => -- s_rxdisp: read, dispatch + isloe := '1'; + -- if chunk done and tx or pe pending and possible + if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then + if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ? + n.state := s_rxdisp; -- wait + else + n.state := s_txprep0; -- otherwise switch to tx flow + end if; + -- if chunk done and tx2 or pe2 pending and possible + elsif cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1') + then + if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ? + n.state := s_rxdisp; -- wait + else + n.state := s_tx2prep0; + end if; + -- if more rx to do and possible + elsif slrxok='1' and unsigned(RXSIZE_FX2)>3 then -- !thres must be >3! + islrd := '1'; + cc_cnt := '1'; + n.rxpipe1 := '1'; + if pipeok='1' then + n.state := s_rxdisp; -- 1 cycle read + --n.state := s_rxprep2; -- 2 cycle read + else + n.state := s_rxpipe; + end if; + -- otherwise back to idle + else + if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ? + n.state := s_rxdisp; -- wait + else + n.state := s_idle; -- to idle + end if; + end if; + + when s_rxpipe => -- s_rxpipe: read, pipe wait + isloe := '1'; + n.state := s_rxprep2; + + when s_txprep0 => -- s_txprep0: switch to tx-fifo + ififo_ce := '1'; + ififo := c_txfifo; + n.state := s_txprep1; + + when s_txprep1 => -- s_txprep1: fifo addr setup + cc_clr := '1'; + n.state := s_txprep2; + + when s_txprep2 => -- s_txprep2: wait for flags + n.state := s_txdisp; + + when s_txdisp => -- s_txdisp: write, dispatch + -- if chunk done and tx2 or pe2 pending and possible + if cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1') + then + n.state := s_tx2prep0; + -- if chunk done and rx pending and possible + elsif cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then + n.state := s_rxprep0; + -- if pktend to do and possible + elsif sltxok = '1' and r.pepend = '1' then + ipktend := '1'; + n.pepend := '0'; + n.state := s_idle; + -- if more tx to do and possible + elsif sltxok = '1' and TXFIFO_VAL = '1' then + cc_cnt := '1'; -- inc chunk count + n.pepend := '0'; -- cancel pe (avoid back-2-back tx+pe) + itxfifo_hold := '0'; + idata_do := TXFIFO_DO; + idata_ceo := '1'; + idata_oe := '1'; + islwr := '1'; + if pipeok = '1' then -- if not almost full + n.state := s_txdisp; -- stream + else + n.state := s_txprep1; -- wait for full flag + end if; + -- otherwise back to idle + else + n.state := s_idle; + end if; + + when s_tx2prep0 => -- s_tx2prep0: switch to tx2-fifo + ififo_ce := '1'; + ififo := c_tx2fifo; + n.state := s_tx2prep1; + + when s_tx2prep1 => -- s_tx2prep1: fifo addr setup + cc_clr := '1'; + n.state := s_tx2prep2; + + when s_tx2prep2 => -- s_tx2prep2: wait for flags + n.state := s_tx2disp; + + when s_tx2disp => -- s_tx2disp: write, dispatch + -- if chunk done and rx pending and possible + if cc_done='1' and slrxok='1' and RXFIFO_BUSY='0' then + n.state := s_rxprep0; + -- if chunk done and tx or pe pending and possible + elsif cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') + then + n.state := s_txprep0; + -- if pktend 2 to do and possible + elsif sltx2ok = '1' and r.pe2pend = '1' then + ipktend := '1'; + n.pe2pend := '0'; + n.state := s_idle; + -- if more tx2 to do and possible + elsif sltx2ok = '1' and TX2FIFO_VAL = '1' then + cc_cnt := '1'; -- inc chunk count + n.pe2pend := '0'; -- cancel pe (avoid back-2-back tx+pe) + itx2fifo_hold := '0'; + idata_do := TX2FIFO_DO; + idata_ceo := '1'; + idata_oe := '1'; + islwr := '1'; + if pipeok = '1' then -- if not almost full + n.state := s_tx2disp; -- stream + else + n.state := s_tx2prep1; -- wait for full flag + end if; + -- otherwise back to idle + else + n.state := s_idle; + end if; + + when others => null; + end case; + + -- rx pipe handling + idata_cei := r.rxpipe1; + n.rxpipe2 := r.rxpipe1; + irxfifo_ena := r.rxpipe2; + + -- chunk counter handling + if cc_clr = '1' then + n.ccnt := (others=>'1'); + elsif cc_cnt='1' and unsigned(r.ccnt) > 0 then + n.ccnt := slv(unsigned(r.ccnt) - 1); + end if; + + -- pktend time-out handling: + -- if tx fifo is non-empty, set counter to max + -- if tx fifo is empty, count down every usec + -- on 1->0 transition queue pktend request + if TXFIFO_VAL = '1' then + n.petocnt := (others=>'1'); + else + if unsigned(r.petocnt) /= 0 then + n.petocnt := slv(unsigned(r.petocnt) - 1); + if unsigned(r.petocnt) = 1 then + n.pepend := '1'; + end if; + end if; + end if; + if TX2FIFO_VAL = '1' then + n.pe2tocnt := (others=>'1'); + else + if unsigned(r.pe2tocnt) /= 0 then + n.pe2tocnt := slv(unsigned(r.pe2tocnt) - 1); + if unsigned(r.pe2tocnt) = 1 then + n.pe2pend := '1'; + end if; + end if; + end if; + + n.moni_ep4_sel := '0'; + n.moni_ep6_sel := '0'; + n.moni_ep8_sel := '0'; + if r.state = s_rxdisp or r.state = s_rxpipe then + n.moni_ep4_sel := '1'; + n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog); + elsif r.state = s_txdisp then + n.moni_ep6_sel := '1'; + n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog); + elsif r.state = s_tx2disp then + n.moni_ep8_sel := '1'; + n.moni_ep8_pf := not FX2_FLAG_N(c_flag_prog); + end if; + + N_REGS <= n; + + FX2_FIFO_CE <= ififo_ce; + FX2_FIFO <= ififo; + + FX2_SLRD_N <= not islrd; + FX2_SLWR_N <= not islwr; + FX2_SLOE_N <= not isloe; + FX2_PKTEND_N <= not ipktend; + + FX2_DATA_CEI <= idata_cei; + FX2_DATA_CEO <= idata_ceo; + FX2_DATA_OE <= idata_oe; + FX2_DATA_DO <= idata_do; + + RXFIFO_ENA <= irxfifo_ena; + TXFIFO_HOLD <= itxfifo_hold; + TX2FIFO_HOLD <= itx2fifo_hold; + + end process proc_next; + + proc_moni: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_MONI_C <= fx2ctl_moni_init; + R_MONI_S <= fx2ctl_moni_init; + else + R_MONI_C <= fx2ctl_moni_init; + R_MONI_C.fifo_ep4 <= R_REGS.moni_ep4_sel; + R_MONI_C.fifo_ep6 <= R_REGS.moni_ep6_sel; + R_MONI_C.fifo_ep8 <= R_REGS.moni_ep8_sel; + R_MONI_C.flag_ep4_empty <= not FX2_FLAG_N(c_flag_rx_ef); + R_MONI_C.flag_ep4_almost <= R_REGS.moni_ep4_pf; + R_MONI_C.flag_ep6_full <= not FX2_FLAG_N(c_flag_tx_ff); + R_MONI_C.flag_ep6_almost <= R_REGS.moni_ep6_pf; + R_MONI_C.flag_ep8_full <= not FX2_FLAG_N(c_flag_tx2_ff); + R_MONI_C.flag_ep8_almost <= R_REGS.moni_ep8_pf; + R_MONI_C.slrd <= not FX2_SLRD_N; + R_MONI_C.slwr <= not FX2_SLWR_N; + R_MONI_C.pktend <= not FX2_PKTEND_N; + R_MONI_S <= R_MONI_C; + end if; + end if; + + end process proc_moni; + + proc_almost: process (RXSIZE_USR, TXSIZE_USR, TX2SIZE_USR) + begin + + -- rxsize_usr is the number of bytes to read + -- txsize_usr is the number of bytes to write + + if unsigned(RXSIZE_USR) <= RXAEMPTY_THRES then + RXAEMPTY <= '1'; + else + RXAEMPTY <= '0'; + end if; + + if unsigned(TXSIZE_USR) <= TXAFULL_THRES then + TXAFULL <= '1'; + else + TXAFULL <= '0'; + end if; + + if unsigned(TX2SIZE_USR) <= TX2AFULL_THRES then + TX2AFULL <= '1'; + else + TX2AFULL <= '0'; + end if; + + end process proc_almost; + + TXBUSY <= TXBUSY_L; + TX2BUSY <= TX2BUSY_L; + + MONI <= R_MONI_S; + +end syn; Index: fx2lib/tb/fx2_2fifo_core.vhd =================================================================== --- fx2lib/tb/fx2_2fifo_core.vhd (nonexistent) +++ fx2lib/tb/fx2_2fifo_core.vhd (revision 24) @@ -0,0 +1,277 @@ +-- $Id: fx2_2fifo_core.vhd 469 2013-01-05 12:29:44Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: fx2_2fifo_core - sim +-- Description: Cypress EZ-USB FX2 (2 fifo core model) +-- +-- Dependencies: memlib/fifo_2c_dram +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-04 469 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simbus.all; +use work.fx2lib.all; +use work.memlib.all; + +entity fx2_2fifo_core is -- EZ-USB FX2 (2 fifo core model) + port ( + CLK : in slbit; -- uplink clock + RESET : in slbit; -- reset + RXDATA : in slv8; -- rx data (ext->fx2) + RXENA : in slbit; -- rx enable + RXBUSY : out slbit; -- rx busy + TXDATA : out slv8; -- tx data (fx2->ext) + TXVAL : out slbit; -- tx valid + IFCLK : out slbit; -- fx2 interface clock + FIFO : in slv2; -- fx2 fifo address + FLAG : out slv4; -- fx2 fifo flags + SLRD_N : in slbit; -- fx2 read enable (act.low) + SLWR_N : in slbit; -- fx2 write enable (act.low) + SLOE_N : in slbit; -- fx2 output enable (act.low) + PKTEND_N : in slbit; -- fx2 packet end (act.low) + DATA : inout slv8 -- fx2 data lines + ); +end fx2_2fifo_core; + + +architecture sim of fx2_2fifo_core is + + constant c_rxfifo : slv2 := c_fifo_ep4; + constant c_txfifo : slv2 := c_fifo_ep6; + + constant c_flag_prog : integer := 0; + constant c_flag_tx_ff : integer := 1; + constant c_flag_rx_ef : integer := 2; + constant c_flag_tx2_ff : integer := 3; + + constant bufsize : positive := 1024; + constant datzero : slv(DATA'range) := (others=>'0'); + type buf_type is array (0 to bufsize-1) of slv(DATA'range); + + signal CLK30 : slbit := '0'; + + signal RXFIFO_DO : slv8 := (others=>'0'); + signal RXFIFO_VAL : slbit := '0'; + signal RXFIFO_HOLD : slbit := '0'; + signal TXFIFO_DI : slv8 := (others=>'0'); + signal TXFIFO_ENA : slbit := '0'; + signal TXFIFO_BUSY : slbit := '0'; + + signal R_FLAG : slv4 := (others=>'0'); + signal R_DATA : slv8 := (others=>'0'); + + -- added for debug purposes + signal R_rxbuf_rind : natural := 0; + signal R_rxbuf_wind : natural := 0; + signal R_rxbuf_nbyt : natural := 0; + signal R_txbuf_rind : natural := 0; + signal R_txbuf_wind : natural := 0; + signal R_txbuf_nbyt : natural := 0; + +begin + + RXFIFO : fifo_2c_dram + generic map ( + AWIDTH => 5, + DWIDTH => 8) + port map ( + CLKW => CLK, + CLKR => CLK30, + RESETW => '0', + RESETR => '0', + DI => RXDATA, + ENA => RXENA, + BUSY => RXBUSY, + DO => RXFIFO_DO, + VAL => RXFIFO_VAL, + HOLD => RXFIFO_HOLD, + SIZEW => open, + SIZER => open + ); + + TXFIFO : fifo_2c_dram + generic map ( + AWIDTH => 5, + DWIDTH => 8) + port map ( + CLKW => CLK30, + CLKR => CLK, + RESETW => '0', + RESETR => '0', + DI => TXFIFO_DI, + ENA => TXFIFO_ENA, + BUSY => TXFIFO_BUSY, + DO => TXDATA, + VAL => TXVAL, + HOLD => '0', + SIZEW => open, + SIZER => open + ); + + proc_ifclk: process + constant offset : time := 200 ns; + constant halfperiod_7 : time := 16700 ps; + constant halfperiod_6 : time := 16600 ps; + begin + + CLK30 <= '0'; + wait for offset; + + clk_loop: loop + CLK30 <= '1'; + wait for halfperiod_7; + CLK30 <= '0'; + wait for halfperiod_7; + CLK30 <= '1'; + wait for halfperiod_6; + CLK30 <= '0'; + wait for halfperiod_7; + CLK30 <= '1'; + wait for halfperiod_7; + CLK30 <= '0'; + wait for halfperiod_6; + exit clk_loop when to_x01(SB_CLKSTOP) = '1'; + end loop; + + wait; -- endless wait, simulator will stop + + end process proc_ifclk; + + proc_state: process (CLK30) + variable rxbuf : buf_type := (others=>datzero); + variable rxbuf_rind : natural := 0; + variable rxbuf_wind : natural := 0; + variable rxbuf_nbyt : natural := 0; + + variable txbuf : buf_type := (others=>datzero); + variable txbuf_rind : natural := 0; + variable txbuf_wind : natural := 0; + variable txbuf_nbyt : natural := 0; + + variable oline : line; + + begin + + if rising_edge(CLK30) then + + RXFIFO_HOLD <= '0'; + TXFIFO_ENA <= '0'; + + -- rxfifo -> rxbuf + if RXFIFO_VAL = '1' then + if rxbuf_nbyt < bufsize then + rxbuf(rxbuf_wind) := RXFIFO_DO; + rxbuf_wind := (rxbuf_wind + 1) mod bufsize; + rxbuf_nbyt := rxbuf_nbyt + 1; + else + RXFIFO_HOLD <= '1'; + end if; + end if; + + -- txbuf -> txfifo + if txbuf_nbyt>0 and TXFIFO_BUSY='0' then + TXFIFO_DI <= txbuf(txbuf_rind); + TXFIFO_ENA <= '1'; + txbuf_rind := (txbuf_rind + 1) mod bufsize; + txbuf_nbyt := txbuf_nbyt - 1; + end if; + + -- slrd cycle: rxbuf -> data + if SLRD_N = '0' then + if rxbuf_nbyt > 0 then + rxbuf_rind := (rxbuf_rind + 1) mod bufsize; + rxbuf_nbyt := rxbuf_nbyt - 1; + else + write(oline, string'("fx2_2fifo_core: SLRD_N=0 when rxbuf empty")); + writeline(output, oline); + end if; + end if; + R_DATA <= rxbuf(rxbuf_rind); + + -- slwr cycle: data -> txbuf + if SLWR_N = '0' then + if txbuf_nbyt < bufsize then + txbuf(txbuf_wind) := DATA; + txbuf_wind := (txbuf_wind + 1) mod bufsize; + txbuf_nbyt := txbuf_nbyt + 1; + else + write(oline, string'("fx2_2fifo_core: SLWR_N=0 when txbuf full")); + writeline(output, oline); + end if; + end if; + + -- prepare flags (note that FLAGs are act.low!) + R_FLAG <= (others=>'1'); + -- FLAGA = indexed, PF + -- rx endpoint -> PF 'almost empty' at 3 bytes to go + if FIFO = c_rxfifo then + if rxbuf_nbyt < 4 then + R_FLAG(0) <= '0'; + end if; + -- tx endpoint -> PF 'almost full' at 3 bytes to go + elsif FIFO = c_txfifo then + if txbuf_nbyt > bufsize-4 then + R_FLAG(0) <= '0'; + end if; + end if; + + -- FLAGB = EP6 FF + if txbuf_nbyt = bufsize then + R_FLAG(1) <= '0'; + end if; + + -- FLAGC = EP4 EF + if rxbuf_nbyt = 0 then + R_FLAG(2) <= '0'; + end if; + + -- FLAGD = EP8 FF + R_FLAG(3) <= '1'; + + -- added for debug purposes + R_rxbuf_rind <= rxbuf_rind; + R_rxbuf_wind <= rxbuf_wind; + R_rxbuf_nbyt <= rxbuf_nbyt; + R_txbuf_rind <= txbuf_rind; + R_txbuf_wind <= txbuf_wind; + R_txbuf_nbyt <= txbuf_nbyt; + + end if; + + end process proc_state; + + IFCLK <= CLK30; + FLAG <= R_FLAG; + + proc_data: process (SLOE_N, R_DATA) + begin + if SLOE_N = '1' then + DATA <= (others=>'Z'); + else + DATA <= R_DATA; + end if; + end process proc_data; + +end sim; Index: fx2lib/tb/fx2_2fifo_core.vbom =================================================================== --- fx2lib/tb/fx2_2fifo_core.vbom (nonexistent) +++ fx2lib/tb/fx2_2fifo_core.vbom (revision 24) @@ -0,0 +1,9 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simlib.vhd +../fx2lib.vhd +../../../vlib/memlib/memlib.vhd +# components +../../../vlib/memlib/fifo_2c_dram.vbom +# design +fx2_2fifo_core.vhd Index: fx2lib/tb =================================================================== --- fx2lib/tb (nonexistent) +++ fx2lib/tb (revision 24)
fx2lib/tb Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: fx2lib/fx2_2fifoctl_ic.vbom =================================================================== --- fx2lib/fx2_2fifoctl_ic.vbom (nonexistent) +++ fx2lib/fx2_2fifoctl_ic.vbom (revision 24) @@ -0,0 +1,13 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +../../vlib/memlib/memlib.vhd +fx2lib.vhd +# components +../../vlib/xlib/iob_reg_o.vbom +../../vlib/xlib/iob_reg_i_gen.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/xlib/iob_reg_io_gen.vbom +../../vlib/memlib/fifo_2c_dram.vbom +# design +fx2_2fifoctl_ic.vhd Index: fx2lib/fx2_3fifoctl_ic.vbom =================================================================== --- fx2lib/fx2_3fifoctl_ic.vbom (nonexistent) +++ fx2lib/fx2_3fifoctl_ic.vbom (revision 24) @@ -0,0 +1,13 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +../../vlib/memlib/memlib.vhd +fx2lib.vhd +# components +../../vlib/xlib/iob_reg_o.vbom +../../vlib/xlib/iob_reg_i_gen.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/xlib/iob_reg_io_gen.vbom +../../vlib/memlib/fifo_2c_dram.vbom +# design +fx2_3fifoctl_ic.vhd Index: fx2lib/fx2lib.vhd =================================================================== --- fx2lib/fx2lib.vhd (nonexistent) +++ fx2lib/fx2lib.vhd (revision 24) @@ -0,0 +1,172 @@ +-- $Id: fx2lib.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2011-2012 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: fx2lib +-- Description: Cypress ez-usb fx2 support +-- +-- Dependencies: - +-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-14 453 1.3 use afull/aempty logic instead of exporting size +-- 2012-01-03 449 1.2.1 reorganize fx2ctl_moni; hardcode ep's +-- 2012-01-01 448 1.2 add fx2_2fifoctl_ic +-- 2011-12-25 445 1.1 change pktend iface in fx2_2fifoctl_as +-- 2011-07-17 394 1.0.1 add c_fifo_epx and fx2ctl_moni_type +-- 2011-07-07 389 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package fx2lib is + + constant c_fifo_ep2 : slv2 := "00"; -- fifo address: end point 2 + constant c_fifo_ep4 : slv2 := "01"; -- fifo address: end point 4 + constant c_fifo_ep6 : slv2 := "10"; -- fifo address: end point 6 + constant c_fifo_ep8 : slv2 := "11"; -- fifo address: end point 8 + + type fx2ctl_moni_type is record -- fx2ctl monitor port + fifo_ep4 : slbit; -- fifo 1 (ep4) active; + fifo_ep6 : slbit; -- fifo 2 (ep6) active; + fifo_ep8 : slbit; -- fifo 3 (ep8) active; + flag_ep4_empty : slbit; -- ep4 empty flag (latched); + flag_ep4_almost : slbit; -- ep4 almost empty flag (latched); + flag_ep6_full : slbit; -- ep6 full flag (latched); + flag_ep6_almost : slbit; -- ep6 almost full flag (latched); + flag_ep8_full : slbit; -- ep8 full flag (latched); + flag_ep8_almost : slbit; -- ep8 almost full flag (latched); + slrd : slbit; -- read strobe + slwr : slbit; -- write strobe + pktend : slbit; -- pktend strobe + end record fx2ctl_moni_type; + + constant fx2ctl_moni_init : fx2ctl_moni_type := ( + '0','0','0', -- fifo_ep[468] + '0','0', -- flag_ep4_(empty|almost) + '0','0', -- flag_ep6_(full|almost) + '0','0', -- flag_ep8_(full|almost) + '0','0','0' -- slrd, slwr, pktend + ); + + +-- ------------------------------------- +component fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async) + generic ( + RXFAWIDTH : positive := 5; -- receive fifo address width + TXFAWIDTH : positive := 5; -- transmit fifo address width + PETOWIDTH : positive := 7; -- packet end time-out counter width + CCWIDTH : positive := 5; -- chunk counter width + RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag + TXAFULL_THRES : natural := 1; -- threshold for tx afull flag + RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles + RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles + WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles + WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles + FLAGDELAY : positive := 2); -- flag delay in clock cycles + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- 1 usec clock enable + RESET : in slbit := '0'; -- reset + RXDATA : out slv8; -- receive data out + RXVAL : out slbit; -- receive data valid + RXHOLD : in slbit; -- receive data hold + RXAEMPTY : out slbit; -- receive almost empty flag + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit data busy + TXAFULL : out slbit; -- transmit almost full flag + MONI : out fx2ctl_moni_type; -- monitor port data + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +component fx2_2fifoctl_ic is -- EZ-USB FX2 driver (2 fifo; int clk) + generic ( + RXFAWIDTH : positive := 5; -- receive fifo address width + TXFAWIDTH : positive := 5; -- transmit fifo address width + PETOWIDTH : positive := 7; -- packet end time-out counter width + CCWIDTH : positive := 5; -- chunk counter width + RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag + TXAFULL_THRES : natural := 1); -- threshold for tx afull flag + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RXDATA : out slv8; -- receive data out + RXVAL : out slbit; -- receive data valid + RXHOLD : in slbit; -- receive data hold + RXAEMPTY : out slbit; -- receive almost empty flag + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit data busy + TXAFULL : out slbit; -- transmit almost full flag + MONI : out fx2ctl_moni_type; -- monitor port data + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +component fx2_3fifoctl_ic is -- EZ-USB FX2 driver (3 fifo; int clk) + generic ( + RXFAWIDTH : positive := 5; -- receive fifo address width + TXFAWIDTH : positive := 5; -- transmit fifo address width + PETOWIDTH : positive := 7; -- packet end time-out counter width + CCWIDTH : positive := 5; -- chunk counter width + RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag + TXAFULL_THRES : natural := 1; -- threshold for tx afull flag + TX2AFULL_THRES : natural := 1); -- threshold for tx2 afull flag + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RXDATA : out slv8; -- receive data out + RXVAL : out slbit; -- receive data valid + RXHOLD : in slbit; -- receive data hold + RXAEMPTY : out slbit; -- receive almost empty flag + TXDATA : in slv8; -- transmit 1 data in + TXENA : in slbit; -- transmit 1 data enable + TXBUSY : out slbit; -- transmit 1 data busy + TXAFULL : out slbit; -- transmit 1 almost full flag + TX2DATA : in slv8; -- transmit 2 data in + TX2ENA : in slbit; -- transmit 2 data enable + TX2BUSY : out slbit; -- transmit 2 data busy + TX2AFULL : out slbit; -- transmit 2 almost full flag + MONI : out fx2ctl_moni_type; -- monitor port data + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +end package fx2lib; Index: fx2lib/fx2_2fifoctl_as.vhd =================================================================== --- fx2lib/fx2_2fifoctl_as.vhd (nonexistent) +++ fx2lib/fx2_2fifoctl_as.vhd (revision 24) @@ -0,0 +1,647 @@ +-- $Id: fx2_2fifoctl_as.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2011-2012 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: fx2_2fifoctl_as - syn +-- Description: Cypress EZ-USB FX2 driver (2 fifo; async) +-- +-- Dependencies: vlib/xlib/iob_reg_o +-- vlib/xlib/iob_reg_i_gen +-- vlib/xlib/iob_reg_o_gen +-- vlib/xlib/iob_reg_io_gen +-- memlib/fifo_1c_dram +-- +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 12.1, 13.1, 13.3; ghdl 0.26-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2012-01-14 453 13.3 O76x xc3s1200e-4 65 153 64 133 s 7.2 +-- 2012-01-03 449 13.3 O76x xc3s1200e-4 67 149 64 133 s 7.2 +-- 2011-12-25 445 13.3 O76x xc3s1200e-4 61 147 64 127 s 7.2 +-- 2011-12-25 444 13.3 O76x xc3s1200e-4 54 140 64 123 s 7.2 +-- 2011-07-07 389 12.1 M53d xc3s1200e-4 45 132 64 109 s 7.9 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-14 453 1.3 common DELAY for PE and WR; use aempty/afull logic +-- 2012-01-04 450 1.2.2 use new FLAG layout (EF,FF now fixed) +-- 2012-01-03 449 1.2.1 use new fx2ctl_moni layout; hardcode ep's +-- 2011-12-25 445 1.2 change pktend handling, now timer based +-- 2011-11-25 433 1.1.1 now numeric_std clean +-- 2011-07-30 400 1.1 capture rx data in 2nd last s_rdpwh cycle +-- 2011-07-24 389 1.0.2 use FX2_FLAG_N to signal that flags are act.low +-- 2011-07-17 394 1.0.1 (RX|TX)FIFOEP now generics; add MONI port +-- 2011-07-08 390 1.0 Initial version +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.memlib.all; +use work.fx2lib.all; + +entity fx2_2fifoctl_as is -- EZ-USB FX2 driver (2 fifo; async) + generic ( + RXFAWIDTH : positive := 5; -- receive fifo address width + TXFAWIDTH : positive := 5; -- transmit fifo address width + PETOWIDTH : positive := 7; -- packet end time-out counter width + CCWIDTH : positive := 5; -- chunk counter width + RXAEMPTY_THRES : natural := 1; -- threshold for rx aempty flag + TXAFULL_THRES : natural := 1; -- threshold for tx afull flag + RDPWLDELAY : positive := 5; -- slrd low delay in clock cycles + RDPWHDELAY : positive := 5; -- slrd high delay in clock cycles + WRPWLDELAY : positive := 5; -- slwr low delay in clock cycles + WRPWHDELAY : positive := 7; -- slwr high delay in clock cycles + FLAGDELAY : positive := 2); -- flag delay in clock cycles + port ( + CLK : in slbit; -- clock + CE_USEC : in slbit; -- 1 usec clock enable + RESET : in slbit := '0'; -- reset + RXDATA : out slv8; -- receive data out + RXVAL : out slbit; -- receive data valid + RXHOLD : in slbit; -- receive data hold + RXAEMPTY : out slbit; -- receive almost empty flag + TXDATA : in slv8; -- transmit data in + TXENA : in slbit; -- transmit data enable + TXBUSY : out slbit; -- transmit data busy + TXAFULL : out slbit; -- transmit almost full flag + MONI : out fx2ctl_moni_type; -- monitor port data + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end fx2_2fifoctl_as; + + +architecture syn of fx2_2fifoctl_as is + + constant c_rxfifo : slv2 := c_fifo_ep4; + constant c_txfifo : slv2 := c_fifo_ep6; + + constant c_flag_prog : integer := 0; + constant c_flag_tx_ff : integer := 1; + constant c_flag_rx_ef : integer := 2; + constant c_flag_tx2_ff : integer := 3; + + type state_type is ( + s_init, -- s_init: init state + s_rdprep, -- s_rdprep: prepare read + s_rdwait, -- s_rdwait: wait for data + s_rdpwl, -- s_rdpwl: read, strobe low + s_rdpwh, -- s_rdpwh: read, strobe high + s_wrprep, -- s_wrprep: prepare write + s_wrpwl, -- s_wrpwl: write, strobe low + s_wrpwh, -- s_wrpwh: write, strobe high + s_peprep, -- s_peprep: prepare pktend + s_pepwl, -- s_pepwl: pktend, strobe low + s_pepwh -- s_pepwh: pktend, strobe high + ); + + type regs_type is record + state : state_type; -- state + petocnt : slv(PETOWIDTH-1 downto 0); -- pktend time out counter + pepend : slbit; -- pktend pending + dlycnt : slv4; -- wait delay counter + moni_ep4_sel : slbit; -- ep4 (rx) select + moni_ep6_sel : slbit; -- ep6 (tx) select + moni_ep4_pf : slbit; -- ep4 (rx) prog flag + moni_ep6_pf : slbit; -- ep6 (rx) prog flag + end record regs_type; + + constant petocnt_init : slv(PETOWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + s_init, -- state + petocnt_init, -- petocnt + '0', -- pepend + (others=>'0'), -- cntdly + '0','0', -- moni_ep(4|6)_sel + '0','0' -- moni_ep(4|6)_pf + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal FX2_FIFO : slv2 := (others=>'0'); + signal FX2_FIFO_CE : slbit := '0'; + signal FX2_FLAG_N : slv4 := (others=>'0'); + signal FX2_SLRD_N : slbit := '1'; + signal FX2_SLWR_N : slbit := '1'; + signal FX2_SLOE_N : slbit := '1'; + signal FX2_PKTEND_N : slbit := '1'; + signal FX2_DATA_CEI : slbit := '0'; + signal FX2_DATA_CEO : slbit := '0'; + signal FX2_DATA_OE : slbit := '0'; + + signal RXFIFO_DI : slv8 := (others=>'0'); + signal RXFIFO_ENA : slbit := '0'; + signal RXFIFO_BUSY : slbit := '0'; + signal RXSIZE : slv(RXFAWIDTH downto 0) := (others=>'0'); + signal TXFIFO_DO : slv8 := (others=>'0'); + signal TXFIFO_VAL : slbit := '0'; + signal TXFIFO_HOLD : slbit := '0'; + signal TXSIZE : slv(TXFAWIDTH downto 0) := (others=>'0'); + + signal TXBUSY_L : slbit := '0'; + +begin + + assert RDPWLDELAY<=2**R_REGS.dlycnt'length and + RDPWHDELAY<=2**R_REGS.dlycnt'length and RDPWHDELAY>=2 and + WRPWLDELAY<=2**R_REGS.dlycnt'length and + WRPWHDELAY<=2**R_REGS.dlycnt'length and + FLAGDELAY<=2**R_REGS.dlycnt'length + report "assert(*DELAY <= 2**dlycnt'length and RDPWHDELAY >=2)" + severity failure; + + assert RXAEMPTY_THRES<=2**RXFAWIDTH and + TXAFULL_THRES<=2**TXFAWIDTH + report "assert((RXAEMPTY|TXAFULL)_THRES <= 2**(RX|TX)FAWIDTH)" + severity failure; + + IOB_FX2_FIFO : iob_reg_o_gen + generic map ( + DWIDTH => 2, + INIT => '0') + port map ( + CLK => CLK, + CE => FX2_FIFO_CE, + DO => FX2_FIFO, + PAD => O_FX2_FIFO + ); + + IOB_FX2_FLAG : iob_reg_i_gen + generic map ( + DWIDTH => 4, + INIT => '0') + port map ( + CLK => CLK, + CE => '1', + DI => FX2_FLAG_N, + PAD => I_FX2_FLAG + ); + + IOB_FX2_SLRD : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => FX2_SLRD_N, + PAD => O_FX2_SLRD_N + ); + + IOB_FX2_SLWR : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => FX2_SLWR_N, + PAD => O_FX2_SLWR_N + ); + + IOB_FX2_SLOE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => FX2_SLOE_N, + PAD => O_FX2_SLOE_N + ); + + IOB_FX2_PKTEND : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => FX2_PKTEND_N, + PAD => O_FX2_PKTEND_N + ); + + IOB_FX2_DATA : iob_reg_io_gen + generic map ( + DWIDTH => 8, + PULL => "KEEP") + port map ( + CLK => CLK, + CEI => FX2_DATA_CEI, + CEO => FX2_DATA_CEO, + OE => FX2_DATA_OE, + DI => RXFIFO_DI, -- input data (read from pad) + DO => TXFIFO_DO, -- output data (write to pad) + PAD => IO_FX2_DATA + ); + + RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based + generic map ( + AWIDTH => RXFAWIDTH, + DWIDTH => 8) + port map ( + CLK => CLK, + RESET => RESET, + DI => RXFIFO_DI, + ENA => RXFIFO_ENA, + BUSY => RXFIFO_BUSY, + DO => RXDATA, + VAL => RXVAL, + HOLD => RXHOLD, + SIZE => RXSIZE + ); + + TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based + generic map ( + AWIDTH => TXFAWIDTH, + DWIDTH => 8) + port map ( + CLK => CLK, + RESET => RESET, + DI => TXDATA, + ENA => TXENA, + BUSY => TXBUSY_L, + DO => TXFIFO_DO, + VAL => TXFIFO_VAL, + HOLD => TXFIFO_HOLD, + SIZE => TXSIZE + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_USEC, + FX2_FLAG_N, TXFIFO_VAL, RXFIFO_BUSY, TXBUSY_L) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable idly_ld : slbit := '0'; + variable idly_val : slv(r.dlycnt'range) := (others=>'0'); + variable idly_end : slbit := '0'; + variable idly_end1 : slbit := '0'; + + variable iflag_rdok : slbit := '0'; + variable iflag_wrok : slbit := '0'; + + variable ififo_ce : slbit := '0'; + variable ififo : slv2 := "00"; + + variable irxfifo_ena : slbit := '0'; + variable itxfifo_hold : slbit := '0'; + + variable islrd : slbit := '0'; + variable islwr : slbit := '0'; + variable isloe : slbit := '0'; + variable ipktend : slbit := '0'; + + variable idata_cei : slbit := '0'; + variable idata_ceo : slbit := '0'; + variable idata_oe : slbit := '0'; + + variable imoni : fx2ctl_moni_type := fx2ctl_moni_init; + + procedure go_rdprep(nstate : out state_type; + idly_ld : out slbit; + idly_val : out slv4; + ififo_ce : out slbit; + ififo : out slv2) is + begin + idly_ld := '1'; + idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length)); + ififo_ce := '1'; + ififo := c_rxfifo; + nstate := s_rdprep; + end procedure go_rdprep; + + procedure go_wrprep(nstate : out state_type; + idly_ld : out slbit; + idly_val : out slv4; + ififo_ce : out slbit; + ififo : out slv2) is + begin + idly_ld := '1'; + idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length)); + ififo_ce := '1'; + ififo := c_txfifo; + nstate := s_wrprep; + end procedure go_wrprep; + + procedure go_peprep(nstate : out state_type; + idly_ld : out slbit; + idly_val : out slv4; + ififo_ce : out slbit; + ififo : out slv2) is + begin + idly_ld := '1'; + idly_val := slv(to_unsigned(FLAGDELAY-1, idly_val'length)); + ififo_ce := '1'; + ififo := c_txfifo; + nstate := s_peprep; + end procedure go_peprep; + + procedure go_rdpwl(nstate : out state_type; + idly_ld : out slbit; + idly_val : out slv4; + islrd : out slbit) is + begin + idly_ld := '1'; + idly_val := slv(to_unsigned(RDPWLDELAY-1, n.dlycnt'length)); + islrd := '1'; + nstate := s_rdpwl; + end procedure go_rdpwl; + + procedure go_wrpwl(nstate : out state_type; + idly_ld : out slbit; + idly_val : out slv4; + islwr : out slbit) is + begin + idly_ld := '1'; + idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length)); + islwr := '1'; + nstate := s_wrpwl; + end procedure go_wrpwl; + + procedure go_pepwl(nstate : out state_type; + idly_ld : out slbit; + idly_val : out slv4; + ipktend : out slbit) is + begin + idly_ld := '1'; + idly_val := slv(to_unsigned(WRPWLDELAY-1, n.dlycnt'length)); + ipktend := '1'; + nstate := s_pepwl; + end procedure go_pepwl; + + begin + + r := R_REGS; + n := R_REGS; + + ififo_ce := '0'; + ififo := "00"; + + irxfifo_ena := '0'; + itxfifo_hold := '1'; + + islrd := '0'; + islwr := '0'; + isloe := '0'; + ipktend := '0'; + + idata_cei := '0'; + idata_ceo := '0'; + idata_oe := '0'; + + imoni := fx2ctl_moni_init; + + iflag_rdok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low! + iflag_wrok := FX2_FLAG_N(c_flag_tx_ff); -- full flag is act.low! + + idly_ld := '0'; + idly_val := (others=>'0'); + idly_end := '1'; + idly_end1 := '0'; + if unsigned(r.dlycnt) /= 0 then + idly_end := '0'; + end if; + if unsigned(r.dlycnt) = 1 then + idly_end1 := '1'; + end if; + + case r.state is + when s_init => -- s_init: + go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + + when s_rdprep => -- s_rdprep: prepare read + if idly_end = '1' then + n.state := s_rdwait; + end if; + + when s_rdwait => -- s_rdwait: wait for data + if r.pepend='1' and TXFIFO_VAL='0' then + go_peprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + + elsif iflag_rdok='1' and + (RXFIFO_BUSY='0' and TXBUSY_L='0') then + go_rdpwl(n.state, idly_ld, idly_val, islrd); + + elsif TXFIFO_VAL = '1' then + go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + end if; + + when s_rdpwl => -- s_rdpwl: read, strobe low + idata_cei := '1'; + isloe := '1'; + if idly_end = '1' then + idly_ld := '1'; + idly_val := slv(to_unsigned(RDPWHDELAY-1, n.dlycnt'length)); + n.state := s_rdpwh; + else + islrd := '1'; + n.state := s_rdpwl; + end if; + + -- Note: data is sampled and written into rxfifo in 2nd last cycle in the + -- last cycle the rxfifo busy reflects therefore last written byte + -- and safely indicates whether another byte will fit. + when s_rdpwh => -- s_rdpwh: read, strobe high + idata_cei := '1'; + isloe := '1'; + if idly_end1 = '1' then -- 2nd last cycle + irxfifo_ena := '1'; -- capture rxdata + end if; + if idly_end = '1' then -- last cycle + if iflag_rdok='1' and + (RXFIFO_BUSY='0' and TXBUSY_L='0') then + go_rdpwl(n.state, idly_ld, idly_val, islrd); + + elsif TXFIFO_VAL = '1' then + go_wrprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + + else + n.state := s_rdwait; + end if; + end if; + + when s_wrprep => -- s_wrprep: prepare write + if idly_end = '1' then + if iflag_wrok = '1' then + go_wrpwl(n.state, idly_ld, idly_val, islwr); + else + go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + end if; + end if; + + when s_wrpwl => -- s_wrpwl: write, strobe low + idata_ceo := '1'; + idata_oe := '1'; + if idly_end = '1' then + idata_ceo := '0'; + itxfifo_hold := '0'; + idly_ld := '1'; + idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length)); + n.state := s_wrpwh; + else + islwr := '1'; + n.state := s_wrpwl; + end if; + + when s_wrpwh => -- s_wrpwh: write, strobe high + idata_oe := '1'; + if idly_end = '1' then + if iflag_wrok='1' and TXFIFO_VAL='1' then + go_wrpwl(n.state, idly_ld, idly_val, islwr); + elsif iflag_wrok='1' and r.pepend='1' and TXFIFO_VAL='0' then + go_pepwl(n.state, idly_ld, idly_val, ipktend); + else + go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + end if; + end if; + + when s_peprep => -- s_peprep: prepare pktend + if idly_end = '1' then + if iflag_wrok = '1' then + go_pepwl(n.state, idly_ld, idly_val, ipktend); + else + go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + end if; + end if; + + when s_pepwl => -- s_pepwl: pktend, strobe low + if idly_end = '1' then + idly_ld := '1'; + idly_val := slv(to_unsigned(WRPWHDELAY-1, n.dlycnt'length)); + n.state := s_pepwh; + else + ipktend := '1'; + n.state := s_pepwl; + end if; + + when s_pepwh => -- s_pepwh: pktend, strobe high + if idly_end = '1' then + n.pepend := '0'; + go_rdprep(n.state, idly_ld, idly_val, ififo_ce, ififo); + end if; + + when others => null; + end case; + + if idly_ld = '1' then + n.dlycnt := idly_val; + elsif idly_end = '0' then + n.dlycnt := slv(unsigned(r.dlycnt) - 1); + end if; + + -- pktend time-out handling: + -- if tx fifo is non-empty, set counter to max + -- if tx fifo is empty, count down every usec + -- on 1->0 transition queue pktend request + if TXFIFO_VAL = '1' then + n.petocnt := (others=>'1'); + else + if CE_USEC = '1' and unsigned(r.petocnt) /= 0 then + n.petocnt := slv(unsigned(r.petocnt) - 1); + if unsigned(r.petocnt) = 1 then + n.pepend := '1'; + end if; + end if; + end if; + + n.moni_ep4_sel := '0'; + n.moni_ep6_sel := '0'; + if r.state = s_wrprep or r.state = s_wrpwl or r.state = s_wrpwh or + r.state = s_peprep or r.state = s_pepwl or r.state = s_pepwh then + n.moni_ep6_sel := '1'; + n.moni_ep6_pf := not FX2_FLAG_N(c_flag_prog); + else + n.moni_ep4_sel := '1'; + n.moni_ep4_pf := not FX2_FLAG_N(c_flag_prog); + end if; + + imoni.fifo_ep4 := r.moni_ep4_sel; + imoni.fifo_ep6 := r.moni_ep6_sel; + imoni.flag_ep4_empty := not FX2_FLAG_N(c_flag_rx_ef); + imoni.flag_ep4_almost := r.moni_ep4_pf; + imoni.flag_ep6_full := not FX2_FLAG_N(c_flag_tx_ff); + imoni.flag_ep6_almost := r.moni_ep6_pf; + imoni.slrd := islrd; + imoni.slwr := islwr; + imoni.pktend := ipktend; + + N_REGS <= n; + + FX2_FIFO_CE <= ififo_ce; + FX2_FIFO <= ififo; + + FX2_SLRD_N <= not islrd; + FX2_SLWR_N <= not islwr; + FX2_SLOE_N <= not isloe; + FX2_PKTEND_N <= not ipktend; + + FX2_DATA_CEI <= idata_cei; + FX2_DATA_CEO <= idata_ceo; + FX2_DATA_OE <= idata_oe; + + RXFIFO_ENA <= irxfifo_ena; + TXFIFO_HOLD <= itxfifo_hold; + + MONI <= imoni; + + end process proc_next; + + proc_almost: process (RXSIZE, TXSIZE) + begin + + -- (rx|tx)size is the number of bytes in fifo + -- --> rxsize is number of bytes which can be read + -- --> 2**txfawidth-txsize is is number of bytes which can be written + + if unsigned(RXSIZE) <= RXAEMPTY_THRES then + RXAEMPTY <= '1'; + else + RXAEMPTY <= '0'; + end if; + + if unsigned(TXSIZE) >= 2**TXFAWIDTH-TXAFULL_THRES then + TXAFULL <= '1'; + else + TXAFULL <= '0'; + end if; + + end process proc_almost; + + TXBUSY <= TXBUSY_L; + +end syn; Index: fx2lib/fx2_2fifoctl_as.vbom =================================================================== --- fx2lib/fx2_2fifoctl_as.vbom (nonexistent) +++ fx2lib/fx2_2fifoctl_as.vbom (revision 24) @@ -0,0 +1,13 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +../../vlib/memlib/memlib.vhd +fx2lib.vhd +# components +../../vlib/xlib/iob_reg_o.vbom +../../vlib/xlib/iob_reg_i_gen.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/xlib/iob_reg_io_gen.vbom +../../vlib/memlib/fifo_1c_dram.vbom +# design +fx2_2fifoctl_as.vhd Index: fx2lib =================================================================== --- fx2lib (nonexistent) +++ fx2lib (revision 24)
fx2lib Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: issi/Makefile =================================================================== --- issi/Makefile (nonexistent) +++ issi/Makefile (revision 24) @@ -0,0 +1,22 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2007-12-14 101 1.0 Initial version +# +# +.PHONY : clean +# +clean : ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: issi/is61lv25616al.vhd =================================================================== --- issi/is61lv25616al.vhd (nonexistent) +++ issi/is61lv25616al.vhd (revision 24) @@ -0,0 +1,170 @@ +-- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: is61lv25616al - sim +-- Description: ISSI 61LV25612AL SRAM model +-- Currently a truely minimalistic functional model, without +-- any timing checks. It assumes, that addr/data is stable at +-- the trailing edge of we. +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-19 427 1.0.2 now numeric_std clean +-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted +-- 2007-12-14 101 1.0 Initial version (written on warsaw airport) +------------------------------------------------------------------------------ +-- Truth table accoring to data sheet: +-- +-- Mode WE_N CE_N OE_N LB_N UB_N D(7:0) D(15:8) +-- Not selected X H X X X high-Z high-Z +-- Output disabled H L H X X high-Z high-Z +-- X L X H H high-Z high-Z +-- Read H L L L H D_out high-Z +-- H L L H L high-Z D_out +-- H L L L L D_out D_out +-- Write L L X L H D_in high-Z +-- L L X H L high-Z D_in +-- L L X L L D_in D_in + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity is61lv25616al is -- ISSI 61LV25612AL SRAM model + port ( + CE_N : in slbit; -- chip enable (act.low) + OE_N : in slbit; -- output enable (act.low) + WE_N : in slbit; -- write enable (act.low) + UB_N : in slbit; -- upper byte enable (act.low) + LB_N : in slbit; -- lower byte enable (act.low) + ADDR : in slv18; -- address lines + DATA : inout slv16 -- data lines + ); +end is61lv25616al; + + +architecture sim of is61lv25616al is + + signal CE : slbit := '0'; + signal OE : slbit := '0'; + signal WE : slbit := '0'; + signal BE_L : slbit := '0'; + signal BE_U : slbit := '0'; + + component is61lv25616al_bank is -- ISSI 61LV25612AL bank + port ( + CE : in slbit; -- chip enable (act.high) + OE : in slbit; -- output enable (act.high) + WE : in slbit; -- write enable (act.high) + BE : in slbit; -- byte enable (act.high) + ADDR : in slv18; -- address lines + DATA : inout slv8 -- data lines + ); + end component; + +begin + + CE <= not CE_N; + OE <= not OE_N; + WE <= not WE_N; + BE_L <= not LB_N; + BE_U <= not UB_N; + + BANK_L : is61lv25616al_bank port map ( + CE => CE, + OE => OE, + WE => WE, + BE => BE_L, + ADDR => ADDR, + DATA => DATA(7 downto 0)); + + BANK_U : is61lv25616al_bank port map ( + CE => CE, + OE => OE, + WE => WE, + BE => BE_U, + ADDR => ADDR, + DATA => DATA(15 downto 8)); + +end sim; + +-- ---------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity is61lv25616al_bank is -- ISSI 61LV25612AL bank + port ( + CE : in slbit; -- chip enable (act.high) + OE : in slbit; -- output enable (act.high) + WE : in slbit; -- write enable (act.high) + BE : in slbit; -- byte enable (act.high) + ADDR : in slv18; -- address lines + DATA : inout slv8 -- data lines + ); +end is61lv25616al_bank; + +architecture sim of is61lv25616al_bank is + + constant T_rc : time := 10 ns; -- read cycle time (min) + constant T_aa : time := 10 ns; -- address access time (max) + constant T_oha : time := 2 ns; -- output hold time (min) + constant T_ace : time := 10 ns; -- ce access time (max) + constant T_doe : time := 4 ns; -- oe access time (max) + constant T_hzoe : time := 4 ns; -- oe to high-Z output (max) + constant T_lzoe : time := 0 ns; -- oe to low-Z output (min) + constant T_hzce : time := 4 ns; -- ce to high-Z output (min=0,max=4) + constant T_lzce : time := 3 ns; -- ce to low-Z output (min) + constant T_ba : time := 4 ns; -- lb,ub access time (max) + constant T_hzb : time := 3 ns; -- lb,ub to high-Z output (min=0,max=3) + constant T_lzb : time := 0 ns; -- lb,ub low-Z output (min) + + constant memsize : positive := 2**(ADDR'length); + constant datzero : slv(DATA'range) := (others=>'0'); + type ram_type is array (0 to memsize-1) of slv(DATA'range); + + signal WE_EFF : slbit := '0'; + +begin + + WE_EFF <= CE and WE and BE; + + proc_sram: process (CE, OE, WE, BE, WE_EFF, ADDR, DATA) + variable ram : ram_type := (others=>datzero); + begin + + if falling_edge(WE_EFF) then -- end of write cycle + -- note: to_x01 used below to prevent + -- that 'z' a written into mem. + ram(to_integer(unsigned(ADDR))) := to_x01(DATA); + end if; + + if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver + DATA <= ram(to_integer(unsigned(ADDR))); + else + DATA <= (others=>'Z'); + end if; + + end process proc_sram; + +end sim; Index: issi/is61lv25616al.vbom =================================================================== --- issi/is61lv25616al.vbom (nonexistent) +++ issi/is61lv25616al.vbom (revision 24) @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +is61lv25616al.vhd Index: issi =================================================================== --- issi (nonexistent) +++ issi (revision 24)
issi Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: s3board/tb/tb_s3board_fusp.vhd =================================================================== --- s3board/tb/tb_s3board_fusp.vhd (nonexistent) +++ s3board/tb/tb_s3board_fusp.vhd (revision 24) @@ -0,0 +1,233 @@ +-- $Id: tb_s3board_fusp.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_s3board_fusp - sim +-- Description: Test bench for s3board (base+fusp) +-- +-- Dependencies: simlib/simclk +-- simlib/simclkcnt +-- rlink/tb/tbcore_rlink +-- tb_s3board_core +-- s3board_fusp_aif [UUT] +-- serport/serport_uart_rxtx +-- +-- To test: generic, any s3board_fusp_aif target +-- +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface +-- 2011-11-19 427 3.0.1 now numeric_std clean +-- 2010-12-30 351 3.0 use rlink/tb now +-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50 +-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_ +-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp +-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8 +-- 2010-05-01 286 1.0 Initial version (derived from tb_s3board) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.rlinklib.all; +use work.rlinktblib.all; +use work.serportlib.all; +use work.s3boardlib.all; +use work.simlib.all; +use work.simbus.all; + +entity tb_s3board_fusp is +end tb_s3board_fusp; + +architecture sim of tb_s3board_fusp is + + signal CLK : slbit := '0'; + + signal CLK_STOP : slbit := '0'; + signal CLK_CYCLE : integer := 0; + + signal RESET : slbit := '0'; + signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !! + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal RX_HOLD : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + signal O_LED : slv8 := (others=>'0'); + signal O_ANO_N : slv4 := (others=>'0'); + signal O_SEG_N : slv8 := (others=>'0'); + + signal O_MEM_CE_N : slv2 := (others=>'1'); + signal O_MEM_BE_N : slv4 := (others=>'1'); + signal O_MEM_WE_N : slbit := '1'; + signal O_MEM_OE_N : slbit := '1'; + signal O_MEM_ADDR : slv18 := (others=>'Z'); + signal IO_MEM_DATA : slv32 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal UART_RESET : slbit := '0'; + signal UART_RXD : slbit := '1'; + signal UART_TXD : slbit := '1'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal R_PORTSEL : slbit := '0'; + + constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8)); + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK, + CLK_STOP => CLK_STOP + ); + + CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); + + TBCORE : tbcore_rlink + port map ( + CLK => CLK, + CLK_STOP => CLK_STOP, + RX_DATA => TXDATA, + RX_VAL => TXENA, + RX_HOLD => RX_HOLD, + TX_DATA => RXDATA, + TX_ENA => RXVAL + ); + + RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb + + S3CORE : entity work.tb_s3board_core + port map ( + I_SWI => I_SWI, + I_BTN => I_BTN, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + UUT : s3board_fusp_aif + port map ( + I_CLK50 => CLK, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => CLKDIV'length) + port map ( + CLK => CLK, + RESET => UART_RESET, + CLKDIV => CLKDIV, + RXSD => UART_RXD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => UART_TXD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N, + O_TXD, O_FUSP_TXD, O_FUSP_RTS_N) + begin + + if R_PORTSEL = '0' then -- use main board rs232, no flow cntl + I_RXD <= UART_TXD; -- write port 0 inputs + UART_RXD <= O_TXD; -- get port 0 outputs + RTS_N <= '0'; + I_FUSP_RXD <= '1'; -- port 1 inputs to idle state + I_FUSP_CTS_N <= '0'; + else -- otherwise use pmod1 rs232 + I_FUSP_RXD <= UART_TXD; -- write port 1 inputs + I_FUSP_CTS_N <= CTS_N; + UART_RXD <= O_FUSP_TXD; -- get port 1 outputs + RTS_N <= O_FUSP_RTS_N; + I_RXD <= '1'; -- port 0 inputs to idle state + end if; + + end process proc_port_mux; + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if RXERR = '1' then + writetimestamp(oline, CLK_CYCLE, " : seen RXERR=1"); + writeline(output, oline); + end if; + + end loop; + + end process proc_moni; + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_portsel then + R_PORTSEL <= to_x01(SB_DATA(0)); + end if; + end if; + end process proc_simbus; + +end sim; Index: s3board/tb/tb_s3board_fusp.vbom =================================================================== --- s3board/tb/tb_s3board_fusp.vbom (nonexistent) +++ s3board/tb/tb_s3board_fusp.vbom (revision 24) @@ -0,0 +1,22 @@ +# Not meant for direct top level usage. Used with +# tb_s3board_fusp_(....)[_ssim].vbom and config +# lines to generate the different cases. +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/rlink/rlinklib.vbom +../../../vlib/rlink/tb/rlinktblib.vhd +../../../vlib/serport/serportlib.vbom +../s3boardlib.vbom +../../../vlib/simlib/simlib.vhd +../../../vlib/simlib/simbus.vhd +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/rlink/tb/tbcore_rlink.vbom +tb_s3board_core.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +${s3board_fusp_aif := s3board_fusp_dummy.vbom} +# design +tb_s3board_fusp.vhd +@top:tb_s3board_fusp Index: s3board/tb/tb_s3board_core.vhd =================================================================== --- s3board/tb/tb_s3board_core.vhd (nonexistent) +++ s3board/tb/tb_s3board_core.vhd (revision 24) @@ -0,0 +1,101 @@ +-- $Id: tb_s3board_core.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_s3board_core - sim +-- Description: Test bench for s3board - core device handling +-- +-- Dependencies: vlib/parts/issi/is61lv25616al +-- +-- To test: generic, any s3board target +-- +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-19 427 1.0.2 now numeric_std clean +-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17 +-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.simbus.all; + +entity tb_s3board_core is + port ( + I_SWI : out slv8; -- s3 switches + I_BTN : out slv4; -- s3 buttons + O_MEM_CE_N : in slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : in slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : in slbit; -- sram: write enable (act.low) + O_MEM_OE_N : in slbit; -- sram: output enable (act.low) + O_MEM_ADDR : in slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end tb_s3board_core; + +architecture sim of tb_s3board_core is + + signal R_SWI : slv8 := (others=>'0'); + signal R_BTN : slv4 := (others=>'0'); + + constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8)); + constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8)); + +begin + + MEM_L : entity work.is61lv25616al + port map ( + CE_N => O_MEM_CE_N(0), + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA(15 downto 0) + ); + + MEM_U : entity work.is61lv25616al + port map ( + CE_N => O_MEM_CE_N(1), + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(3), + LB_N => O_MEM_BE_N(2), + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA(31 downto 16) + ); + + proc_simbus: process (SB_VAL) + begin + if SB_VAL'event and to_x01(SB_VAL)='1' then + if SB_ADDR = sbaddr_swi then + R_SWI <= to_x01(SB_DATA(R_SWI'range)); + end if; + if SB_ADDR = sbaddr_btn then + R_BTN <= to_x01(SB_DATA(R_BTN'range)); + end if; + end if; + end process proc_simbus; + + I_SWI <= R_SWI; + I_BTN <= R_BTN; + +end sim; Index: s3board/tb/tb_s3board_core.vbom =================================================================== --- s3board/tb/tb_s3board_core.vbom (nonexistent) +++ s3board/tb/tb_s3board_core.vbom (revision 24) @@ -0,0 +1,10 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/simlib/simbus.vhd +# components +../../../vlib/serport/serport_uart_rx.vbom +../../../vlib/serport/serport_uart_tx.vbom +../../issi/is61lv25616al.vbom +# design +tb_s3board_core.vhd Index: s3board/tb/Makefile =================================================================== --- s3board/tb/Makefile (nonexistent) +++ s3board/tb/Makefile (revision 24) @@ -0,0 +1,40 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.3 use includes from rtl/make +# 2010-05-16 291 1.2.2 rename tb_memctl_s3sram->tb_s3_sram_memctl +# 2010-05-01 286 1.2.1 add tb_s3board_usp_dummy +# 2009-11-21 252 1.2 add ISim support +# 2007-11-26 98 1.1 use make includes +# 2007-09-23 84 1.0 Initial version +# +EXE_all = tb_s3board_dummy +EXE_all += tb_s3board_fusp_dummy +EXE_all += tb_s3_sram_memctl +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: s3board/tb/tb_s3_sram_memctl.vbom =================================================================== --- s3board/tb/tb_s3_sram_memctl.vbom (nonexistent) +++ s3board/tb/tb_s3_sram_memctl.vbom (revision 24) @@ -0,0 +1,11 @@ +# libs +../../../vlib/slvtypes.vhd +../s3boardlib.vbom +../../../vlib/simlib/simlib.vhd +# components +../../../vlib/simlib/simclk.vbom +../../../vlib/simlib/simclkcnt.vbom +../../issi/is61lv25616al.vbom +${uut := ../s3_sram_memctl.vbom} +# design +tb_s3_sram_memctl.vhd Index: s3board/tb/tb_s3_sram_memctl.vhd =================================================================== --- s3board/tb/tb_s3_sram_memctl.vhd (nonexistent) +++ s3board/tb/tb_s3_sram_memctl.vhd (revision 24) @@ -0,0 +1,356 @@ +-- $Id: tb_s3_sram_memctl.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_s3_sram_memctl - sim +-- Description: Test bench for s3_sram_memctl +-- +-- Dependencies: vlib/simlib/simclk +-- vlib/simlib/simclkcnt +-- bplib/issi/is61lv25616al +-- s3_sram_memctl [UUT] +-- +-- To test: s3_sram_memctl +-- +-- Verified (with tb_s3_sram_memctl_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2007-12-16 101 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok +-- 2007-12-16 101 - 0.26 - - c:ok +-- +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 use new simclk/simclkcnt +-- 2011-11-21 432 1.0.6 now numeric_std clean +-- 2010-05-23 293 1.0.5 output # busy cycles; change CHK pipeline logic +-- 2010-05-16 291 1.0.4 rename tb_memctl_s3sram->tb_s3_sram_memctl +-- 2008-03-24 129 1.0.3 CLK_CYCLE now 31 bits +-- 2008-02-17 117 1.0.2 use req,we rather req_r,req_w interface +-- 2008-01-20 113 1.0.1 rename memdrv -> memctl_s3sram +-- 2007-12-15 101 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.s3boardlib.all; +use work.simlib.all; + +entity tb_s3_sram_memctl is +end tb_s3_sram_memctl; + +architecture sim of tb_s3_sram_memctl is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + signal REQ : slbit := '0'; + signal WE : slbit := '0'; + signal BUSY : slbit := '0'; + signal ACK_R : slbit := '0'; + signal ACK_W : slbit := '0'; + signal ACT_R : slbit := '0'; + signal ACT_W : slbit := '0'; + signal ADDR : slv18 := (others=>'0'); + signal BE : slv4 := (others=>'0'); + signal DI : slv32 := (others=>'0'); + signal DO : slv32 := (others=>'0'); + signal O_MEM_CE_N : slv2 := (others=>'0'); + signal O_MEM_BE_N : slv4 := (others=>'0'); + signal O_MEM_WE_N : slbit := '0'; + signal O_MEM_OE_N : slbit := '0'; + signal O_MEM_ADDR : slv18 := (others=>'0'); + signal IO_MEM_DATA : slv32 := (others=>'0'); + + signal R_MEMON : slbit := '0'; + signal N_CHK_DATA : slbit := '0'; + signal N_REF_DATA : slv32 := (others=>'0'); + signal N_REF_ADDR : slv18 := (others=>'0'); + signal R_CHK_DATA_AL : slbit := '0'; + signal R_REF_DATA_AL : slv32 := (others=>'0'); + signal R_REF_ADDR_AL : slv18 := (others=>'0'); + signal R_CHK_DATA_DL : slbit := '0'; + signal R_REF_DATA_DL : slv32 := (others=>'0'); + signal R_REF_ADDR_DL : slv18 := (others=>'0'); + + signal CLK_STOP : slbit := '0'; + signal CLK_CYCLE : integer := 0; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant setup_time : time := 5 ns; + constant c2out_time : time := 10 ns; + +begin + + CLKGEN : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK, + CLK_STOP => CLK_STOP + ); + + CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); + + MEM_L : entity work.is61lv25616al + port map ( + CE_N => O_MEM_CE_N(0), + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(1), + LB_N => O_MEM_BE_N(0), + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA(15 downto 0) + ); + + MEM_U : entity work.is61lv25616al + port map ( + CE_N => O_MEM_CE_N(1), + OE_N => O_MEM_OE_N, + WE_N => O_MEM_WE_N, + UB_N => O_MEM_BE_N(3), + LB_N => O_MEM_BE_N(2), + ADDR => O_MEM_ADDR, + DATA => IO_MEM_DATA(31 downto 16) + ); + + UUT : s3_sram_memctl + port map ( + CLK => CLK, + RESET => RESET, + REQ => REQ, + WE => WE, + BUSY => BUSY, + ACK_R => ACK_R, + ACK_W => ACK_W, + ACT_R => ACT_R, + ACT_W => ACT_W, + ADDR => ADDR, + BE => BE, + DI => DI, + DO => DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + proc_stim: process + file fstim : text open read_mode is "tb_s3_sram_memctl_stim"; + variable iline : line; + variable oline : line; + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + variable idelta : integer := 0; + variable iaddr : slv18 := (others=>'0'); + variable idata : slv32 := (others=>'0'); + variable ibe : slv4 := (others=>'0'); + variable ival : slbit := '0'; + variable nbusy : integer := 0; + + begin + + wait for clock_offset - setup_time; + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + if ok then + case dname is + when ".memon" => -- .memon + read_ea(iline, ival); + R_MEMON <= ival; + wait for 2*clock_period; + + when ".reset" => -- .reset + write(oline, string'(".reset")); + writeline(output, oline); + RESET <= '1'; + wait for clock_period; + RESET <= '0'; + wait for 9*clock_period; + + when ".wait " => -- .wait + read_ea(iline, idelta); + wait for idelta*clock_period; + + when "read " => -- read + readgen_ea(iline, iaddr, 16); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + REQ <= '1'; + WE <= '0'; + + writetimestamp(oline, CLK_CYCLE, ": stim read "); + writegen(oline, iaddr, right, 6, 16); + write(oline, string'(" ")); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + N_CHK_DATA <= '1', '0' after clock_period; + N_REF_DATA <= idata; + N_REF_ADDR <= iaddr; + + wait for clock_period; + REQ <= '0'; + + when "write " => -- write + readgen_ea(iline, iaddr, 16); + read_ea(iline, ibe); + readgen_ea(iline, idata, 16); + ADDR <= iaddr; + BE <= ibe; + DI <= idata; + REQ <= '1'; + WE <= '1'; + + writetimestamp(oline, CLK_CYCLE, ": stim write"); + writegen(oline, iaddr, right, 6, 16); + writegen(oline, ibe , right, 5, 2); + writegen(oline, idata, right, 9, 16); + + nbusy := 0; + while BUSY = '1' loop + nbusy := nbusy + 1; + wait for clock_period; + end loop; + + write(oline, string'(" nbusy=")); + write(oline, nbusy, right, 2); + writeline(output, oline); + + wait for clock_period; + REQ <= '0'; + + when others => -- bad directive + write(oline, string'("?? unknown directive: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + else + report "failed to find command" severity failure; + + end if; + + testempty_ea(iline); + + end loop; -- file fstim + + wait for 10*clock_period; + + writetimestamp(oline, CLK_CYCLE, ": DONE "); + writeline(output, oline); + + CLK_STOP <= '1'; + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + + proc_moni: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if ACK_R = '1' then + writetimestamp(oline, CLK_CYCLE, ": moni "); + writegen(oline, DO, right, 9, 16); + if R_CHK_DATA_DL = '1' then + write(oline, string'(" CHECK")); + if R_REF_DATA_DL = DO then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL, exp=")); + writegen(oline, R_REF_DATA_DL, right, 9, 16); + write(oline, string'(" for a=")); + writegen(oline, R_REF_ADDR_DL, right, 5, 16); + end if; + R_CHK_DATA_DL <= '0'; + end if; + writeline(output, oline); + end if; + + if R_CHK_DATA_AL = '1' then + R_CHK_DATA_DL <= R_CHK_DATA_AL; + R_REF_DATA_DL <= R_REF_DATA_AL; + R_REF_ADDR_DL <= R_REF_ADDR_AL; + R_CHK_DATA_AL <= '0'; + end if; + if N_CHK_DATA = '1' then + R_CHK_DATA_AL <= N_CHK_DATA; + R_REF_DATA_AL <= N_REF_DATA; + R_REF_ADDR_AL <= N_REF_ADDR; + end if; + + end loop; + + end process proc_moni; + + + proc_memon: process + variable oline : line; + begin + + loop + wait until rising_edge(CLK); + + if R_MEMON = '1' then + writetimestamp(oline, CLK_CYCLE, ": mem "); + write(oline, string'(" ce=")); + write(oline, not O_MEM_CE_N, right, 2); + write(oline, string'(" be=")); + write(oline, not O_MEM_BE_N, right, 4); + write(oline, string'(" we=")); + write(oline, not O_MEM_WE_N, right); + write(oline, string'(" oe=")); + write(oline, not O_MEM_OE_N, right); + write(oline, string'(" a=")); + writegen(oline, O_MEM_ADDR, right, 5, 16); + write(oline, string'(" d=")); + writegen(oline, IO_MEM_DATA, right, 8, 16); + writeline(output, oline); + end if; + + end loop; + + end process proc_memon; + + +end sim; Index: s3board/tb/tb_s3_sram_memctl_stim.dat =================================================================== --- s3board/tb/tb_s3_sram_memctl_stim.dat (nonexistent) +++ s3board/tb/tb_s3_sram_memctl_stim.dat (revision 24) @@ -0,0 +1,176 @@ +# $Id: tb_s3_sram_memctl_stim.dat 290 2010-05-16 08:44:36Z mueller $ +# +.memon 0 +# +C write full word 16 cells +# +write 00000 1111 30201000 +write 00001 1111 31211101 +write 00002 1111 32221202 +write 00003 1111 33231303 +write 00004 1111 34241404 +write 00005 1111 35251505 +write 00006 1111 36261606 +write 00007 1111 37271707 +write 00008 1111 38281808 +write 00009 1111 39291909 +write 0000a 1111 3a2a1a0a +write 0000b 1111 3b2b1b0b +write 0000c 1111 3c2c1c0c +write 0000d 1111 3d2d1d0d +write 0000e 1111 3e2e1e0e +write 0000f 1111 3f2f1f0f +# +C read 16 cells +# +read 00000 30201000 +read 00001 31211101 +read 00002 32221202 +read 00003 33231303 +read 00004 34241404 +read 00005 35251505 +read 00006 36261606 +read 00007 37271707 +read 00008 38281808 +read 00009 39291909 +read 0000a 3a2a1a0a +read 0000b 3b2b1b0b +read 0000c 3c2c1c0c +read 0000d 3d2d1d0d +read 0000e 3e2e1e0e +read 0000f 3f2f1f0f +# +C write selected bytes in first 16 cells +# +write 00000 0000 70605040 +write 00001 0001 71615141 +write 00002 0010 72625242 +write 00003 0011 73635343 +write 00004 0100 74645444 +write 00005 0101 75655545 +write 00006 0110 76665646 +write 00007 0111 77675747 +write 00008 1000 78685848 +write 00009 1001 79695949 +write 0000a 1010 7a6a5a4a +write 0000b 1011 7b6b5b4b +write 0000c 1100 7c6c5c4c +write 0000d 1101 7d6d5d4d +write 0000e 1110 7e6e5e4e +write 0000f 1111 7f6f5f4f +# +C read back +# +read 00000 30201000 +read 00001 31211141 +read 00002 32225202 +read 00003 33235343 +read 00004 34641404 +read 00005 35651545 +read 00006 36665606 +read 00007 37675747 +read 00008 78281808 +read 00009 79291949 +read 0000a 7a2a5a0a +read 0000b 7b2b5b4b +read 0000c 7c6c1c0c +read 0000d 7d6d1d4d +read 0000e 7e6e5e0e +read 0000f 7f6f5f4f +# +C read and write with waits +# +.wait 3 +write 00010 1111 30201000 +.wait 2 +write 00011 1111 31211101 +.wait 1 +write 00012 1111 32221202 +write 00013 1111 33231303 +# +.wait 3 +read 00010 30201000 +.wait 2 +read 00011 31211101 +.wait 1 +read 0000e 7e6e5e0e +read 0000f 7f6f5f4f +# +C read and write mixed, with waits +# +.wait 2 +write 00014 1111 34241404 +.wait 2 +read 00012 32221202 +.wait 2 +write 00015 1111 35251505 +.wait 2 +read 00013 33231303 +# +.wait 1 +write 00016 1111 36261606 +.wait 1 +read 00014 34241404 +.wait 1 +write 00017 1111 37271707 +.wait 1 +read 00015 35251505 +# +write 00018 1111 38281808 +read 00016 36261606 +write 00019 1111 39291909 +read 00017 37271707 +# +.wait 2 +write 0001a 1111 3a2a1a0a +write 0001b 1111 3b2b1b0b +.wait 2 +read 00018 38281808 +read 00019 39291909 +.wait 2 +write 0001c 1111 3c2c1c0c +write 0001d 1111 3d2d1d0d +.wait 2 +read 0001a 3a2a1a0a +read 0001b 3b2b1b0b +# +.wait 1 +write 0001e 1111 3e2e1e0e +write 0001f 1111 3f2f1f0f +.wait 1 +read 0001c 3c2c1c0c +read 0001d 3d2d1d0d +.wait 1 +write 00014 0100 74645444 +write 00015 0101 75655545 +.wait 1 +read 0001e 3e2e1e0e +read 0001f 3f2f1f0f +# +write 00016 0110 76665646 +write 00017 0111 77675747 +read 00010 30201000 +read 00011 31211101 +write 00018 1000 78685848 +write 00019 1001 79695949 +read 00012 32221202 +read 00013 33231303 +# +write 0001a 1010 7a6a5a4a +write 0001b 1011 7b6b5b4b +write 0001c 1100 7c6c5c4c +read 00014 34641404 +read 00015 35651545 +read 00016 36665606 +write 0001d 1101 7d6d5d4d +write 0001e 1110 7e6e5e4e +write 0001f 1111 7f6f5f4f +read 00017 37675747 +read 00018 78281808 +read 00019 79291949 +read 0001a 7a2a5a0a +read 0001b 7b2b5b4b +read 0001c 7c6c1c0c +read 0001d 7d6d1d4d +read 0001e 7e6e5e0e +read 0001f 7f6f5f4f Index: s3board/tb/s3board_fusp_dummy.vhd =================================================================== --- s3board/tb/s3board_fusp_dummy.vhd (nonexistent) +++ s3board/tb/s3board_fusp_dummy.vhd (revision 24) @@ -0,0 +1,78 @@ +-- $Id: s3board_fusp_dummy.vhd 336 2010-11-06 18:28:27Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s3board_fusp_dummy - syn +-- Description: s3board minimal target (base+fusp; serport loopback) +-- +-- Dependencies: - +-- To test: tb_s3board_fusp +-- Target Devices: generic +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2010-11-06 336 1.0.3 rename input pin CLK -> I_CLK50 +-- 2010-05-21 292 1.0.2 rename _PM1_ -> _FUSP_ +-- 2010-05-16 291 1.0.1 rename s3board_usp_dummy->s3board_fusp_dummy +-- 2010-05-01 286 1.0 Initial version (derived from s3board_dummy) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.s3boardlib.all; + +entity s3board_fusp_dummy is -- S3BOARD dummy (base+fusp; loopback) + -- implements s3board_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end s3board_fusp_dummy; + +architecture syn of s3board_fusp_dummy is + +begin + + O_TXD <= I_RXD; + O_FUSP_TXD <= I_FUSP_RXD; + O_FUSP_RTS_N <= I_FUSP_CTS_N; + + SRAM : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; Index: s3board/tb/s3board_fusp_dummy.vbom =================================================================== --- s3board/tb/s3board_fusp_dummy.vbom (nonexistent) +++ s3board/tb/s3board_fusp_dummy.vbom (revision 24) @@ -0,0 +1,7 @@ +# libs +../../../vlib/slvtypes.vhd +../s3boardlib.vbom +# components +../s3_sram_dummy.vbom +# design +s3board_fusp_dummy.vhd Index: s3board/tb/tb_s3_sram_memctl_ssim.vbom =================================================================== --- s3board/tb/tb_s3_sram_memctl_ssim.vbom (nonexistent) +++ s3board/tb/tb_s3_sram_memctl_ssim.vbom (revision 24) @@ -0,0 +1,4 @@ +# configure for _*sim case +uut = s3_sram_memctl_ssim.vhd +tb_s3_sram_memctl.vbom +@top:tb_s3_sram_memctl Index: s3board/tb/tbw.dat =================================================================== --- s3board/tb/tbw.dat (nonexistent) +++ s3board/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 353 2011-01-02 21:02:48Z mueller $ +# +[tb_s3board_dummy] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: s3board/tb/.cvsignore =================================================================== --- s3board/tb/.cvsignore (nonexistent) +++ s3board/tb/.cvsignore (revision 24) @@ -0,0 +1,13 @@ +tb_s3board_dummy +tb_s3board_dummy_[sft]sim +tb_s3board_dummy_ISim +tb_s3board_dummy_ISim_[sft]sim +tb_s3board_fusp_dummy +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tb_s3_sram_memctl +tb_s3_sram_memctl_[sft]sim +tb_s3_sram_memctl_stim +tb_s3_sram_memctl_ISim +tb_s3_sram_memctl_ISim_[sft]sim Index: s3board/tb =================================================================== --- s3board/tb (nonexistent) +++ s3board/tb (revision 24)
s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,45 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_s3board_dummy +tb_s3board_dummy_[sft]sim +tb_s3board_dummy_ISim +tb_s3board_dummy_ISim_[sft]sim +tb_s3board_fusp_dummy +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tb_s3_sram_memctl +tb_s3_sram_memctl_[sft]sim +tb_s3_sram_memctl_stim +tb_s3_sram_memctl_ISim +tb_s3_sram_memctl_ISim_[sft]sim Index: s3board/Makefile =================================================================== --- s3board/Makefile (nonexistent) +++ s3board/Makefile (revision 24) @@ -0,0 +1,27 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2007-12-09 100 1.0.1 drop ISE_p definition +# 2007-09-16 83 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: s3board/s3_sram_dummy.vhd =================================================================== --- s3board/s3_sram_dummy.vhd (nonexistent) +++ s3board/s3_sram_dummy.vhd (revision 24) @@ -0,0 +1,56 @@ +-- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s3_sram_dummy - syn +-- Description: s3board: SRAM protection dummy +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2010-04-17 278 1.0.2 renamed from sram_dummy +-- 2007-12-09 101 1.0.1 use _N for active low +-- 2007-12-08 100 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity s3_sram_dummy is -- SRAM protection dummy + port ( + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end s3_sram_dummy; + + +architecture syn of s3_sram_dummy is +begin + + O_MEM_CE_N <= "11"; -- disable sram chips + O_MEM_BE_N <= "1111"; + O_MEM_WE_N <= '1'; + O_MEM_OE_N <= '1'; + O_MEM_ADDR <= (others=>'0'); + IO_MEM_DATA <= (others=>'0'); + +end syn; Index: s3board/s3boardlib.vhd =================================================================== --- s3board/s3boardlib.vhd (nonexistent) +++ s3board/s3boardlib.vhd (revision 24) @@ -0,0 +1,126 @@ +-- $Id: s3boardlib.vhd 426 2011-11-18 18:14:08Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: s3boardlib +-- Description: S3BOARD components +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib +-- 2011-07-08 390 1.3.4 move s3_(dispdrv|humanio*) to bpgenlib +-- 2011-07-03 387 1.3.3 move s3_rs232_iob_(int|ext) to bpgenlib +-- 2010-12-30 351 1.3.2 use rblib; rename human s3_humanio_rri -> _rbus +-- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50 +-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib) +-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_ +-- 2010-05-16 291 1.2.1 rename memctl_s3sram -> s3_sram_memctl; _usp->_fusp +-- 2010-05-01 286 1.2 added s3board_usp_aif (base+pm1_rs232) +-- 2010-04-17 278 1.1.6 rename, prefix dispdrv,sram_summy with s3_; +-- add s3_rs232_iob_(int|ext|int_ext) +-- 2010-04-11 276 1.1.5 add DEBOUNCE for s3_humanio +-- 2010-04-10 275 1.1.4 add s3_humanio +-- 2008-02-17 117 1.1.3 memctl_s3sram: use req,we interface +-- 2008-01-20 113 1.1.2 rename memdrv -> memctl_s3sram +-- 2007-12-16 101 1.1.1 use _N for active low +-- 2007-12-09 100 1.1 add sram memory signals; sram_dummy; memdrv +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package s3boardlib is + +component s3board_aif is -- S3BOARD, abstract iface, base + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end component; + +component s3board_fusp_aif is -- S3BOARD, abstract iface, base+fusp + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end component; + +component s3_sram_dummy is -- SRAM protection dummy + port ( + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end component; + +component s3_sram_memctl is -- SRAM driver + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv18; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end component; + +end package s3boardlib; Index: s3board/s3_sram_memctl.vhd =================================================================== --- s3board/s3_sram_memctl.vhd (nonexistent) +++ s3board/s3_sram_memctl.vhd (revision 24) @@ -0,0 +1,366 @@ +-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s3_sram_memctl - syn +-- Description: s3board: SRAM driver +-- +-- Dependencies: vlib/xlib/iob_reg_o +-- vlib/xlib/iob_reg_o_gen +-- vlib/xlib/iob_reg_io_gen +-- Test bench: tb/tb_s3_sram_memctl +-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3 +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-05-23 293 11.4 L68 xc3s1000-4 7 22 0 14 s 8.5 +-- 2008-02-16 116 8.2.03 I34 xc3s1000-4 5 30 0 17 s 7.0 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-19 427 1.0.6 now numeric_std clean +-- 2010-06-03 299 1.0.5 add "KEEP" for data iob; +-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl +-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface +-- 2008-01-20 113 1.0.2 rename memdrv -> memctl_s3sram +-- 2007-12-15 101 1.0.1 use _N for active low; get ce/we clocking right +-- 2007-12-08 100 1.0 Initial version +-- +-- Timing of some signals: +-- +-- single read request: +-- +-- state |_idle |_read |_idle | +-- +-- CLK __|^^^|___|^^^|___|^^^|___|^ +-- +-- REQ _______|^^^^^|______________ +-- WE ____________________________ +-- +-- IOB_CE __________|^^^^^^^|_________ +-- IOB_OE __________|^^^^^^^|_________ +-- +-- DO oooooooooooooooooo|ddddddd|d +-- BUSY ____________________________ +-- ACK_R __________________|^^^^^^^|_ +-- +-- single write request: +-- +-- state |_idle |_write1|_write2|_idle | +-- +-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^ +-- +-- REQ _______|^^^^^|______________ +-- WE _______|^^^^^|______________ +-- +-- IOB_CE __________|^^^^^^^^^^^^^^^|_________ +-- IOB_BE __________|^^^^^^^^^^^^^^^|_________ +-- IOB_OE ____________________________________ +-- IOB_WE ______________|^^^^^^^|_____________ +-- +-- BUSY __________|^^^^^^^|_________________ +-- ACK_W __________________|^^^^^^^|_________ +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; + +entity s3_sram_memctl is -- SRAM driver for S3BOARD + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv18; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end s3_sram_memctl; + + +architecture syn of s3_sram_memctl is + + type state_type is ( + s_idle, -- s_idle: wait for req + s_read, -- s_read: read cycle + s_write1, -- s_write1: write cycle, 1st half + s_write2, -- s_write2: write cycle, 2nd half + s_bta_r2w, -- s_bta_r2w: bus turn around: r->w + s_bta_w2r -- s_bta_w2r: bus turn around: w->r + ); + + type regs_type is record + state : state_type; -- state + ackr : slbit; -- signal ack_r + end record regs_type; + + constant regs_init : regs_type := ( + s_idle, + '0' -- ackr + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal CLK_180 : slbit := '0'; + signal MEM_CE_N : slv2 := "00"; + signal MEM_BE_N : slv4 := "0000"; + signal MEM_WE_N : slbit := '0'; + signal MEM_OE_N : slbit := '0'; + signal ADDR_CE : slbit := '0'; + signal DATA_CEI : slbit := '0'; + signal DATA_CEO : slbit := '0'; + signal DATA_OE : slbit := '0'; + +begin + + CLK_180 <= not CLK; + + IOB_MEM_CE : iob_reg_o_gen + generic map ( + DWIDTH => 2, + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_CE_N, + PAD => O_MEM_CE_N + ); + + IOB_MEM_BE : iob_reg_o_gen + generic map ( + DWIDTH => 4, + INIT => '1') + port map ( + CLK => CLK, + CE => ADDR_CE, + DO => MEM_BE_N, + PAD => O_MEM_BE_N + ); + + IOB_MEM_WE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK_180, + CE => '1', + DO => MEM_WE_N, + PAD => O_MEM_WE_N + ); + + IOB_MEM_OE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_OE_N, + PAD => O_MEM_OE_N + ); + + IOB_MEM_ADDR : iob_reg_o_gen + generic map ( + DWIDTH => 18) + port map ( + CLK => CLK, + CE => ADDR_CE, + DO => ADDR, + PAD => O_MEM_ADDR + ); + + IOB_MEM_DATA : iob_reg_io_gen + generic map ( + DWIDTH => 32, + PULL => "KEEP") + port map ( + CLK => CLK, + CEI => DATA_CEI, + CEO => DATA_CEO, + OE => DATA_OE, + DI => DO, + DO => DI, + PAD => IO_MEM_DATA + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, REQ, WE, BE) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibusy : slbit := '0'; + variable iackw : slbit := '0'; + variable iactr : slbit := '0'; + variable iactw : slbit := '0'; + variable imem_ce : slv2 := "00"; + variable imem_be : slv4 := "0000"; + variable imem_we : slbit := '0'; + variable imem_oe : slbit := '0'; + variable iaddr_ce : slbit := '0'; + variable idata_cei : slbit := '0'; + variable idata_ceo : slbit := '0'; + variable idata_oe : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + n.ackr := '0'; + + ibusy := '0'; + iackw := '0'; + iactr := '0'; + iactw := '0'; + + imem_ce := "00"; + imem_be := "1111"; + imem_we := '0'; + imem_oe := '0'; + iaddr_ce := '0'; + idata_cei := '0'; + idata_ceo := '0'; + idata_oe := '0'; + + case r.state is + when s_idle => -- s_idle: wait for req + if REQ = '1' then -- if IO requested + if WE = '0' then -- if READ requested + iaddr_ce := '1'; -- latch address and be's + imem_ce := "11"; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + n.state := s_read; -- next: read + else -- if WRITE requested + iaddr_ce := '1'; -- latch address and be's + idata_ceo := '1'; -- latch output data + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := "11"; -- ce SRAM next cycle + imem_be := BE; -- use request BE's + n.state := s_write1; -- next: write 1st part + end if; + end if; + + when s_read => -- s_read: read cycle + idata_cei := '1'; -- latch input data + iactr := '1'; -- signal mem read + n.ackr := '1'; -- ACK_R next cycle + if REQ = '1' then -- if IO requested + if WE = '0' then -- if READ requested + iaddr_ce := '1'; -- latch address and be's + imem_ce := "11"; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + n.state := s_read; -- next: continue read + else -- if WRITE requested + iaddr_ce := '1'; -- latch address and be's + idata_ceo := '1'; -- latch output data + imem_be := BE; -- use request BE's + n.state := s_bta_r2w; -- next: bus turn around cycle + end if; + else + n.state := s_idle; -- next: idle if nothing to do + end if; + + when s_write1 => -- s_write1: write cycle, 1st half + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := "11"; -- ce SRAM next cycle + imem_we := '1'; -- we SRAM next shifted cycle + n.state := s_write2; -- next: write cycle, 2nd half + + when s_write2 => -- s_write2: write cycle, 2nd half + iactw := '1'; -- signal mem write + iackw := '1'; -- signal write acknowledge + idata_cei := '1'; -- latch input data (from SRAM) + if REQ = '1' then -- if IO requested + if WE = '1' then -- if WRITE requested + iaddr_ce := '1'; -- latch address and be's + idata_ceo := '1'; -- latch output data + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := "11"; -- ce SRAM next cycle + imem_be := BE; -- use request BE's + n.state := s_write1; -- next: continue read + else -- if READ requested + iaddr_ce := '1'; -- latch address and be's + n.state := s_bta_w2r; -- next: bus turn around cycle + end if; + else + n.state := s_idle; -- next: idle if nothing to do + end if; + + when s_bta_r2w => -- s_bta_r2w: bus turn around: r->w + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + imem_ce := "11"; -- ce SRAM next cycle + idata_oe := '1'; -- oe FPGA next cycle + n.state := s_write1; -- next: start write + + when s_bta_w2r => -- s_bta_w2r: bus turn around: w->r + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := "11"; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + n.state := s_read; -- next: start read + + when others => null; + end case; + + N_REGS <= n; + + MEM_CE_N <= not imem_ce; + MEM_WE_N <= not imem_we; + MEM_BE_N <= not imem_be; + MEM_OE_N <= not imem_oe; + ADDR_CE <= iaddr_ce; + DATA_CEI <= idata_cei; + DATA_CEO <= idata_ceo; + DATA_OE <= idata_oe; + + BUSY <= ibusy; + ACK_R <= r.ackr; + ACK_W <= iackw; + ACT_R <= iactr; + ACT_W <= iactw; + + end process proc_next; + +end syn; Index: s3board/s3board_pins.ucf =================================================================== --- s3board/s3board_pins.ucf (nonexistent) +++ s3board/s3board_pins.ucf (revision 24) @@ -0,0 +1,133 @@ +## $Id: s3board_pins.ucf 402 2011-08-05 18:56:44Z mueller $ +## +## Pin locks for S3BOARD core functionality: +## - internal RS232 +## - human I/O (switches, buttons, leds, display) +## - sram +## +## Revision History: +## Date Rev Version Comment +## 2010-11-06 336 1.1.1 Rename CLK -> I_CLK50 +## 2008-05-25 150 1.1 Use DRIVE=6|SLEW=SLOW|KEEPER for memory data lines +## 2008-02-17 101 1.0 Initial version +## +## Note: default is DRIVE=12 | SLEW=SLOW +## +## clocks -------------------------------------------------------------------- +NET "I_CLK50" LOC = "t9" | IOSTANDARD=LVCMOS33; +## +## RS232 interface ----------------------------------------------------------- +NET "I_RXD" LOC = "t13" | IOSTANDARD=LVCMOS33; +NET "O_TXD" LOC = "r13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## switches and buttons ------------------------------------------------------ +NET "I_SWI<0>" LOC = "f12" | IOSTANDARD=LVCMOS33; +NET "I_SWI<1>" LOC = "g12" | IOSTANDARD=LVCMOS33; +NET "I_SWI<2>" LOC = "h14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<3>" LOC = "h13" | IOSTANDARD=LVCMOS33; +NET "I_SWI<4>" LOC = "j14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<5>" LOC = "j13" | IOSTANDARD=LVCMOS33; +NET "I_SWI<6>" LOC = "k14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<7>" LOC = "k13" | IOSTANDARD=LVCMOS33; +## +NET "I_BTN<0>" LOC = "m13" | IOSTANDARD=LVCMOS33; +NET "I_BTN<1>" LOC = "m14" | IOSTANDARD=LVCMOS33; +NET "I_BTN<2>" LOC = "l13" | IOSTANDARD=LVCMOS33; +NET "I_BTN<3>" LOC = "l14" | IOSTANDARD=LVCMOS33; +## +## LEDs ---------------------------------------------------------------------- +NET "O_LED<0>" LOC = "k12" | IOSTANDARD=LVCMOS33; +NET "O_LED<1>" LOC = "p14" | IOSTANDARD=LVCMOS33; +NET "O_LED<2>" LOC = "l12" | IOSTANDARD=LVCMOS33; +NET "O_LED<3>" LOC = "n14" | IOSTANDARD=LVCMOS33; +NET "O_LED<4>" LOC = "p13" | IOSTANDARD=LVCMOS33; +NET "O_LED<5>" LOC = "n12" | IOSTANDARD=LVCMOS33; +NET "O_LED<6>" LOC = "p12" | IOSTANDARD=LVCMOS33; +NET "O_LED<7>" LOC = "p11" | IOSTANDARD=LVCMOS33; +NET "O_LED<*>" DRIVE=12 | SLEW=SLOW; +## +## 7 segment display --------------------------------------------------------- +NET "O_ANO_N<0>" LOC = "d14" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<1>" LOC = "g14" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<2>" LOC = "f14" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<3>" LOC = "e13" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW; +## +NET "O_SEG_N<0>" LOC = "e14" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<1>" LOC = "g13" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<2>" LOC = "n15" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<3>" LOC = "p15" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<4>" LOC = "r16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<5>" LOC = "f13" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<6>" LOC = "n16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<7>" LOC = "p16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW; +## +## SRAM ---------------------------------------------------------------------- +NET "O_MEM_CE_N<0>" LOC = "p7" | IOSTANDARD=LVCMOS33; +NET "O_MEM_CE_N<1>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_CE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_BE_N<0>" LOC = "p6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<1>" LOC = "t4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<2>" LOC = "p5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<3>" LOC = "r4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_WE_N" LOC = "g3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_OE_N" LOC = "k4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_ADDR<0>" LOC = "l5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<1>" LOC = "n3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<2>" LOC = "m4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<3>" LOC = "m3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<4>" LOC = "l4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<5>" LOC = "g4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<6>" LOC = "f3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<7>" LOC = "f4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<8>" LOC = "e3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<9>" LOC = "e4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<10>" LOC = "g5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<11>" LOC = "h3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<12>" LOC = "h4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<13>" LOC = "j4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<14>" LOC = "j3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<15>" LOC = "k3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<16>" LOC = "k5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<17>" LOC = "l3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST; +## +NET "IO_MEM_DATA<0>" LOC = "n7" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<1>" LOC = "t8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<2>" LOC = "r6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<3>" LOC = "t5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<4>" LOC = "r5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<5>" LOC = "c2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<6>" LOC = "c1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<7>" LOC = "b1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<8>" LOC = "d3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<9>" LOC = "p8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<10>" LOC = "f2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<11>" LOC = "h1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<12>" LOC = "j2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<13>" LOC = "l2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<14>" LOC = "p1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<15>" LOC = "r1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<16>" LOC = "p2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<17>" LOC = "n2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<18>" LOC = "m2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<19>" LOC = "k1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<20>" LOC = "j1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<21>" LOC = "g2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<22>" LOC = "e1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<23>" LOC = "d1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<24>" LOC = "d2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<25>" LOC = "e2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<26>" LOC = "g1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<27>" LOC = "f5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<28>" LOC = "c3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<29>" LOC = "k2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<30>" LOC = "m1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<31>" LOC = "n1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## Index: s3board/s3boardlib.vbom =================================================================== --- s3board/s3boardlib.vbom (nonexistent) +++ s3board/s3boardlib.vbom (revision 24) @@ -0,0 +1,3 @@ +# libs +../../vlib/slvtypes.vhd +s3boardlib.vhd Index: s3board/s3board_a2_pm1_rs232.ucf =================================================================== --- s3board/s3board_a2_pm1_rs232.ucf (nonexistent) +++ s3board/s3board_a2_pm1_rs232.ucf (revision 24) @@ -0,0 +1,15 @@ +## $Id: s3board_a2_pm1_rs232.ucf 295 2010-05-29 16:58:01Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-05-22 293 1.1 Rename PM1 -> FUSP +## 2010-04-24 281 1.0 Initial version +## +## expansion connector A2 / slot PMod 1 / usage RS232 for FTDI USB serport --- +## +## PmodRS232: pins: 1 RTS; 2 CTS; 3 RXD; 4 TXD; 5 GND; 6 VCC +## +NET "O_FUSP_RTS_N" LOC = "c6" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "e7" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "c7" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "d7" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; Index: s3board/s3_sram_dummy.vbom =================================================================== --- s3board/s3_sram_dummy.vbom (nonexistent) +++ s3board/s3_sram_dummy.vbom (revision 24) @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +s3_sram_dummy.vhd Index: s3board/s3_sram_memctl.vbom =================================================================== --- s3board/s3_sram_memctl.vbom (nonexistent) +++ s3board/s3_sram_memctl.vbom (revision 24) @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_o.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/xlib/iob_reg_io_gen.vbom +# design +s3_sram_memctl.vhd Index: s3board =================================================================== --- s3board (nonexistent) +++ s3board (revision 24)
s3board Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: micron/mt45w8mw16b.vhd =================================================================== --- micron/mt45w8mw16b.vhd (nonexistent) +++ micron/mt45w8mw16b.vhd (revision 24) @@ -0,0 +1,243 @@ +-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: mt45w8mw16b - sim +-- Description: Micron MT45W8MW16B CellularRAM model +-- Currently a much simplified model +-- - only async accesses +-- - ignores CLK and CRE +-- - simple model for response of DATA lines, but no +-- check for timing violations of control lines +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-19 427 1.3.2 now numeric_std clean +-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa) +-- 2010-06-03 298 1.3 add timing model again +-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now +-- 2010-05-21 293 1.1 add BCR (only read of default so far) +-- 2010-05-16 291 1.0 Initial version (inspired by is61lv25616al) +------------------------------------------------------------------------------ +-- Truth table accoring to data sheet: +-- +-- Asynchronous Mode (BCR(15)=1) +-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA +-- Read L L L L H L L act data-out +-- Write L L L X L L L act data-in +-- Standby L X H X X L X 'z' 'z' +-- CRE write L L L H L H X act 'z' +-- CRE read L L L L H H L act conf-out +-- +-- Burst Mode (BCR(15)=0) +-- Operation CLK ADV_N CE_N OE_N WE_N CRE xB_N WT DATA +-- Async read L L L L H L L act data-out +-- Async write L L L X L L L act data-in +-- Standby L X H X X L X 'z' 'z' +-- Initial burst read 0-1 L L X H L L act X +-- Initial burst write 0-1 L L H L L X act X +-- Burst continue 0-1 H L X X X X act data-in/out +-- CRE write 0-1 L L H L H X act 'z' +-- CRE read 0-1 L L L H H L act conf-out +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; + +entity mt45w8mw16b is -- Micron MT45W8MW16B CellularRAM model + port ( + CLK : in slbit; -- clock for synchonous operation + CE_N : in slbit; -- chip enable (act.low) + OE_N : in slbit; -- output enable (act.low) + WE_N : in slbit; -- write enable (act.low) + UB_N : in slbit; -- upper byte enable (act.low) + LB_N : in slbit; -- lower byte enable (act.low) + ADV_N : in slbit; -- address valid (act.low) + CRE : in slbit; -- control register enable + MWAIT : out slbit; -- wait (for burst read/write) + ADDR : in slv23; -- address lines + DATA : inout slv16 -- data lines + ); +end mt45w8mw16b; + + +architecture sim of mt45w8mw16b is + + -- timing constants for -701 speed grade (70 ns; 104 MHz) + constant T_aa : time := 70 ns; -- address access time (max) + constant T_apa : time := 20 ns; -- page acess time (max) + constant T_oh : time := 5 ns; -- output hold from addr change (max) + constant T_oe : time := 20 ns; -- output enable to valid output (max) + constant T_ohz : time := 8 ns; -- output disable to high-z output (max) + constant T_olz : time := 3 ns; -- output enable to low-z output (min) + constant T_lz : time := 10 ns; -- chip enable to low-z output (min) + constant T_hz : time := 8 ns; -- chip disable to high-z output (max) + + constant memsize : positive := 2**(ADDR'length); + constant datzero : slv(DATA'range) := (others=>'0'); + type ram_type is array (0 to memsize-1) of slv(DATA'range); + + constant bcr_f_mode : integer := 15; -- operating mode + constant bcr_f_ilat : integer := 14; -- initial latency + subtype bcr_f_lc is integer range 13 downto 11; -- latency counter + constant bcr_f_wp : integer := 10; -- wait polarity + constant bcr_f_wc : integer := 8; -- wait configuration + subtype bcr_f_drive is integer range 5 downto 4; -- drive strength + constant bcr_f_bw : integer := 3; -- burst wrap + subtype bcr_f_bl is integer range 2 downto 0; -- burst length + + subtype f_byte1 is integer range 15 downto 8; + subtype f_byte0 is integer range 7 downto 0; + + signal CE : slbit := '0'; + signal OE : slbit := '0'; + signal WE : slbit := '0'; + signal BE_L : slbit := '0'; + signal BE_U : slbit := '0'; + signal ADV : slbit := '0'; + signal WE_L_EFF : slbit := '0'; + signal WE_U_EFF : slbit := '0'; + + signal R_BCR_MODE : slbit := '1'; -- mode: def: async + signal R_BCR_ILAT : slbit := '0'; -- ilat: def: variable + signal R_BCR_LC : slv3 := "011"; -- lc: def: code 3 + signal R_BCR_WP : slbit := '1'; -- wp: def: active high + signal R_BCR_WC : slbit := '1'; -- wc: def: assert one before + signal R_BCR_DRIVE : slv2 := "01"; -- drive:def: 1/2 + signal R_BCR_BW : slbit := '1'; -- bw: def: no wrap + signal R_BCR_BL : slv3 := "111"; -- bl: def: continuous + + signal L_ADDR : slv23 := (others=>'0'); + signal DOUT_VAL_EN : slbit := '0'; + signal DOUT_VAL_AA : slbit := '0'; + signal DOUT_VAL_PA : slbit := '0'; + signal DOUT_VAL_OE : slbit := '0'; + signal DOUT_LZ_CE : slbit := '0'; + signal DOUT_LZ_OE : slbit := '0'; + + signal OEWE : slbit := '0'; + signal DOUT : slv16 := (others=>'0'); +begin + + CE <= not CE_N; + OE <= not OE_N; + WE <= not WE_N; + BE_L <= not LB_N; + BE_U <= not UB_N; + ADV <= not ADV_N; + + WE_L_EFF <= CE and WE and BE_L; + WE_U_EFF <= CE and WE and BE_U; + + -- address valid logic, latch ADDR when ADV true + proc_adv: process (ADV, ADDR) + begin + if ADV = '1' then + L_ADDR <= ADDR; + end if; + end process proc_adv; + + proc_dout_val: process (CE, OE, WE, BE_L, BE_U, ADV, L_ADDR) + variable addr_last : slv23 := (others=>'1'); + begin + if (CE'event and CE='1') or + (BE_L'event and BE_L='1') or + (BE_U'event and BE_U='1') or + (WE'event and WE='0') or + (ADV'event and ADV='1') then + DOUT_VAL_EN <= '0', '1' after T_aa; + end if; + if L_ADDR'event then + DOUT_VAL_PA <= '0', '1' after T_apa; + if L_ADDR(22 downto 4) /= addr_last(22 downto 4) then + DOUT_VAL_AA <= '0', '1' after T_aa; + end if; + addr_last := L_ADDR; + end if; + if rising_edge(OE) then + DOUT_VAL_OE <= '0', '1' after T_oe; + end if; + end process proc_dout_val; + + -- to simplify things assume that OE and (not WE) have same effect on output + -- drivers. The timing rules are very similar indeed... + OEWE <= OE and (not WE); + + proc_dout_lz: process (CE, OEWE) + begin + if (CE'event) then + if CE = '1' then + DOUT_LZ_CE <= '1' after T_lz; + else + DOUT_LZ_CE <= '0' after T_hz; + end if; + end if; + if (OEwe'event) then + if OEWE = '1' then + DOUT_LZ_OE <= '1' after T_olz; + else + DOUT_LZ_OE <= '0' after T_ohz; + end if; + end if; + end process proc_dout_lz; + + proc_cram: process (CE, OE, WE, WE_L_EFF, WE_U_EFF, L_ADDR, DATA) + variable ram : ram_type := (others=>datzero); + begin + + -- end of write cycle + -- note: to_x01 used below to prevent that 'z' a written into mem. + if falling_edge(WE_L_EFF) then + ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0)); + end if; + if falling_edge(WE_U_EFF) then + ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1)); + end if; + + DOUT <= ram(to_integer(unsigned(L_ADDR))); + + end process proc_cram; + + proc_data: process (DOUT, DOUT_VAL_EN, DOUT_VAL_AA, DOUT_VAL_PA, DOUT_VAL_OE, + DOUT_LZ_CE, DOUT_LZ_OE) + variable idout : slv16 := (others=>'0'); + begin + idout := DOUT; + if DOUT_VAL_EN='0' or DOUT_VAL_AA='0' or + DOUT_VAL_PA='0' or DOUT_VAL_OE='0' then + idout := (others=>'X'); + end if; + if DOUT_LZ_CE='0' or DOUT_LZ_OE='0' then + idout := (others=>'Z'); + end if; + DATA <= idout; + end process proc_data; + + proc_mwait: process (CE) + begin + -- WT driver (just a dummy) + if CE = '1' then + MWAIT <= '1'; + else + MWAIT <= 'Z'; + end if; + end process proc_mwait; + +end sim; Index: micron/mt45w8mw16b.vbom =================================================================== --- micron/mt45w8mw16b.vbom (nonexistent) +++ micron/mt45w8mw16b.vbom (revision 24) @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +mt45w8mw16b.vhd Index: micron =================================================================== --- micron (nonexistent) +++ micron (revision 24)
micron Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: . =================================================================== --- . (nonexistent) +++ . (revision 24)
. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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