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/w11/tags/w11a_V0.6/rtl/ibus
- from Rev 21 to Rev 24
- ↔ Reverse comparison
Rev 21 → Rev 24
/ibdr_pc11.vhd
0,0 → 1,323
-- $Id: ibdr_pc11.vhd 515 2013-05-04 17:28:59Z mueller $ |
-- |
-- Copyright 2009-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibdr_pc11 - syn |
-- Description: ibus dev(rem): PC11 |
-- |
-- Dependencies: - |
-- Test bench: xxdp: zpcae0 |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.3; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0 |
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2013-05-04 515 1.3 BUGFIX: r.rbuf was immediately cleared ! Was broken |
-- since ibus V2 update, never tested afterwards... |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; |
-- 2010-10-17 333 1.2 use ibus V2 interface |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now |
-- causes interrupt, if enabled; validated with zpcae0 |
-- 2009-06-01 221 0.9 Initial version (untested) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_pc11 is -- ibus dev(rem): PC11 |
-- fixed address: 177550 |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ_PTR : out slbit; -- interrupt request, reader |
EI_REQ_PTP : out slbit; -- interrupt request, punch |
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader |
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch |
); |
end ibdr_pc11; |
|
architecture syn of ibdr_pc11 is |
|
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16)); |
|
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset |
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset |
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset |
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset |
|
constant rcsr_ibf_rerr : integer := 15; |
constant rcsr_ibf_rbusy : integer := 11; |
constant rcsr_ibf_rdone : integer := 7; |
constant rcsr_ibf_rie : integer := 6; |
constant rcsr_ibf_renb : integer := 0; |
|
constant pcsr_ibf_perr : integer := 15; |
constant pcsr_ibf_prdy : integer := 7; |
constant pcsr_ibf_pie : integer := 6; |
|
constant pbuf_ibf_pval : integer := 8; |
constant pbuf_ibf_rbusy : integer := 9; |
|
type regs_type is record -- state registers |
ibsel : slbit; -- ibus select |
rerr : slbit; -- rcsr: reader error |
rbusy : slbit; -- rcsr: reader busy |
rdone : slbit; -- rcsr: reader done |
rie : slbit; -- rcsr: reader interrupt enable |
rbuf : slv8; -- rbuf: |
rintreq : slbit; -- ptr interrupt request |
perr : slbit; -- pcsr: punch error |
prdy : slbit; -- pcsr: punch ready |
pie : slbit; -- pcsr: punch interrupt enable |
pbuf : slv8; -- pbuf: |
pintreq : slbit; -- ptp interrupt request |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- ibsel |
'1', -- rerr (init=1!) |
'0','0','0', -- rbusy,rdone,rie |
(others=>'0'), -- rbuf |
'0', -- rintreq |
'1', -- perr (init=1!) |
'1', -- prdy (init=1!) |
'0', -- pie |
(others=>'0'), -- pbuf |
'0' -- pintreq |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
begin |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if BRESET = '1' then -- BRESET is 1 for system and ibus reset |
R_REGS <= regs_init; -- |
if RESET = '0' then -- if RESET=0 we do just an ibus reset |
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag |
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag |
end if; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable idout : slv16 := (others=>'0'); |
variable ibreq : slbit := '0'; |
variable ibrd : slbit := '0'; |
variable ibw0 : slbit := '0'; |
variable ibw1 : slbit := '0'; |
variable ilam : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
idout := (others=>'0'); |
ibreq := IB_MREQ.re or IB_MREQ.we; |
ibrd := IB_MREQ.re; |
ibw0 := IB_MREQ.we and IB_MREQ.be0; |
ibw1 := IB_MREQ.we and IB_MREQ.be1; |
ilam := '0'; |
|
-- ibus address decoder |
n.ibsel := '0'; |
if IB_MREQ.aval='1' and |
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then |
n.ibsel := '1'; |
end if; |
|
-- ibus transactions |
if r.ibsel = '1' then |
case IB_MREQ.addr(2 downto 1) is |
|
when ibaddr_rcsr => -- RCSR -- reader control status ----- |
|
idout(rcsr_ibf_rerr) := r.rerr; |
idout(rcsr_ibf_rbusy) := r.rbusy; |
idout(rcsr_ibf_rdone) := r.rdone; |
idout(rcsr_ibf_rie) := r.rie; |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibw0 = '1' then |
n.rie := IB_MREQ.din(rcsr_ibf_rie); |
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1 |
if r.rie = '0' and -- IE 0->1 transition |
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set |
(r.rerr='1' or r.rdone='1') then -- but err or done set |
n.rintreq := '1'; -- request interrupt |
end if; |
else -- set IE to 0 |
n.rintreq := '0'; -- cancel interrupts |
end if; |
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB |
if r.rerr = '0' then -- if not in error state |
n.rbusy := '1'; -- set busy |
n.rdone := '0'; -- clear done |
n.rbuf := (others=>'0'); -- clear buffer |
n.rintreq := '0'; -- cancel interrupt |
ilam := '1'; -- rri lam |
else -- if in error state |
if r.rie = '1' then -- if interrupts on |
n.rintreq := '1'; -- request interrupt |
end if; |
end if; |
end if; |
end if; |
|
else -- rri --------------------- |
if ibw1 = '1' then |
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit |
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition |
and r.rerr='0' then |
n.rbusy := '0'; -- clear busy |
n.rdone := '0'; -- clear done |
if r.rie = '1' then -- if interrupts on |
n.rintreq := '1'; -- request interrupt |
end if; |
end if; |
end if; |
end if; |
|
when ibaddr_rbuf => -- RBUF -- reader data buffer -------- |
|
idout(r.rbuf'range) := r.rbuf; |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibreq = '1' then -- !! PC11 is unusual !! |
n.rdone := '0'; -- *any* read or write will clear done |
n.rbuf := (others=>'0'); -- and the reader buffer |
n.rintreq := '0'; -- also interrupt is canceled |
end if; |
|
else -- rri --------------------- |
if ibw0 = '1' then |
n.rbuf := IB_MREQ.din(n.rbuf'range); |
n.rbusy := '0'; |
n.rdone := '1'; |
if r.rie = '1' then |
n.rintreq := '1'; |
end if; |
end if; |
end if; |
|
when ibaddr_pcsr => -- PCSR -- punch control status ------ |
|
idout(pcsr_ibf_perr) := r.perr; |
idout(pcsr_ibf_prdy) := r.prdy; |
idout(pcsr_ibf_pie) := r.pie; |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibw0 = '1' then |
n.pie := IB_MREQ.din(pcsr_ibf_pie); |
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1 |
if r.pie='0' and -- IE 0->1 transition |
(r.perr='1' or r.prdy='1') then -- but err or done set |
n.pintreq := '1'; -- request interrupt |
end if; |
else -- set IE to 0 |
n.pintreq := '0'; -- cancel interrupts |
end if; |
end if; |
|
else -- rri --------------------- |
if ibw1 = '1' then |
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit |
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition |
and r.perr='0' then |
n.prdy := '1'; -- set ready |
if r.pie = '1' then -- if interrupts on |
n.pintreq := '1'; -- request interrupt |
end if; |
end if; |
end if; |
end if; |
|
when ibaddr_pbuf => -- PBUF -- punch data buffer --------- |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibw0 = '1' then |
if r.perr = '0' then -- if not in error state |
n.pbuf := IB_MREQ.din(n.pbuf'range); |
n.prdy := '0'; -- clear ready |
n.pintreq := '0'; -- cancel interrupts |
ilam := '1'; -- rri lam |
else -- if in error state |
if r.pie = '1' then -- if interrupts on |
n.pintreq := '1'; -- request interrupt |
end if; |
end if; |
end if; |
|
else -- rri --------------------- |
idout(r.pbuf'range) := r.pbuf; |
idout(pbuf_ibf_pval) := not r.prdy; |
idout(pbuf_ibf_rbusy) := r.rbusy; |
if ibrd = '1' then |
n.prdy := '1'; |
if r.pie = '1' then |
n.pintreq := '1'; |
end if; |
end if; |
end if; |
|
when others => null; |
end case; |
|
end if; |
|
-- other state changes |
if EI_ACK_PTR = '1' then |
n.rintreq := '0'; |
end if; |
if EI_ACK_PTP = '1' then |
n.pintreq := '0'; |
end if; |
|
N_REGS <= n; |
|
IB_SRES.dout <= idout; |
IB_SRES.ack <= r.ibsel and ibreq; |
IB_SRES.busy <= '0'; |
|
RB_LAM <= ilam; |
EI_REQ_PTR <= r.rintreq; |
EI_REQ_PTP <= r.pintreq; |
|
end process proc_next; |
|
|
end syn; |
/ibdr_lp11.vhd
0,0 → 1,217
-- $Id: ibdr_lp11.vhd 515 2013-05-04 17:28:59Z mueller $ |
-- |
-- Copyright 2009-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibdr_lp11 - syn |
-- Description: ibus dev(rem): LP11 |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.3; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 12 35 0 24 s 5.6 |
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2013-05-04 515 1.3 BUGFIX: r.err was cleared in racc read ! |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; |
-- 2010-10-17 333 1.2 use ibus V2 interface |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1 |
-- 2009-05-30 220 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- Notes: |
-- - the ERR bit is just a status flag |
-- - no hardware interlock (DONE forced 0 when ERR=1), like in simh |
-- - also no interrupt when ERR goes 1, like in simh |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_lp11 is -- ibus dev(rem): LP11 |
-- fixed address: 177514 |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end ibdr_lp11; |
|
architecture syn of ibdr_lp11 is |
|
constant ibaddr_lp11 : slv16 := slv(to_unsigned(8#177514#,16)); |
|
constant ibaddr_csr : slv1 := "0"; -- csr address offset |
constant ibaddr_buf : slv1 := "1"; -- buf address offset |
|
constant csr_ibf_err : integer := 15; |
constant csr_ibf_done : integer := 7; |
constant csr_ibf_ie : integer := 6; |
constant buf_ibf_val : integer := 8; |
|
type regs_type is record -- state registers |
ibsel : slbit; -- ibus select |
err : slbit; -- csr: error flag |
done : slbit; -- csr: done flag |
ie : slbit; -- csr: interrupt enable |
buf : slv7; -- buf: |
intreq : slbit; -- interrupt request |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- ibsel |
'1', -- err !! is set !! |
'1', -- done !! is set !! |
'0', -- ie |
(others=>'0'), -- buf |
'0' -- intreq |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
begin |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if BRESET = '1' then -- BRESET is 1 for system and ibus reset |
R_REGS <= regs_init; |
if RESET = '0' then -- if RESET=0 we do just an ibus reset |
R_REGS.err <= N_REGS.err; -- don't reset ERR flag |
end if; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, IB_MREQ, EI_ACK) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable idout : slv16 := (others=>'0'); |
variable ibreq : slbit := '0'; |
variable ibrd : slbit := '0'; |
variable ibw0 : slbit := '0'; |
variable ibw1 : slbit := '0'; |
variable ilam : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
idout := (others=>'0'); |
ibreq := IB_MREQ.re or IB_MREQ.we; |
ibrd := IB_MREQ.re; |
ibw0 := IB_MREQ.we and IB_MREQ.be0; |
ibw1 := IB_MREQ.we and IB_MREQ.be1; |
ilam := '0'; |
|
-- ibus address decoder |
n.ibsel := '0'; |
if IB_MREQ.aval='1' and |
IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then |
n.ibsel := '1'; |
end if; |
|
-- ibus transactions |
if r.ibsel = '1' then |
case IB_MREQ.addr(1 downto 1) is |
|
when ibaddr_csr => -- CSR -- control status ------------- |
idout(csr_ibf_err) := r.err; |
idout(csr_ibf_done) := r.done; |
idout(csr_ibf_ie) := r.ie; |
if IB_MREQ.racc = '0' then -- cpu |
if ibw0 = '1' then |
n.ie := IB_MREQ.din(csr_ibf_ie); |
if IB_MREQ.din(csr_ibf_ie) = '1' then |
if r.done='1' and r.ie='0' then -- ie set while done=1 |
n.intreq := '1'; -- request interrupt |
end if; |
else |
n.intreq := '0'; |
end if; |
end if; |
else -- rri |
if ibw1 = '1' then |
n.err := IB_MREQ.din(csr_ibf_err); |
end if; |
end if; |
|
when ibaddr_buf => -- BUF -- data buffer ---------------- |
if IB_MREQ.racc = '0' then -- cpu |
if ibw0 = '1' then |
n.buf := IB_MREQ.din(n.buf'range); |
if r.err = '0' then -- if online (handle via rbus) |
ilam := '1'; -- request attention |
n.done := '0'; -- clear done |
n.intreq := '0'; -- clear interrupt |
else -- if offline (discard locally) |
n.done := '1'; -- set done |
if r.ie = '1' then -- if interrupts enabled |
n.intreq := '1'; -- request interrupt |
end if; |
end if; |
end if; |
else -- rri |
idout(r.buf'range) := r.buf; |
idout(buf_ibf_val) := not r.done; |
if ibrd = '1' then |
n.done := '1'; |
if r.ie = '1' then |
n.intreq := '1'; |
end if; |
end if; |
end if; |
|
when others => null; |
end case; |
|
end if; |
|
-- other state changes |
if EI_ACK = '1' then |
n.intreq := '0'; |
end if; |
|
N_REGS <= n; |
|
IB_SRES.dout <= idout; |
IB_SRES.ack <= r.ibsel and ibreq; |
IB_SRES.busy <= '0'; |
|
RB_LAM <= ilam; |
EI_REQ <= r.intreq; |
|
end process proc_next; |
|
|
end syn; |
/Makefile
0,0 → 1,27
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-08-13 405 1.1 use includes from rtl/make |
# 2008-08-22 161 1.0 Initial version |
# |
VBOM_all = $(wildcard *.vbom) |
NGC_all = $(VBOM_all:.vbom=.ngc) |
# |
# reference board for test synthesis is Spartan-6 based Nexys3 |
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk |
# |
.PHONY : all clean |
# |
all : $(NGC_all) |
# |
clean : ise_clean |
# |
#---- |
# |
include $(RETROBASE)/rtl/make/generic_xflow.mk |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
endif |
# |
/ibdr_dl11.vhd
0,0 → 1,349
-- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibdr_dl11 - syn |
-- Description: ibus dev(rem): DL11-A/B |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6 |
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3 |
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; |
-- 2010-10-17 333 1.2 use ibus V2 interface |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit |
-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list |
-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK |
-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change) |
-- 2008-01-27 115 1.0.3 bugfix: set ilam when rbuf read by cpu; |
-- add xdone and rrdy bits to rri xbuf read |
-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now) |
-- 2008-01-20 112 1.0.1 use BRESET |
-- 2008-01-05 108 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B |
generic ( |
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16))); |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ_RX : out slbit; -- interrupt request, receiver |
EI_REQ_TX : out slbit; -- interrupt request, transmitter |
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver |
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter |
); |
end ibdr_dl11; |
|
architecture syn of ibdr_dl11 is |
|
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset |
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset |
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset |
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset |
|
subtype rcsr_ibf_rrlim is integer range 14 downto 12; |
constant rcsr_ibf_rdone : integer := 7; |
constant rcsr_ibf_rie : integer := 6; |
|
constant xcsr_ibf_xrdy : integer := 7; |
constant xcsr_ibf_xie : integer := 6; |
constant xcsr_ibf_xmaint: integer := 2; |
|
constant xbuf_ibf_xval : integer := 8; |
constant xbuf_ibf_rrdy : integer := 9; |
|
type regs_type is record -- state registers |
ibsel : slbit; -- ibus select |
rrlim : slv3; -- rcsr: receiver rate limit |
rdone : slbit; -- rcsr: receiver done |
rie : slbit; -- rcsr: receiver interrupt enable |
rbuf : slv8; -- rbuf: |
rval : slbit; -- rx rbuf valid |
rintreq : slbit; -- rx interrupt request |
rdlybsy : slbit; -- rx delay busy |
rdlycnt : slv10; -- rx delay counter |
xrdy : slbit; -- xcsr: transmitter ready |
xie : slbit; -- xcsr: transmitter interrupt enable |
xmaint : slbit; -- xcsr: maintenance mode |
xbuf : slv8; -- xbuf: |
xintreq : slbit; -- tx interrupt request |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- ibsel |
(others=>'0'), -- rrlim |
'0','0', -- rdone, rie |
(others=>'0'), -- rbuf |
'0','0','0', -- rval,rintreq,rdlybsy |
(others=>'0'), -- rdlycnt |
'1', -- xrdy !! is set !! |
'0','0', -- xie,xmaint |
(others=>'0'), -- xbuf |
'0' -- xintreq |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
begin |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if BRESET = '1' then |
R_REGS <= regs_init; |
if RESET = '0' then -- if RESET=0 we do just an ibus reset |
R_REGS.rrlim <= N_REGS.rrlim; -- don't reset rx rate limit |
R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy |
R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter |
end if; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable idout : slv16 := (others=>'0'); |
variable ibreq : slbit := '0'; |
variable ibrd : slbit := '0'; |
variable ibw0 : slbit := '0'; |
variable ibw1 : slbit := '0'; |
variable ilam : slbit := '0'; |
variable rdlystart : slbit := '0'; |
variable rdlyinit : slv10 := (others=>'0'); |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
idout := (others=>'0'); |
ibreq := IB_MREQ.re or IB_MREQ.we; |
ibrd := IB_MREQ.re; |
ibw0 := IB_MREQ.we and IB_MREQ.be0; |
ibw1 := IB_MREQ.we and IB_MREQ.be1; |
ilam := '0'; |
rdlystart := '0'; |
|
-- ibus address decoder |
n.ibsel := '0'; |
if IB_MREQ.aval='1' and |
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then |
n.ibsel := '1'; |
end if; |
|
-- ibus transactions |
if r.ibsel = '1' then |
case IB_MREQ.addr(2 downto 1) is |
|
when ibaddr_rcsr => -- RCSR -- receive control status ---- |
idout(rcsr_ibf_rdone) := r.rdone; |
idout(rcsr_ibf_rie) := r.rie; |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibw0 = '1' then |
n.rie := IB_MREQ.din(rcsr_ibf_rie); |
if IB_MREQ.din(rcsr_ibf_rie) = '1' then |
if r.rdone='1' and r.rie='0' then -- ie set while done=1 |
n.rintreq := '1'; -- request interrupt |
end if; |
else |
n.rintreq := '0'; |
end if; |
end if; |
|
else -- rri --------------------- |
idout(rcsr_ibf_rrlim) := r.rrlim; |
if ibw1 = '1' then |
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim); |
end if; |
end if; |
|
when ibaddr_rbuf => -- RBUF -- receive data buffer ------- |
|
idout(r.rbuf'range) := r.rbuf; |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibrd = '1' then |
n.rdone := '0'; -- clear DONE |
n.rval := '0'; -- clear rbuf valid |
n.rintreq := '0'; -- clear pending interrupts |
rdlystart := '1'; -- start rx delay counter |
if r.xmaint = '0' then -- if not in loop-back |
ilam := '1'; -- request rb attention |
end if; |
end if; |
|
else -- rri --------------------- |
if ibw0 = '1' then |
n.rbuf := IB_MREQ.din(n.rbuf'range); |
n.rval := '1'; -- set rbuf valid |
if r.rdlybsy = '0' then -- if rdly timer not running |
n.rdone := '1'; -- set DONE |
if r.rie = '1' then -- if rx interrupt enabled |
n.rintreq := '1'; -- request interrupt |
end if; |
end if; |
end if; |
end if; |
|
when ibaddr_xcsr => -- XCSR -- transmit control status --- |
|
idout(xcsr_ibf_xrdy) := r.xrdy; |
idout(xcsr_ibf_xie) := r.xie; |
idout(xcsr_ibf_xmaint):= r.xmaint; |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibw0 = '1' then |
n.xie := IB_MREQ.din(xcsr_ibf_xie); |
if IB_MREQ.din(xcsr_ibf_xie) = '1' then |
if r.xrdy='1' and r.xie='0' then -- ie set while ready=1 |
n.xintreq := '1'; -- request interrupt |
end if; |
else |
n.xintreq := '0'; |
end if; |
n.xmaint := IB_MREQ.din(xcsr_ibf_xmaint); |
end if; |
end if; |
|
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------ |
|
if IB_MREQ.racc = '0' then -- cpu --------------------- |
if ibw0 = '1' then |
n.xbuf := IB_MREQ.din(n.xbuf'range); |
n.xrdy := '0'; |
n.xintreq := '0'; |
if r.xmaint = '0' then |
ilam := '1'; |
end if; |
end if; |
|
else -- rri --------------------- |
idout(r.xbuf'range) := r.xbuf; |
if r.xmaint = '0' then -- if not in maintenace mode |
idout(xbuf_ibf_xval) := not r.xrdy; |
idout(xbuf_ibf_rrdy) := not r.rval; |
end if; |
if ibrd = '1' then |
n.xrdy := '1'; |
if r.xie = '1' then |
n.xintreq := '1'; |
end if; |
end if; |
end if; |
|
when others => null; |
end case; |
|
else -- if unselected handle loop-back |
if r.xmaint = '1' and -- if in maintenace mode |
r.xrdy='0' and -- and transmit pending |
r.rdone='0' and -- and receive buffer empty |
r.rdlybsy='0' then -- and rdly timer not running |
n.rbuf := r.xbuf; -- copy transmit to receive buffer |
n.xrdy := '1'; -- mark transmit done |
n.rdone := '1'; -- make receive done |
if r.rie = '1' then -- if rx interrupt enabled |
n.rintreq := '1'; -- request it |
end if; |
if r.xie = '1' then -- if tx interrupt enabled |
n.xintreq := '1'; -- request it |
end if; |
end if; |
|
end if; |
|
-- other state changes |
|
rdlyinit := (others=>'0'); |
case r.rrlim is |
when "000" => rdlyinit := "0000000000"; -- rlim=0 -> disabled |
when "001" => rdlyinit := "0000000011"; -- rlim=1 -> delay by 3+ usec |
when "010" => rdlyinit := "0000001111"; -- rlim=2 -> delay by 15+ usec |
when "011" => rdlyinit := "0000111111"; -- rlim=3 -> delay by 63+ usec |
when "100" => rdlyinit := "0001111111"; -- rlim=4 -> delay by 127+ usec |
when "101" => rdlyinit := "0011111111"; -- rlim=5 -> delay by 255+ usec |
when "110" => rdlyinit := "0111111111"; -- rlim=6 -> delay by 511+ usec |
when "111" => rdlyinit := "1111111111"; -- rlim=7 -> delay by 1023+ usec |
when others => null; |
end case; |
|
if rdlystart = '1' then -- if rdly timer start requested |
n.rdlycnt := rdlyinit; -- init counter |
if r.rrlim /= "000" then -- rate limiter enabled ? |
n.rdlybsy := '1'; -- set busy |
end if; |
elsif CE_USEC = '1' then -- if end-of-usec |
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement |
if r.rdlybsy='1' and -- if delay busy |
unsigned(r.rdlycnt) = 0 then -- and counter at zero |
n.rdlybsy := '0'; -- clear busy |
if n.rval = '1' then -- if rbuf is valid or is set |
-- valid this cycle (use n.!!) |
n.rdone := '1'; -- set DONE |
if r.rie = '1' then -- if rx interrupt enabled |
n.rintreq := '1'; -- request interrupt |
end if; |
end if; |
end if; |
end if; |
|
if EI_ACK_RX = '1' then |
n.rintreq := '0'; |
end if; |
if EI_ACK_TX = '1' then |
n.xintreq := '0'; |
end if; |
|
N_REGS <= n; |
|
IB_SRES.dout <= idout; |
IB_SRES.ack <= r.ibsel and ibreq; |
IB_SRES.busy <= '0'; |
|
RB_LAM <= ilam; |
EI_REQ_RX <= r.rintreq; |
EI_REQ_TX <= r.xintreq; |
|
end process proc_next; |
|
|
end syn; |
/ibd_kw11l.vhd
0,0 → 1,170
-- $Id: ibd_kw11l.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibd_kw11l - syn |
-- Description: ibus dev(loc): KW11-L (line clock) |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 9 23 0 14 s 5.3 |
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.1.1 now numeric_std clean |
-- 2010-10-17 333 1.1 use ibus V2 interface |
-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset |
-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list |
-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK |
-- 2008-01-20 112 1.0.2 fix proc_next sensitivity list; use BRESET |
-- 2008-01-06 111 1.0.1 Renamed to ibd_kw11l (RRI_REQ not used) |
-- 2008-01-05 110 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibd_kw11l is -- ibus dev(loc): KW11-L (line clock) |
-- fixed address: 177546 |
port ( |
CLK : in slbit; -- clock |
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end ibd_kw11l; |
|
architecture syn of ibd_kw11l is |
|
constant ibaddr_kw11l : slv16 := slv(to_unsigned(8#177546#,16)); |
|
constant lks_ibf_ie : integer := 6; |
constant lks_ibf_moni : integer := 7; |
|
constant twidth : natural := 5; |
constant tdivide : natural := 20; |
|
type regs_type is record -- state registers |
ibsel : slbit; -- ibus select |
ie : slbit; -- interrupt enable |
moni : slbit; -- monitor bit |
intreq : slbit; -- interrupt request |
tcnt : slv(twidth-1 downto 0); -- timer counter |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- ibsel |
'0', -- ie |
'1', -- moni (set on reset !!) |
'0', -- intreq |
(others=>'0') -- tcnt |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
begin |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if BRESET = '1' then -- BRESET is 1 for system and ibus reset |
R_REGS <= regs_init; |
if RESET = '0' then -- if RESET=0 we do just an ibus reset |
R_REGS.tcnt <= N_REGS.tcnt; -- don't clear msec tick counter |
end if; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, IB_MREQ, CE_MSEC, EI_ACK) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable idout : slv16 := (others=>'0'); |
variable ibreq : slbit := '0'; |
variable ibw0 : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
idout := (others=>'0'); |
ibreq := IB_MREQ.re or IB_MREQ.we; |
ibw0 := IB_MREQ.we and IB_MREQ.be0; |
|
-- ibus address decoder |
n.ibsel := '0'; |
if IB_MREQ.aval='1' and |
IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then |
n.ibsel := '1'; |
end if; |
|
-- ibus output driver |
if r.ibsel = '1' then |
idout(lks_ibf_ie) := R_REGS.ie; |
idout(lks_ibf_moni) := R_REGS.moni; |
end if; |
|
-- ibus write transactions |
if r.ibsel='1' and ibw0='1' then |
n.ie := IB_MREQ.din(lks_ibf_ie); |
n.moni := IB_MREQ.din(lks_ibf_moni); |
if IB_MREQ.din(lks_ibf_ie)='0' or IB_MREQ.din(lks_ibf_moni)='0' then |
n.intreq := '0'; |
end if; |
end if; |
|
-- other state changes |
if CE_MSEC = '1' then |
n.tcnt := slv(unsigned(r.tcnt) + 1); |
if unsigned(r.tcnt) = tdivide-1 then |
n.tcnt := (others=>'0'); |
n.moni := '1'; |
if r.ie = '1' then |
n.intreq := '1'; |
end if; |
end if; |
end if; |
|
if EI_ACK = '1' then |
n.intreq := '0'; |
end if; |
|
N_REGS <= n; |
|
IB_SRES.dout <= idout; |
IB_SRES.ack <= r.ibsel and ibreq; |
IB_SRES.busy <= '0'; |
|
EI_REQ <= r.intreq; |
|
end process proc_next; |
|
end syn; |
/ibdr_rk11.vhd
0,0 → 1,481
-- $Id: ibdr_rk11.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibdr_rk11 - syn |
-- Description: ibus dev(rem): RK11-A/B |
-- |
-- Dependencies: ram_1swar_gen |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 46 248 16 137 s 7.2 |
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1 |
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; |
-- 2010-10-17 333 1.2 use ibus V2 interface |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec |
-- BUGFIX: sector counter now counts 000,...,013. |
-- 2009-05-21 217 1.0.8 cancel pending interrupt requests when IE=0 |
-- 2009-05-16 216 1.0.7 BUGFIX: correct interrupt on IE 0->1 logic |
-- BUGFIX: re-work the seek complete handling |
-- 2008-08-22 161 1.0.6 use iblib |
-- 2008-05-30 151 1.0.5 BUGFIX: do control reset locally now, add CRDONE |
-- 2008-03-30 131 1.0.4 issue interrupt when IDE bit set with GO=0 |
-- 2008-02-23 118 1.0.3 remove redundant condition in rkda access code |
-- fix bug in control reset logic (we's missing) |
-- 2008-01-20 113 1.0.2 Fix busy handling when control reset done |
-- 2008-01-20 112 1.0.1 Fix scp handling; use BRESET |
-- 2008-01-06 111 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.memlib.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_rk11 is -- ibus dev(rem): RK11 |
-- fixed address: 177400 |
port ( |
CLK : in slbit; -- clock |
CE_MSEC : in slbit; -- msec pulse |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end ibdr_rk11; |
|
architecture syn of ibdr_rk11 is |
|
constant ibaddr_rk11 : slv16 := slv(to_unsigned(8#177400#,16)); |
|
constant ibaddr_rkds : slv3 := "000"; -- rkds address offset |
constant ibaddr_rker : slv3 := "001"; -- rker address offset |
constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset |
constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset |
constant ibaddr_rkba : slv3 := "100"; -- rkba address offset |
constant ibaddr_rkda : slv3 := "101"; -- rkda address offset |
constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset |
constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset |
|
subtype rkds_ibf_id is integer range 15 downto 13; |
constant rkds_ibf_adry : integer := 6; |
constant rkds_ibf_scsa : integer := 4; |
subtype rkds_ibf_sc is integer range 3 downto 0; |
|
subtype rker_ibf_he is integer range 15 downto 5; |
constant rker_ibf_cse : integer := 1; |
constant rker_ibf_wce : integer := 0; |
|
constant rkcs_ibf_err : integer := 15; |
constant rkcs_ibf_he : integer := 14; |
constant rkcs_ibf_scp : integer := 13; |
constant rkcs_ibf_maint : integer := 12; |
constant rkcs_ibf_rdy : integer := 7; |
constant rkcs_ibf_ide : integer := 6; |
subtype rkcs_ibf_mex is integer range 5 downto 4; |
subtype rkcs_ibf_func is integer range 3 downto 1; |
constant rkcs_ibf_go : integer := 0; |
|
subtype rkda_ibf_drsel is integer range 15 downto 13; |
|
subtype rkmr_ibf_rid is integer range 15 downto 13; -- rem id |
constant rkmr_ibf_crdone: integer := 11; -- contr. reset done |
constant rkmr_ibf_sbclr : integer := 10; -- clear sbusy's |
constant rkmr_ibf_creset: integer := 9; -- control reset |
constant rkmr_ibf_fdone : integer := 8; -- func done |
subtype rkmr_ibf_sdone is integer range 7 downto 0; -- seek done |
|
type state_type is ( |
s_idle, |
s_init |
); |
|
type regs_type is record -- state registers |
ibsel : slbit; -- ibus select |
state : state_type; -- state |
id : slv3; -- rkds: drive id of search done |
sc : slv4; -- rkds: sector counter |
cse : slbit; -- rker: check sum error |
wce : slbit; -- rker: write check error |
he : slbit; -- rkcs: hard error |
scp : slbit; -- rkcs: seek complete |
maint : slbit; -- rkcs: maintenance mode |
rdy : slbit; -- rkcs: control ready |
ide : slbit; -- rkcs: interrupt on done enable |
drsel : slv3; -- rkda: currently selected drive |
fireq : slbit; -- func done interrupt request flag |
sireq : slv8; -- seek done interrupt request flags |
sbusy : slv8; -- seek busy flags |
rid : slv3; -- drive id for rem ds reads |
icnt : slv3; -- init state counter |
creset : slbit; -- control reset flag |
crdone : slbit; -- control reset done since last fdone |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- ibsel |
s_init, -- state |
(others=>'0'), -- id |
(others=>'0'), -- sc |
'0','0', -- cse, wce |
'0','0','0', -- he, scp, maint |
'1', -- rdy (SET TO 1) |
'0', -- ide |
(others=>'0'), -- drsel |
'0', -- fireq |
(others=>'0'), -- sireq |
(others=>'0'), -- sbusy |
(others=>'0'), -- rid |
(others=>'0'), -- icnt |
'0','1' -- creset, crdone |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
signal MEM_1_WE : slbit := '0'; |
signal MEM_0_WE : slbit := '0'; |
signal MEM_ADDR : slv4 := (others=>'0'); |
signal MEM_DIN : slv16 := (others=>'0'); |
signal MEM_DOUT : slv16 := (others=>'0'); |
|
begin |
|
MEM_1 : ram_1swar_gen |
generic map ( |
AWIDTH => 4, |
DWIDTH => 8) |
port map ( |
CLK => CLK, |
WE => MEM_1_WE, |
ADDR => MEM_ADDR, |
DI => MEM_DIN(ibf_byte1), |
DO => MEM_DOUT(ibf_byte1)); |
|
MEM_0 : ram_1swar_gen |
generic map ( |
AWIDTH => 4, |
DWIDTH => 8) |
port map ( |
CLK => CLK, |
WE => MEM_0_WE, |
ADDR => MEM_ADDR, |
DI => MEM_DIN(ibf_byte0), |
DO => MEM_DOUT(ibf_byte0)); |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if BRESET='1' or R_REGS.creset='1' then |
R_REGS <= regs_init; |
if R_REGS.creset = '1' then |
R_REGS.sbusy <= N_REGS.sbusy; |
end if; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable ibhold : slbit := '0'; |
variable icrip : slbit := '0'; |
variable idout : slv16 := (others=>'0'); |
variable ibrem : slbit := '0'; |
variable ibreq : slbit := '0'; |
variable ibrd : slbit := '0'; |
variable ibw0 : slbit := '0'; |
variable ibw1 : slbit := '0'; |
variable ibwrem : slbit := '0'; |
variable ilam : slbit := '0'; |
variable iscval : slbit := '0'; |
variable iscid : slv3 := (others=>'0'); |
variable iei_req : slbit := '0'; |
|
variable imem_we0 : slbit := '0'; |
variable imem_we1 : slbit := '0'; |
variable imem_addr : slv4 := (others=>'0'); |
variable imem_din : slv16 := (others=>'0'); |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
ibhold := '0'; |
icrip := '0'; |
idout := (others=>'0'); |
ibrem := IB_MREQ.racc or r.maint; |
ibreq := IB_MREQ.re or IB_MREQ.we; |
ibrd := IB_MREQ.re; |
ibw0 := IB_MREQ.we and IB_MREQ.be0; |
ibw1 := IB_MREQ.we and IB_MREQ.be1; |
ibwrem := IB_MREQ.we and ibrem; |
ilam := '0'; |
iscval := '0'; |
iscid := (others=>'0'); |
iei_req := '0'; |
|
imem_we0 := '0'; |
imem_we1 := '0'; |
imem_addr := '0' & IB_MREQ.addr(3 downto 1); |
imem_din := IB_MREQ.din; |
|
-- ibus address decoder |
n.ibsel := '0'; |
if IB_MREQ.aval = '1' and |
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then |
n.ibsel := '1'; |
end if; |
|
-- internal state machine (for control reset) |
case r.state is |
when s_idle => |
null; |
|
when s_init => |
ibhold := r.ibsel; -- hold ibus when controller busy |
icrip := '1'; |
n.icnt := slv(unsigned(r.icnt) + 1); |
if unsigned(r.icnt) = 7 then |
n.state := s_idle; |
end if; |
|
when others => null; |
end case; |
|
|
-- ibus transactions |
|
if r.ibsel='1' and ibhold='0' then -- selected and not holding |
idout := MEM_DOUT; |
imem_we0 := ibw0; |
imem_we1 := ibw1; |
|
case IB_MREQ.addr(3 downto 1) is |
|
when ibaddr_rkds => -- RKDS -- drive status register ---- |
if ibrem = '0' then |
imem_addr := '1' & r.drsel; -- loc read ds data: drsel as addr. |
else |
imem_addr := '1' & r.rid; -- rem read ds data: rid as addr. |
end if; |
idout(rkds_ibf_id) := r.id; |
if ibrem = '0' then -- loc ? simulate drive sector monitor |
if r.sc = MEM_DOUT(rkds_ibf_sc) then |
idout(rkds_ibf_scsa) := '1'; |
else |
idout(rkds_ibf_scsa) := '0'; |
end if; |
idout(rkds_ibf_sc) := r.sc; |
end if; |
|
if r.sbusy(to_integer(unsigned(imem_addr(2 downto 0))))='1' then |
idout(rkds_ibf_adry) := '0'; -- clear drive access rdy |
end if; |
|
if ibwrem = '1' then -- rem write ? than update ds data |
imem_addr := '1' & IB_MREQ.din(rkds_ibf_id); -- use id field as addr |
else -- loc write ? |
imem_we0 := '0'; -- suppress we, is read-only |
imem_we1 := '0'; |
end if; |
|
when ibaddr_rker => -- RKER -- error register ------------ |
idout(4 downto 2) := (others=>'0'); -- unassigned bits |
idout(rker_ibf_cse) := r.cse; -- use state bits (cleared at go !) |
idout(rker_ibf_wce) := r.wce; |
|
if ibwrem = '1' then -- rem write ? |
if unsigned(IB_MREQ.din(rker_ibf_he)) /= 0 then -- hard errors set ? |
n.he := '1'; |
else |
n.he := '0'; |
end if; |
n.cse := IB_MREQ.din(rker_ibf_cse); -- mirror cse bit |
n.wce := IB_MREQ.din(rker_ibf_wce); -- mirror wce bit |
else -- loc write ? |
imem_we0 := '0'; -- suppress we, is read-only |
imem_we1 := '0'; |
end if; |
|
when ibaddr_rkcs => -- RKCS -- control status register --- |
idout(rkcs_ibf_err) := r.he or r.cse or r.wce; |
idout(rkcs_ibf_he) := r.he; |
idout(rkcs_ibf_scp) := r.scp; |
idout(rkcs_ibf_rdy) := r.rdy; |
idout(rkcs_ibf_go) := not r.rdy; |
|
if ibw1 = '1' then |
n.maint := IB_MREQ.din(rkcs_ibf_maint); -- mirror maint bit |
end if; |
|
if ibw0 = '1' then |
n.ide := IB_MREQ.din(rkcs_ibf_ide); -- mirror ide bit |
if n.ide = '0' then -- if IE 0 or set to 0 |
n.fireq := '0'; -- cancel all pending |
n.sireq := (others=>'0'); -- interrupt requests |
end if; |
|
if IB_MREQ.din(rkcs_ibf_go) = '1' then -- GO=1 ? |
if r.rdy = '1' then -- ready and GO ? |
n.scp := '0'; -- go clears scp ! |
n.rdy := '0'; -- mark busy |
n.cse := '0'; -- clear soft errors |
n.wce := '0'; |
n.fireq := '0'; -- cancel pend. int |
|
if unsigned(IB_MREQ.din(rkcs_ibf_func))=0 then -- control reset? |
n.creset := '1'; -- handle locally |
else |
ilam := '1'; -- issue lam |
end if; |
|
if unsigned(IB_MREQ.din(rkcs_ibf_func))=4 or -- if seek |
unsigned(IB_MREQ.din(rkcs_ibf_func))=6 then -- or drive reset |
n.sbusy(to_integer(unsigned(r.drsel))) := '1'; -- set busy |
end if; |
|
end if; |
else -- GO=0 |
if r.ide = '0' and -- if ide now 0 |
IB_MREQ.din(rkcs_ibf_ide)='1' and -- and is set to 1 |
r.rdy='1' then -- and controller ready |
n.fireq := '1'; -- issue interrupt |
end if; |
end if; |
end if; |
|
when ibaddr_rkda => -- RKDA -- disk address register ----- |
if ibrem = '0' then -- loc access ? |
if r.rdy = '0' then -- controller busy ? |
imem_we0 := '0'; -- suppress write |
imem_we1 := '0'; |
end if; |
end if; |
if imem_we1 = '1' then |
n.drsel := IB_MREQ.din(rkda_ibf_drsel); -- mirror drsel bits |
end if; |
|
when ibaddr_rkmr => -- RKMR -- maintenance register ------ |
idout := (others=>'0'); |
idout(rkmr_ibf_rid) := r.rid; |
idout(rkmr_ibf_crdone) := r.crdone; |
idout(rkmr_ibf_sdone) := r.sbusy; |
if ibwrem = '1' then -- rem write ? |
n.rid := IB_MREQ.din(rkmr_ibf_rid); |
|
if r.ide='1' and IB_MREQ.din(rkmr_ibf_sbclr)='0' then |
n.sireq := r.sireq or (IB_MREQ.din(rkmr_ibf_sdone) and r.sbusy); |
end if; |
n.sbusy := r.sbusy and not IB_MREQ.din(rkmr_ibf_sdone); |
|
if IB_MREQ.din(rkmr_ibf_fdone) = '1' then -- func completed |
n.rdy := '1'; |
n.crdone := '0'; |
if r.ide = '1' then |
n.fireq := '1'; |
end if; |
end if; |
if IB_MREQ.din(rkmr_ibf_creset) = '1' then -- control reset |
n.creset := '1'; |
end if; |
end if; |
|
when others => -- all other regs |
null; |
|
end case; |
|
end if; |
|
iscval := '1'; |
if r.sireq(7) = '1' then iscid := "111"; |
elsif r.sireq(6) = '1' then iscid := "110"; |
elsif r.sireq(5) = '1' then iscid := "101"; |
elsif r.sireq(4) = '1' then iscid := "100"; |
elsif r.sireq(3) = '1' then iscid := "011"; |
elsif r.sireq(2) = '1' then iscid := "010"; |
elsif r.sireq(1) = '1' then iscid := "001"; |
elsif r.sireq(0) = '1' then iscid := "000"; |
else |
iscval := '0'; |
end if; |
|
if r.ide = '1' then |
if r.fireq='1' or iscval='1' then |
iei_req := '1'; |
end if; |
end if; |
|
if EI_ACK = '1' then -- interrupt executed |
if r.fireq = '1' then |
n.scp := '0'; -- clear scp flag, is command end |
n.fireq := '0'; |
elsif iscval = '1' then -- was a seek done |
n.scp := '1'; -- signal seek complete interrupt |
n.id := iscid; -- load id |
n.sireq(to_integer(unsigned(iscid))) := '0'; -- reset sireq bit |
end if; |
end if; |
|
if icrip = '1' then -- control reset in progress ? |
imem_addr := '0' & r.icnt; -- use icnt as addr |
imem_din := (others=>'0'); -- force data to zero |
imem_we0 := '1'; -- enable writes |
imem_we1 := '1'; |
end if; |
|
if CE_MSEC = '1' then -- advance sector counter every msec |
if unsigned(r.sc) = 8#13# then -- sector counter (count to 8#13#) |
n.sc := (others=>'0'); |
else |
n.sc := slv(unsigned(r.sc) + 1); |
end if; |
end if; |
|
N_REGS <= n; |
|
MEM_0_WE <= imem_we0; |
MEM_1_WE <= imem_we1; |
MEM_ADDR <= imem_addr; |
MEM_DIN <= imem_din; |
|
IB_SRES.dout <= idout; |
IB_SRES.ack <= r.ibsel and ibreq; |
IB_SRES.busy <= ibhold and ibreq; |
|
RB_LAM <= ilam; |
EI_REQ <= iei_req; |
|
end process proc_next; |
|
|
end syn; |
/iblib.vhd
0,0 → 1,149
-- $Id: iblib.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: iblib |
-- Description: Definitions for ibus interface and bus entities |
-- |
-- Dependencies: - |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon |
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw |
-- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type |
-- 2009-06-01 221 1.0.1 added dip signal to ib_mreq_type |
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
|
package iblib is |
|
type ib_mreq_type is record -- ibus - master request |
aval : slbit; -- address valid |
re : slbit; -- read enable |
we : slbit; -- write enable |
rmw : slbit; -- read-modify-write |
be0 : slbit; -- byte enable low |
be1 : slbit; -- byte enable high |
cacc : slbit; -- console access |
racc : slbit; -- remote access |
addr : slv13_1; -- address bit(12:1) |
din : slv16; -- data (input to slave) |
end record ib_mreq_type; |
|
constant ib_mreq_init : ib_mreq_type := |
('0','0','0','0', -- aval, re, we, rmw |
'0','0','0','0', -- be0, be1, cacc, racc |
(others=>'0'), -- addr |
(others=>'0')); -- din |
|
type ib_sres_type is record -- ibus - slave response |
ack : slbit; -- acknowledge |
busy : slbit; -- busy |
dout : slv16; -- data (output from slave) |
end record ib_sres_type; |
|
constant ib_sres_init : ib_sres_type := |
('0','0', -- ack, busy |
(others=>'0')); -- dout |
|
type ib_sres_vector is array (natural range <>) of ib_sres_type; |
|
subtype ibf_byte1 is integer range 15 downto 8; |
subtype ibf_byte0 is integer range 7 downto 0; |
|
component ib_sel is -- ibus address select logic |
generic ( |
IB_ADDR : slv16; -- ibus address base |
SAWIDTH : natural := 0); -- device subaddress space width |
port ( |
CLK : in slbit; -- clock |
IB_MREQ : in ib_mreq_type; -- ibus request |
SEL : out slbit -- select state bit |
); |
end component; |
|
component ib_sres_or_2 is -- ibus result or, 2 input |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2 |
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output |
); |
end component; |
component ib_sres_or_3 is -- ibus result or, 3 input |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2 |
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3 |
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output |
); |
end component; |
component ib_sres_or_4 is -- ibus result or, 4 input |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2 |
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3 |
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4 |
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output |
); |
end component; |
|
component ib_sres_or_gen is -- ibus result or, generic |
generic ( |
WIDTH : natural := 4); -- number of input ports |
port ( |
IB_SRES_IN : in ib_sres_vector(1 to WIDTH); -- ib_sres input array |
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output |
); |
end component; |
|
type intmap_type is record -- interrupt map entry type |
vec : integer; -- vector address |
pri : integer; -- priority |
end record intmap_type; |
constant intmap_init : intmap_type := (0,0); |
|
type intmap_array_type is array (15 downto 0) of intmap_type; |
constant intmap_array_init : intmap_array_type := (others=>intmap_init); |
|
component ib_intmap is -- external interrupt mapper |
generic ( |
INTMAP : intmap_array_type := intmap_array_init); |
port ( |
EI_REQ : in slv16_1; -- interrupt request lines |
EI_ACKM : in slbit; -- interrupt acknowledge (from master) |
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor) |
EI_PRI : out slv3; -- interrupt priority |
EI_VECT : out slv9_2 -- interrupt vector |
); |
end component; |
|
-- |
-- components for use in test benches (not synthesizable) |
-- |
|
component ib_sres_or_mon is -- ibus result or monitor |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2 |
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3 |
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4 |
); |
end component; |
|
end package iblib; |
/ibdlib.vhd
0,0 → 1,276
-- $Id: ibdlib.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: ibdlib |
-- Description: Definitions for ibus devices |
-- |
-- Dependencies: - |
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.1.2 now numeric_std clean |
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys |
-- 2009-06-07 224 1.0.4 add iist_mreq and iist_sreq; |
-- 2009-06-01 221 1.0.3 add RESET to kw11l; add iist; |
-- 2009-05-30 220 1.0.2 add most additional device def's |
-- 2009-05-24 219 1.0.1 add CE_MSEC to _rk11; add _maxisys |
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
package ibdlib is |
|
type iist_line_type is record -- iist line |
dcf : slbit; -- disconnect flag |
req : slbit; -- request |
stf : slbit; -- sanity timer flag |
imask : slv4; -- interrupt mask |
bmask : slv4; -- boot mask |
par : slbit; -- parity (odd) |
frm : slbit; -- frame error flag |
end record iist_line_type; |
|
constant iist_line_init : iist_line_type := ('1','0','0',"0000","0000",'0','0'); |
|
type iist_bus_type is array (3 downto 0) of iist_line_type; |
constant iist_bus_init : iist_bus_type := (others=>iist_line_init); |
|
type iist_mreq_type is record -- iist->cpu requests |
lock : slbit; -- lock-up CPU |
boot : slbit; -- boot-up CPU |
end record iist_mreq_type; |
|
constant iist_mreq_init : iist_mreq_type := ('0','0'); |
|
type iist_sres_type is record -- cpu->iist responses |
ack_lock : slbit; -- release lock |
ack_boot : slbit; -- boot started |
end record iist_sres_type; |
|
constant iist_sres_init : iist_sres_type := ('0','0'); |
|
-- ise 13.1 xst can bug check if generic defaults in a package are defined via |
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok. |
-- As workaround the ibus default addresses are defined here as constant. |
constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16)); |
constant ibaddr_dl11 : slv16 := slv(to_unsigned(8#177560#,16)); |
|
component ibd_iist is -- ibus dev(loc): IIST |
-- fixed address: 177500 |
generic ( |
SID : slv2 := "00"); -- self id |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit; -- interrupt acknowledge |
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's) |
IIST_OUT : out iist_line_type; -- iist output |
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests |
IIST_SRES : in iist_sres_type -- cpu->iist responses |
); |
end component; |
|
component ibd_kw11p is -- ibus dev(loc): KW11-P (line clock) |
-- fixed address: 172540 |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end component; |
|
component ibd_kw11l is -- ibus dev(loc): KW11-L (line clock) |
-- fixed address: 177546 |
port ( |
CLK : in slbit; -- clock |
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end component; |
|
component ibdr_rl11 is -- ibus dev(rem): RL11 |
-- fixed address: 174400 |
port ( |
CLK : in slbit; -- clock |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end component; |
|
component ibdr_rk11 is -- ibus dev(rem): RK11 |
-- fixed address: 177400 |
port ( |
CLK : in slbit; -- clock |
CE_MSEC : in slbit; -- msec pulse |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end component; |
|
component ibdr_tm11 is -- ibus dev(rem): TM11 |
-- fixed address: 172520 |
port ( |
CLK : in slbit; -- clock |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end component; |
|
component ibdr_dz11 is -- ibus dev(rem): DZ11 |
generic ( |
IB_ADDR : slv16 := ibaddr_dz11); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ_RX : out slbit; -- interrupt request, receiver |
EI_REQ_TX : out slbit; -- interrupt request, transmitter |
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver |
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter |
); |
end component; |
|
component ibdr_dl11 is -- ibus dev(rem): DL11-A/B |
generic ( |
IB_ADDR : slv16 := ibaddr_dl11); |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ_RX : out slbit; -- interrupt request, receiver |
EI_REQ_TX : out slbit; -- interrupt request, transmitter |
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver |
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter |
); |
end component; |
|
component ibdr_pc11 is -- ibus dev(rem): PC11 |
-- fixed address: 177550 |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ_PTR : out slbit; -- interrupt request, reader |
EI_REQ_PTP : out slbit; -- interrupt request, punch |
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader |
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch |
); |
end component; |
|
component ibdr_lp11 is -- ibus dev(rem): LP11 |
-- fixed address: 177514 |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slbit; -- remote attention |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit -- interrupt acknowledge |
); |
end component; |
|
component ibdr_sdreg is -- ibus dev(rem): Switch/Display regs |
-- fixed address: 177570 |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
DISPREG : out slv16 -- display register |
); |
end component; |
|
component ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slv16_1; -- remote attention vector |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_ACKM : in slbit; -- interrupt acknowledge (from master) |
EI_PRI : out slv3; -- interrupt priority (to cpu) |
EI_VECT : out slv9_2; -- interrupt vector (to cpu) |
DISPREG : out slv16 -- display register |
); |
end component; |
|
component ibdr_maxisys is -- ibus(rem) full system |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slv16_1; -- remote attention vector |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_ACKM : in slbit; -- interrupt acknowledge (from master) |
EI_PRI : out slv3; -- interrupt priority (to cpu) |
EI_VECT : out slv9_2; -- interrupt vector (to cpu) |
DISPREG : out slv16 -- display register |
); |
end component; |
|
end package ibdlib; |
/ibd_iist.vhd
0,0 → 1,684
-- $Id: ibd_iist.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibd_iist - syn |
-- Description: ibus dev(loc): IIST |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 112 510 0 291 s 15.8 |
-- 2010-10-17 314 12.1 M53d xc3s1000-4 111 504 0 290 s 15.6 |
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8 |
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 0.8.1 now numeric_std clean |
-- 2010-10-17 333 0.8 use ibus V2 interface |
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im |
-- also for dcf_dcf and exc_rte; add iist_mreq and |
-- iist_sreq, boot and lock interfaces |
-- 2009-06-05 223 0.6 level interrupt, parity logic, exc.ui logic |
-- st logic modified (partially tested) |
-- 2009-06-01 221 0.5 Initial version (untested, lock&boot missing) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
use work.ibdlib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibd_iist is -- ibus dev(loc): IIST |
-- fixed address: 177500 |
generic ( |
SID : slv2 := "00"); -- self id |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
RESET : in slbit; -- system reset |
BRESET : in slbit; -- ibus reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_REQ : out slbit; -- interrupt request |
EI_ACK : in slbit; -- interrupt acknowledge |
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's) |
IIST_OUT : out iist_line_type; -- iist output |
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests |
IIST_SRES : in iist_sres_type -- cpu->iist responses |
); |
end ibd_iist; |
|
architecture syn of ibd_iist is |
|
constant ibaddr_iist : slv16 := slv(to_unsigned(8#177500#,16)); |
|
constant tdlysnd : natural := 150; -- send delay timer |
|
constant ibaddr_acr : slv1 := "0"; -- acr address offset |
constant ibaddr_adr : slv1 := "1"; -- adr address offset |
|
constant acr_ibf_clr : integer := 15; -- clear flag |
subtype acr_ibf_sid is integer range 9 downto 8; -- self id |
subtype acr_ibf_ac is integer range 3 downto 0; -- ac code |
|
constant ac_pge : slv4 := "0000"; -- 0 program generated enables |
constant ac_pgc : slv4 := "0001"; -- 1 program generated control/status |
constant ac_ste : slv4 := "0010"; -- 2 sanity timer enables |
constant ac_stc : slv4 := "0011"; -- 3 sanity timer control/status |
constant ac_msk : slv4 := "0100"; -- 4 input masks |
constant ac_pgf : slv4 := "0101"; -- 5 program generated flags |
constant ac_stf : slv4 := "0110"; -- 6 sanity timer flags |
constant ac_dcf : slv4 := "0111"; -- 7 disconnect flags |
constant ac_exc : slv4 := "1000"; -- 10 exceptions |
constant ac_mtc : slv4 := "1101"; -- 15 maintenance control |
|
subtype pge_ibf_pbe is integer range 11 downto 8; -- pg boot ena |
subtype pge_ibf_pie is integer range 3 downto 0; -- pg int ena |
|
constant pgc_ibf_err : integer := 15; -- error |
constant pgc_ibf_grj : integer := 14; -- go reject |
constant pgc_ibf_pgrmr : integer := 13; -- pg req refused |
constant pgc_ibf_strmr : integer := 12; -- st req refused |
constant pgc_ibf_rdy : integer := 11; -- ready flag |
subtype pgc_ibf_sid is integer range 9 downto 8; -- self id |
constant pgc_ibf_ip : integer := 3; -- int pending |
constant pgc_ibf_ie : integer := 2; -- int enable |
constant pgc_ibf_ptp : integer := 1; -- pg parity |
constant pgc_ibf_go : integer := 0; -- go flag |
|
subtype ste_ibf_sbe is integer range 11 downto 8; -- st boot enable |
subtype ste_ibf_sie is integer range 3 downto 0; -- st int enable |
|
subtype stc_ibf_count is integer range 15 downto 8; -- count |
constant stc_ibf_tmo : integer := 3; -- timeout |
constant stc_ibf_lke : integer := 2; -- lockup enable |
constant stc_ibf_stp : integer := 1; -- st parity |
constant stc_ibf_enb : integer := 0; -- enable |
|
subtype msk_ibf_bm is integer range 11 downto 8; -- boot mask |
subtype msk_ibf_im is integer range 3 downto 0; -- int mask |
|
subtype pgf_ibf_pbf is integer range 11 downto 8; -- boot flags |
subtype pgf_ibf_pif is integer range 3 downto 0; -- int flags |
|
subtype stf_ibf_sbf is integer range 11 downto 8; -- boot flags |
subtype stf_ibf_sif is integer range 3 downto 0; -- int flags |
|
subtype dcf_ibf_brk is integer range 11 downto 8; -- break flags |
subtype dcf_ibf_dcf is integer range 3 downto 0; -- disconnect flags |
|
subtype exc_ibf_ui is integer range 11 downto 8; -- unexpected int |
subtype exc_ibf_rte is integer range 3 downto 0; -- transm. error |
|
constant mtc_ibf_mttp : integer := 11; -- maint. type |
constant mtc_ibf_mfrm : integer := 10; -- maint. frame err |
subtype mtc_ibf_mid is integer range 9 downto 8; -- maint. id |
constant mtc_ibf_dsbt : integer := 3; -- disable boot |
constant mtc_ibf_enmxd : integer := 2; -- enable maint mux |
constant mtc_ibf_enmlp : integer := 1; -- enable maint loop |
constant mtc_ibf_dsdrv : integer := 0; -- disable driver |
|
type state_type is ( |
s_idle, -- idle state |
s_clear, -- handle acr clr |
s_stsnd, -- handle st transmit |
s_pgsnd -- handle pg transmit |
); |
|
type regs_type is record -- state registers |
ibsel : slbit; -- ibus select |
acr_ac : slv4; -- acr: ac |
pge_pbe : slv4; -- pge: pg boot ena |
pge_pie : slv4; -- pge: pg int ena |
pgc_grj : slbit; -- pgc: go reject |
pgc_pgrmr : slbit; -- pgc: pg req refused |
pgc_strmr : slbit; -- pgc: st req refused |
pgc_ie : slbit; -- pgc: int enable |
pgc_ptp : slbit; -- pgc: pg parity |
ste_sbe : slv4; -- ste: st boot enable |
ste_sie : slv4; -- ste: st int enable |
stc_count : slv8; -- stc: count |
stc_tmo : slbit; -- stc: timeout |
stc_lke : slbit; -- stc: lockup enable |
stc_stp : slbit; -- stc: st parity |
stc_enb : slbit; -- stc: enable |
msk_bm : slv4; -- msk: boot mask |
msk_im : slv4; -- msk: int mask |
pgf_pbf : slv4; -- pgf: boot flags |
pgf_pif : slv4; -- pgf: int flags |
stf_sbf : slv4; -- stf: boot flags |
stf_sif : slv4; -- stf: int flags |
dcf_brk : slv4; -- dcf: break flags |
dcf_dcf : slv4; -- dcf: disconnect flags |
exc_ui : slv4; -- exc: unexpected int |
exc_rte : slv4; -- exc: transm. error |
mtc_mttp : slbit; -- mtc: maint. type |
mtc_mfrm : slbit; -- mtc: maint. frame err |
mtc_mid : slv2; -- mtc: maint. id |
mtc_dsbt : slbit; -- mtc: disable boot |
mtc_enmxd : slbit; -- mtc: enable maint mux |
mtc_enmlp : slbit; -- mtc: enable maint loop |
mtc_dsdrv : slbit; -- mtc: disable driver |
state : state_type; -- state |
req_clear : slbit; -- request clear |
req_stsnd : slbit; -- request sanity timer transmit |
req_pgsnd : slbit; -- request prog. gen. transmit |
tcnt256 : slv8; -- usec clock divider for st clock |
tcntsnd : slv8; -- timer for transmit delay |
req_lock : slbit; -- cpu lock request |
req_boot : slbit; -- cpu boot request |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- ibsel |
"0000", -- acr_ac |
"0000","0000", -- pge_pbe, pge_pie |
'0', -- pgc_grj |
'0','0', -- pgc_pgrmr, pgc_strmr |
'0','0', -- pgc_ie, pgc_ptp |
"0000","0000", -- ste_sbe, ste_sie |
(others=>'0'), -- stc_count |
'0','0', -- stc_tmo, stc_lke |
'0','0', -- stc_stp, stc_enb |
"0000","0000", -- msk_bm, msk_im |
"0000","0000", -- pgf_pbf, pgf_pif |
"0000","0000", -- stf_sbf, stf_sif |
"0000","0000", -- dcf_brk, dcf_dcf |
"0000","0000", -- exc_ui, exc_rte |
'0','0', -- mtc_mttp, mtc_mfrm |
"00", -- mtc_mid |
'0','0', -- mtc_dsbt, mtc_enmxd |
'0','0', -- mtc_enmlp, mtc_dsdrv |
s_idle, -- state |
'0', -- req_clear |
'0','0', -- req_stsnd, req_pgsnd |
(others=>'0'), -- tcnt256 |
(others=>'0'), -- tcntsnd |
'0','0' -- req_lock, req_boot |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
begin |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if BRESET = '1' or -- BRESET is 1 for system and ibus reset |
R_REGS.req_clear='1' then |
R_REGS <= regs_init; -- |
if RESET = '0' then -- if RESET=0 we do just an ibus reset |
R_REGS.pgf_pbf <= N_REGS.pgf_pbf; -- don't reset pg boot flags |
R_REGS.stf_sbf <= N_REGS.stf_sbf; -- don't reset st boot flags |
R_REGS.tcnt256 <= N_REGS.tcnt256; -- don't reset st clock divider |
end if; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, CE_USEC, IB_MREQ, EI_ACK, EI_ACK, |
IIST_BUS(0), IIST_BUS(1), IIST_BUS(2), IIST_BUS(3), |
IIST_SRES) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable ibhold : slbit := '0'; |
variable idout : slv16 := (others=>'0'); |
variable ibreq : slbit := '0'; |
variable ibrd : slbit := '0'; |
variable ibw0 : slbit := '0'; |
variable ibw1 : slbit := '0'; |
variable int_or : slbit := '0'; |
variable tcnt256_end : slbit := '0'; |
variable tcntsnd_end : slbit := '0'; |
variable eff_id : slv2 := "00"; |
variable eff_bus : iist_bus_type := iist_bus_init; |
variable par_err : slbit := '0'; |
variable act_ibit : slbit := '0'; |
variable act_bbit : slbit := '0'; |
variable iout : iist_line_type := iist_line_init; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
ibhold := '0'; |
idout := (others=>'0'); |
ibreq := IB_MREQ.re or IB_MREQ.we; |
ibrd := IB_MREQ.re; |
ibw0 := IB_MREQ.we and IB_MREQ.be0; |
ibw1 := IB_MREQ.we and IB_MREQ.be1; |
|
int_or := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr; |
for i in r.dcf_dcf'range loop |
int_or := int_or or r.dcf_dcf(i) or |
r.exc_rte(i) or |
r.pgf_pif(i) or |
r.stf_sif(i); |
end loop; -- i |
|
tcnt256_end := '0'; |
if CE_USEC='1' and r.stc_enb='1'then -- if st enabled on every usec |
n.tcnt256 := slv(unsigned(r.tcnt256) + 1); -- advance 8 bit counter |
if unsigned(r.tcnt256) = 255 then -- if wrap |
tcnt256_end := '1'; -- signal 256 usec passed |
end if; |
end if; |
|
tcntsnd_end := '0'; |
n.tcntsnd := slv(unsigned(r.tcntsnd) + 1); -- advance send timer counter |
if unsigned(r.tcntsnd) = tdlysnd-1 then -- if delay time reached |
tcntsnd_end := '1'; -- signal end |
end if; |
|
eff_id := SID; -- effective self-id, normally SID |
if r.mtc_enmxd = '1' then -- if maint. mux enabled |
eff_id := r.mtc_mid; -- use maint. id |
end if; |
|
eff_bus := IIST_BUS; |
|
par_err := '0'; |
act_ibit := '0'; |
act_bbit := '0'; |
iout := iist_line_init; -- default state of out line |
|
-- ibus address decoder |
n.ibsel := '0'; |
if IB_MREQ.aval='1' and |
IB_MREQ.addr(12 downto 2)=ibaddr_iist(12 downto 2) then |
n.ibsel := '1'; |
end if; |
|
-- internal state machine |
case r.state is |
when s_idle => -- idle state |
n.tcntsnd := (others=>'0'); -- keep send delay timer zero |
if r.req_stsnd = '1' then -- sanity timer request pending |
n.state := s_stsnd; |
elsif r.req_pgsnd = '1' then -- prog. gen. request pending |
n.state := s_pgsnd; |
end if; |
|
when s_clear => -- handle acr clr |
ibhold := r.ibsel; -- keep req pending if selected |
-- r.req_clear is set when in this state and cause a reset in prog_regs |
-- --> n.req_clear := '0'; |
-- --> n.state := s_idle; |
|
when s_stsnd => -- handle st transmit |
if tcntsnd_end = '1' then -- send delay expired |
n.req_stsnd := '0'; -- clear st transmit request |
iout.req := '1'; -- do transmit |
iout.stf := '1'; -- signal type = st |
iout.imask := r.ste_sie; -- int enables |
iout.bmask := r.ste_sbe; -- boot enables |
iout.par := not r.stc_stp; -- send parity (odd incl. stf!) |
iout.frm := '0'; -- frame always ok |
n.state := s_idle; |
end if; |
|
when s_pgsnd => -- handle pg transmit |
if tcntsnd_end = '1' then -- send delay expired |
n.req_pgsnd := '0'; -- clear pg transmit request |
iout.req := '1'; -- do transmit |
iout.stf := '0'; -- signal type = pg |
iout.imask := r.pge_pie; -- int enables |
iout.bmask := r.pge_pbe; -- boot enables |
iout.par := r.pgc_ptp; -- send parity |
iout.frm := '0'; -- frame always ok |
n.state := s_idle; |
end if; |
|
when others => null; |
end case; |
|
if r.mtc_enmxd = '1' then -- if maintenance mux enabled |
iout.stf := r.mtc_mttp; -- force type from mtc_mttp |
iout.frm := r.mtc_mfrm; -- force frame from mtc_mfrm |
end if; |
|
-- ibus transactions |
if r.ibsel = '1' and ibhold='0' then |
|
if IB_MREQ.addr(1 downto 1) = "0" then -- ACR -- access control reg ----- |
|
idout(acr_ibf_sid) := SID; |
idout(acr_ibf_ac) := r.acr_ac; |
|
if ibw1 = '1' then |
if IB_MREQ.din(acr_ibf_clr) = '1' then |
n.req_clear := '1'; |
n.state := s_clear; |
end if; |
end if; |
if ibw0 = '1' then |
n.acr_ac := IB_MREQ.din(acr_ibf_ac); |
end if; |
|
else -- ADR -- access data reg -------- |
case r.acr_ac is |
|
when ac_pge => -- PGE -- program gen enables -------- |
|
idout(pge_ibf_pbe) := r.pge_pbe; |
idout(pge_ibf_pie) := r.pge_pie; |
|
if IB_MREQ.we = '1' then |
|
if r.req_pgsnd = '0' then -- no pg transmit pending |
if ibw1 = '1' then |
n.pge_pbe := IB_MREQ.din(pge_ibf_pbe); |
end if; |
if ibw0 = '1' then |
n.pge_pie := IB_MREQ.din(pge_ibf_pie); |
end if; |
else -- if collision with pg transmit |
n.pgc_pgrmr := '1'; -- set pge refused flag |
end if; |
|
end if; |
|
when ac_pgc => -- PGC -- program gen control/status - |
|
idout(pgc_ibf_err) := r.pgc_grj or r.pgc_pgrmr or r.pgc_strmr; |
idout(pgc_ibf_grj) := r.pgc_grj; |
idout(pgc_ibf_pgrmr) := r.pgc_pgrmr; |
idout(pgc_ibf_strmr) := r.pgc_strmr; |
idout(pgc_ibf_rdy) := not r.req_pgsnd; |
idout(pgc_ibf_sid) := eff_id; |
idout(pgc_ibf_ip) := int_or; |
idout(pgc_ibf_ie) := r.pgc_ie; |
idout(pgc_ibf_ptp) := r.pgc_ptp; |
|
if ibw1 = '1' then |
if IB_MREQ.din(pgc_ibf_err) = '1' then -- '1' written into ERR |
n.pgc_grj := '0'; -- clears GRJ |
n.pgc_pgrmr := '0'; -- clears PGRMR |
n.pgc_strmr := '0'; -- clears STRMR |
end if; |
end if; |
if ibw0 = '1' then |
n.pgc_ie := IB_MREQ.din(pgc_ibf_ie); |
n.pgc_ptp := IB_MREQ.din(pgc_ibf_ptp); |
if IB_MREQ.din(pgc_ibf_go) = '1' then -- GO bit set |
if r.req_pgsnd = '0' then -- if ready (no pgsnd pend) |
n.req_pgsnd := '1'; -- request pgsnd |
else -- if not ready |
n.pgc_grj := '1'; -- set go reject flag |
end if; |
end if; |
end if; |
|
when ac_ste => -- STE -- sanity timer enables ------- |
|
idout(ste_ibf_sbe) := r.ste_sbe; |
idout(ste_ibf_sie) := r.ste_sie; |
|
if IB_MREQ.we = '1' then |
|
if r.req_stsnd = '0' then -- no st transmit pending |
if ibw1 = '1' then |
n.ste_sbe := IB_MREQ.din(ste_ibf_sbe); |
end if; |
if ibw0 = '1' then |
n.ste_sie := IB_MREQ.din(ste_ibf_sie); |
end if; |
|
else -- if collision with st transmit |
n.pgc_strmr := '1'; -- set ste refused flag |
end if; |
|
end if; |
|
when ac_stc => -- STC -- sanity timer control/status |
|
idout(stc_ibf_count) := r.stc_count; |
idout(stc_ibf_tmo) := r.stc_tmo; |
idout(stc_ibf_lke) := r.stc_lke; |
idout(stc_ibf_stp) := r.stc_stp; |
idout(stc_ibf_enb) := r.stc_enb; |
|
if ibw1 = '1' then |
n.stc_count := IB_MREQ.din(stc_ibf_count); -- reset st count |
n.tcnt256 := (others=>'0'); -- reset usec count |
end if; |
if ibw0 = '1' then |
if IB_MREQ.din(stc_ibf_tmo) = '1' then -- 1 written into TMO |
n.stc_tmo := '0'; |
end if; |
n.stc_lke := IB_MREQ.din(stc_ibf_lke); |
n.stc_stp := IB_MREQ.din(stc_ibf_stp); |
n.stc_enb := IB_MREQ.din(stc_ibf_enb); |
end if; |
|
when ac_msk => -- MSK -- input masks ---------------- |
|
idout(msk_ibf_bm) := r.msk_bm; |
idout(msk_ibf_im) := r.msk_im; |
|
if ibw1 = '1' then |
n.msk_bm := IB_MREQ.din(msk_ibf_bm); |
end if; |
if ibw0 = '1' then |
n.msk_im := IB_MREQ.din(msk_ibf_im); |
end if; |
|
when ac_pgf => -- PGF -- program generated flags ---- |
|
idout(pgf_ibf_pbf) := r.pgf_pbf; |
idout(pgf_ibf_pif) := r.pgf_pif; |
|
if ibw1 = '1' then |
n.pgf_pbf := r.pgf_pbf and not IB_MREQ.din(pgf_ibf_pbf); |
end if; |
if ibw0 = '1' then |
n.pgf_pif := r.pgf_pif and not IB_MREQ.din(pgf_ibf_pif); |
end if; |
|
when ac_stf => -- STF -- sanity timer flags --------- |
|
idout(stf_ibf_sbf) := r.stf_sbf; |
idout(stf_ibf_sif) := r.stf_sif; |
|
if ibw1 = '1' then |
n.stf_sbf := r.stf_sbf and not IB_MREQ.din(stf_ibf_sbf); |
end if; |
if ibw0 = '1' then |
n.stf_sif := r.stf_sif and not IB_MREQ.din(stf_ibf_sif); |
end if; |
|
when ac_dcf => -- DCE -- disconnect flags ----------- |
|
idout(dcf_ibf_brk) := r.dcf_brk; |
idout(dcf_ibf_dcf) := r.dcf_dcf; |
|
if ibw0 = '1' then |
n.dcf_dcf := r.dcf_dcf and not IB_MREQ.din(dcf_ibf_dcf); |
end if; |
|
when ac_exc => -- EXC -- exceptions ----------------- |
|
idout(exc_ibf_ui) := r.exc_ui; |
idout(exc_ibf_rte) := r.exc_rte; |
|
if ibw1 = '1' then |
n.exc_ui := r.exc_ui and not IB_MREQ.din(exc_ibf_ui); |
end if; |
if ibw0 = '1' then |
n.exc_rte := r.exc_rte and not IB_MREQ.din(exc_ibf_rte); |
end if; |
|
when ac_mtc => -- MTC -- maintenance control -------- |
|
idout(mtc_ibf_mttp) := r.mtc_mttp; |
idout(mtc_ibf_mfrm) := r.mtc_mfrm; |
idout(mtc_ibf_mid) := r.mtc_mid; |
idout(mtc_ibf_dsbt) := r.mtc_dsbt; |
idout(mtc_ibf_enmxd) := r.mtc_enmxd; |
idout(mtc_ibf_enmlp) := r.mtc_enmlp; |
idout(mtc_ibf_dsdrv) := r.mtc_dsdrv; |
|
if ibw1 = '1' then |
n.mtc_mttp := IB_MREQ.din(mtc_ibf_mttp); |
n.mtc_mfrm := IB_MREQ.din(mtc_ibf_mfrm); |
n.mtc_mid := IB_MREQ.din(mtc_ibf_mid); |
end if; |
if ibw0 = '1' then |
n.mtc_dsbt := IB_MREQ.din(mtc_ibf_dsbt); |
n.mtc_enmxd := IB_MREQ.din(mtc_ibf_enmxd); |
n.mtc_enmlp := IB_MREQ.din(mtc_ibf_enmlp); |
n.mtc_dsdrv := IB_MREQ.din(mtc_ibf_dsdrv); |
end if; |
|
when others => -- access to undefined AC code ------- |
null; |
|
end case; |
|
if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10 |
if IB_MREQ.rmw = '0' then -- if not 1st part of rmw |
n.acr_ac := slv(unsigned(r.acr_ac) + 1); -- autoincrement |
end if; |
end if; |
|
end if; |
|
end if; |
|
-- sanity timer |
|
if tcnt256_end = '1' then -- if 256 usec expired (and enabled) |
n.stc_count := slv(unsigned(r.stc_count) - 1); |
if unsigned(r.stc_count) = 0 then -- if sanity timer expired |
n.stc_tmo := '1'; -- set timeout flag |
n.req_stsnd := '1'; -- request st transmit |
if r.stc_lke = '1' then -- if lockup enabled |
n.req_lock := '1'; -- request lockup |
end if; |
end if; |
end if; |
|
-- process iist bus inputs |
|
if r.mtc_enmlp = '1' then -- if mainentance loop |
for i in eff_bus'range loop |
eff_bus(i) := iout; -- local signal on all input ports |
eff_bus(i).dcf := '0'; -- all ports considered connected |
end loop; -- i |
end if; |
|
for i in eff_bus'range loop |
|
par_err := eff_bus(i).stf xor |
eff_bus(i).imask(0) xor eff_bus(i).imask(1) xor |
eff_bus(i).imask(2) xor eff_bus(i).imask(3) xor |
eff_bus(i).bmask(0) xor eff_bus(i).bmask(1) xor |
eff_bus(i).bmask(2) xor eff_bus(i).bmask(3) xor |
not eff_bus(i).par; |
|
act_ibit := eff_bus(i).imask(to_integer(unsigned(eff_id))); |
act_bbit := eff_bus(i).bmask(to_integer(unsigned(eff_id))); |
|
n.dcf_brk(i) := eff_bus(i).dcf; -- trace dcf state in brk |
|
if eff_bus(i).dcf = '1' then -- if disconnected |
if r.msk_im(i) = '0' then -- if not disabled |
n.dcf_dcf(i) := '1'; -- set dcf flag |
end if; |
|
else -- if connected |
if eff_bus(i).req = '1' then -- request received ? |
if eff_bus(i).frm='1' or -- frame error seen ? |
par_err='1' then -- parity error seen ? |
if r.msk_im(i) = '0' then -- if not disabled |
n.exc_rte(i) := '1'; -- set rte flag |
end if; |
|
else -- here if valid request seen |
if act_ibit = '1' then -- interrupt request |
if r.msk_im(i) = '1' then -- if disabled |
n.exc_ui(i) := '1'; -- set ui flag |
else -- if enabled |
n.req_lock := '0'; -- release lock |
if eff_bus(i).stf = '0' then -- and pg request |
n.pgf_pif(i) := '1'; -- set pif flag |
else -- and st request |
n.stf_sif(i) := '1'; -- set sif flag |
end if; |
end if; |
end if; -- act_ibit='1' |
|
if act_bbit = '1' then -- boot request |
if r.msk_bm(i) = '1' then -- if msk disabled |
n.exc_ui(i) := '1'; -- set ui flag |
else -- if msk enabled |
if r.mtc_dsbt = '0' then -- if mtc enabled |
n.req_lock := '0'; -- release lock |
n.req_boot := '1'; -- request boot |
end if; |
if eff_bus(i).stf = '0' then -- and pg request |
n.pgf_pbf(i) := '1'; -- set pbf flag |
else -- and st request |
n.stf_sbf(i) := '1'; -- set sbf flag |
end if; |
end if; |
end if; -- act_bbit='1' |
|
end if; |
|
end if; |
end if; |
end loop; |
|
-- process cpu->iist responses |
if IIST_SRES.ack_lock = '1' then |
n.req_lock := '0'; |
end if; |
if IIST_SRES.ack_boot = '1' then |
n.req_boot := '0'; |
end if; |
|
N_REGS <= n; |
|
IB_SRES.dout <= idout; |
IB_SRES.ack <= r.ibsel and ibreq; |
IB_SRES.busy <= ibhold and ibreq; |
|
EI_REQ <= r.pgc_ie and int_or; |
|
if r.mtc_dsdrv = '1' then -- if driver disconnected |
iout.dcf := '1'; -- set dcf flag |
iout.req := '0'; -- suppress requests |
end if; |
IIST_OUT <= iout; -- and finally send it out... |
|
IIST_MREQ.lock <= r.req_lock; |
IIST_MREQ.boot <= r.req_boot; |
|
end process proc_next; |
|
|
end syn; |
/ibdr_minisys.vhd
0,0 → 1,214
-- $Id: ibdr_minisys.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibdr_minisys - syn |
-- Description: ibus(rem) devices for minimal system:SDR+KW+DL+RK |
-- |
-- Dependencies: ibdr_sdreg |
-- ibd_kw11l |
-- ibdr_dl11 |
-- ibdr_rk11 |
-- ib_sres_or_4 |
-- ib_intmap |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 128 469 16 265 s 7.8 |
-- 2010-10-17 314 12.1 M53d xc3s1000-4 122 472 16 269 s 7.6 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.1.2 now numeric_std clean |
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC |
-- to _dl11 |
-- 2009-05-31 221 1.0.6 add RESET to kw11l; |
-- 2009-05-24 219 1.0.5 _rk11 uses now CE_MSEC |
-- 2008-08-22 161 1.0.4 use iblib, ibdlib |
-- 2008-05-09 144 1.0.3 use EI_ACK with _kw11l, _dl11 |
-- 2008-04-18 136 1.0.2 add RESET port, use for ibdr_sdreg |
-- 2008-01-20 113 1.0.1 RRI_LAM now vector |
-- 2008-01-20 112 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- mini system setup |
-- |
-- ibbase vec pri slot attn device name |
-- |
-- 177546 100 6 4 - KW11-L |
-- 177400 220 5 3 4 RK11 |
-- 177560 060 4 2 1 DL11-RX 1st |
-- 064 4 1 ^ DL11-TX 1st |
-- 177570 - - - - sdreg |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
use work.ibdlib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slv16_1; -- remote attention vector |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_ACKM : in slbit; -- interrupt acknowledge (from master) |
EI_PRI : out slv3; -- interrupt priority (to cpu) |
EI_VECT : out slv9_2; -- interrupt vector (to cpu) |
DISPREG : out slv16 -- display register |
); |
end ibdr_minisys; |
|
architecture syn of ibdr_minisys is |
|
constant conf_intmap : intmap_array_type := |
(intmap_init, -- line 15 |
intmap_init, -- line 14 |
intmap_init, -- line 13 |
intmap_init, -- line 12 |
intmap_init, -- line 11 |
intmap_init, -- line 10 |
intmap_init, -- line 9 |
intmap_init, -- line 8 |
intmap_init, -- line 7 |
intmap_init, -- line 6 |
intmap_init, -- line 5 |
(8#100#,6), -- line 4 KW11-L |
(8#220#,5), -- line 3 RK11 |
(8#060#,4), -- line 2 DL11-RX |
(8#064#,4), -- line 1 DL11-TX |
intmap_init -- line 0 |
); |
|
signal RB_LAM_DL11 : slbit := '0'; |
signal RB_LAM_RK11 : slbit := '0'; |
|
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init; |
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init; |
signal IB_SRES_DL11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init; |
|
signal EI_REQ : slv16_1 := (others=>'0'); |
signal EI_ACK : slv16_1 := (others=>'0'); |
|
signal EI_REQ_KW11L : slbit := '0'; |
signal EI_REQ_DL11RX : slbit := '0'; |
signal EI_REQ_DL11TX : slbit := '0'; |
signal EI_REQ_RK11 : slbit := '0'; |
|
signal EI_ACK_KW11L : slbit := '0'; |
signal EI_ACK_DL11RX : slbit := '0'; |
signal EI_ACK_DL11TX : slbit := '0'; |
signal EI_ACK_RK11 : slbit := '0'; |
|
begin |
|
SDREG : ibdr_sdreg |
port map ( |
CLK => CLK, |
RESET => RESET, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_SDREG, |
DISPREG => DISPREG |
); |
|
KW11L : ibd_kw11l |
port map ( |
CLK => CLK, |
CE_MSEC => CE_MSEC, |
RESET => RESET, |
BRESET => BRESET, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_KW11L, |
EI_REQ => EI_REQ_KW11L, |
EI_ACK => EI_ACK_KW11L |
); |
|
DL11 : ibdr_dl11 |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM_DL11, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_DL11, |
EI_REQ_RX => EI_REQ_DL11RX, |
EI_REQ_TX => EI_REQ_DL11TX, |
EI_ACK_RX => EI_ACK_DL11RX, |
EI_ACK_TX => EI_ACK_DL11TX |
); |
|
RK11 : ibdr_rk11 |
port map ( |
CLK => CLK, |
CE_MSEC => CE_MSEC, |
BRESET => BRESET, |
RB_LAM => RB_LAM_RK11, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_RK11, |
EI_REQ => EI_REQ_RK11, |
EI_ACK => EI_ACK_RK11 |
); |
|
SRES_OR : ib_sres_or_4 |
port map ( |
IB_SRES_1 => IB_SRES_SDREG, |
IB_SRES_2 => IB_SRES_KW11L, |
IB_SRES_3 => IB_SRES_DL11, |
IB_SRES_4 => IB_SRES_RK11, |
IB_SRES_OR => IB_SRES |
); |
|
INTMAP : ib_intmap |
generic map ( |
INTMAP => conf_intmap) |
port map ( |
EI_REQ => EI_REQ, |
EI_ACKM => EI_ACKM, |
EI_ACK => EI_ACK, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT |
); |
|
EI_REQ(4) <= EI_REQ_KW11L; |
EI_REQ(3) <= EI_REQ_RK11; |
EI_REQ(2) <= EI_REQ_DL11RX; |
EI_REQ(1) <= EI_REQ_DL11TX; |
|
EI_ACK_KW11L <= EI_ACK(4); |
EI_ACK_RK11 <= EI_ACK(3); |
EI_ACK_DL11RX <= EI_ACK(2); |
EI_ACK_DL11TX <= EI_ACK(1); |
|
RB_LAM(1) <= RB_LAM_DL11; |
RB_LAM(2) <= '0'; -- for 2nd DL11 |
RB_LAM(3) <= '0'; -- for DZ11 |
RB_LAM(4) <= RB_LAM_RK11; |
RB_LAM(15 downto 5) <= (others=>'0'); |
|
end syn; |
/ibdr_maxisys.vhd
0,0 → 1,422
-- $Id: ibdr_maxisys.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibdr_maxisys - syn |
-- Description: ibus(rem) devices for full system |
-- |
-- Dependencies: ibd_iist |
-- ibd_kw11l |
-- ibdr_rk11 |
-- ibdr_dl11 |
-- ibdr_pc11 |
-- ibdr_lp11 |
-- ibdr_sdreg |
-- ib_sres_or_4 |
-- ib_sres_or_3 |
-- ib_intmap |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 312 1058 16 617 s 10.3 |
-- 2010-10-17 314 12.1 M53d xc3s1000-4 300 1094 16 626 s 10.4 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.1.2 now numeric_std clean |
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM; |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11 |
-- 2009-06-20 227 1.0.3 rename generate labels. |
-- 2009-06-07 224 1.0.2 add iist_mreq and iist_sres interfaces |
-- 2009-06-01 221 1.0.1 add CE_USEC; add RESET to kw11l; add _pc11, _iist |
-- 2009-05-24 219 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- |
-- full system setup |
-- |
-- ibbase vec pri slot attn sror device name |
-- |
-- 172540 104 ?7 14 17 - 1/1 KW11-P |
-- 177500 260 6 13 16 - 1/2 IIST |
-- 177546 100 6 12 15 - 1/3 KW11-L |
-- 174510 120 5 14 9 1/4 DEUNA |
-- 176700 254 5 13 6 2/1 RH70/RP06 |
-- 174400 160 5 11 12 5 2/2 RL11 |
-- 177400 220 5 10 11 4 2/3 RK11 |
-- 172520 224 5 10 7 2/4 TM11 |
-- 160100 310? 5 9 9 3 3/1 DZ11-RX |
-- 314? 5 8 8 ^ DZ11-TX |
-- 177560 060 4 7 7 1 3/2 DL11-RX 1st |
-- 064 4 6 6 ^ DL11-TX 1st |
-- 176500 300 4 5 5 2 3/3 DL11-RX 2nd |
-- 304 4 4 4 ^ DL11-TX 2nd |
-- 177550 070 4 3 3 10 4/1 PC11/PTR |
-- 074 4 2 2 ^ PC11/PTP |
-- 177514 200 4 1 1 8 4/2 LP11 |
-- 177570 - - - - 4/3 sdreg |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
use work.ibdlib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_maxisys is -- ibus(rem) full system |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
CE_MSEC : in slbit; -- msec pulse |
RESET : in slbit; -- reset |
BRESET : in slbit; -- ibus reset |
RB_LAM : out slv16_1; -- remote attention vector |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
EI_ACKM : in slbit; -- interrupt acknowledge (from master) |
EI_PRI : out slv3; -- interrupt priority (to cpu) |
EI_VECT : out slv9_2; -- interrupt vector (to cpu) |
DISPREG : out slv16 -- display register |
); |
end ibdr_maxisys; |
|
architecture syn of ibdr_maxisys is |
|
constant conf_intmap : intmap_array_type := |
(intmap_init, -- line 15 |
(8#104#,6), -- line 14 KW11-P |
(8#260#,6), -- line 13 IIST |
(8#100#,6), -- line 12 KW11-L |
(8#160#,5), -- line 11 RL11 |
(8#220#,5), -- line 10 RK11 |
(8#310#,5), -- line 9 DZ11-RX |
(8#314#,5), -- line 8 DZ11-TX |
(8#060#,4), -- line 7 DL11-RX 1st |
(8#064#,4), -- line 6 DL11-TX 1st |
(8#300#,4), -- line 5 DL11-RX 2nd |
(8#304#,4), -- line 4 DL11-TX 2nd |
(8#070#,4), -- line 3 PC11-PTR |
(8#074#,4), -- line 2 PC11-PTP |
(8#200#,4), -- line 1 LP11 |
intmap_init -- line 0 |
); |
|
signal RB_LAM_DENUA : slbit := '0'; |
signal RB_LAM_RP06 : slbit := '0'; |
signal RB_LAM_RL11 : slbit := '0'; |
signal RB_LAM_RK11 : slbit := '0'; |
signal RB_LAM_TM11 : slbit := '0'; |
signal RB_LAM_DZ11 : slbit := '0'; |
signal RB_LAM_DL11_0 : slbit := '0'; |
signal RB_LAM_DL11_1 : slbit := '0'; |
signal RB_LAM_PC11 : slbit := '0'; |
signal RB_LAM_LP11 : slbit := '0'; |
|
signal IB_SRES_IIST : ib_sres_type := ib_sres_init; |
signal IB_SRES_KW11P : ib_sres_type := ib_sres_init; |
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init; |
signal IB_SRES_DEUNA : ib_sres_type := ib_sres_init; |
signal IB_SRES_RP06 : ib_sres_type := ib_sres_init; |
signal IB_SRES_RL11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_RK11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_TM11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_DZ11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_DL11_0 : ib_sres_type := ib_sres_init; |
signal IB_SRES_DL11_1 : ib_sres_type := ib_sres_init; |
signal IB_SRES_PC11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_LP11 : ib_sres_type := ib_sres_init; |
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init; |
|
signal IB_SRES_1 : ib_sres_type := ib_sres_init; |
signal IB_SRES_2 : ib_sres_type := ib_sres_init; |
signal IB_SRES_3 : ib_sres_type := ib_sres_init; |
signal IB_SRES_4 : ib_sres_type := ib_sres_init; |
|
signal EI_REQ : slv16_1 := (others=>'0'); |
signal EI_ACK : slv16_1 := (others=>'0'); |
|
signal EI_REQ_IIST : slbit := '0'; |
signal EI_REQ_KW11P : slbit := '0'; |
signal EI_REQ_KW11L : slbit := '0'; |
signal EI_REQ_DEUNA : slbit := '0'; |
signal EI_REQ_RP06 : slbit := '0'; |
signal EI_REQ_RL11 : slbit := '0'; |
signal EI_REQ_RK11 : slbit := '0'; |
signal EI_REQ_TM11 : slbit := '0'; |
signal EI_REQ_DZ11RX : slbit := '0'; |
signal EI_REQ_DZ11TX : slbit := '0'; |
signal EI_REQ_DL11RX_0 : slbit := '0'; |
signal EI_REQ_DL11TX_0 : slbit := '0'; |
signal EI_REQ_DL11RX_1 : slbit := '0'; |
signal EI_REQ_DL11TX_1 : slbit := '0'; |
signal EI_REQ_PC11PTR : slbit := '0'; |
signal EI_REQ_PC11PTP : slbit := '0'; |
signal EI_REQ_LP11 : slbit := '0'; |
|
signal EI_ACK_IIST : slbit := '0'; |
signal EI_ACK_KW11P : slbit := '0'; |
signal EI_ACK_KW11L : slbit := '0'; |
signal EI_ACK_DEUNA : slbit := '0'; |
signal EI_ACK_RP06 : slbit := '0'; |
signal EI_ACK_RL11 : slbit := '0'; |
signal EI_ACK_RK11 : slbit := '0'; |
signal EI_ACK_TM11 : slbit := '0'; |
signal EI_ACK_DZ11RX : slbit := '0'; |
signal EI_ACK_DZ11TX : slbit := '0'; |
signal EI_ACK_DL11RX_0 : slbit := '0'; |
signal EI_ACK_DL11TX_0 : slbit := '0'; |
signal EI_ACK_DL11RX_1 : slbit := '0'; |
signal EI_ACK_DL11TX_1 : slbit := '0'; |
signal EI_ACK_PC11PTR : slbit := '0'; |
signal EI_ACK_PC11PTP : slbit := '0'; |
signal EI_ACK_LP11 : slbit := '0'; |
|
signal IIST_BUS : iist_bus_type := iist_bus_init; |
signal IIST_OUT_0 : iist_line_type := iist_line_init; |
signal IIST_MREQ : iist_mreq_type := iist_mreq_init; |
signal IIST_SRES : iist_sres_type := iist_sres_init; |
|
begin |
|
IIST: if true generate |
begin |
I0 : ibd_iist |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => RESET, |
BRESET => BRESET, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_IIST, |
EI_REQ => EI_REQ_IIST, |
EI_ACK => EI_ACK_IIST, |
IIST_BUS => IIST_BUS, |
IIST_OUT => IIST_OUT_0, |
IIST_MREQ => IIST_MREQ, |
IIST_SRES => IIST_SRES |
); |
|
IIST_BUS(0) <= IIST_OUT_0; |
IIST_BUS(1) <= iist_line_init; |
IIST_BUS(2) <= iist_line_init; |
IIST_BUS(3) <= iist_line_init; |
|
end generate IIST; |
|
KW11L : ibd_kw11l |
port map ( |
CLK => CLK, |
CE_MSEC => CE_MSEC, |
RESET => RESET, |
BRESET => BRESET, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_KW11L, |
EI_REQ => EI_REQ_KW11L, |
EI_ACK => EI_ACK_KW11L |
); |
|
RK11: if true generate |
begin |
I0 : ibdr_rk11 |
port map ( |
CLK => CLK, |
CE_MSEC => CE_MSEC, |
BRESET => BRESET, |
RB_LAM => RB_LAM_RK11, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_RK11, |
EI_REQ => EI_REQ_RK11, |
EI_ACK => EI_ACK_RK11 |
); |
end generate RK11; |
|
DL11_0 : ibdr_dl11 |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM_DL11_0, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_DL11_0, |
EI_REQ_RX => EI_REQ_DL11RX_0, |
EI_REQ_TX => EI_REQ_DL11TX_0, |
EI_ACK_RX => EI_ACK_DL11RX_0, |
EI_ACK_TX => EI_ACK_DL11TX_0 |
); |
|
DL11_1: if true generate |
begin |
I0 : ibdr_dl11 |
generic map ( |
IB_ADDR => slv(to_unsigned(8#176500#,16))) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
RESET => RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM_DL11_1, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_DL11_1, |
EI_REQ_RX => EI_REQ_DL11RX_1, |
EI_REQ_TX => EI_REQ_DL11TX_1, |
EI_ACK_RX => EI_ACK_DL11RX_1, |
EI_ACK_TX => EI_ACK_DL11TX_1 |
); |
end generate DL11_1; |
|
PC11: if true generate |
begin |
I0 : ibdr_pc11 |
port map ( |
CLK => CLK, |
RESET => RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM_PC11, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_PC11, |
EI_REQ_PTR => EI_REQ_PC11PTR, |
EI_REQ_PTP => EI_REQ_PC11PTP, |
EI_ACK_PTR => EI_ACK_PC11PTR, |
EI_ACK_PTP => EI_ACK_PC11PTP |
); |
end generate PC11; |
|
LP11: if true generate |
begin |
I0 : ibdr_lp11 |
port map ( |
CLK => CLK, |
RESET => RESET, |
BRESET => BRESET, |
RB_LAM => RB_LAM_LP11, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_LP11, |
EI_REQ => EI_REQ_LP11, |
EI_ACK => EI_ACK_LP11 |
); |
end generate LP11; |
|
SDREG : ibdr_sdreg |
port map ( |
CLK => CLK, |
RESET => RESET, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES_SDREG, |
DISPREG => DISPREG |
); |
|
SRES_OR_1 : ib_sres_or_4 |
port map ( |
IB_SRES_1 => IB_SRES_KW11P, |
IB_SRES_2 => IB_SRES_IIST, |
IB_SRES_3 => IB_SRES_KW11L, |
IB_SRES_4 => IB_SRES_DEUNA, |
IB_SRES_OR => IB_SRES_1 |
); |
|
SRES_OR_2 : ib_sres_or_4 |
port map ( |
IB_SRES_1 => IB_SRES_RP06, |
IB_SRES_2 => IB_SRES_RL11, |
IB_SRES_3 => IB_SRES_RK11, |
IB_SRES_4 => IB_SRES_TM11, |
IB_SRES_OR => IB_SRES_2 |
); |
|
SRES_OR_3 : ib_sres_or_3 |
port map ( |
IB_SRES_1 => IB_SRES_DZ11, |
IB_SRES_2 => IB_SRES_DL11_0, |
IB_SRES_3 => IB_SRES_DL11_1, |
IB_SRES_OR => IB_SRES_3 |
); |
|
SRES_OR_4 : ib_sres_or_3 |
port map ( |
IB_SRES_1 => IB_SRES_PC11, |
IB_SRES_2 => IB_SRES_LP11, |
IB_SRES_3 => IB_SRES_SDREG, |
IB_SRES_OR => IB_SRES_4 |
); |
|
SRES_OR : ib_sres_or_4 |
port map ( |
IB_SRES_1 => IB_SRES_1, |
IB_SRES_2 => IB_SRES_2, |
IB_SRES_3 => IB_SRES_3, |
IB_SRES_4 => IB_SRES_4, |
IB_SRES_OR => IB_SRES |
); |
|
INTMAP : ib_intmap |
generic map ( |
INTMAP => conf_intmap) |
port map ( |
EI_REQ => EI_REQ, |
EI_ACKM => EI_ACKM, |
EI_ACK => EI_ACK, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT |
); |
|
EI_REQ(14) <= EI_REQ_KW11P; |
EI_REQ(13) <= EI_REQ_IIST; |
EI_REQ(12) <= EI_REQ_KW11L; |
EI_REQ(11) <= EI_REQ_RL11; |
EI_REQ(10) <= EI_REQ_RK11; |
EI_REQ( 9) <= EI_REQ_DZ11RX; |
EI_REQ( 8) <= EI_REQ_DZ11TX; |
EI_REQ( 7) <= EI_REQ_DL11RX_0; |
EI_REQ( 6) <= EI_REQ_DL11TX_0; |
EI_REQ( 5) <= EI_REQ_DL11RX_1; |
EI_REQ( 4) <= EI_REQ_DL11TX_1; |
EI_REQ( 3) <= EI_REQ_PC11PTR; |
EI_REQ( 2) <= EI_REQ_PC11PTP; |
EI_REQ( 1) <= EI_REQ_LP11; |
|
EI_ACK_KW11P <= EI_ACK(14); |
EI_ACK_IIST <= EI_ACK(13); |
EI_ACK_KW11L <= EI_ACK(12); |
EI_ACK_RL11 <= EI_ACK(11); |
EI_ACK_RK11 <= EI_ACK(10); |
EI_ACK_DZ11RX <= EI_ACK( 9); |
EI_ACK_DZ11TX <= EI_ACK( 8); |
EI_ACK_DL11RX_0 <= EI_ACK( 7); |
EI_ACK_DL11TX_0 <= EI_ACK( 6); |
EI_ACK_DL11RX_1 <= EI_ACK( 5); |
EI_ACK_DL11TX_1 <= EI_ACK( 4); |
EI_ACK_PC11PTR <= EI_ACK( 3); |
EI_ACK_PC11PTP <= EI_ACK( 2); |
EI_ACK_LP11 <= EI_ACK( 1); |
|
RB_LAM(15 downto 11) <= (others=>'0'); |
RB_LAM(10) <= RB_LAM_PC11; |
RB_LAM( 9) <= RB_LAM_DENUA; |
RB_LAM( 8) <= RB_LAM_LP11; |
RB_LAM( 7) <= RB_LAM_TM11; |
RB_LAM( 6) <= RB_LAM_RP06; |
RB_LAM( 5) <= RB_LAM_RL11; |
RB_LAM( 4) <= RB_LAM_RK11; |
RB_LAM( 3) <= RB_LAM_DZ11; |
RB_LAM( 2) <= RB_LAM_DL11_1; |
RB_LAM( 1) <= RB_LAM_DL11_0; |
|
end syn; |
/ib_intmap.vhd
0,0 → 1,139
-- $Id: ib_intmap.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ib_intmap - syn |
-- Description: pdp11: external interrupt mapper |
-- |
-- Dependencies: - |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2008-08-22 161 1.2.1 renamed pdp11_ -> ib_; use iblib |
-- 2008-01-20 112 1.2 add INTMAP generic to externalize config |
-- 2008-01-06 111 1.1 add EI_ACK output lines, remove EI_LINE |
-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned |
-- 2007-06-14 56 1.0.1 Use slvtypes.all |
-- 2007-05-12 26 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity ib_intmap is -- external interrupt mapper |
generic ( |
INTMAP : intmap_array_type := intmap_array_init); |
port ( |
EI_REQ : in slv16_1; -- interrupt request lines |
EI_ACKM : in slbit; -- interrupt acknowledge (from master) |
EI_ACK : out slv16_1; -- interrupt acknowledge (to requestor) |
EI_PRI : out slv3; -- interrupt priority |
EI_VECT : out slv9_2 -- interrupt vector |
); |
end ib_intmap; |
|
architecture syn of ib_intmap is |
|
signal EI_LINE : slv4 := (others=>'0'); -- external interrupt line |
|
type intp_type is array (15 downto 0) of slv3; |
type intv_type is array (15 downto 0) of slv9; |
|
constant conf_intp : intp_type := |
(slv(to_unsigned(INTMAP(15).pri,3)), -- line 15 |
slv(to_unsigned(INTMAP(14).pri,3)), -- line 14 |
slv(to_unsigned(INTMAP(13).pri,3)), -- line 13 |
slv(to_unsigned(INTMAP(12).pri,3)), -- line 12 |
slv(to_unsigned(INTMAP(11).pri,3)), -- line 11 |
slv(to_unsigned(INTMAP(10).pri,3)), -- line 10 |
slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9 |
slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8 |
slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7 |
slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6 |
slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5 |
slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4 |
slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3 |
slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2 |
slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1 |
slv(to_unsigned( 0,3)) -- line 0 (always 0 !!) |
); |
|
constant conf_intv : intv_type := |
(slv(to_unsigned(INTMAP(15).vec,9)), -- line 15 |
slv(to_unsigned(INTMAP(14).vec,9)), -- line 14 |
slv(to_unsigned(INTMAP(13).vec,9)), -- line 13 |
slv(to_unsigned(INTMAP(12).vec,9)), -- line 12 |
slv(to_unsigned(INTMAP(11).vec,9)), -- line 11 |
slv(to_unsigned(INTMAP(10).vec,9)), -- line 10 |
slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9 |
slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8 |
slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7 |
slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6 |
slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5 |
slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4 |
slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3 |
slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2 |
slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1 |
slv(to_unsigned( 0,9)) -- line 0 (always 0 !!) |
); |
|
-- attribute PRIORITY_EXTRACT : string; |
-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force"; |
|
begin |
|
EI_LINE <= "1111" when EI_REQ(15)='1' else |
"1110" when EI_REQ(14)='1' else |
"1101" when EI_REQ(13)='1' else |
"1100" when EI_REQ(12)='1' else |
"1011" when EI_REQ(11)='1' else |
"1010" when EI_REQ(10)='1' else |
"1001" when EI_REQ( 9)='1' else |
"1000" when EI_REQ( 8)='1' else |
"0111" when EI_REQ( 7)='1' else |
"0110" when EI_REQ( 6)='1' else |
"0101" when EI_REQ( 5)='1' else |
"0100" when EI_REQ( 4)='1' else |
"0011" when EI_REQ( 3)='1' else |
"0010" when EI_REQ( 2)='1' else |
"0001" when EI_REQ( 1)='1' else |
"0000"; |
|
proc_intmap : process (EI_LINE, EI_ACKM) |
variable iline : integer := 0; |
variable iei_ack : slv16 := (others=>'0'); |
begin |
|
iline := to_integer(unsigned(EI_LINE)); |
|
iei_ack := (others=>'0'); |
if EI_ACKM = '1' then |
iei_ack(iline) := '1'; |
end if; |
|
EI_ACK <= iei_ack(EI_ACK'range); |
EI_PRI <= conf_intp(iline); |
EI_VECT <= conf_intv(iline)(8 downto 2); |
|
end process proc_intmap; |
|
end syn; |
/ibdr_sdreg.vhd
0,0 → 1,147
-- $Id: ibdr_sdreg.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ibdr_sdreg - syn |
-- Description: ibus dev(rem): Switch/Display register |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-10-17 333 12.1 M53d xc3s1000-4 34 40 0 30 s 4.0 |
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 32 39 0 29 s 2.5 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.2.1 now numeric_std clean |
-- 2010-10-17 333 1.2 use ibus V2 interface |
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ |
-- 2008-08-22 161 1.0.4 use iblib |
-- 2008-04-18 136 1.0.3 use RESET. Switch/Display not cleared by console |
-- reset or reset instruction, only by cpu_reset |
-- 2008-01-20 112 1.0.2 use BRESET |
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy) |
-- reorganize code, all in state_type/proc_next |
-- 2007-12-31 108 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
entity ibdr_sdreg is -- ibus dev(rem): Switch/Display regs |
-- fixed address: 177570 |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
DISPREG : out slv16 -- display register |
); |
end ibdr_sdreg; |
|
architecture syn of ibdr_sdreg is |
|
constant ibaddr_sdreg : slv16 := slv(to_unsigned(8#177570#,16)); |
|
type regs_type is record -- state registers |
ibsel : slbit; -- ibus select |
sreg : slv16; -- switch register |
dreg : slv16; -- display register |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- ibsel |
(others=>'0'), -- sreg |
(others=>'0') -- dreg |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
begin |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, IB_MREQ) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable idout : slv16 := (others=>'0'); |
variable ibreq : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
idout := (others=>'0'); |
ibreq := IB_MREQ.re or IB_MREQ.we; |
|
-- ibus address decoder |
n.ibsel := '0'; |
if IB_MREQ.aval='1' and |
IB_MREQ.addr=ibaddr_sdreg(12 downto 1) then |
n.ibsel := '1'; |
end if; |
|
-- ibus output driver |
if r.ibsel = '1' then |
if IB_MREQ.racc = '0' then |
idout := r.sreg; -- cpu will read switch register |
else |
idout := r.dreg; -- rri will read display register |
end if; |
end if; |
|
-- ibus write transactions |
if r.ibsel='1' and IB_MREQ.we='1' then |
if IB_MREQ.racc = '0' then -- cpu will write display register |
if IB_MREQ.be1 = '1' then |
n.dreg(ibf_byte1) := IB_MREQ.din(ibf_byte1); |
end if; |
if IB_MREQ.be0 = '1' then |
n.dreg(ibf_byte0) := IB_MREQ.din(ibf_byte0); |
end if; |
else -- rri will write switch register |
n.sreg := IB_MREQ.din; -- byte write not supported |
end if; |
end if; |
|
N_REGS <= n; |
|
IB_SRES.dout <= idout; |
IB_SRES.ack <= r.ibsel and ibreq; |
IB_SRES.busy <= '0'; |
|
DISPREG <= r.dreg; |
|
end process proc_next; |
|
|
end syn; |
/ib_sel.vhd
0,0 → 1,69
-- $Id: ib_sel.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ib_sel - syn |
-- Description: ibus: address select logic |
-- |
-- Dependencies: - |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: xst 12.1; ghdl 0.29 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity ib_sel is -- ibus address select logic |
generic ( |
IB_ADDR : slv16; -- ibus address base |
SAWIDTH : natural := 0); -- device subaddress space width |
port ( |
CLK : in slbit; -- clock |
IB_MREQ : in ib_mreq_type; -- ibus request |
SEL : out slbit -- select state bit |
); |
end ib_sel; |
|
architecture syn of ib_sel is |
signal R_SEL : slbit := '0'; |
begin |
|
assert SAWIDTH<=10 -- at most 1k words devices |
report "assert(SAWIDTH<=10)" severity failure; |
|
proc_regs: process (CLK) |
variable isel : slbit := '0'; |
begin |
if rising_edge(CLK) then |
isel := '0'; |
if IB_MREQ.aval='1' and |
IB_MREQ.addr(12 downto SAWIDTH+1)=IB_ADDR(12 downto SAWIDTH+1) then |
isel := '1'; |
end if; |
R_SEL <= isel; |
end if; |
end process proc_regs; |
|
SEL <= R_SEL; |
|
end syn; |
/ib_sres_or_mon.vhd
0,0 → 1,99
-- $Id: ib_sres_or_mon.vhd 336 2010-11-06 18:28:27Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ib_sres_or_mon - sim |
-- Description: ibus result or monitor |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Tool versions: ghdl 0.29 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches) |
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity ib_sres_or_mon is -- ibus result or monitor |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type; -- ib_sres input 2 |
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3 |
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4 |
); |
end ib_sres_or_mon; |
|
architecture sim of ib_sres_or_mon is |
|
begin |
|
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4) |
constant dzero : slv16 := (others=>'0'); |
variable oline : line; |
variable nack : integer := 0; |
variable nbusy : integer := 0; |
variable ndout : integer := 0; |
begin |
|
nack := 0; |
nbusy := 0; |
ndout := 0; |
|
if IB_SRES_1.ack /= '0' then nack := nack + 1; end if; |
if IB_SRES_2.ack /= '0' then nack := nack + 1; end if; |
if IB_SRES_3.ack /= '0' then nack := nack + 1; end if; |
if IB_SRES_4.ack /= '0' then nack := nack + 1; end if; |
|
if IB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if; |
if IB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if; |
if IB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if; |
if IB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if; |
|
if IB_SRES_1.dout /= dzero then ndout := ndout + 1; end if; |
if IB_SRES_2.dout /= dzero then ndout := ndout + 1; end if; |
if IB_SRES_3.dout /= dzero then ndout := ndout + 1; end if; |
if IB_SRES_4.dout /= dzero then ndout := ndout + 1; end if; |
|
if now > 0 ns and (nack>1 or nbusy>1 or ndout>1) then |
write(oline, now, right, 12); |
if nack > 1 then |
write(oline, string'(" #ack=")); |
write(oline, nack); |
end if; |
if nbusy > 1 then |
write(oline, string'(" #busy=")); |
write(oline, nbusy); |
end if; |
if ndout > 1 then |
write(oline, string'(" #dout=")); |
write(oline, ndout); |
end if; |
write(oline, string'(" FAIL in ")); |
write(oline, ib_sres_or_mon'path_name); |
writeline(output, oline); |
end if; |
|
end process proc_comb; |
|
end sim; |
/ib_sres_or_2.vhd
0,0 → 1,73
-- $Id: ib_sres_or_2.vhd 335 2010-10-24 22:24:23Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ib_sres_or_2 - syn |
-- Description: ibus: result or, 2 input |
-- |
-- Dependencies: - |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-10-23 335 1.1 add ib_sres_or_mon |
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib |
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy) |
-- 2007-12-29 107 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity ib_sres_or_2 is -- ibus result or, 2 input |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2 |
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output |
); |
end ib_sres_or_2; |
|
architecture syn of ib_sres_or_2 is |
|
begin |
|
proc_comb : process (IB_SRES_1, IB_SRES_2) |
begin |
|
IB_SRES_OR.ack <= IB_SRES_1.ack or |
IB_SRES_2.ack; |
IB_SRES_OR.busy <= IB_SRES_1.busy or |
IB_SRES_2.busy; |
IB_SRES_OR.dout <= IB_SRES_1.dout or |
IB_SRES_2.dout; |
|
end process proc_comb; |
|
-- synthesis translate_off |
ORMON : ib_sres_or_mon |
port map ( |
IB_SRES_1 => IB_SRES_1, |
IB_SRES_2 => IB_SRES_2, |
IB_SRES_3 => ib_sres_init, |
IB_SRES_4 => ib_sres_init |
); |
-- synthesis translate_on |
|
end syn; |
/ib_sres_or_3.vhd
0,0 → 1,77
-- $Id: ib_sres_or_3.vhd 335 2010-10-24 22:24:23Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ib_sres_or_3 - syn |
-- Description: ibus: result or, 3 input |
-- |
-- Dependencies: - |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-10-23 335 1.1 add ib_sres_or_mon |
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib |
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy) |
-- 2007-12-29 107 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity ib_sres_or_3 is -- ibus result or, 3 input |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2 |
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3 |
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output |
); |
end ib_sres_or_3; |
|
architecture syn of ib_sres_or_3 is |
|
begin |
|
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3) |
begin |
|
IB_SRES_OR.ack <= IB_SRES_1.ack or |
IB_SRES_2.ack or |
IB_SRES_3.ack; |
IB_SRES_OR.busy <= IB_SRES_1.busy or |
IB_SRES_2.busy or |
IB_SRES_3.busy; |
IB_SRES_OR.dout <= IB_SRES_1.dout or |
IB_SRES_2.dout or |
IB_SRES_3.dout; |
|
end process proc_comb; |
|
-- synthesis translate_off |
ORMON : ib_sres_or_mon |
port map ( |
IB_SRES_1 => IB_SRES_1, |
IB_SRES_2 => IB_SRES_2, |
IB_SRES_3 => IB_SRES_3, |
IB_SRES_4 => ib_sres_init |
); |
-- synthesis translate_on |
|
end syn; |
/ib_sres_or_4.vhd
0,0 → 1,81
-- $Id: ib_sres_or_4.vhd 335 2010-10-24 22:24:23Z mueller $ |
-- |
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: ib_sres_or_4 - syn |
-- Description: ibus: result or, 4 input |
-- |
-- Dependencies: - |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-10-23 335 1.1 add ib_sres_or_mon |
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib |
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy) |
-- 2007-12-29 107 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity ib_sres_or_4 is -- ibus result or, 4 input |
port ( |
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1 |
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2 |
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3 |
IB_SRES_4 : in ib_sres_type := ib_sres_init; -- ib_sres input 4 |
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output |
); |
end ib_sres_or_4; |
|
architecture syn of ib_sres_or_4 is |
|
begin |
|
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4) |
begin |
|
IB_SRES_OR.ack <= IB_SRES_1.ack or |
IB_SRES_2.ack or |
IB_SRES_3.ack or |
IB_SRES_4.ack; |
IB_SRES_OR.busy <= IB_SRES_1.busy or |
IB_SRES_2.busy or |
IB_SRES_3.busy or |
IB_SRES_4.busy; |
IB_SRES_OR.dout <= IB_SRES_1.dout or |
IB_SRES_2.dout or |
IB_SRES_3.dout or |
IB_SRES_4.dout; |
|
end process proc_comb; |
|
-- synthesis translate_off |
ORMON : ib_sres_or_mon |
port map ( |
IB_SRES_1 => IB_SRES_1, |
IB_SRES_2 => IB_SRES_2, |
IB_SRES_3 => IB_SRES_3, |
IB_SRES_4 => IB_SRES_4 |
); |
-- synthesis translate_on |
|
end syn; |
/ib_sel.vbom
0,0 → 1,6
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# components |
# design |
ib_sel.vhd |
/ib_sres_or_mon.vbom
0,0 → 1,5
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# design |
ib_sres_or_mon.vhd |
/ib_sres_or_2.vbom
0,0 → 1,7
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# components |
[ghdl,isim]ib_sres_or_mon.vbom |
# design |
ib_sres_or_2.vhd |
/ib_sres_or_4.vbom
0,0 → 1,7
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# components |
[ghdl,isim]ib_sres_or_mon.vbom |
# design |
ib_sres_or_4.vhd |
/ib_sres_or_3.vbom
0,0 → 1,7
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# components |
[ghdl,isim]ib_sres_or_mon.vbom |
# design |
ib_sres_or_3.vhd |
/ibdr_lp11.vbom
0,0 → 1,5
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# design |
ibdr_lp11.vhd |
/ibd_kw11l.vbom
0,0 → 1,5
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# design |
ibd_kw11l.vhd |
/ibdr_rk11.vbom
0,0 → 1,9
# libs |
../vlib/slvtypes.vhd |
../vlib/memlib/memlib.vhd |
iblib.vhd |
# components |
[ghdl,isim]../vlib/memlib/ram_1swar_gen.vbom |
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom |
# design |
ibdr_rk11.vhd |
/ibd_iist.vbom
0,0 → 1,6
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
ibdlib.vhd |
# design |
ibd_iist.vhd |
/ibdr_minisys.vbom
0,0 → 1,13
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
ibdlib.vhd |
# components |
ibdr_sdreg.vbom |
ibd_kw11l.vbom |
ibdr_dl11.vbom |
ibdr_rk11.vbom |
ib_sres_or_4.vbom |
ib_intmap.vbom |
# design |
ibdr_minisys.vhd |
/ibdr_maxisys.vbom
0,0 → 1,17
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
ibdlib.vhd |
# components |
ibd_iist.vbom |
ibd_kw11l.vbom |
ibdr_rk11.vbom |
ibdr_dl11.vbom |
ibdr_pc11.vbom |
ibdr_lp11.vbom |
ibdr_sdreg.vbom |
ib_sres_or_4.vbom |
ib_sres_or_3.vbom |
ib_intmap.vbom |
# design |
ibdr_maxisys.vhd |
/ibdr_dl11.vbom
0,0 → 1,5
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# design |
ibdr_dl11.vhd |
/ib_intmap.vbom
0,0 → 1,5
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# design |
ib_intmap.vhd |
/ibdr_sdreg.vbom
0,0 → 1,5
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# design |
ibdr_sdreg.vhd |
/ibdr_pc11.vbom
0,0 → 1,5
# libs |
../vlib/slvtypes.vhd |
iblib.vhd |
# design |
ibdr_pc11.vhd |
.
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log