OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /w11/tags/w11a_V0.6/rtl/sys_gen/tst_rlink/nexys3/tb
    from Rev 22 to Rev 24
    Reverse comparison

Rev 22 → Rev 24

/sys_conf_sim.vhd
0,0 → 1,49
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
 
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
 
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
 
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
end package sys_conf;
/tb_tst_rlink_n3_ssim.vbom
0,0 → 1,6
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
nexys3_fusp_aif = sys_tst_rlink_n3_ssim.vhd
tb_tst_rlink_n3.vbom
@top:tb_tst_rlink_n3
/Makefile
0,0 → 1,32
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-11-26 433 1.0 Initial version
#
EXE_all = tb_tst_rlink_n3
#
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean
rm -f sys_tst_rlink_n3.ucf
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
endif
#
/tb_tst_rlink_n3.vbom
0,0 → 1,7
# configure tb_nexsy3_fusp with sys_tst_rlink_n3 target;
# use vhdl configure file (tb_tst_rlink_n3.vhd) to allow
# that all configurations will co-exist in work library
${nexys3_fusp_aif := ../sys_tst_rlink_n3.vbom}
sys_conf = sys_conf_sim.vhd
../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom
tb_tst_rlink_n3.vhd
/tbw.dat
0,0 → 1,6
# $Id: tbw.dat 433 2011-11-27 22:04:39Z mueller $
#
[tb_tst_rlink_n3]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
/sys_tst_rlink_n3.ucf_cpp
0,0 → 1,6
link ../sys_tst_rlink_n3.ucf_cpp
sys_tst_rlink_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: .cvsignore =================================================================== --- .cvsignore (nonexistent) +++ .cvsignore (revision 24) @@ -0,0 +1,7 @@ +tb_tst_rlink_n3 +tb_tst_rlink_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_n3.ucf +*.dep_ucf_cpp Index: tb_tst_rlink_n3.vhd =================================================================== --- tb_tst_rlink_n3.vhd (nonexistent) +++ tb_tst_rlink_n3.vhd (revision 24) @@ -0,0 +1,39 @@ +-- $Id: tb_tst_rlink_n3.vhd 435 2011-12-04 20:15:25Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_n3 +-- Description: Configuration for tb_tst_rlink_n3 for tb_nexys3_fusp +-- +-- Dependencies: sys_tst_rlink_n3 +-- +-- To test: sys_tst_rlink_n3 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-xx xxx - 0.29 13.1 O40d xc6slx16-2 u:??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_n3 of tb_nexys3_fusp is + + for sim + for all : nexys3_fusp_aif + use entity work.sys_tst_rlink_n3; + end for; + end for; + +end tb_tst_rlink_n3; Index: . =================================================================== --- . (nonexistent) +++ . (revision 24)
. Property changes : Added: svn:ignore ## -0,0 +1,39 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_rlink_n3 +tb_tst_rlink_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_n3.ucf +*.dep_ucf_cpp

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.