URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
Compare Revisions
- This comparison shows the changes necessary to convert path
/w11/tags/w11a_V0.6/rtl/sys_gen/tst_serloop/nexys3
- from Rev 19 to Rev 24
- ↔ Reverse comparison
Rev 19 → Rev 24
/tb/Makefile
0,0 → 1,34
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-12-11 438 1.0.1 added tb_tst_serloop1_n3 |
# 2011-11-27 433 1.0 Initial version |
# |
EXE_all = tb_tst_serloop1_n3 |
# |
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk |
# |
.PHONY : all all_ssim all_tsim clean |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
all_tsim : $(EXE_all:=_tsim) |
# |
clean : ise_clean ghdl_clean isim_clean |
# |
#----- |
# |
include $(RETROBASE)/rtl/make/generic_ghdl.mk |
include $(RETROBASE)/rtl/make/generic_isim.mk |
include $(RETROBASE)/rtl/make/generic_xflow.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_isim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
/tb/tb_tst_serloop1_n3.vhd
0,0 → 1,139
-- $Id: tb_tst_serloop1_n3.vhd 444 2011-12-25 10:04:58Z mueller $ |
-- |
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tb_tst_serloop1_n3 - sim |
-- Description: Test bench for sys_tst_serloop1_n3 |
-- |
-- Dependencies: simlib/simclk |
-- sys_tst_serloop1_n3 [UUT] |
-- tb/tb_tst_serloop |
-- |
-- To test: sys_tst_serloop1_n3 |
-- |
-- Target Devices: generic |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-12-23 444 1.1 use new simclk |
-- 2011-12-11 438 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
|
entity tb_tst_serloop1_n3 is |
end tb_tst_serloop1_n3; |
|
architecture sim of tb_tst_serloop1_n3 is |
|
signal CLK100 : slbit := '0'; |
signal CLK_STOP : slbit := '0'; |
|
signal I_RXD : slbit := '1'; |
signal O_TXD : slbit := '1'; |
signal I_SWI : slv8 := (others=>'0'); |
signal I_BTN : slv5 := (others=>'0'); |
|
signal O_FUSP_RTS_N : slbit := '0'; |
signal I_FUSP_CTS_N : slbit := '0'; |
signal I_FUSP_RXD : slbit := '1'; |
signal O_FUSP_TXD : slbit := '1'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '1'; |
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv5 := (others=>'0'); |
|
signal FUSP_RTS_N : slbit := '0'; |
signal FUSP_CTS_N : slbit := '0'; |
signal FUSP_RXD : slbit := '1'; |
signal FUSP_TXD : slbit := '1'; |
|
constant clock_period : time := 10 ns; |
constant clock_offset : time := 200 ns; |
constant delay_time : time := 2 ns; |
|
begin |
|
SYSCLK : simclk |
generic map ( |
PERIOD => clock_period, |
OFFSET => clock_offset) |
port map ( |
CLK => CLK100, |
CLK_STOP => CLK_STOP |
); |
|
UUT : entity work.sys_tst_serloop1_n3 |
port map ( |
I_CLK100 => CLK100, |
I_RXD => I_RXD, |
O_TXD => O_TXD, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => open, |
O_ANO_N => open, |
O_SEG_N => open, |
O_MEM_CE_N => open, |
O_MEM_BE_N => open, |
O_MEM_WE_N => open, |
O_MEM_OE_N => open, |
O_MEM_ADV_N => open, |
O_MEM_CLK => open, |
O_MEM_CRE => open, |
I_MEM_WAIT => '0', |
O_MEM_ADDR => open, |
IO_MEM_DATA => open, |
O_PPCM_CE_N => open, |
O_PPCM_RST_N => open, |
O_FUSP_RTS_N => O_FUSP_RTS_N, |
I_FUSP_CTS_N => I_FUSP_CTS_N, |
I_FUSP_RXD => I_FUSP_RXD, |
O_FUSP_TXD => O_FUSP_TXD |
); |
|
GENTB : entity work.tb_tst_serloop |
port map ( |
CLKS => CLK100, |
CLKH => CLK100, |
CLK_STOP => CLK_STOP, |
P0_RXD => RXD, |
P0_TXD => TXD, |
P0_RTS_N => '0', |
P0_CTS_N => open, |
P1_RXD => FUSP_RXD, |
P1_TXD => FUSP_TXD, |
P1_RTS_N => FUSP_RTS_N, |
P1_CTS_N => FUSP_CTS_N, |
SWI => SWI, |
BTN => BTN(3 downto 0) |
); |
|
I_RXD <= RXD after delay_time; |
TXD <= O_TXD after delay_time; |
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; |
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; |
I_FUSP_RXD <= FUSP_RXD after delay_time; |
FUSP_TXD <= O_FUSP_TXD after delay_time; |
|
I_SWI <= SWI after delay_time; |
I_BTN <= BTN after delay_time; |
|
end sim; |
/tb/tbw.dat
0,0 → 1,6
# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $ |
# |
[tb_tst_serloop1_n3] |
tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat |
[tb_tst_serloop2_n3] |
tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat |
/tb/tb_tst_serloop1_n3.vbom
0,0 → 1,11
# conf |
sys_conf = sys_conf1_sim.vhd |
# libs |
../../../../vlib/slvtypes.vhd |
../../../../vlib/simlib/simlib.vhd |
# components |
../../../../vlib/simlib/simclk.vbom |
../sys_tst_serloop1_n3.vbom |
../../tb/tb_tst_serloop.vbom |
# design |
tb_tst_serloop1_n3.vhd |
/tb/sys_tst_serloop1_n3.ucf_cpp
0,0 → 1,11
link ../sys_tst_serloop1_n3.ucf_cpp |
tb/sys_tst_serloop1_n3.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: tb/sys_conf1_sim.vhd
===================================================================
--- tb/sys_conf1_sim.vhd (nonexistent)
+++ tb/sys_conf1_sim.vhd (revision 24)
@@ -0,0 +1,43 @@
+-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop1_n3 (for test bench)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-11 438 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ -- in simulation a usec is shortened to 20 cycles (0.2 usec) and a msec
+ -- to 100 cycles (1 usec). This affects the pulse generators (usec) and
+ -- mainly the autobauder. A break will be detected after 128 msec periods,
+ -- this in simulation after 128 usec or 6400 cycles. This is compatible with
+ -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
+
+ constant sys_conf_clkdiv_usecdiv : integer := 20; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+ constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+end package sys_conf;
Index: tb/.cvsignore
===================================================================
--- tb/.cvsignore (nonexistent)
+++ tb/.cvsignore (revision 24)
@@ -0,0 +1,10 @@
+tb_tst_serloop1_n3
+tb_tst_serloop1_n3_[sft]sim
+tb_tst_serloop1_n3_ISim
+tb_tst_serloop1_n3_ISim_[sft]sim
+tb_tst_serloop2_n3
+tb_tst_serloop2_n3_[sft]sim
+tb_tst_serloop2_n3_ISim
+tb_tst_serloop2_n3_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: tb
===================================================================
--- tb (nonexistent)
+++ tb (revision 24)
tb
Property changes :
Added: svn:ignore
## -0,0 +1,42 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_tst_serloop1_n3
+tb_tst_serloop1_n3_[sft]sim
+tb_tst_serloop1_n3_ISim
+tb_tst_serloop1_n3_ISim_[sft]sim
+tb_tst_serloop2_n3
+tb_tst_serloop2_n3_[sft]sim
+tb_tst_serloop2_n3_ISim
+tb_tst_serloop2_n3_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: sys_tst_serloop1_n3.vhd
===================================================================
--- sys_tst_serloop1_n3.vhd (nonexistent)
+++ sys_tst_serloop1_n3.vhd (revision 24)
@@ -0,0 +1,243 @@
+-- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_tst_serloop1_n3 - syn
+-- Description: Tester serial link for nexys3 (serport_1clock case)
+--
+-- Dependencies: genlib/clkdivce
+-- bpgen/bp_rs232_2l4l_iob
+-- bpgen/sn_humanio
+-- tst_serloop_hiomap
+-- vlib/serport/serport_1clock
+-- tst_serloop
+-- vlib/nxcramlib/nx_cram_dummy
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3)
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.tst_serlooplib.all;
+use work.serportlib.all;
+use work.nxcramlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_serloop1_n3 is -- top level
+ -- implements nexys3_fusp_aif
+ port (
+ I_CLK100 : in slbit; -- 100 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit; -- ppcm: ...
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_tst_serloop1_n3;
+
+architecture syn of sys_tst_serloop1_n3 is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal RXD : slbit := '0';
+ signal TXD : slbit := '0';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv5 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
+ signal HIO_STAT : hio_stat_type := hio_stat_init;
+
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXHOLD : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal SER_MONI : serport_moni_type := serport_moni_init;
+
+begin
+
+ CLK <= I_CLK100;
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 8,
+ USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
+ MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
+ port map (
+ CLK => CLK,
+ CE_USEC => open,
+ CE_MSEC => CE_MSEC
+ );
+
+ HIO : sn_humanio
+ generic map (
+ BWIDTH => 5,
+ DEBOUNCE => sys_conf_hio_debounce)
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ CE_MSEC => CE_MSEC,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RESET <= BTN(0); -- BTN(0) will reset tester !!
+
+ HIOMAP : tst_serloop_hiomap
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ SWI => SWI,
+ BTN => BTN(3 downto 0),
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP
+ );
+
+ IOB_RS232 : bp_rs232_2l4l_iob
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ SEL => SWI(0), -- port selection
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ SERPORT : serport_1clock
+ generic map (
+ CDWIDTH => 15,
+ CDINIT => sys_conf_uart_cdinit,
+ RXFAWIDTH => 5,
+ TXFAWIDTH => 5)
+ port map (
+ CLK => CLK,
+ CE_MSEC => CE_MSEC,
+ RESET => RESET,
+ ENAXON => HIO_CNTL.enaxon,
+ ENAESC => HIO_CNTL.enaesc,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY,
+ MONI => SER_MONI,
+ RXSD => RXD,
+ TXSD => TXD,
+ RXRTS_N => RTS_N,
+ TXCTS_N => CTS_N
+ );
+
+ TESTER : tst_serloop
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
+ O_PPCM_RST_N <= '1'; --
+
+end syn;
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 24)
@@ -0,0 +1,28 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-27 433 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+endif
+#
Index: sys_tst_serloop1_n3.vbom
===================================================================
--- sys_tst_serloop1_n3.vbom (nonexistent)
+++ sys_tst_serloop1_n3.vbom (revision 24)
@@ -0,0 +1,20 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../tst_serlooplib.vbom
+../../../vlib/serport/serportlib.vbom
+../../../bplib/nxcramlib/nxcramlib.vhd
+${sys_conf := sys_conf1.vhd}
+# components
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio.vbom
+../tst_serloop_hiomap.vbom
+../../../vlib/serport/serport_1clock.vbom
+../tst_serloop.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+# design
+sys_tst_serloop1_n3.vhd
+@ucf_cpp: sys_tst_serloop1_n3.ucf
Index: sys_conf1.vhd
===================================================================
--- sys_conf1.vhd (nonexistent)
+++ sys_conf1.vhd (revision 24)
@@ -0,0 +1,37 @@
+-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop1_n3 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-09 438 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+ constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200
+
+end package sys_conf;
Index: sys_tst_serloop1_n3.ucf_cpp
===================================================================
--- sys_tst_serloop1_n3.ucf_cpp (nonexistent)
+++ sys_tst_serloop1_n3.ucf_cpp (revision 24)
@@ -0,0 +1,19 @@
+## $Id: sys_tst_serloop1_n3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-12-09 438 1.0 Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns AFTER "I_CLK100";
+
+## std board
+##
+#include "bplib/nexys3/nexys3_pins.ucf"
+##
+## Pmod B0 - RS232
+##
+#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
Index: .cvsignore
===================================================================
--- .cvsignore (nonexistent)
+++ .cvsignore (revision 24)
@@ -0,0 +1,5 @@
+_impactbatch.log
+sys_tst_serloop1_n3.ucf
+sys_tst_serloop2_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 24)
.
Property changes :
Added: svn:ignore
## -0,0 +1,37 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_serloop1_n3.ucf
+sys_tst_serloop2_n3.ucf
+*.dep_ucf_cpp
+*.svf