URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
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- This comparison shows the changes necessary to convert path
/w11/tags/w11a_V0.6/rtl/sys_gen/tst_serloop
- from Rev 19 to Rev 24
- ↔ Reverse comparison
Rev 19 → Rev 24
/tst_serloop.vbom
0,0 → 1,7
# libs |
../../vlib/slvtypes.vhd |
../../vlib/serport/serportlib.vbom |
tst_serlooplib.vhd |
# components |
# design |
tst_serloop.vhd |
/tst_serlooplib.vhd
0,0 → 1,111
-- $Id: tst_serlooplib.vhd 476 2013-01-26 22:23:53Z mueller $ |
-- |
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: tst_serlooplib |
-- Description: Definitions for tst_serloop records and helpers |
-- |
-- Dependencies: - |
-- Tool versions: xst 13.1; ghdl 0.29 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type |
-- 2011-12-09 437 1.0.1 rename serport stat->moni port |
-- 2011-10-14 416 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.serportlib.all; |
|
package tst_serlooplib is |
|
constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity) |
constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity) |
constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx) |
constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back) |
|
type hio_cntl_type is record -- humanio controls |
mode : slv2; -- mode (idle,(tx|tx)blast,loop) |
enaxon : slbit; -- enable xon/xoff handling |
enaesc : slbit; -- enable xon/xoff escaping |
enathrottle : slbit; -- enable 1 msec tx throttling |
enaftdi : slbit; -- enable ftdi flush handling |
end record hio_cntl_type; |
|
constant hio_cntl_init : hio_cntl_type := ( |
c_mode_idle, -- mode |
'0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi |
); |
|
type hio_stat_type is record -- humanio status |
rxfecnt : slv16; -- rx frame error counter |
rxoecnt : slv16; -- rx overrun error counter |
rxsecnt : slv16; -- rx sequence error counter |
rxcnt : slv32; -- rx char counter |
txcnt : slv32; -- tx char counter |
rxuicnt : slv8; -- rx unsolicited input counter |
rxuidat : slv8; -- rx unsolicited input data |
rxokcnt : slv16; -- rxok 1->0 transition counter |
txokcnt : slv16; -- txok 1->0 transition counter |
end record hio_stat_type; |
|
constant hio_stat_init : hio_stat_type := ( |
(others=>'0'), -- rxfecnt |
(others=>'0'), -- rxoecnt |
(others=>'0'), -- rxsecnt |
(others=>'0'), -- rxcnt |
(others=>'0'), -- txcnt |
(others=>'0'), -- rxuicnt |
(others=>'0'), -- rxuidat |
(others=>'0'), -- rxokcnt |
(others=>'0') -- txokcnt |
); |
|
-- ------------------------------------- |
|
component tst_serloop is -- tester for serport components |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
CE_MSEC : in slbit; -- msec pulse |
HIO_CNTL : in hio_cntl_type; -- humanio controls |
HIO_STAT : out hio_stat_type; -- humanio status |
SER_MONI : in serport_moni_type; -- serport monitor |
RXDATA : in slv8; -- receiver data out |
RXVAL : in slbit; -- receiver data valid |
RXHOLD : out slbit; -- receiver data hold |
TXDATA : out slv8; -- transmit data in |
TXENA : out slbit; -- transmit data enable |
TXBUSY : in slbit -- transmit busy |
); |
end component; |
|
component tst_serloop_hiomap is -- default human I/O mapper |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
HIO_CNTL : out hio_cntl_type; -- tester controls from hio |
HIO_STAT : in hio_stat_type; -- tester status to display by hio |
SER_MONI : in serport_moni_type; -- serport monitor to display by hio |
SWI : in slv8; -- switch settings |
BTN : in slv4; -- button settings |
LED : out slv8; -- led data |
DSP_DAT : out slv16; -- display data |
DSP_DP : out slv4 -- display decimal points |
); |
end component; |
|
end package tst_serlooplib; |
/tb/tb_tst_serloop.vhd
0,0 → 1,562
-- $Id: tb_tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $ |
-- |
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tb_tst_serloop - sim |
-- Description: Generic test bench for sys_tst_serloop_xx |
-- |
-- Dependencies: vlib/simlib/simclkcnt |
-- vlib/serport/serport_uart_rxtx |
-- vlib/serport/serport_xontx |
-- |
-- To test: sys_tst_serloop_xx |
-- |
-- Target Devices: generic |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-12-23 444 1.1 use new simclkcnt |
-- 2011-11-13 425 1.0 Initial version |
-- 2011-11-06 420 0.5 First draft |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.serportlib.all; |
|
entity tb_tst_serloop is |
port ( |
CLKS : in slbit; -- clock for serport |
CLKH : in slbit; -- clock for humanio |
CLK_STOP : out slbit; -- clock stop |
P0_RXD : out slbit; -- port 0 receive data (board view) |
P0_TXD : in slbit; -- port 0 transmit data (board view) |
P0_RTS_N : in slbit; -- port 0 rts_n |
P0_CTS_N : out slbit; -- port 0 cts_n |
P1_RXD : out slbit; -- port 1 receive data (board view) |
P1_TXD : in slbit; -- port 1 transmit data (board view) |
P1_RTS_N : in slbit; -- port 1 rts_n |
P1_CTS_N : out slbit; -- port 1 cts_n |
SWI : out slv8; -- hio switches |
BTN : out slv4 -- hio buttons |
); |
end tb_tst_serloop; |
|
architecture sim of tb_tst_serloop is |
|
signal CLK_STOP_L : slbit := '0'; |
signal CLK_CYCLE : integer := 0; |
|
signal UART_RESET : slbit := '0'; |
signal UART_RXD : slbit := '1'; |
signal UART_TXD : slbit := '1'; |
signal CTS_N : slbit := '0'; |
signal RTS_N : slbit := '0'; |
|
signal CLKDIV : slv13 := (others=>'0'); |
signal RXDATA : slv8 := (others=>'0'); |
signal RXVAL : slbit := '0'; |
signal RXERR : slbit := '0'; |
signal RXACT : slbit := '0'; |
signal TXDATA : slv8 := (others=>'0'); |
signal TXENA : slbit := '0'; |
signal TXBUSY : slbit := '0'; |
|
signal UART_TXDATA : slv8 := (others=>'0'); |
signal UART_TXENA : slbit := '0'; |
signal UART_TXBUSY : slbit := '0'; |
|
signal ACTPORT : slbit := '0'; |
signal BREAK : slbit := '0'; |
|
signal CTS_CYCLE : integer := 0; |
signal CTS_FRACT : integer := 0; |
signal XON_CYCLE : integer := 0; |
signal XON_FRACT : integer := 0; |
|
signal S2M_ACTIVE : slbit := '0'; |
signal S2M_SIZE : integer := 0; |
signal S2M_ENAESC : slbit := '0'; |
signal S2M_ENAXON : slbit := '0'; |
|
signal M2S_XONSEEN : slbit := '0'; |
signal M2S_XOFFSEEN : slbit := '0'; |
|
signal R_XONRXOK : slbit := '1'; |
signal R_XONTXOK : slbit := '1'; |
|
begin |
|
CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE); |
|
UART : serport_uart_rxtx |
generic map ( |
CDWIDTH => 13) |
port map ( |
CLK => CLKS, |
RESET => UART_RESET, |
CLKDIV => CLKDIV, |
RXSD => UART_RXD, |
RXDATA => RXDATA, |
RXVAL => RXVAL, |
RXERR => RXERR, |
RXACT => RXACT, |
TXSD => UART_TXD, |
TXDATA => UART_TXDATA, |
TXENA => UART_TXENA, |
TXBUSY => UART_TXBUSY |
); |
|
XONTX : serport_xontx |
port map ( |
CLK => CLKS, |
RESET => UART_RESET, |
ENAXON => S2M_ENAXON, |
ENAESC => S2M_ENAESC, |
UART_TXDATA => UART_TXDATA, |
UART_TXENA => UART_TXENA, |
UART_TXBUSY => UART_TXBUSY, |
TXDATA => TXDATA, |
TXENA => TXENA, |
TXBUSY => TXBUSY, |
RXOK => R_XONRXOK, |
TXOK => R_XONTXOK |
); |
|
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N, |
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N) |
variable eff_txd : slbit := '0'; |
begin |
|
if BREAK = '0' then -- if no break active |
eff_txd := UART_TXD; -- send uart |
else -- otherwise |
eff_txd := '0'; -- force '0' |
end if; |
|
if ACTPORT = '0' then -- use port 0 |
P0_RXD <= eff_txd; -- write port 0 inputs |
P0_CTS_N <= CTS_N; |
UART_RXD <= P0_TXD; -- get port 0 outputs |
RTS_N <= P0_RTS_N; |
P1_RXD <= '1'; -- port 1 inputs to idle state |
P1_CTS_N <= '0'; |
else -- use port 1 |
P1_RXD <= eff_txd; -- write port 1 inputs |
P1_CTS_N <= CTS_N; |
UART_RXD <= P1_TXD; -- get port 1 outputs |
RTS_N <= P1_RTS_N; |
P0_RXD <= '1'; -- port 0 inputs to idle state |
P0_CTS_N <= '0'; |
end if; |
end process proc_port_mux; |
|
proc_cts: process(CLKS) |
variable cts_timer : integer := 0; |
begin |
|
if rising_edge(CLKS) then |
if CTS_CYCLE = 0 then -- if cts throttle off |
CTS_N <= '0'; -- cts permanently asserted |
|
else -- otherwise determine throttling |
|
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends |
cts_timer := cts_timer - 1; -- decrement |
else |
cts_timer := CTS_CYCLE-1; -- otherwise reload |
end if; |
|
if cts_timer < cts_fract then -- if in lower 'fract' counts |
CTS_N <= '1'; -- throttle: deassert CTS |
else -- otherwise |
CTS_N <= '0'; -- let go: assert CTS |
end if; |
|
end if; |
end if; |
|
end process proc_cts; |
|
proc_xonrxok: process(CLKS) |
variable xon_timer : integer := 0; |
begin |
if rising_edge(CLKS) then |
if XON_CYCLE = 0 then -- if xon throttle off |
R_XONRXOK <= '1'; -- xonrxok permanently asserted |
|
else -- otherwise determine throttling |
|
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends |
xon_timer := xon_timer - 1; -- decrement |
else |
xon_timer := XON_CYCLE-1; -- otherwise reload |
end if; |
|
if xon_timer < xon_fract then -- if in lower 'fract' counts |
R_XONRXOK <= '0'; -- throttle: deassert xonrxok |
else -- otherwise |
R_XONRXOK <= '1'; -- let go: assert xonrxok |
end if; |
|
end if; |
end if; |
end process proc_xonrxok; |
|
proc_xontxok: process(CLKS) |
begin |
if rising_edge(CLKS) then |
if M2S_XONSEEN = '1' then |
R_XONTXOK <= '1'; |
elsif M2S_XOFFSEEN = '1' then |
R_XONTXOK <= '0'; |
end if; |
end if; |
end process proc_xontxok; |
|
proc_stim: process |
file fstim : text open read_mode is "tb_tst_serloop_stim"; |
variable iline : line; |
variable oline : line; |
variable idelta : integer := 0; |
variable iactport : slbit := '0'; |
variable iswi : slv8 := (others=>'0'); |
variable btn_num : integer := 0; |
variable i_cycle : integer := 0; |
variable i_fract : integer := 0; |
variable nbyte : integer := 0; |
variable enaesc : slbit := '0'; |
variable enaxon : slbit := '0'; |
variable bcnt : integer := 0; |
variable itxdata : slv8 := (others=>'0'); |
variable ok : boolean; |
variable dname : string(1 to 6) := (others=>' '); |
|
procedure waitclk(ncyc : in integer) is |
begin |
for i in 1 to ncyc loop |
wait until rising_edge(CLKS); |
end loop; -- i |
end procedure waitclk; |
|
begin |
|
-- initialize some top level out signals |
SWI <= (others=>'0'); |
BTN <= (others=>'0'); |
|
wait until rising_edge(CLKS); |
|
file_loop: while not endfile(fstim) loop |
|
readline (fstim, iline); |
|
readcomment(iline, ok); |
next file_loop when ok; |
|
readword(iline, dname, ok); |
if ok then |
case dname is |
when "wait " => -- wait |
read_ea(iline, idelta); |
writetimestamp(oline, CLK_CYCLE, ": wait "); |
write(oline, idelta, right, 5); |
writeline(output, oline); |
waitclk(idelta); |
|
when "port " => -- switch rs232 port |
read_ea(iline, iactport); |
ACTPORT <= iactport; |
writetimestamp(oline, CLK_CYCLE, ": port "); |
write(oline, iactport, right, 5); |
writeline(output, oline); |
|
when "cts " => -- setup cts throttling |
read_ea(iline, i_cycle); |
read_ea(iline, i_fract); |
CTS_CYCLE <= i_cycle; |
CTS_FRACT <= i_fract; |
writetimestamp(oline, CLK_CYCLE, ": cts "); |
write(oline, i_cycle, right, 5); |
write(oline, i_fract, right, 5); |
writeline(output, oline); |
|
when "xon " => -- setup xon throttling |
read_ea(iline, i_cycle); |
read_ea(iline, i_fract); |
XON_CYCLE <= i_cycle; |
XON_FRACT <= i_fract; |
writetimestamp(oline, CLK_CYCLE, ": cts "); |
write(oline, i_cycle, right, 5); |
write(oline, i_fract, right, 5); |
writeline(output, oline); |
|
when "swi " => -- new SWI settings |
read_ea(iline, iswi); |
read_ea(iline, idelta); |
writetimestamp(oline, CLK_CYCLE, ": swi "); |
write(oline, iswi, right, 10); |
write(oline, idelta, right, 5); |
writeline(output, oline); |
wait until rising_edge(CLKH); |
SWI <= iswi; |
wait until rising_edge(CLKS); |
waitclk(idelta); |
|
when "btn " => -- BTN push (3 cyc down + 3 cyc wait) |
read_ea(iline, btn_num); |
read_ea(iline, idelta); |
if btn_num>=0 and btn_num<=3 then |
writetimestamp(oline, CLK_CYCLE, ": btn "); |
write(oline, btn_num, right, 5); |
write(oline, idelta, right, 5); |
writeline(output, oline); |
wait until rising_edge(CLKH); |
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse |
wait until rising_edge(CLKH); |
wait until rising_edge(CLKH); |
wait until rising_edge(CLKH); |
BTN(btn_num) <= '0'; |
wait until rising_edge(CLKH); |
wait until rising_edge(CLKH); |
wait until rising_edge(CLKH); |
wait until rising_edge(CLKS); |
waitclk(idelta); |
else |
write(oline, string'("!! btn: btn number out of range")); |
writeline(output, oline); |
end if; |
|
when "expect" => -- expect n bytes data |
read_ea(iline, nbyte); |
read_ea(iline, enaesc); |
read_ea(iline, enaxon); |
writetimestamp(oline, CLK_CYCLE, ": expect"); |
write(oline, nbyte, right, 5); |
write(oline, enaesc, right, 3); |
write(oline, enaxon, right, 3); |
writeline(output, oline); |
|
if nbyte > 0 then |
S2M_ACTIVE <= '1'; |
S2M_SIZE <= nbyte; |
else |
S2M_ACTIVE <= '0'; |
end if; |
S2M_ENAESC <= enaesc; |
S2M_ENAXON <= enaxon; |
wait until rising_edge(CLKS); |
|
when "send " => -- send n bytes data |
read_ea(iline, nbyte); |
read_ea(iline, enaesc); |
read_ea(iline, enaxon); |
writetimestamp(oline, CLK_CYCLE, ": send "); |
write(oline, nbyte, right, 5); |
write(oline, enaesc, right, 3); |
write(oline, enaxon, right, 3); |
writeline(output, oline); |
bcnt := 0; |
itxdata := (others=>'0'); |
|
wait until falling_edge(CLKS); |
while bcnt < nbyte loop |
while TXBUSY='1' or RTS_N='1' loop |
wait until falling_edge(CLKS); |
end loop; |
|
TXDATA <= itxdata; |
itxdata := slv(unsigned(itxdata) + 1); |
bcnt := bcnt + 1; |
|
TXENA <= '1'; |
wait until falling_edge(CLKS); |
TXENA <= '0'; |
wait until falling_edge(CLKS); |
end loop; |
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send... |
wait until falling_edge(CLKS); |
end loop; |
wait until rising_edge(CLKS); |
|
when "break " => -- send a break for n cycles |
read_ea(iline, idelta); |
writetimestamp(oline, CLK_CYCLE, ": break "); |
write(oline, idelta, right, 5); |
writeline(output, oline); |
-- send break for n cycles |
BREAK <= '1'; |
waitclk(idelta); |
BREAK <= '0'; |
-- wait for 3 bit cell width |
waitclk(3*to_integer(unsigned(CLKDIV)+1)); |
-- send 'sync' character |
wait until falling_edge(CLKS); |
TXDATA <= "10000000"; |
TXENA <= '1'; |
wait until falling_edge(CLKS); |
TXENA <= '0'; |
wait until rising_edge(CLKS); |
|
when "clkdiv" => -- set new clock divider |
read_ea(iline, idelta); |
writetimestamp(oline, CLK_CYCLE, ": clkdiv"); |
write(oline, idelta, right, 5); |
writeline(output, oline); |
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length)); |
UART_RESET <= '1'; |
wait until rising_edge(CLKS); |
UART_RESET <= '0'; |
|
when others => -- unknown command |
write(oline, string'("?? unknown command: ")); |
write(oline, dname); |
writeline(output, oline); |
report "aborting" severity failure; |
end case; |
|
else |
report "failed to find command" severity failure; |
|
end if; |
|
testempty_ea(iline); |
end loop; -- file_loop |
|
writetimestamp(oline, CLK_CYCLE, ": DONE "); |
writeline(output, oline); |
|
-- extra wait for at least two character times (20 bit times) |
-- to allow tx and rx of the last character |
waitclk(20*(to_integer(unsigned(CLKDIV))+1)); |
|
CLK_STOP_L <= '1'; |
|
wait for 500 ns; -- allows dcm's to stop |
|
wait; -- suspend proc_stim forever |
-- clock is stopped, sim will end |
|
end process proc_stim; |
|
CLK_STOP <= CLK_STOP_L; |
|
proc_moni: process |
variable oline : line; |
variable dclk : integer := 0; |
variable active_1 : slbit := '0'; |
variable irxdata : slv8 := (others=>'0'); |
variable irxeff : slv8 := (others=>'0'); |
variable irxval : slbit := '0'; |
variable doesc : slbit := '0'; |
variable bcnt : integer := 0; |
variable xseen : slbit := '0'; |
begin |
|
loop |
wait until falling_edge(CLKS); |
|
M2S_XONSEEN <= '0'; |
M2S_XOFFSEEN <= '0'; |
|
if S2M_ACTIVE='1' and active_1='0' then -- start expect message |
irxdata := (others=>'0'); |
bcnt := 0; |
end if; |
|
if S2M_ACTIVE='0' and active_1='1' then -- end expect message |
if bcnt = S2M_SIZE then |
writetimestamp(oline, CLK_CYCLE, ": OK: message seen"); |
else |
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen="); |
write(oline, bcnt, right, 5); |
write(oline, string'(" expect=")); |
write(oline, S2M_SIZE, right, 5); |
end if; |
writeline(output, oline); |
end if; |
|
active_1 := S2M_ACTIVE; |
|
if RXVAL = '1' then |
writetimestamp(oline, CLK_CYCLE, ": char: "); |
write(oline, RXDATA, right, 10); |
write(oline, string'(" (")); |
writeoct(oline, RXDATA, right, 3); |
write(oline, string'(") dt=")); |
write(oline, dclk, right, 4); |
|
irxeff := RXDATA; |
irxval := '1'; |
if doesc = '1' then |
irxeff := not RXDATA; |
irxval := '1'; |
doesc := '0'; |
write(oline, string'(" eff=")); |
write(oline, irxeff, right, 10); |
write(oline, string'(" (")); |
writeoct(oline, irxeff, right, 3); |
write(oline, string'(")")); |
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then |
doesc := '1'; |
irxval := '0'; |
write(oline, string'(" XESC seen")); |
end if; |
|
xseen := '0'; |
if S2M_ENAXON = '1' then |
if RXDATA = c_serport_xon then |
write(oline, string'(" XON seen")); |
M2S_XONSEEN <= '1'; |
xseen := '1'; |
elsif RXDATA = c_serport_xoff then |
write(oline, string'(" XOFF seen")); |
M2S_XOFFSEEN <= '1'; |
xseen := '1'; |
end if; |
end if; |
|
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then |
if irxeff = irxdata then |
write(oline, string'(" OK")); |
else |
write(oline, string'(" FAIL: expect=")); |
write(oline, irxdata, right, 10); |
end if; |
irxdata := slv(unsigned(irxdata) + 1); |
bcnt := bcnt + 1; |
end if; |
|
writeline(output, oline); |
dclk := 0; |
|
end if; |
|
if RXERR = '1' then |
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'"); |
writeline(output, oline); |
end if; |
|
dclk := dclk + 1; |
|
end loop; |
|
end process proc_moni; |
|
end sim; |
/tb/tb_tst_serloop.vbom
0,0 → 1,10
# libs |
../../../vlib/slvtypes.vhd |
../../../vlib/simlib/simlib.vhd |
../../../vlib/serport/serportlib.vbom |
# components |
../../../vlib/simlib/simclkcnt.vbom |
../../../vlib/serport/serport_uart_rxtx.vbom |
../../../vlib/serport/serport_xontx.vbom |
# design |
tb_tst_serloop.vhd |
/tb/tb_tst_serloop_stim.dat
0,0 → 1,124
# $Id: tb_tst_serloop_stim.dat 441 2011-12-20 17:01:16Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-11-06 420 1.0 Initial version |
# |
C ------------------------------------------------ |
C try SWI settings |
# only the 4 LBS (disp and enable control) |
# don't touch the 2 mode settings here !! |
# |
wait 10 |
# |
swi 10000000 2 |
swi 01000000 2 |
swi 00100000 2 |
swi 00010000 2 |
swi 00000000 2 |
wait 2 |
# |
C ------------------------------------------------ |
C loop-back message with 16 bytes on port 0 |
# |
port 0 |
swi 00000000 2 |
btn 0 10 |
# |
# mode=11(loop); |
swi 00000110 2 |
btn 1 10 |
# |
expect 16 0 0 |
send 16 0 0 |
wait 100 |
expect 0 0 0 |
C ------------------------------------------------ |
C loop-back message with 16 bytes on port 1 |
# |
port 1 |
swi 00000001 2 |
btn 0 10 |
# |
# mode=11(loop);port=1 |
swi 00000111 2 |
btn 1 10 |
# |
expect 16 0 0 |
send 16 0 0 |
wait 100 |
expect 0 0 0 |
# |
C ------------------------------------------------ |
C loop-back message with 32 bytes escaped on port 0 |
# |
port 0 |
swi 00000000 2 |
btn 0 10 |
# |
# enaesc=1; mode=11(loop) |
swi 00100110 2 |
btn 1 10 |
# |
expect 32 1 0 |
send 32 1 0 |
wait 100 |
expect 0 0 0 |
# |
C ------------------------------------------------ |
C loop-back message with 256 bytes escaped on port 1; cts throttle |
# |
port 1 |
swi 00000001 2 |
btn 0 10 |
# |
# enaesc=1; mode=11(loop); port=1 |
swi 00100111 2 |
btn 1 10 |
# |
cts 200 100 |
expect 256 1 0 |
send 256 1 0 |
wait 1500 |
expect 0 0 0 |
cts 0 0 |
# |
C ------------------------------------------------ |
C loop-back message with 256 bytes escaped on port 0; xon throttle |
# |
port 0 |
swi 00000000 2 |
btn 0 10 |
# |
# enaesc=1;enaxon=1; mode=11(loop); port=0 |
swi 00110110 2 |
btn 1 10 |
# |
xon 200 100 |
expect 256 1 1 |
send 256 1 1 |
wait 1500 |
expect 0 0 0 |
xon 0 0 |
C ------------------------------------------------ |
C loop-back message with 256 bytes escaped on port 1; xon throttle |
# |
port 1 |
swi 00000001 2 |
btn 0 10 |
# |
# enaesc=1;enaxon=1; mode=11(loop); port=1 |
swi 00110111 2 |
btn 1 10 |
# |
xon 200 100 |
expect 256 1 1 |
send 256 1 1 |
wait 1500 |
expect 0 0 0 |
xon 0 0 |
# |
C ------------------------------------------------ |
C cool down |
wait 200 |
|
tb
Property changes :
Added: svn:ignore
## -0,0 +1,32 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: tst_serlooplib.vbom
===================================================================
--- tst_serlooplib.vbom (nonexistent)
+++ tst_serlooplib.vbom (revision 24)
@@ -0,0 +1,3 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/serport/serportlib.vbom
Index: nexys2/tb/Makefile
===================================================================
--- nexys2/tb/Makefile (nonexistent)
+++ nexys2/tb/Makefile (revision 24)
@@ -0,0 +1,34 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-13 424 1.0 Initial version
+#
+EXE_all = tb_tst_serloop1_n2
+EXE_all += tb_tst_serloop2_n2
+#
+include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk
+#
+.PHONY : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean isim_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+include $(RETROBASE)/rtl/make/generic_isim.mk
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(VBOM_all:.vbom=.dep_isim)
+include $(wildcard *.o.dep_ghdl)
+endif
+#
Index: nexys2/tb/tb_tst_serloop1_n2.vhd
===================================================================
--- nexys2/tb/tb_tst_serloop1_n2.vhd (nonexistent)
+++ nexys2/tb/tb_tst_serloop1_n2.vhd (revision 24)
@@ -0,0 +1,139 @@
+-- $Id: tb_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_tst_serloop1_n2 - sim
+-- Description: Test bench for sys_tst_serloop1_n2
+--
+-- Dependencies: simlib/simclk
+-- sys_tst_serloop2_n2 [UUT]
+-- tb/tb_tst_serloop
+--
+-- To test: sys_tst_serloop1_n2
+--
+-- Target Devices: generic
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
+-- 2011-12-16 439 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.simlib.all;
+
+entity tb_tst_serloop1_n2 is
+end tb_tst_serloop1_n2;
+
+architecture sim of tb_tst_serloop1_n2 is
+
+ signal CLK50 : slbit := '0';
+ signal CLK_STOP : slbit := '0';
+
+ signal I_RXD : slbit := '1';
+ signal O_TXD : slbit := '1';
+ signal I_SWI : slv8 := (others=>'0');
+ signal I_BTN : slv4 := (others=>'0');
+
+ signal O_FUSP_RTS_N : slbit := '0';
+ signal I_FUSP_CTS_N : slbit := '0';
+ signal I_FUSP_RXD : slbit := '1';
+ signal O_FUSP_TXD : slbit := '1';
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '1';
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+
+ signal FUSP_RTS_N : slbit := '0';
+ signal FUSP_CTS_N : slbit := '0';
+ signal FUSP_RXD : slbit := '1';
+ signal FUSP_TXD : slbit := '1';
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant delay_time : time := 2 ns;
+
+begin
+
+ SYSCLK : simclk
+ generic map (
+ PERIOD => clock_period,
+ OFFSET => clock_offset)
+ port map (
+ CLK => CLK50,
+ CLK_STOP => CLK_STOP
+ );
+
+ UUT : entity work.sys_tst_serloop1_n2
+ port map (
+ I_CLK50 => CLK50,
+ I_RXD => I_RXD,
+ O_TXD => O_TXD,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => open,
+ O_ANO_N => open,
+ O_SEG_N => open,
+ O_MEM_CE_N => open,
+ O_MEM_BE_N => open,
+ O_MEM_WE_N => open,
+ O_MEM_OE_N => open,
+ O_MEM_ADV_N => open,
+ O_MEM_CLK => open,
+ O_MEM_CRE => open,
+ I_MEM_WAIT => '0',
+ O_MEM_ADDR => open,
+ IO_MEM_DATA => open,
+ O_FLA_CE_N => open,
+ O_FUSP_RTS_N => O_FUSP_RTS_N,
+ I_FUSP_CTS_N => I_FUSP_CTS_N,
+ I_FUSP_RXD => I_FUSP_RXD,
+ O_FUSP_TXD => O_FUSP_TXD
+ );
+
+ GENTB : entity work.tb_tst_serloop
+ port map (
+ CLKS => CLK50,
+ CLKH => CLK50,
+ CLK_STOP => CLK_STOP,
+ P0_RXD => RXD,
+ P0_TXD => TXD,
+ P0_RTS_N => '0',
+ P0_CTS_N => open,
+ P1_RXD => FUSP_RXD,
+ P1_TXD => FUSP_TXD,
+ P1_RTS_N => FUSP_RTS_N,
+ P1_CTS_N => FUSP_CTS_N,
+ SWI => SWI,
+ BTN => BTN
+ );
+
+ I_RXD <= RXD after delay_time;
+ TXD <= O_TXD after delay_time;
+ FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
+ I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
+ I_FUSP_RXD <= FUSP_RXD after delay_time;
+ FUSP_TXD <= O_FUSP_TXD after delay_time;
+
+ I_SWI <= SWI after delay_time;
+ I_BTN <= BTN after delay_time;
+
+end sim;
Index: nexys2/tb/tb_tst_serloop2_n2.vhd
===================================================================
--- nexys2/tb/tb_tst_serloop2_n2.vhd (nonexistent)
+++ nexys2/tb/tb_tst_serloop2_n2.vhd (revision 24)
@@ -0,0 +1,167 @@
+-- $Id: tb_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_tst_serloop2_n2 - sim
+-- Description: Test bench for sys_tst_serloop2_n2
+--
+-- Dependencies: simlib/simclk
+-- vlib/xlib/dcm_sfs
+-- sys_tst_serloop2_n2 [UUT]
+-- tb/tb_tst_serloop
+--
+-- To test: sys_tst_serloop2_n2
+--
+-- Target Devices: generic
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
+-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
+-- 2011-11-17 426 1.0.1 use dcm_sfs now
+-- 2011-11-13 424 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.simlib.all;
+
+entity tb_tst_serloop2_n2 is
+end tb_tst_serloop2_n2;
+
+architecture sim of tb_tst_serloop2_n2 is
+
+ signal CLK50 : slbit := '0';
+ signal CLK_STOP : slbit := '0';
+
+ signal CLKS : slbit := '0';
+ signal CLKH : slbit := '0';
+
+ signal I_RXD : slbit := '1';
+ signal O_TXD : slbit := '1';
+ signal I_SWI : slv8 := (others=>'0');
+ signal I_BTN : slv4 := (others=>'0');
+
+ signal O_FUSP_RTS_N : slbit := '0';
+ signal I_FUSP_CTS_N : slbit := '0';
+ signal I_FUSP_RXD : slbit := '1';
+ signal O_FUSP_TXD : slbit := '1';
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '1';
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+
+ signal FUSP_RTS_N : slbit := '0';
+ signal FUSP_CTS_N : slbit := '0';
+ signal FUSP_RXD : slbit := '1';
+ signal FUSP_TXD : slbit := '1';
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant delay_time : time := 2 ns;
+
+begin
+
+ SYSCLK : simclk
+ generic map (
+ PERIOD => clock_period,
+ OFFSET => clock_offset)
+ port map (
+ CLK => CLK50,
+ CLK_STOP => CLK_STOP
+ );
+
+ DCM_S : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => 5,
+ CLKFX_MULTIPLY => 6,
+ CLKIN_PERIOD => 20.0)
+ port map (
+ CLKIN => CLK50,
+ CLKFX => CLKS,
+ LOCKED => open
+ );
+
+ DCM_H : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => 2,
+ CLKFX_MULTIPLY => 4,
+ CLKIN_PERIOD => 20.0)
+ port map (
+ CLKIN => CLK50,
+ CLKFX => CLKH,
+ LOCKED => open
+ );
+
+ UUT : entity work.sys_tst_serloop2_n2
+ port map (
+ I_CLK50 => CLK50,
+ I_RXD => I_RXD,
+ O_TXD => O_TXD,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => open,
+ O_ANO_N => open,
+ O_SEG_N => open,
+ O_MEM_CE_N => open,
+ O_MEM_BE_N => open,
+ O_MEM_WE_N => open,
+ O_MEM_OE_N => open,
+ O_MEM_ADV_N => open,
+ O_MEM_CLK => open,
+ O_MEM_CRE => open,
+ I_MEM_WAIT => '0',
+ O_MEM_ADDR => open,
+ IO_MEM_DATA => open,
+ O_FLA_CE_N => open,
+ O_FUSP_RTS_N => O_FUSP_RTS_N,
+ I_FUSP_CTS_N => I_FUSP_CTS_N,
+ I_FUSP_RXD => I_FUSP_RXD,
+ O_FUSP_TXD => O_FUSP_TXD
+ );
+
+ GENTB : entity work.tb_tst_serloop
+ port map (
+ CLKS => CLKS,
+ CLKH => CLKH,
+ CLK_STOP => CLK_STOP,
+ P0_RXD => RXD,
+ P0_TXD => TXD,
+ P0_RTS_N => '0',
+ P0_CTS_N => open,
+ P1_RXD => FUSP_RXD,
+ P1_TXD => FUSP_TXD,
+ P1_RTS_N => FUSP_RTS_N,
+ P1_CTS_N => FUSP_CTS_N,
+ SWI => SWI,
+ BTN => BTN
+ );
+
+ I_RXD <= RXD after delay_time;
+ TXD <= O_TXD after delay_time;
+ FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
+ I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
+ I_FUSP_RXD <= FUSP_RXD after delay_time;
+ FUSP_TXD <= O_FUSP_TXD after delay_time;
+
+ I_SWI <= SWI after delay_time;
+ I_BTN <= BTN after delay_time;
+
+end sim;
Index: nexys2/tb/tbw.dat
===================================================================
--- nexys2/tb/tbw.dat (nonexistent)
+++ nexys2/tb/tbw.dat (revision 24)
@@ -0,0 +1,6 @@
+# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $
+#
+[tb_tst_serloop1_n2]
+tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat
+[tb_tst_serloop2_n2]
+tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat
Index: nexys2/tb/tb_tst_serloop1_n2.vbom
===================================================================
--- nexys2/tb/tb_tst_serloop1_n2.vbom (nonexistent)
+++ nexys2/tb/tb_tst_serloop1_n2.vbom (revision 24)
@@ -0,0 +1,11 @@
+# conf
+sys_conf = sys_conf1_sim.vhd
+# libs
+../../../../vlib/slvtypes.vhd
+../../../../vlib/simlib/simlib.vhd
+# components
+../../../../vlib/simlib/simclk.vbom
+../sys_tst_serloop1_n2.vbom
+../../tb/tb_tst_serloop.vbom
+# design
+tb_tst_serloop1_n2.vhd
Index: nexys2/tb/tb_tst_serloop2_n2.vbom
===================================================================
--- nexys2/tb/tb_tst_serloop2_n2.vbom (nonexistent)
+++ nexys2/tb/tb_tst_serloop2_n2.vbom (revision 24)
@@ -0,0 +1,13 @@
+# conf
+sys_conf = sys_conf2_sim.vhd
+# libs
+../../../../vlib/slvtypes.vhd
+../../../../vlib/xlib/xlib.vhd
+../../../../vlib/simlib/simlib.vhd
+# components
+../../../../vlib/simlib/simclk.vbom
+../../../../vlib/xlib/dcm_sfs_gsim.vbom
+../sys_tst_serloop2_n2.vbom
+../../tb/tb_tst_serloop.vbom
+# design
+tb_tst_serloop2_n2.vhd
Index: nexys2/tb/sys_tst_serloop1_n2.ucf_cpp
===================================================================
--- nexys2/tb/sys_tst_serloop1_n2.ucf_cpp (nonexistent)
+++ nexys2/tb/sys_tst_serloop1_n2.ucf_cpp (revision 24)
@@ -0,0 +1 @@
+link ../sys_tst_serloop1_n2.ucf_cpp
\ No newline at end of file
nexys2/tb/sys_tst_serloop1_n2.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nexys2/tb/sys_tst_serloop2_n2.ucf_cpp
===================================================================
--- nexys2/tb/sys_tst_serloop2_n2.ucf_cpp (nonexistent)
+++ nexys2/tb/sys_tst_serloop2_n2.ucf_cpp (revision 24)
@@ -0,0 +1 @@
+link ../sys_tst_serloop2_n2.ucf_cpp
\ No newline at end of file
nexys2/tb/sys_tst_serloop2_n2.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nexys2/tb/sys_conf1_sim.vhd
===================================================================
--- nexys2/tb/sys_conf1_sim.vhd (nonexistent)
+++ nexys2/tb/sys_conf1_sim.vhd (revision 24)
@@ -0,0 +1,43 @@
+-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop1_n2 (for test bench)
+--
+-- Dependencies: -
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-16 439 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ -- in simulation a usec is shortened to 10 cycles (0.2 usec) and a msec
+ -- to 50 cycles (1 usec). This affects the pulse generators (usec) and
+ -- mainly the autobauder. A break will be detected after 128 msec periods,
+ -- this in simulation after 128 usec or 6400 cycles. This is compatible with
+ -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
+
+ constant sys_conf_clkdiv_usecdiv : integer := 10; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+ constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+end package sys_conf;
Index: nexys2/tb/sys_conf2_sim.vhd
===================================================================
--- nexys2/tb/sys_conf2_sim.vhd (nonexistent)
+++ nexys2/tb/sys_conf2_sim.vhd (revision 24)
@@ -0,0 +1,44 @@
+-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop2_n2 (for test bench)
+--
+-- Dependencies: -
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-13 424 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ -- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
+ -- to 60 cycles (1 usec). This affects the pulse generators (usec) and
+ -- mainly the autobauder. A break will be detected after 128 msec periods,
+ -- this in simulation after 128 usec or 6400 cycles. This is compatible with
+ -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
+
+ constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec
+ constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+ constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+end package sys_conf;
Index: nexys2/tb/.cvsignore
===================================================================
--- nexys2/tb/.cvsignore (nonexistent)
+++ nexys2/tb/.cvsignore (revision 24)
@@ -0,0 +1,10 @@
+tb_tst_serloop1_n2
+tb_tst_serloop1_n2_[sft]sim
+tb_tst_serloop1_n2_ISim
+tb_tst_serloop1_n2_ISim_[sft]sim
+tb_tst_serloop2_n2
+tb_tst_serloop2_n2_[sft]sim
+tb_tst_serloop2_n2_ISim
+tb_tst_serloop2_n2_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: nexys2/tb
===================================================================
--- nexys2/tb (nonexistent)
+++ nexys2/tb (revision 24)
nexys2/tb
Property changes :
Added: svn:ignore
## -0,0 +1,42 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_tst_serloop1_n2
+tb_tst_serloop1_n2_[sft]sim
+tb_tst_serloop1_n2_ISim
+tb_tst_serloop1_n2_ISim_[sft]sim
+tb_tst_serloop2_n2
+tb_tst_serloop2_n2_[sft]sim
+tb_tst_serloop2_n2_ISim
+tb_tst_serloop2_n2_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: nexys2/sys_tst_serloop1_n2.vhd
===================================================================
--- nexys2/sys_tst_serloop1_n2.vhd (nonexistent)
+++ nexys2/sys_tst_serloop1_n2.vhd (revision 24)
@@ -0,0 +1,241 @@
+-- $Id: sys_tst_serloop1_n2.vhd 476 2013-01-26 22:23:53Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_tst_serloop1_n2 - syn
+-- Description: Tester serial link for nexys2
+--
+-- Dependencies: genlib/clkdivce
+-- bpgen/bp_rs232_2l4l_iob
+-- bpgen/sn_humanio
+-- tst_serloop_hiomap
+-- vlib/serport/serport_1clock
+-- tst_serloop
+-- vlib/nxcramlib/nx_cram_dummy
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2011-12-16 439 13.1 O40d xc3s1200e-4 433 634 64 490 t 13.1
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-23 444 1.1 remove clksys output hack
+-- 2011-12-16 439 1.0 Initial version
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.tst_serlooplib.all;
+use work.serportlib.all;
+use work.nxcramlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_serloop1_n2 is -- top level
+ -- implements nexys2_fusp_aif
+ port (
+ I_CLK50 : in slbit; -- 50 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n2 switches
+ I_BTN : in slv4; -- n2 buttons
+ O_LED : out slv8; -- n2 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_tst_serloop1_n2;
+
+architecture syn of sys_tst_serloop1_n2 is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal RXD : slbit := '0';
+ signal TXD : slbit := '0';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
+ signal HIO_STAT : hio_stat_type := hio_stat_init;
+
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXHOLD : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal SER_MONI : serport_moni_type := serport_moni_init;
+
+begin
+
+ CLK <= I_CLK50;
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 7,
+ USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
+ MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
+ port map (
+ CLK => CLK,
+ CE_USEC => open,
+ CE_MSEC => CE_MSEC
+ );
+
+ HIO : sn_humanio
+ generic map (
+ DEBOUNCE => sys_conf_hio_debounce)
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ CE_MSEC => CE_MSEC,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RESET <= BTN(0); -- BTN(0) will reset tester !!
+
+ HIOMAP : tst_serloop_hiomap
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP
+ );
+
+ IOB_RS232 : bp_rs232_2l4l_iob
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ SEL => SWI(0), -- port selection
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ SERPORT : serport_1clock
+ generic map (
+ CDWIDTH => 15,
+ CDINIT => sys_conf_uart_cdinit,
+ RXFAWIDTH => 5,
+ TXFAWIDTH => 5)
+ port map (
+ CLK => CLK,
+ CE_MSEC => CE_MSEC,
+ RESET => RESET,
+ ENAXON => HIO_CNTL.enaxon,
+ ENAESC => HIO_CNTL.enaesc,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY,
+ MONI => SER_MONI,
+ RXSD => RXD,
+ TXSD => TXD,
+ RXRTS_N => RTS_N,
+ TXCTS_N => CTS_N
+ );
+
+ TESTER : tst_serloop
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_FLA_CE_N <= '1'; -- keep Flash memory disabled
+
+end syn;
Index: nexys2/sys_tst_serloop2_n2.vhd
===================================================================
--- nexys2/sys_tst_serloop2_n2.vhd (nonexistent)
+++ nexys2/sys_tst_serloop2_n2.vhd (revision 24)
@@ -0,0 +1,284 @@
+-- $Id: sys_tst_serloop2_n2.vhd 476 2013-01-26 22:23:53Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_tst_serloop2_n2 - syn
+-- Description: Tester serial link for nexys2
+--
+-- Dependencies: vlib/xlib/dcm_sfs
+-- genlib/clkdivce
+-- bpgen/bp_rs232_2l4l_iob
+-- bpgen/sn_humanio
+-- tst_serloop_hiomap
+-- vlib/serport/serport_2clock
+-- tst_serloop
+-- vlib/nxcramlib/nx_cram_dummy
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2011-12-16 439 13.1 O40d xc3s1200e-4 516 696 64 575 t xx.x
+-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x
+-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-23 444 1.1 remove clksys output hack
+-- 2011-12-09 437 1.0.4 rename serport stat->moni port
+-- 2011-11-26 433 1.0.3 use nx_cram_dummy now
+-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage
+-- 2011-11-17 426 1.0.1 use dcm_sfs now
+-- 2011-11-12 423 1.0 Initial version
+-- 2011-11-09 422 0.5 First draft
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.tst_serlooplib.all;
+use work.serportlib.all;
+use work.nxcramlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_serloop2_n2 is -- top level
+ -- implements nexys2_fusp_aif
+ port (
+ I_CLK50 : in slbit; -- 50 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n2 switches
+ I_BTN : in slv4; -- n2 buttons
+ O_LED : out slv8; -- n2 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_tst_serloop2_n2;
+
+architecture syn of sys_tst_serloop2_n2 is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal CLKS : slbit := '0';
+ signal CES_MSEC : slbit := '0';
+
+ signal RXD : slbit := '0';
+ signal TXD : slbit := '0';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
+ signal HIO_STAT : hio_stat_type := hio_stat_init;
+
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXHOLD : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal SER_MONI : serport_moni_type := serport_moni_init;
+
+begin
+
+ DCM_U : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => 2,
+ CLKFX_MULTIPLY => 4,
+ CLKIN_PERIOD => 20.0)
+ port map (
+ CLKIN => I_CLK50,
+ CLKFX => CLK,
+ LOCKED => open
+ );
+
+ CLKDIV_U : clkdivce
+ generic map (
+ CDUWIDTH => 7,
+ USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20
+ MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
+ port map (
+ CLK => CLK,
+ CE_USEC => open,
+ CE_MSEC => CE_MSEC
+ );
+
+ DCM_S : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => 5,
+ CLKFX_MULTIPLY => 6,
+ CLKIN_PERIOD => 20.0)
+ port map (
+ CLKIN => I_CLK50,
+ CLKFX => CLKS,
+ LOCKED => open
+ );
+
+ CLKDIV_S : clkdivce
+ generic map (
+ CDUWIDTH => 6,
+ USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
+ MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
+ port map (
+ CLK => CLKS,
+ CE_USEC => open,
+ CE_MSEC => CES_MSEC
+ );
+
+ HIO : sn_humanio
+ generic map (
+ DEBOUNCE => sys_conf_hio_debounce)
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ CE_MSEC => CE_MSEC,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RESET <= BTN(0); -- BTN(0) will reset tester !!
+
+ HIOMAP : tst_serloop_hiomap
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP
+ );
+
+ IOB_RS232 : bp_rs232_2l4l_iob
+ port map (
+ CLK => CLKS,
+ RESET => '0',
+ SEL => SWI(0), -- port selection
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ SERPORT : serport_2clock
+ generic map (
+ CDWIDTH => 15,
+ CDINIT => sys_conf_uart_cdinit,
+ RXFAWIDTH => 5,
+ TXFAWIDTH => 5)
+ port map (
+ CLKU => CLK,
+ RESET => RESET,
+ CLKS => CLKS,
+ CES_MSEC => CES_MSEC,
+ ENAXON => HIO_CNTL.enaxon,
+ ENAESC => HIO_CNTL.enaesc,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY,
+ MONI => SER_MONI,
+ RXSD => RXD,
+ TXSD => TXD,
+ RXRTS_N => RTS_N,
+ TXCTS_N => CTS_N
+ );
+
+ TESTER : tst_serloop
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_FLA_CE_N <= '1'; -- keep Flash memory disabled
+
+end syn;
Index: nexys2/Makefile
===================================================================
--- nexys2/Makefile (nonexistent)
+++ nexys2/Makefile (revision 24)
@@ -0,0 +1,28 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-09 422 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+endif
+#
Index: nexys2/sys_tst_serloop1_n2.vbom
===================================================================
--- nexys2/sys_tst_serloop1_n2.vbom (nonexistent)
+++ nexys2/sys_tst_serloop1_n2.vbom (revision 24)
@@ -0,0 +1,19 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../tst_serlooplib.vbom
+../../../vlib/serport/serportlib.vbom
+../../../bplib/nxcramlib/nxcramlib.vhd
+${sys_conf := sys_conf1.vhd}
+# components
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio.vbom
+../tst_serloop_hiomap.vbom
+../../../vlib/serport/serport_1clock.vbom
+../tst_serloop.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+# design
+sys_tst_serloop1_n2.vhd
+@ucf_cpp: sys_tst_serloop1_n2.ucf
Index: nexys2/sys_tst_serloop2_n2.vbom
===================================================================
--- nexys2/sys_tst_serloop2_n2.vbom (nonexistent)
+++ nexys2/sys_tst_serloop2_n2.vbom (revision 24)
@@ -0,0 +1,22 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../tst_serlooplib.vbom
+../../../vlib/serport/serportlib.vbom
+../../../bplib/nxcramlib/nxcramlib.vhd
+${sys_conf := sys_conf2.vhd}
+# components
+[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
+[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio.vbom
+../tst_serloop_hiomap.vbom
+../../../vlib/serport/serport_2clock.vbom
+../tst_serloop.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+# design
+sys_tst_serloop2_n2.vhd
+@ucf_cpp: sys_tst_serloop2_n2.ucf
Index: nexys2/sys_conf1.vhd
===================================================================
--- nexys2/sys_conf1.vhd (nonexistent)
+++ nexys2/sys_conf1.vhd (revision 24)
@@ -0,0 +1,37 @@
+-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop1_n2 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-16 439 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkdiv_usecdiv : integer := 50; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+ constant sys_conf_uart_cdinit : integer := 434-1; -- 50000000/115200
+
+end package sys_conf;
Index: nexys2/sys_conf2.vhd
===================================================================
--- nexys2/sys_conf2.vhd (nonexistent)
+++ nexys2/sys_conf2.vhd (revision 24)
@@ -0,0 +1,39 @@
+-- $Id: sys_conf2.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-13 424 1.0 Initial version
+-- 2011-10-25 419 0.5 First draft
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec
+ constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+ constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
+
+end package sys_conf;
Index: nexys2/sys_tst_serloop1_n2.ucf_cpp
===================================================================
--- nexys2/sys_tst_serloop1_n2.ucf_cpp (nonexistent)
+++ nexys2/sys_tst_serloop1_n2.ucf_cpp (revision 24)
@@ -0,0 +1,19 @@
+## $Id: sys_tst_serloop1_n2.ucf_cpp 441 2011-12-20 17:01:16Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-12-16 439 1.0 Initial version
+##
+
+NET "I_CLK50" TNM_NET = "I_CLK50";
+TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK50";
+OFFSET = OUT 20 ns AFTER "I_CLK50";
+
+## std board
+##
+#include "bplib/nexys2/nexys2_pins.ucf"
+##
+## Pmod B0 - RS232
+##
+#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
Index: nexys2/sys_tst_serloop2_n2.ucf_cpp
===================================================================
--- nexys2/sys_tst_serloop2_n2.ucf_cpp (nonexistent)
+++ nexys2/sys_tst_serloop2_n2.ucf_cpp (revision 24)
@@ -0,0 +1,32 @@
+## $Id: sys_tst_serloop2_n2.ucf_cpp 441 2011-12-20 17:01:16Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-12-16 439 1.0.1 set maxdelay clk-clks to 12 ns
+## 2011-09-17 410 1.0 Initial version
+##
+
+NET "I_CLK50" TNM_NET = "I_CLK50";
+TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK50";
+OFFSET = OUT 20 ns AFTER "I_CLK50";
+
+## rules to prevent default 'cross clock' constraints for the dcm generated
+## clocks CLK(100 MHz) and CLKS(60 MHz). All essential domain crossing done
+## via fifo's or dedicated capture/synch flops.
+
+NET "CLK" TNM_NET = "CLK";
+NET "CLKS" TNM_NET = "CLKS";
+TIMESPEC "TS_CDC_CLK_CLKS" = FROM "CLK" TO "CLKS" 12 ns;
+TIMESPEC "TS_CDC_CLKS_CLK" = FROM "CLKS" TO "CLK" 12 ns;
+
+## rule to allow that two DCMs are driven by one clock pin.
+NET "I_CLK50" CLOCK_DEDICATED_ROUTE = FALSE;
+
+## std board
+##
+#include "bplib/nexys2/nexys2_pins.ucf"
+##
+## Pmod B0 - RS232
+##
+#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
Index: nexys2/.cvsignore
===================================================================
--- nexys2/.cvsignore (nonexistent)
+++ nexys2/.cvsignore (revision 24)
@@ -0,0 +1,5 @@
+_impactbatch.log
+sys_tst_serloop1_n2.ucf
+sys_tst_serloop2_n2.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys2
===================================================================
--- nexys2 (nonexistent)
+++ nexys2 (revision 24)
nexys2
Property changes :
Added: svn:ignore
## -0,0 +1,37 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_serloop1_n2.ucf
+sys_tst_serloop2_n2.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys3/tb/Makefile
===================================================================
--- nexys3/tb/Makefile (nonexistent)
+++ nexys3/tb/Makefile (revision 24)
@@ -0,0 +1,34 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-12-11 438 1.0.1 added tb_tst_serloop1_n3
+# 2011-11-27 433 1.0 Initial version
+#
+EXE_all = tb_tst_serloop1_n3
+#
+include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
+#
+.PHONY : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean isim_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+include $(RETROBASE)/rtl/make/generic_isim.mk
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(VBOM_all:.vbom=.dep_isim)
+include $(wildcard *.o.dep_ghdl)
+endif
+#
Index: nexys3/tb/tb_tst_serloop1_n3.vhd
===================================================================
--- nexys3/tb/tb_tst_serloop1_n3.vhd (nonexistent)
+++ nexys3/tb/tb_tst_serloop1_n3.vhd (revision 24)
@@ -0,0 +1,139 @@
+-- $Id: tb_tst_serloop1_n3.vhd 444 2011-12-25 10:04:58Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_tst_serloop1_n3 - sim
+-- Description: Test bench for sys_tst_serloop1_n3
+--
+-- Dependencies: simlib/simclk
+-- sys_tst_serloop1_n3 [UUT]
+-- tb/tb_tst_serloop
+--
+-- To test: sys_tst_serloop1_n3
+--
+-- Target Devices: generic
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-23 444 1.1 use new simclk
+-- 2011-12-11 438 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.simlib.all;
+
+entity tb_tst_serloop1_n3 is
+end tb_tst_serloop1_n3;
+
+architecture sim of tb_tst_serloop1_n3 is
+
+ signal CLK100 : slbit := '0';
+ signal CLK_STOP : slbit := '0';
+
+ signal I_RXD : slbit := '1';
+ signal O_TXD : slbit := '1';
+ signal I_SWI : slv8 := (others=>'0');
+ signal I_BTN : slv5 := (others=>'0');
+
+ signal O_FUSP_RTS_N : slbit := '0';
+ signal I_FUSP_CTS_N : slbit := '0';
+ signal I_FUSP_RXD : slbit := '1';
+ signal O_FUSP_TXD : slbit := '1';
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '1';
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv5 := (others=>'0');
+
+ signal FUSP_RTS_N : slbit := '0';
+ signal FUSP_CTS_N : slbit := '0';
+ signal FUSP_RXD : slbit := '1';
+ signal FUSP_TXD : slbit := '1';
+
+ constant clock_period : time := 10 ns;
+ constant clock_offset : time := 200 ns;
+ constant delay_time : time := 2 ns;
+
+begin
+
+ SYSCLK : simclk
+ generic map (
+ PERIOD => clock_period,
+ OFFSET => clock_offset)
+ port map (
+ CLK => CLK100,
+ CLK_STOP => CLK_STOP
+ );
+
+ UUT : entity work.sys_tst_serloop1_n3
+ port map (
+ I_CLK100 => CLK100,
+ I_RXD => I_RXD,
+ O_TXD => O_TXD,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => open,
+ O_ANO_N => open,
+ O_SEG_N => open,
+ O_MEM_CE_N => open,
+ O_MEM_BE_N => open,
+ O_MEM_WE_N => open,
+ O_MEM_OE_N => open,
+ O_MEM_ADV_N => open,
+ O_MEM_CLK => open,
+ O_MEM_CRE => open,
+ I_MEM_WAIT => '0',
+ O_MEM_ADDR => open,
+ IO_MEM_DATA => open,
+ O_PPCM_CE_N => open,
+ O_PPCM_RST_N => open,
+ O_FUSP_RTS_N => O_FUSP_RTS_N,
+ I_FUSP_CTS_N => I_FUSP_CTS_N,
+ I_FUSP_RXD => I_FUSP_RXD,
+ O_FUSP_TXD => O_FUSP_TXD
+ );
+
+ GENTB : entity work.tb_tst_serloop
+ port map (
+ CLKS => CLK100,
+ CLKH => CLK100,
+ CLK_STOP => CLK_STOP,
+ P0_RXD => RXD,
+ P0_TXD => TXD,
+ P0_RTS_N => '0',
+ P0_CTS_N => open,
+ P1_RXD => FUSP_RXD,
+ P1_TXD => FUSP_TXD,
+ P1_RTS_N => FUSP_RTS_N,
+ P1_CTS_N => FUSP_CTS_N,
+ SWI => SWI,
+ BTN => BTN(3 downto 0)
+ );
+
+ I_RXD <= RXD after delay_time;
+ TXD <= O_TXD after delay_time;
+ FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
+ I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
+ I_FUSP_RXD <= FUSP_RXD after delay_time;
+ FUSP_TXD <= O_FUSP_TXD after delay_time;
+
+ I_SWI <= SWI after delay_time;
+ I_BTN <= BTN after delay_time;
+
+end sim;
Index: nexys3/tb/tbw.dat
===================================================================
--- nexys3/tb/tbw.dat (nonexistent)
+++ nexys3/tb/tbw.dat (revision 24)
@@ -0,0 +1,6 @@
+# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $
+#
+[tb_tst_serloop1_n3]
+tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat
+[tb_tst_serloop2_n3]
+tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat
Index: nexys3/tb/tb_tst_serloop1_n3.vbom
===================================================================
--- nexys3/tb/tb_tst_serloop1_n3.vbom (nonexistent)
+++ nexys3/tb/tb_tst_serloop1_n3.vbom (revision 24)
@@ -0,0 +1,11 @@
+# conf
+sys_conf = sys_conf1_sim.vhd
+# libs
+../../../../vlib/slvtypes.vhd
+../../../../vlib/simlib/simlib.vhd
+# components
+../../../../vlib/simlib/simclk.vbom
+../sys_tst_serloop1_n3.vbom
+../../tb/tb_tst_serloop.vbom
+# design
+tb_tst_serloop1_n3.vhd
Index: nexys3/tb/sys_tst_serloop1_n3.ucf_cpp
===================================================================
--- nexys3/tb/sys_tst_serloop1_n3.ucf_cpp (nonexistent)
+++ nexys3/tb/sys_tst_serloop1_n3.ucf_cpp (revision 24)
@@ -0,0 +1 @@
+link ../sys_tst_serloop1_n3.ucf_cpp
\ No newline at end of file
nexys3/tb/sys_tst_serloop1_n3.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: nexys3/tb/sys_conf1_sim.vhd
===================================================================
--- nexys3/tb/sys_conf1_sim.vhd (nonexistent)
+++ nexys3/tb/sys_conf1_sim.vhd (revision 24)
@@ -0,0 +1,43 @@
+-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop1_n3 (for test bench)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-11 438 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ -- in simulation a usec is shortened to 20 cycles (0.2 usec) and a msec
+ -- to 100 cycles (1 usec). This affects the pulse generators (usec) and
+ -- mainly the autobauder. A break will be detected after 128 msec periods,
+ -- this in simulation after 128 usec or 6400 cycles. This is compatible with
+ -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
+
+ constant sys_conf_clkdiv_usecdiv : integer := 20; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+ constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+end package sys_conf;
Index: nexys3/tb/.cvsignore
===================================================================
--- nexys3/tb/.cvsignore (nonexistent)
+++ nexys3/tb/.cvsignore (revision 24)
@@ -0,0 +1,10 @@
+tb_tst_serloop1_n3
+tb_tst_serloop1_n3_[sft]sim
+tb_tst_serloop1_n3_ISim
+tb_tst_serloop1_n3_ISim_[sft]sim
+tb_tst_serloop2_n3
+tb_tst_serloop2_n3_[sft]sim
+tb_tst_serloop2_n3_ISim
+tb_tst_serloop2_n3_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: nexys3/tb
===================================================================
--- nexys3/tb (nonexistent)
+++ nexys3/tb (revision 24)
nexys3/tb
Property changes :
Added: svn:ignore
## -0,0 +1,42 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_tst_serloop1_n3
+tb_tst_serloop1_n3_[sft]sim
+tb_tst_serloop1_n3_ISim
+tb_tst_serloop1_n3_ISim_[sft]sim
+tb_tst_serloop2_n3
+tb_tst_serloop2_n3_[sft]sim
+tb_tst_serloop2_n3_ISim
+tb_tst_serloop2_n3_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: nexys3/sys_tst_serloop1_n3.vhd
===================================================================
--- nexys3/sys_tst_serloop1_n3.vhd (nonexistent)
+++ nexys3/sys_tst_serloop1_n3.vhd (revision 24)
@@ -0,0 +1,243 @@
+-- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_tst_serloop1_n3 - syn
+-- Description: Tester serial link for nexys3 (serport_1clock case)
+--
+-- Dependencies: genlib/clkdivce
+-- bpgen/bp_rs232_2l4l_iob
+-- bpgen/sn_humanio
+-- tst_serloop_hiomap
+-- vlib/serport/serport_1clock
+-- tst_serloop
+-- vlib/nxcramlib/nx_cram_dummy
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3)
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.tst_serlooplib.all;
+use work.serportlib.all;
+use work.nxcramlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_serloop1_n3 is -- top level
+ -- implements nexys3_fusp_aif
+ port (
+ I_CLK100 : in slbit; -- 100 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit; -- ppcm: ...
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_tst_serloop1_n3;
+
+architecture syn of sys_tst_serloop1_n3 is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal RXD : slbit := '0';
+ signal TXD : slbit := '0';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv5 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
+ signal HIO_STAT : hio_stat_type := hio_stat_init;
+
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXHOLD : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal SER_MONI : serport_moni_type := serport_moni_init;
+
+begin
+
+ CLK <= I_CLK100;
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 8,
+ USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20
+ MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
+ port map (
+ CLK => CLK,
+ CE_USEC => open,
+ CE_MSEC => CE_MSEC
+ );
+
+ HIO : sn_humanio
+ generic map (
+ BWIDTH => 5,
+ DEBOUNCE => sys_conf_hio_debounce)
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ CE_MSEC => CE_MSEC,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RESET <= BTN(0); -- BTN(0) will reset tester !!
+
+ HIOMAP : tst_serloop_hiomap
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ SWI => SWI,
+ BTN => BTN(3 downto 0),
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP
+ );
+
+ IOB_RS232 : bp_rs232_2l4l_iob
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ SEL => SWI(0), -- port selection
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ SERPORT : serport_1clock
+ generic map (
+ CDWIDTH => 15,
+ CDINIT => sys_conf_uart_cdinit,
+ RXFAWIDTH => 5,
+ TXFAWIDTH => 5)
+ port map (
+ CLK => CLK,
+ CE_MSEC => CE_MSEC,
+ RESET => RESET,
+ ENAXON => HIO_CNTL.enaxon,
+ ENAESC => HIO_CNTL.enaesc,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY,
+ MONI => SER_MONI,
+ RXSD => RXD,
+ TXSD => TXD,
+ RXRTS_N => RTS_N,
+ TXCTS_N => CTS_N
+ );
+
+ TESTER : tst_serloop
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
+ O_PPCM_RST_N <= '1'; --
+
+end syn;
Index: nexys3/Makefile
===================================================================
--- nexys3/Makefile (nonexistent)
+++ nexys3/Makefile (revision 24)
@@ -0,0 +1,28 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-27 433 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+endif
+#
Index: nexys3/sys_tst_serloop1_n3.vbom
===================================================================
--- nexys3/sys_tst_serloop1_n3.vbom (nonexistent)
+++ nexys3/sys_tst_serloop1_n3.vbom (revision 24)
@@ -0,0 +1,20 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../tst_serlooplib.vbom
+../../../vlib/serport/serportlib.vbom
+../../../bplib/nxcramlib/nxcramlib.vhd
+${sys_conf := sys_conf1.vhd}
+# components
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio.vbom
+../tst_serloop_hiomap.vbom
+../../../vlib/serport/serport_1clock.vbom
+../tst_serloop.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+# design
+sys_tst_serloop1_n3.vhd
+@ucf_cpp: sys_tst_serloop1_n3.ucf
Index: nexys3/sys_conf1.vhd
===================================================================
--- nexys3/sys_conf1.vhd (nonexistent)
+++ nexys3/sys_conf1.vhd (revision 24)
@@ -0,0 +1,37 @@
+-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop1_n3 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-09 438 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+ constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200
+
+end package sys_conf;
Index: nexys3/sys_tst_serloop1_n3.ucf_cpp
===================================================================
--- nexys3/sys_tst_serloop1_n3.ucf_cpp (nonexistent)
+++ nexys3/sys_tst_serloop1_n3.ucf_cpp (revision 24)
@@ -0,0 +1,19 @@
+## $Id: sys_tst_serloop1_n3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-12-09 438 1.0 Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns AFTER "I_CLK100";
+
+## std board
+##
+#include "bplib/nexys3/nexys3_pins.ucf"
+##
+## Pmod B0 - RS232
+##
+#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
Index: nexys3/.cvsignore
===================================================================
--- nexys3/.cvsignore (nonexistent)
+++ nexys3/.cvsignore (revision 24)
@@ -0,0 +1,5 @@
+_impactbatch.log
+sys_tst_serloop1_n3.ucf
+sys_tst_serloop2_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys3
===================================================================
--- nexys3 (nonexistent)
+++ nexys3 (revision 24)
nexys3
Property changes :
Added: svn:ignore
## -0,0 +1,37 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_serloop1_n3.ucf
+sys_tst_serloop2_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: tst_serloop_hiomap.vhd
===================================================================
--- tst_serloop_hiomap.vhd (nonexistent)
+++ tst_serloop_hiomap.vhd (revision 24)
@@ -0,0 +1,219 @@
+-- $Id: tst_serloop_hiomap.vhd 476 2013-01-26 22:23:53Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tst_serloop_hiomap - syn
+-- Description: default human I/O mapper
+--
+-- Dependencies: -
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-09 437 1.0.2 rename serport stat->moni port
+-- 2011-11-16 426 1.0.1 setup leds and dps
+-- 2011-11-05 420 1.0 Initial version
+------------------------------------------------------------------------------
+--
+-- Usage of Switches, Buttons, LEDs:
+--
+-- BTN(3): -- unused --
+-- (2): -- unused --
+-- (1): load enables from SWI(7:4)
+-- SWI(7) -> ENAFTDI
+-- SWI(6) -> ENATHROTTLE
+-- SWI(5) -> ENAESC
+-- SWI(4) -> ENAXON
+-- (0): reset state [!! decoded by top level design !!]
+--
+-- SWI(7:4) select display or enable pattern (when BTN(1) pressed)
+-- (3) -- unused --
+-- (2:1): mode 00 idle
+-- 01 rxblast
+-- 10 txblast
+-- 11 loop
+-- SWI(0) 0 -> main board RS232 port
+-- 1 -> Pmod1 RS232 port
+--
+-- LED(7) enaesc
+-- (6) enaxon
+-- (5) rxfecnt > 0 (frame error)
+-- (4) rxoecnt > 0 (overrun error)
+-- (3) rxsecnt > 0 (sequence error)
+-- (2) abact (shows ab activity)
+-- (1) (not rxok) or (not txok) (shows back preasure)
+-- (0) rxact or txact (shows activity)
+--
+-- DSP data as selected by SWI(7:4)
+-- 0000 -> rxfecnt
+-- 0001 -> rxoecnt
+-- 0010 -> rxsecnt
+-- 0100 -> rxcnt.l
+-- 0101 -> rxcnt.h
+-- 0110 -> txcnt.l
+-- 0111 -> txcnt.h
+-- 1000 -> rxokcnt
+-- 1001 -> txokcnt
+-- 1010 -> rxuicnt,rxuidat
+-- 1111 -> abclkdiv
+--
+-- DP(3): not SER_MONI.txok (shows tx back preasure)
+-- (2): SER_MONI.txact (shows tx activity)
+-- (1): not SER_MONI.rxok (shows rx back preasure)
+-- (0): SER_MONI.rxact (shows rx activity)
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.serportlib.all;
+use work.tst_serlooplib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity tst_serloop_hiomap is -- default human I/O mapper
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ HIO_CNTL : out hio_cntl_type; -- tester controls from hio
+ HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
+ SER_MONI : in serport_moni_type; -- serport monitor to display by hio
+ SWI : in slv8; -- switch settings
+ BTN : in slv4; -- button settings
+ LED : out slv8; -- led data
+ DSP_DAT : out slv16; -- display data
+ DSP_DP : out slv4 -- display decimal points
+ );
+end tst_serloop_hiomap;
+
+architecture syn of tst_serloop_hiomap is
+
+ type regs_type is record
+ enaxon : slbit; -- enable xon/xoff handling
+ enaesc : slbit; -- enable xon/xoff escaping
+ enathrottle : slbit; -- enable 1 msec tx throttling
+ enaftdi : slbit; -- enable ftdi flush handling
+ dspdat : slv16; -- display data
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ '0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi
+ (others=>'0') -- dspdat
+
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable icntl : hio_cntl_type := hio_cntl_init;
+ variable iled : slv8 := (others=>'0');
+ variable idat : slv16 := (others=>'0');
+ variable idp : slv4 := (others=>'0');
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ icntl := hio_cntl_init;
+ iled := (others=>'0');
+ idat := (others=>'0');
+ idp := (others=>'0');
+
+ -- handle BTN(1) "load enables" press
+
+ if BTN(1) = '1' then
+ n.enaxon := SWI(4);
+ n.enaesc := SWI(5);
+ n.enathrottle := SWI(6);
+ n.enaftdi := SWI(7);
+ end if;
+
+ -- setup tester controls
+
+ icntl.mode := SWI(2 downto 1);
+ icntl.enaxon := r.enaxon;
+ icntl.enaesc := r.enaesc;
+ icntl.enathrottle := r.enathrottle;
+ icntl.enaftdi := r.enaftdi;
+
+ -- setup leds
+ iled(7) := icntl.enaesc;
+ iled(6) := icntl.enaxon;
+ if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if;
+ if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if;
+ if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if;
+ iled(2) := SER_MONI.abact;
+ iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok);
+ iled(0) := SER_MONI.rxact or SER_MONI.txact;
+
+ -- setup display data
+
+ case SWI(7 downto 4) is
+ when "0000" => idat := HIO_STAT.rxfecnt;
+ when "0001" => idat := HIO_STAT.rxoecnt;
+ when "0010" => idat := HIO_STAT.rxsecnt;
+ when "0100" => idat := HIO_STAT.rxcnt(15 downto 0);
+ when "0101" => idat := HIO_STAT.rxcnt(31 downto 16);
+ when "0110" => idat := HIO_STAT.txcnt(15 downto 0);
+ when "0111" => idat := HIO_STAT.txcnt(31 downto 16);
+ when "1000" => idat := HIO_STAT.rxokcnt;
+ when "1001" => idat := HIO_STAT.txokcnt;
+ when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat;
+ when "1111" => idat := SER_MONI.abclkdiv;
+ when others => null;
+ end case;
+ n.dspdat := idat;
+
+ -- setup display decimal points
+
+ idp(3) := not SER_MONI.txok; -- tx back preasure
+ idp(2) := SER_MONI.txact; -- tx activity
+ idp(1) := not SER_MONI.rxok; -- rx back preasure
+ idp(0) := SER_MONI.rxact; -- rx activity
+
+ N_REGS <= n;
+
+ HIO_CNTL <= icntl;
+ LED <= iled;
+ DSP_DAT <= r.dspdat;
+ DSP_DP <= idp;
+
+ end process proc_next;
+
+end syn;
Index: tst_serloop_hiomap.vbom
===================================================================
--- tst_serloop_hiomap.vbom (nonexistent)
+++ tst_serloop_hiomap.vbom (revision 24)
@@ -0,0 +1,7 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/serport/serportlib.vbom
+tst_serlooplib.vbom
+# components
+# design
+tst_serloop_hiomap.vhd
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 24)
@@ -0,0 +1,28 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-10-14 416 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+include $(RETROBASE)/rtl/make/xflow_default_s3board.mk
+#
+.PHONY : all clean realclean
+#
+all : tst_serloop
+#
+clean : ise_clean
+#
+realclean :
+ rm -f tst_serloop
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+endif
+#
Index: s3board/sys_tst_serloop_s3.vhd
===================================================================
--- s3board/sys_tst_serloop_s3.vhd (nonexistent)
+++ s3board/sys_tst_serloop_s3.vhd (revision 24)
@@ -0,0 +1,243 @@
+-- $Id: sys_tst_serloop_s3.vhd 476 2013-01-26 22:23:53Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_tst_serloop_s3 - syn
+-- Description: Tester serial link for s3board
+--
+-- Dependencies: vlib/xlib/dcm_sfs
+-- genlib/clkdivce
+-- bpgen/bp_rs232_2l4l_iob
+-- bpgen/sn_humanio
+-- tst_serloop_hiomap
+-- vlib/serport/serport_1clock
+-- tst_serloop
+-- s3board/s3_sram_dummy
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2011-11-16 426 13.1 O40d xc3s1000-4 424 602 64 476 t 13.6
+-- 2011-11-13 425 13.1 O40d xc3s1000-4 421 586 64 466 t 13.6
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-09 437 1.0.2 rename serport stat->moni port
+-- 2011-11-17 426 1.0.1 use dcm_sfs now
+-- 2011-11-12 423 1.0 Initial version
+-- 2011-10-25 419 0.5 First draft
+------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.tst_serlooplib.all;
+use work.serportlib.all;
+use work.s3boardlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_serloop_s3 is -- top level
+ port (
+ I_CLK50 : in slbit; -- 50 MHz board clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- s3 switches
+ I_BTN : in slv4; -- s3 buttons
+ O_LED : out slv8; -- s3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
+ O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
+ O_MEM_ADDR : out slv18; -- sram: address lines
+ IO_MEM_DATA : inout slv32; -- sram: data lines
+ O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
+ I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
+ I_FUSP_RXD : in slbit; -- fusp: rs232 rx
+ O_FUSP_TXD : out slbit -- fusp: rs232 tx
+ );
+end sys_tst_serloop_s3;
+
+architecture syn of sys_tst_serloop_s3 is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal RXD : slbit := '0';
+ signal TXD : slbit := '0';
+ signal CTS_N : slbit := '0';
+ signal RTS_N : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
+ signal HIO_STAT : hio_stat_type := hio_stat_init;
+
+ signal RXDATA : slv8 := (others=>'0');
+ signal RXVAL : slbit := '0';
+ signal RXHOLD : slbit := '0';
+ signal TXDATA : slv8 := (others=>'0');
+ signal TXENA : slbit := '0';
+ signal TXBUSY : slbit := '0';
+
+ signal SER_MONI : serport_moni_type := serport_moni_init;
+
+begin
+
+ DCM : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => 5,
+ CLKFX_MULTIPLY => 6,
+ CLKIN_PERIOD => 20.0)
+ port map (
+ CLKIN => I_CLK50,
+ CLKFX => CLK,
+ LOCKED => open
+ );
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 6,
+ USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 60 sim: 12
+ MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC
+ );
+
+ HIO : sn_humanio
+ generic map (
+ DEBOUNCE => sys_conf_hio_debounce)
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ CE_MSEC => CE_MSEC,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RESET <= BTN(0); -- BTN(0) will reset tester !!
+
+ HIOMAP : tst_serloop_hiomap
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP
+ );
+
+ IOB_RS232 : bp_rs232_2l4l_iob
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ SEL => SWI(0), -- port selection
+ RXD => RXD,
+ TXD => TXD,
+ CTS_N => CTS_N,
+ RTS_N => RTS_N,
+ I_RXD0 => I_RXD,
+ O_TXD0 => O_TXD,
+ I_RXD1 => I_FUSP_RXD,
+ O_TXD1 => O_FUSP_TXD,
+ I_CTS1_N => I_FUSP_CTS_N,
+ O_RTS1_N => O_FUSP_RTS_N
+ );
+
+ SERPORT : serport_1clock
+ generic map (
+ CDWIDTH => 15,
+ CDINIT => sys_conf_uart_cdinit,
+ RXFAWIDTH => 5,
+ TXFAWIDTH => 5)
+ port map (
+ CLK => CLK,
+ CE_MSEC => CE_MSEC,
+ RESET => RESET,
+ ENAXON => HIO_CNTL.enaxon,
+ ENAESC => HIO_CNTL.enaesc,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY,
+ MONI => SER_MONI,
+ RXSD => RXD,
+ TXSD => TXD,
+ RXRTS_N => RTS_N,
+ TXCTS_N => CTS_N
+ );
+
+ TESTER : tst_serloop
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ SER_MONI => SER_MONI,
+ RXDATA => RXDATA,
+ RXVAL => RXVAL,
+ RXHOLD => RXHOLD,
+ TXDATA => TXDATA,
+ TXENA => TXENA,
+ TXBUSY => TXBUSY
+ );
+
+ SRAM : s3_sram_dummy -- connect SRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+end syn;
+
Index: s3board/sys_tst_serloop_s3.vbom
===================================================================
--- s3board/sys_tst_serloop_s3.vbom (nonexistent)
+++ s3board/sys_tst_serloop_s3.vbom (revision 24)
@@ -0,0 +1,22 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../tst_serlooplib.vbom
+../../../vlib/serport/serportlib.vbom
+../../../bplib/s3board/s3boardlib.vbom
+${sys_conf := sys_conf.vhd}
+# components
+[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom
+[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio.vbom
+../tst_serloop_hiomap.vbom
+../../../vlib/serport/serport_1clock.vbom
+../tst_serloop.vbom
+../../../bplib/s3board/s3_sram_dummy.vbom
+# design
+sys_tst_serloop_s3.vhd
+@ucf_cpp: sys_tst_serloop_s3.ucf
Index: s3board/tb/Makefile
===================================================================
--- s3board/tb/Makefile (nonexistent)
+++ s3board/tb/Makefile (revision 24)
@@ -0,0 +1,33 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-11-05 420 1.0 Initial version
+#
+EXE_all = tb_tst_serloop_s3
+#
+include $(RETROBASE)/rtl/make/xflow_default_s3board.mk
+#
+.PHONY : all all_ssim all_tsim clean
+#
+all : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean isim_clean
+#
+#-----
+#
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+include $(RETROBASE)/rtl/make/generic_isim.mk
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(VBOM_all:.vbom=.dep_isim)
+include $(wildcard *.o.dep_ghdl)
+endif
+#
Index: s3board/tb/tb_tst_serloop_s3.vhd
===================================================================
--- s3board/tb/tb_tst_serloop_s3.vhd (nonexistent)
+++ s3board/tb/tb_tst_serloop_s3.vhd (revision 24)
@@ -0,0 +1,149 @@
+-- $Id: tb_tst_serloop_s3.vhd 444 2011-12-25 10:04:58Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tb_tst_serloop_s3 - sim
+-- Description: Test bench for sys_tst_serloop_s3
+--
+-- Dependencies: simlib/simclk
+-- vlib/xlib/dcm_sfs
+-- sys_tst_serloop_s3 [UUT]
+-- tb/tb_tst_serloop
+--
+-- To test: sys_tst_serloop_s3
+--
+-- Target Devices: generic
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-23 444 1.1 use new simclk
+-- 2011-11-17 426 1.0.1 use dcm_sfs now
+-- 2011-11-06 420 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.simlib.all;
+
+entity tb_tst_serloop_s3 is
+end tb_tst_serloop_s3;
+
+architecture sim of tb_tst_serloop_s3 is
+
+ signal CLK50 : slbit := '0';
+ signal CLK_STOP : slbit := '0';
+
+ signal CLKS : slbit := '0';
+
+ signal I_RXD : slbit := '1';
+ signal O_TXD : slbit := '1';
+ signal I_SWI : slv8 := (others=>'0');
+ signal I_BTN : slv4 := (others=>'0');
+
+ signal O_FUSP_RTS_N : slbit := '0';
+ signal I_FUSP_CTS_N : slbit := '0';
+ signal I_FUSP_RXD : slbit := '1';
+ signal O_FUSP_TXD : slbit := '1';
+
+ signal RXD : slbit := '1';
+ signal TXD : slbit := '1';
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv4 := (others=>'0');
+
+ signal FUSP_RTS_N : slbit := '0';
+ signal FUSP_CTS_N : slbit := '0';
+ signal FUSP_RXD : slbit := '1';
+ signal FUSP_TXD : slbit := '1';
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant delay_time : time := 2 ns;
+
+begin
+
+ SYSCLK : simclk
+ generic map (
+ PERIOD => clock_period,
+ OFFSET => clock_offset)
+ port map (
+ CLK => CLK50,
+ CLK_STOP => CLK_STOP
+ );
+
+ DCM_S : dcm_sfs
+ generic map (
+ CLKFX_DIVIDE => 5,
+ CLKFX_MULTIPLY => 6,
+ CLKIN_PERIOD => 20.0)
+ port map (
+ CLKIN => CLK50,
+ CLKFX => CLKS,
+ LOCKED => open
+ );
+
+ UUT : entity work.sys_tst_serloop_s3
+ port map (
+ I_CLK50 => CLK50,
+ I_RXD => I_RXD,
+ O_TXD => O_TXD,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => open,
+ O_ANO_N => open,
+ O_SEG_N => open,
+ O_MEM_CE_N => open,
+ O_MEM_BE_N => open,
+ O_MEM_WE_N => open,
+ O_MEM_OE_N => open,
+ O_MEM_ADDR => open,
+ IO_MEM_DATA => open,
+ O_FUSP_RTS_N => O_FUSP_RTS_N,
+ I_FUSP_CTS_N => I_FUSP_CTS_N,
+ I_FUSP_RXD => I_FUSP_RXD,
+ O_FUSP_TXD => O_FUSP_TXD
+ );
+
+ GENTB : entity work.tb_tst_serloop
+ port map (
+ CLKS => CLKS,
+ CLKH => CLKS,
+ CLK_STOP => CLK_STOP,
+ P0_RXD => RXD,
+ P0_TXD => TXD,
+ P0_RTS_N => '0',
+ P0_CTS_N => open,
+ P1_RXD => FUSP_RXD,
+ P1_TXD => FUSP_TXD,
+ P1_RTS_N => FUSP_RTS_N,
+ P1_CTS_N => FUSP_CTS_N,
+ SWI => SWI,
+ BTN => BTN
+ );
+
+ I_RXD <= RXD after delay_time;
+ TXD <= O_TXD after delay_time;
+ FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
+ I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
+ I_FUSP_RXD <= FUSP_RXD after delay_time;
+ FUSP_TXD <= O_FUSP_TXD after delay_time;
+
+ I_SWI <= SWI after delay_time;
+ I_BTN <= BTN after delay_time;
+
+end sim;
Index: s3board/tb/tbw.dat
===================================================================
--- s3board/tb/tbw.dat (nonexistent)
+++ s3board/tb/tbw.dat (revision 24)
@@ -0,0 +1,4 @@
+# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $
+#
+[tb_tst_serloop_s3]
+tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat
Index: s3board/tb/tb_tst_serloop_s3.vbom
===================================================================
--- s3board/tb/tb_tst_serloop_s3.vbom (nonexistent)
+++ s3board/tb/tb_tst_serloop_s3.vbom (revision 24)
@@ -0,0 +1,13 @@
+# conf
+sys_conf = sys_conf_sim.vhd
+# libs
+../../../../vlib/slvtypes.vhd
+../../../../vlib/xlib/xlib.vhd
+../../../../vlib/simlib/simlib.vhd
+# components
+../../../../vlib/simlib/simclk.vbom
+../../../../vlib/xlib/dcm_sfs_gsim.vbom
+../sys_tst_serloop_s3.vbom
+../../tb/tb_tst_serloop.vbom
+# design
+tb_tst_serloop_s3.vhd
Index: s3board/tb/sys_conf_sim.vhd
===================================================================
--- s3board/tb/sys_conf_sim.vhd (nonexistent)
+++ s3board/tb/sys_conf_sim.vhd (revision 24)
@@ -0,0 +1,43 @@
+-- $Id: sys_conf_sim.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop_s3 (for test bench)
+--
+-- Dependencies: -
+-- Tool versions: xst 11.4; ghdl 0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-05 420 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ -- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
+ -- to 60 cycles (1 usec). This affects the pulse generators (usec) and
+ -- mainly the autobauder. A break will be detected after 128 msec periods,
+ -- this in simulation after 128 usec or 6400 cycles. This is compatible with
+ -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
+
+ constant sys_conf_clkdiv_usecdiv : integer := 12; -- shortened !
+ constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
+ constant sys_conf_hio_debounce : boolean := false; -- no debouncers
+ constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
+
+end package sys_conf;
Index: s3board/tb/.cvsignore
===================================================================
--- s3board/tb/.cvsignore (nonexistent)
+++ s3board/tb/.cvsignore (revision 24)
@@ -0,0 +1,6 @@
+tb_tst_serloop_s3
+tb_tst_serloop_s3_[sft]sim
+tb_tst_serloop_s3_ISim
+tb_tst_serloop_s3_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: s3board/tb/sys_tst_serloop_s3.ucf_cpp
===================================================================
--- s3board/tb/sys_tst_serloop_s3.ucf_cpp (nonexistent)
+++ s3board/tb/sys_tst_serloop_s3.ucf_cpp (revision 24)
@@ -0,0 +1 @@
+link ../sys_tst_serloop_s3.ucf_cpp
\ No newline at end of file
s3board/tb/sys_tst_serloop_s3.ucf_cpp
Property changes :
Added: svn:special
## -0,0 +1 ##
+*
\ No newline at end of property
Index: s3board/tb
===================================================================
--- s3board/tb (nonexistent)
+++ s3board/tb (revision 24)
s3board/tb
Property changes :
Added: svn:ignore
## -0,0 +1,38 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_tst_serloop_s3
+tb_tst_serloop_s3_[sft]sim
+tb_tst_serloop_s3_ISim
+tb_tst_serloop_s3_ISim_[sft]sim
+tb_tst_serloop_stim
+*.dep_ucf_cpp
Index: s3board/Makefile
===================================================================
--- s3board/Makefile (nonexistent)
+++ s3board/Makefile (revision 24)
@@ -0,0 +1,28 @@
+# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2011-10-14 416 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+include $(RETROBASE)/rtl/make/xflow_default_s3board.mk
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+endif
+#
Index: s3board/sys_conf.vhd
===================================================================
--- s3board/sys_conf.vhd (nonexistent)
+++ s3board/sys_conf.vhd (revision 24)
@@ -0,0 +1,38 @@
+-- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_serloop_s3 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.1; ghdl 0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-13 424 1.0 Initial version
+-- 2011-10-25 419 0.5 First draft
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkdiv_usecdiv : integer := 60; -- default usec
+ constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+ constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
+
+end package sys_conf;
Index: s3board/sys_tst_serloop_s3.mfset
===================================================================
--- s3board/sys_tst_serloop_s3.mfset (nonexistent)
+++ s3board/sys_tst_serloop_s3.mfset (revision 24)
@@ -0,0 +1,34 @@
+# $Id: sys_tst_serloop_s3.mfset 441 2011-12-20 17:01:16Z mueller $
+#
+# ----------------------------------------------------------------------------
+[xst]
+INFO:.*Mux is complete : default of case is discarded
+
+Unconnected output port 'LOCKED' of component 'dcm_sfs'
+Unconnected output port 'SIZE' of component 'fifo_1c_dram'
+Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
+
+Input > is never used
+Input > is never used
+Input > is never used
+Input > is never used
+
+Signal > is assigned but never used
+Signal is assigned but never used
+
+#
+# ----------------------------------------------------------------------------
+[tra]
+
+#
+# ----------------------------------------------------------------------------
+[map]
+INFO:.*
+
+#
+# ----------------------------------------------------------------------------
+[par]
+
+#
+# ----------------------------------------------------------------------------
+[bgn]
Index: s3board/.cvsignore
===================================================================
--- s3board/.cvsignore (nonexistent)
+++ s3board/.cvsignore (revision 24)
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_serloop_s3.ucf
+*.dep_ucf_cpp
+*.svf
Index: s3board/sys_tst_serloop_s3.ucf_cpp
===================================================================
--- s3board/sys_tst_serloop_s3.ucf_cpp (nonexistent)
+++ s3board/sys_tst_serloop_s3.ucf_cpp (revision 24)
@@ -0,0 +1,19 @@
+## $Id: sys_tst_serloop_s3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-10-25 419 1.0 Initial version
+##
+
+NET "I_CLK50" TNM_NET = "I_CLK50";
+TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK50";
+OFFSET = OUT 20 ns AFTER "I_CLK50";
+
+## std board
+##
+#include "bplib/s3board/s3board_pins.ucf"
+##
+## Pmod1-RS232 on A2 connector
+##
+#include "bplib/s3board/s3board_a2_pm1_rs232.ucf"
Index: s3board
===================================================================
--- s3board (nonexistent)
+++ s3board (revision 24)
s3board
Property changes :
Added: svn:ignore
## -0,0 +1,36 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_serloop_s3.ucf
+*.dep_ucf_cpp
+*.svf
Index: tst_serloop.vhd
===================================================================
--- tst_serloop.vhd (nonexistent)
+++ tst_serloop.vhd (revision 24)
@@ -0,0 +1,241 @@
+-- $Id: tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $
+--
+-- Copyright 2011- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: tst_serloop - syn
+-- Description: simple stand-alone tester for serport components
+--
+-- Dependencies: -
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.1; ghdl 0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs
+-- 2011-12-09 437 1.0.1 rename serport stat->moni port
+-- 2011-11-06 420 1.0 Initial version
+-- 2011-10-14 416 0.5 First draft
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.serportlib.all;
+use work.tst_serlooplib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity tst_serloop is -- tester for serport components
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CE_MSEC : in slbit; -- msec pulse
+ HIO_CNTL : in hio_cntl_type; -- humanio controls
+ HIO_STAT : out hio_stat_type; -- humanio status
+ SER_MONI : in serport_moni_type; -- serport monitor
+ RXDATA : in slv8; -- receiver data out
+ RXVAL : in slbit; -- receiver data valid
+ RXHOLD : out slbit; -- receiver data hold
+ TXDATA : out slv8; -- transmit data in
+ TXENA : out slbit; -- transmit data enable
+ TXBUSY : in slbit -- transmit busy
+ );
+end tst_serloop;
+
+architecture syn of tst_serloop is
+
+ type regs_type is record
+ rxdata : slv8; -- next rx char
+ txdata : slv8; -- next tx char
+ rxfecnt : slv16; -- rx frame error counter
+ rxoecnt : slv16; -- rx overrun error counter
+ rxsecnt : slv16; -- rx sequence error counter
+ rxcnt : slv32; -- rx char counter
+ txcnt : slv32; -- tx char counter
+ rxuicnt : slv8; -- rx unsolicited input counter
+ rxuidat : slv8; -- rx unsolicited input data
+ rxokcnt : slv16; -- rxok 1->0 transition counter
+ txokcnt : slv16; -- txok 1->0 transition counter
+ rxok_1 : slbit; -- rxok last cycle
+ txok_1 : slbit; -- txok last cycle
+ rxthrottle : slbit; -- rx throttle flag
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ (others=>'0'), -- rxdata
+ (others=>'0'), -- txdata
+ (others=>'0'), -- rxfecnt
+ (others=>'0'), -- rxoecnt
+ (others=>'0'), -- rxsecnt
+ (others=>'0'), -- rxcnt
+ (others=>'0'), -- txcnt
+ (others=>'0'), -- rxuicnt
+ (others=>'0'), -- rxuidat
+ (others=>'0'), -- rxokcnt
+ (others=>'0'), -- txokcnt
+ '0','0', -- rxok_1,txok_1
+ '0' -- rxthrottle
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI,
+ RXDATA, RXVAL, TXBUSY)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable irxhold : slbit := '1';
+ variable itxena : slbit := '0';
+ variable itxdata : slv8 := (others=>'0');
+ variable skipxon : slbit := '0';
+
+ function nextchar(skipxon: in slbit; data: in slv8) return slv8 is
+ variable inc : slv8 := (others=>'0');
+ begin
+ inc := "00000001";
+ if skipxon='1' and (data=c_serport_xon or data=c_serport_xoff) then
+ inc := "00000010";
+ end if;
+ return slv(unsigned(data)+unsigned(inc));
+ end function nextchar;
+
+ begin
+ r := R_REGS;
+ n := R_REGS;
+
+ irxhold := '1';
+ itxena := '0';
+
+ itxdata := RXDATA;
+ if HIO_CNTL.mode = c_mode_txblast then
+ itxdata := r.txdata;
+ end if;
+
+ skipxon := '0';
+ if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then
+ skipxon := '1';
+ end if;
+
+ if HIO_CNTL.enathrottle = '1' then
+ if CE_MSEC = '1' then
+ n.rxthrottle := not r.rxthrottle;
+ end if;
+ else
+ n.rxthrottle := '0';
+ end if;
+
+
+ case HIO_CNTL.mode is
+ when c_mode_idle =>
+ null;
+
+ when c_mode_rxblast =>
+ if RXVAL='1' and r.rxthrottle='0' then
+ irxhold := '0';
+ if RXDATA /= r.rxdata then
+ n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
+ end if;
+ n.rxdata := nextchar(skipxon, RXDATA);
+ end if;
+
+ when c_mode_txblast =>
+ if TXBUSY = '0' then
+ itxena := '1';
+ n.txdata := nextchar(skipxon, r.txdata);
+ end if;
+ irxhold := '0';
+ if RXVAL = '1' then
+ n.rxuicnt := slv(unsigned(r.rxuicnt) + 1);
+ n.rxuidat := RXDATA;
+ end if;
+
+ when c_mode_loop =>
+ if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then
+ irxhold := '0';
+ itxena := '1';
+ end if;
+
+ when others => null;
+ end case;
+
+
+ if SER_MONI.abact = '1' then -- if auto bauder active
+ n.rxfecnt := (others=>'0'); -- reset frame error counter
+ else -- otherwise
+ if SER_MONI.rxerr = '1' then -- count rx frame errors
+ n.rxfecnt := slv(unsigned(r.rxfecnt) + 1);
+ end if;
+ end if;
+
+ if SER_MONI.rxovr = '1' then
+ n.rxoecnt := slv(unsigned(r.rxoecnt) + 1);
+ end if;
+
+ if RXVAL='1' and irxhold='0' then
+ n.rxcnt := slv(unsigned(r.rxcnt) + 1);
+ end if;
+
+ if itxena = '1' then
+ n.txcnt := slv(unsigned(r.txcnt) + 1);
+ end if;
+
+ n.rxok_1 := SER_MONI.rxok;
+ n.txok_1 := SER_MONI.txok;
+
+ if SER_MONI.rxok='0' and r.rxok_1='1' then
+ n.rxokcnt := slv(unsigned(r.rxokcnt) + 1);
+ end if;
+ if SER_MONI.txok='0' and r.txok_1='1' then
+ n.txokcnt := slv(unsigned(r.txokcnt) + 1);
+ end if;
+
+ N_REGS <= n;
+
+ RXHOLD <= irxhold;
+ TXENA <= itxena;
+ TXDATA <= itxdata;
+
+ HIO_STAT.rxfecnt <= r.rxfecnt;
+ HIO_STAT.rxoecnt <= r.rxoecnt;
+ HIO_STAT.rxsecnt <= r.rxsecnt;
+ HIO_STAT.rxcnt <= r.rxcnt;
+ HIO_STAT.txcnt <= r.txcnt;
+ HIO_STAT.rxuicnt <= r.rxuicnt;
+ HIO_STAT.rxuidat <= r.rxuidat;
+ HIO_STAT.rxokcnt <= r.rxokcnt;
+ HIO_STAT.txokcnt <= r.txokcnt;
+
+ end process proc_next;
+
+end syn;
Index: .cvsignore
===================================================================
--- .cvsignore (nonexistent)
+++ .cvsignore (revision 24)
@@ -0,0 +1 @@
+tst_serloop
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 24)
.
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tst_serloop