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    /w11/tags/w11a_V0.6/rtl/sys_gen
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Rev 22 → Rev 24

/tst_fx2loop/tst_fx2loop.c
0,0 → 1,1045
/* $Id: tst_fx2loop.c 530 2013-08-09 21:25:04Z mueller $ */
/*
* Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
*
* This program is free software; you may redistribute and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2, or at your option any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for complete details.
*
*
* Revision History:
* Date Rev Version Comment
* 2013-08-09 530 2.1.2 -read: write up to 9 nstead of 7 words
* 2012-04-09 461 2.1.1 fix loop back code: fix run-down, add pipe drain
* 2012-03-24 460 2.1 add message loop back code (preliminary)
* 2012-03-10 459 2.0 re-write for asynchronous libusb interface
* 2012-02-12 457 1.1 redo argument handling; add -stat and -rndm
* 2012-01-15 453 1.0.1 add -tx2blast; fix bug in loop read loop
* 2011-12-29 446 1.0 Initial version (only -read/write/loop)
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <string.h>
#include <limits.h>
#include <signal.h>
#include <poll.h>
#include <errno.h>
#include <sys/timerfd.h>
 
#include <libusb-1.0/libusb.h>
 
static int nsigint = 0;
static int endpoll = 0;
static libusb_context* pUsbContext = 0;
static libusb_device** pUsbDevList = 0;
static int UsbDevCount = 0;
static libusb_device_handle* pUsbDevHdl = 0;
 
static struct pollfd pollfd_fds[16];
static int pollfd_nfds = 0;
 
struct dsc_queue {
int par_nfrm;
int par_nque;
double stat_nbuf;
double stat_nbyt;
double stat_npt;
uint16_t cval;
};
 
static struct dsc_queue dsc_rx;
static struct dsc_queue dsc_tx1;
static struct dsc_queue dsc_tx2;
 
static int par_nwmsg = 0;
static int par_nwrndm = 0;
static int par_stat = 0;
static int par_trace = 0;
static int par_nsec = 0;
 
static int cur_nwmsg = 0;
static double stat_nmsg = 0.;
 
static double t_start;
static int nreq = 0;
 
static char** argv;
static int argc;
static int argi;
 
 
void usage(FILE* of);
int get_pint(char* p);
double get_double(char* p);
int get_arg_pint(int min, int max, const char* text);
 
void do_write(uint16_t* buf, int nw);
void do_read(int ep);
void do_run();
void do_stat();
void usb_claim();
void usb_release();
char* usb_strerror(int rc);
void prt_time(void);
double get_time(void);
void bad_syscall_exit(const char* text, int rc);
void bad_usbcall_exit(const char* text, int rc);
void bad_transfer_exit(struct libusb_transfer *t, const char* text);
 
void sigint_handler(int signum)
{
printf("\n");
nsigint += 1;
if (nsigint > 3) {
fprintf(stderr, "tst_fx2loop-F: 3rd ^C, aborting\n");
exit(EXIT_FAILURE);
}
return;
}
 
int main(int main_argc, char *main_argv[])
{
argc = main_argc;
argv = main_argv;
argi = 1;
int i;
 
/* setup ^C handler */
struct sigaction new_action;
 
new_action.sa_handler = sigint_handler;
sigemptyset (&new_action.sa_mask);
new_action.sa_flags = 0;
sigaction (SIGINT, &new_action, NULL);
 
/* capture -help case here */
for (i = 1; i < argc; i++) {
if (strcmp(argv[i], "-help") == 0) {
usage(stdout);
return EXIT_SUCCESS;
}
}
 
/* determine usb device path (first arg or from RETRO_FX2_VID/PID */
char devbuf[10];
char* path = 0;
 
if (argc > argi && argv[argi][0] != '-') {
path = argv[argi];
argi += 1;
} else {
char* env_vid = getenv("RETRO_FX2_VID");
char* env_pid = getenv("RETRO_FX2_PID");
if (env_vid && strlen(env_vid) == 4 &&
env_pid && strlen(env_pid) == 4) {
strncpy(devbuf , env_vid,4);
devbuf[4] = ':';
strncpy(devbuf+5, env_pid,4);
devbuf[9] = 0;
path = devbuf;
} else {
fprintf(stderr,
"tst_fx2loop-F: RETRO_FX2_VID/PID not or ill defined\n");
return EXIT_FAILURE;
}
}
 
/* init libusb, connect to device */
libusb_init(&pUsbContext);
libusb_set_debug(pUsbContext, 3);
UsbDevCount = libusb_get_device_list(pUsbContext, &pUsbDevList);
 
libusb_device* mydev = 0;
 
if (strlen(path)==8 && path[0]=='/' && path[4]=='/') {
char busnam[4];
char devnam[4];
strncpy(busnam, path+1, 3);
strncpy(devnam, path+5, 3);
busnam[3] = 0;
devnam[3] = 0;
 
char* endptr;
uint8_t busnum = strtol(busnam, &endptr, 10);
uint8_t devnum = strtol(devnam, &endptr, 10);
 
int idev;
for (idev=0; idev<UsbDevCount; idev++) {
libusb_device* udev = pUsbDevList[idev];
if (libusb_get_bus_number(udev) == busnum &&
libusb_get_device_address(udev) == devnum) {
mydev = udev;
}
}
 
} else if (strlen(path)==9 && path[4]==':') {
char vennam[5];
char pronam[5];
memcpy(vennam, path, 4);
memcpy(pronam, path+5, 4);
vennam[4] = 0;
pronam[4] = 0;
 
char* endptr;
uint16_t vennum = strtol(vennam, &endptr, 16);
uint16_t pronum = strtol(pronam, &endptr, 16);
 
int idev;
for (idev=0; idev<UsbDevCount; idev++) {
libusb_device* udev = pUsbDevList[idev];
struct libusb_device_descriptor devdsc;
libusb_get_device_descriptor(udev, &devdsc);
if (devdsc.idVendor==vennum && devdsc.idProduct==pronum) {
mydev = udev;
}
}
 
} else {
fprintf(stderr, "tst_fx2loop-F: dev not in /bus/dev or vend:prod form\n");
return EXIT_FAILURE;
}
 
if (mydev == 0) {
fprintf(stderr, "tst_fx2loop-F: no usb device %s found\n", path);
return EXIT_FAILURE;
}
 
int rc;
rc = libusb_open(mydev, &pUsbDevHdl);
if (rc) {
fprintf(stderr, "tst_fx2loop-F: failed to open %s rc=%d: %s\n",
path, rc, usb_strerror(rc));
return EXIT_FAILURE;
}
 
/* check for internal timeout handling support */
if (libusb_pollfds_handle_timeouts(pUsbContext) == 0) {
fprintf(stderr, "tst_fx2loop-F: libusb_pollfds_handle_timeouts == 0\n"
" this program will not run on this legacy system\n");
return EXIT_FAILURE;
}
 
for (; argi < argc; ) {
 
/* handle setup options ----------------------------------------------- */
if (strcmp(argv[argi],"-nbrx") == 0) {
argi += 1;
dsc_rx.par_nfrm = get_arg_pint(1, 256, "rx buffer size invalid");
} else if (strcmp(argv[argi],"-nqrx") == 0) {
argi += 1;
dsc_rx.par_nque = get_arg_pint(1, 8, "rx buffer count invalid");
 
} else if (strcmp(argv[argi],"-nbtx") == 0) {
argi += 1;
dsc_tx1.par_nfrm = get_arg_pint(1, 256, "tx1 buffer size invalid");
} else if (strcmp(argv[argi],"-nqtx") == 0) {
argi += 1;
dsc_tx1.par_nque = get_arg_pint(1, 8, "tx1 buffer count invalid");
 
} else if (strcmp(argv[argi],"-nbtx2") == 0) {
argi += 1;
dsc_tx2.par_nfrm = get_arg_pint(1, 256, "tx2 buffer size invalid");
} else if (strcmp(argv[argi],"-nqtx2") == 0) {
argi += 1;
dsc_tx2.par_nque = get_arg_pint(1, 8, "tx2 buffer count invalid");
 
} else if (strcmp(argv[argi],"-nwmsg") == 0) {
argi += 1;
par_nwmsg = get_arg_pint(1, 4096, "loopback message size invalid");
 
} else if (strcmp(argv[argi],"-rndm") == 0) {
argi += 1;
par_nwrndm = 1;
} else if (strcmp(argv[argi],"-stat") == 0) {
argi += 1;
par_stat = 1;
} else if (strcmp(argv[argi],"-trace") == 0) {
argi += 1;
par_trace = 1;
 
/* handle action options ---------------------------------------------- */
} else if (strcmp(argv[argi],"-write") == 0) {
uint16_t buf[4096];
int nw = 0;
argi += 1;
while(argi < argc && nw < 4096) {
char *argp = argv[argi];
if (argp[0] == '-') break;
char* endptr;
long val = strtol(argp, &endptr, 0);
if ((endptr && endptr[0]) || val < 0 || val > 0xffff) {
nw = 0;
break;
}
argi += 1;
buf[nw++] = (uint16_t)val;
}
if (nw == 0) {
fprintf(stderr, "tst_fx2loop-E: bad word list\n");
break;
}
do_write(buf, nw);
 
} else if (strcmp(argv[argi],"-read") == 0) {
argi += 1;
int ep = 6;
if (argi < argc) ep = get_pint(argv[argi++]);
if (ep != 6 && ep != 8) {
fprintf(stderr, "tst_fx2loop-F: bad read endpoint (must be 6 or 8)\n");
return EXIT_FAILURE;
}
do_read(ep);
} else if (strcmp(argv[argi],"-run") == 0) {
argi += 1;
if (argi < argc) par_nsec = get_pint(argv[argi++]);
if (par_nsec < 0) {
fprintf(stderr, "tst_fx2loop-E: bad args for -run\n");
break;
}
do_run();
do_stat();
 
} else {
fprintf(stderr, "tst_fx2loop-F: unknown option %s\n", argv[argi]);
usage(stderr);
return EXIT_FAILURE;
}
}
 
return EXIT_SUCCESS;
}
 
/*--------------------------------------------------------------------------*/
void usage(FILE* of)
{
fprintf(of, "Usage: tst_fx2loop [dev] [setup-opts...] [action-opts...]\n");
fprintf(of, " arguments:\n");
fprintf(of, " dev path usb device, either bus/dev or vend:prod\n");
fprintf(of, " default is $RETRO_FX2_VID:$RETRO_FX2_VID\n");
fprintf(of, " setup options:\n");
fprintf(of, " -nbrx nb buffer size (in 512B) for rxblast\n");
fprintf(of, " -nqrx nb number of buffers for rxblast\n");
fprintf(of, " -nbtx nb buffer size (in 512B) for txblast or loop\n");
fprintf(of, " -nqtx nb number of buffers for txblast or loop\n");
fprintf(of, " -nbtx2 nb buffer size (in 512B) for tx2blast\n");
fprintf(of, " -nqtx2 nb number of buffers for tx2blast\n");
fprintf(of, " -nwmsg nw number words for loop test\n");
fprintf(of, " -rndm use random length for loop test\n");
fprintf(of, " -stat print live stats\n");
fprintf(of, " -trace trace usb calls\n");
fprintf(of, " action options:\n");
fprintf(of, " -write w0 w1 ... write list of words to endpoint 4\n");
fprintf(of, " -read ep read from endpoint ep\n");
fprintf(of, " -run ns run tests for nw seconds\n");
}
 
/*--------------------------------------------------------------------------*/
 
int get_pint(char* p)
{
char *endptr;
long num = 0;
 
num = strtol(p, &endptr, 0);
if ((endptr && *endptr) || num < 0 || num > INT_MAX) {
fprintf(stderr, "tst_fx2loop-E: \"%s\" not a non-negative integer\n", p);
return -1;
}
return num;
}
 
/*--------------------------------------------------------------------------*/
 
double get_double(char* p)
{
char *endptr;
double num = 0.;
 
num = strtod(p, &endptr);
if ((endptr && *endptr) || num < 0.) {
fprintf(stderr, "tst_fx2loop-E: \"%s\" not a valid positive float\n", p);
return -1.;
}
return num;
}
 
/*--------------------------------------------------------------------------*/
 
int get_arg_pint(int min, int max, const char* text)
{
int tmp = -1;
if (argi < argc) tmp = get_pint(argv[argi++]);
if (tmp < min || tmp > max) {
fprintf(stderr, "tst_fx2loop-F: %s\n", text);
exit(EXIT_FAILURE);
}
return tmp;
}
 
/*--------------------------------------------------------------------------*/
 
void do_write(uint16_t* buf, int nw)
{
int rc;
int i;
int ntrans;
int tout = 1000;
int ep = 4;
 
usb_claim();
rc = libusb_bulk_transfer(pUsbDevHdl, ep,
(unsigned char *)buf, nw*2, &ntrans, tout);
if (rc!=0 || ntrans != nw*2) {
fprintf(stderr, "tst_fx2loop-E: bulk write failed ntrans=%d rc=%d: %s \n",
ntrans, rc, usb_strerror(rc));
} else {
prt_time();
printf("write %4d word:", nw);
for (i = 0; i < nw; i++) printf(" %4.4x", buf[i]);
printf("\n");
}
usb_release();
 
return;
}
 
/*--------------------------------------------------------------------------*/
 
void do_read(int ep)
{
int rc;
int i;
int ntrans;
uint16_t buf[4096];
int tout = 1000;
int nloop;
 
usb_claim();
for (nloop=0;;nloop++) {
rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80,
(unsigned char *)buf, 2*4096, &ntrans, tout);
if (ntrans==0 && rc) {
if (rc==LIBUSB_ERROR_TIMEOUT && ntrans==0 && nloop>0) break;
fprintf(stderr, "tst_fx2loop-E: bulk read failed ntrans=%d rc=%d: %s \n",
ntrans, rc, usb_strerror(rc));
break;
}
prt_time();
printf("read %4d word:", ntrans/2);
int nprt = ntrans/2;
if (nprt > 9) nprt = 9;
for (i = 0; i < nprt; i++) printf(" %4.4x", (uint16_t)buf[i]);
printf("\n");
if (nsigint>0) break;
}
usb_release();
return;
}
 
/*----------------------------------------------------------*/
void pollfd_add(int fd, short events, void *user_data)
{
if (pollfd_nfds >= 16) {
fprintf(stderr, "tst_fx2loop-F: pollfd list overflow\n");
exit(EXIT_FAILURE);
}
if (par_trace) {
prt_time();
printf("pollfd_add: fd=%3d evt=%4.4x\n", fd, events);
}
pollfd_fds[pollfd_nfds].fd = fd;
pollfd_fds[pollfd_nfds].events = events;
pollfd_fds[pollfd_nfds].revents = 0;
pollfd_nfds += 1;
return;
}
 
/*----------------------------------------------------------*/
void pollfd_remove(int fd, void *user_data)
{
int iw = 0;
int ir = 0;
if (par_trace) {
prt_time();
printf("pollfd_remove: fd=%3d\n", fd);
}
for (ir = 0; ir < pollfd_nfds; ir++) {
if (pollfd_fds[ir].fd != fd) {
pollfd_fds[iw].fd = pollfd_fds[ir].fd;
pollfd_fds[iw].events = pollfd_fds[ir].events;
pollfd_fds[iw].revents = pollfd_fds[ir].revents;
iw += 1;
}
}
pollfd_nfds = iw;
return;
}
 
/*----------------------------------------------------------*/
void pollfd_init()
{
const struct libusb_pollfd** plist = libusb_get_pollfds(pUsbContext);
const struct libusb_pollfd** p;
for (p = plist; *p !=0; p++) {
pollfd_add((*p)->fd, (*p)->events, NULL);
}
 
free(plist);
 
libusb_set_pollfd_notifiers(pUsbContext, pollfd_add, pollfd_remove,NULL);
 
return;
}
 
/*----------------------------------------------------------*/
int keep_running()
{
if (nsigint > 0) return 0;
if (par_nsec > 0 && (get_time()-t_start) > par_nsec) return 0;
return 1;
}
 
/* forward declaration needed... */
void cb_rxblast(struct libusb_transfer *t);
 
/*----------------------------------------------------------*/
void que_write()
{
int rc;
int i;
int nw = 512*dsc_rx.par_nfrm/2;
int length = 2*nw;
uint16_t* pdat;
 
struct libusb_transfer* t = libusb_alloc_transfer(0);
 
t->dev_handle = pUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = 4;
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 1000;
t->status = 0;
t->buffer = malloc(length);
t->length = length;
t->actual_length = 0;
t->callback = cb_rxblast;
t->user_data = 0;
 
pdat = (uint16_t*)(t->buffer);
for (i = 0; i < nw; i++) *pdat++ = dsc_rx.cval++;
rc = libusb_submit_transfer(t);
if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
 
nreq += 1;
 
if (par_trace) {
prt_time();
printf("que_write: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length);
}
 
return;
}
 
/*----------------------------------------------------------*/
void que_read(int ep, int nb, libusb_transfer_cb_fn cb)
{
int rc;
int length = 512*nb;
 
struct libusb_transfer* t = libusb_alloc_transfer(0);
 
t->dev_handle = pUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = (unsigned char) (ep|0x80);
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 1000;
t->status = 0;
t->buffer = malloc(length);
t->length = length;
t->actual_length = 0;
t->callback = cb;
t->user_data = 0;
 
rc = libusb_submit_transfer(t);
if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
 
nreq += 1;
 
if (par_trace) {
prt_time();
printf("que_read: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length);
}
 
return;
}
 
/*----------------------------------------------------------*/
void send_msg()
{
int rc;
int i;
int nw = par_nwmsg;
int length;
uint16_t* pdat;
 
if (par_nwrndm) nw = 1 + (random() % par_nwmsg);
length = 2 * nw;
cur_nwmsg = nw;
 
struct libusb_transfer* t = libusb_alloc_transfer(0);
 
t->dev_handle = pUsbDevHdl;
t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
t->endpoint = 4;
t->type = LIBUSB_TRANSFER_TYPE_BULK;
t->timeout = 1000;
t->status = 0;
t->buffer = malloc(length);
t->length = length;
t->actual_length = 0;
t->callback = cb_rxblast;
t->user_data = 0;
 
pdat = (uint16_t*)(t->buffer);
for (i = 0; i < nw-1; i++) *pdat++ = dsc_rx.cval++;
*pdat++ = 0xdead;
rc = libusb_submit_transfer(t);
if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
 
nreq += 1;
 
if (par_trace) {
prt_time();
printf("send_msg: ep=%1d l=%5d", t->endpoint&(~0x80), t->length);
printf(" buf=%4.4x,..", ((uint16_t*)(t->buffer))[0]);
for (i = nw-2; i < nw; i++) {
printf(",%4.4x", ((uint16_t*)(t->buffer))[i]);
}
printf("\n");
}
return;
}
 
/*----------------------------------------------------------*/
void cb_rxblast(struct libusb_transfer *t)
{
nreq -= 1;
 
if (par_trace) {
prt_time();
printf("cb_rx : ep=%d l=%5d al=%5d\n",
t->endpoint&(~0x80), t->length, t->actual_length);
}
 
bad_transfer_exit(t, "cb_rxblast");
dsc_rx.stat_nbuf += 1;
dsc_rx.stat_nbyt += t->actual_length;
 
if (par_nwmsg==0 && keep_running()) que_write();
 
return;
}
 
/*----------------------------------------------------------*/
void cb_txblast(struct libusb_transfer *t, int ep, libusb_transfer_cb_fn cb,
struct dsc_queue* pdsc)
{
nreq -= 1;
 
if (par_trace) {
prt_time();
printf("cb_txx: ep=%d l=%5d al=%5d\n",
t->endpoint&(~0x80), t->length, t->actual_length);
}
 
bad_transfer_exit(t, "cb_txblast");
if (t->actual_length > 0) {
uint16_t* pdat = (uint16_t*)(t->buffer);
int nw = t->actual_length/2;
int i;
if (pdsc->stat_nbuf == 0) pdsc->cval = pdat[0];
for (i = 0; i < nw; i++) {
uint16_t dat = *pdat++;
if (pdsc->cval != dat) {
prt_time();
printf("FAIL: on ep=%d seen %4.4x expect %4.4x after %10.0f char\n",
ep&(~0x80), dat, pdsc->cval, pdsc->stat_nbyt+2*i);
pdsc->cval = dat;
}
pdsc->cval += 1;
}
}
 
pdsc->stat_nbuf += 1;
pdsc->stat_nbyt += t->actual_length;
if (t->actual_length < t->length) pdsc->stat_npt += 1;
 
if (keep_running()) que_read(ep, pdsc->par_nfrm, cb);
}
 
/*----------------------------------------------------------*/
void cb_tx1blast(struct libusb_transfer *t)
{
cb_txblast(t, 6, cb_tx1blast, &dsc_tx1);
return;
}
 
/*----------------------------------------------------------*/
void cb_tx2blast(struct libusb_transfer *t)
{
cb_txblast(t, 8, cb_tx2blast, &dsc_tx2);
return;
}
 
/*----------------------------------------------------------*/
void cb_txloop(struct libusb_transfer *t)
{
nreq -= 1;
 
if (par_trace) {
prt_time();
printf("cb_txl: ep=%d l=%5d al=%5d\n",
t->endpoint&(~0x80), t->length, t->actual_length);
}
 
bad_transfer_exit(t, "cb_txloop");
if (t->actual_length > 0) {
uint16_t* pdat = (uint16_t*)(t->buffer);
int nw = t->actual_length/2;
int i;
 
for (i = 0; i < nw; i++) {
uint16_t dat = *pdat++;
 
if (cur_nwmsg > 0) {
uint16_t dat_exp = (cur_nwmsg>1) ? dsc_tx1.cval++ : 0xdead;
if (dat_exp != dat) {
prt_time();
printf("FAIL: on ep=6 seen %4.4x expect %4.4x after %10.0f char\n",
dat, dat_exp, dsc_tx1.stat_nbyt+2*i);
if (cur_nwmsg>1) dsc_tx1.cval = dat + 1;
}
cur_nwmsg -= 1;
if (cur_nwmsg==0 && dat==0xdead) stat_nmsg += 1;
} else {
prt_time();
printf("FAIL: on ep=6 seen %4.4x unexpected after %10.0f char\n",
dat, dsc_tx1.stat_nbyt+2*i);
}
}
}
 
dsc_tx1.stat_nbuf += 1;
dsc_tx1.stat_nbyt += t->actual_length;
if (t->actual_length < t->length) dsc_tx1.stat_npt += 1;
 
if (cur_nwmsg==0) { /* end of message seen */
if (keep_running()) {
send_msg();
} else {
if (par_trace) { prt_time(); printf("set endpoll = 1\n"); }
endpoll = 1;
}
}
que_read(6, dsc_tx1.par_nfrm, cb_txloop);
 
return;
}
 
/*----------------------------------------------------------*/
void tx_pipe_drain(int ep)
{
unsigned char buf[16384];
int ntrans;
int rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80,
buf, sizeof(buf), &ntrans, 10);
if (rc == LIBUSB_ERROR_TIMEOUT) return;
if (rc) bad_usbcall_exit("pipe drain: libusb_bulk_transfer()", rc);
 
fprintf(stderr, "tst_fx2loop-I: pipe drain for ep=%d: ntrans=%d\n",
ep&(~0x80), ntrans);
 
return;
}
 
/*--------------------------------------------------------------------------*/
void do_run()
{
int rc;
int fd_timer = -1;
int i;
struct itimerspec tspec;
struct dsc_queue dsc_rx_last = dsc_rx;
struct dsc_queue dsc_tx1_last = dsc_tx1;
struct dsc_queue dsc_tx2_last = dsc_tx2;
 
if (par_trace) {
prt_time();
printf("rx:nf=%d,nq=%d; tx1:nf=%d,nq=%d; tx2:nf=%d,nq=%d\n",
dsc_rx.par_nfrm, dsc_rx.par_nque,
dsc_tx1.par_nfrm, dsc_tx2.par_nque,
dsc_tx2.par_nfrm, dsc_tx2.par_nque);
}
 
/* setup pollfd list */
fd_timer = timerfd_create(CLOCK_MONOTONIC, TFD_NONBLOCK);
if (fd_timer < 0) bad_syscall_exit("timerfd_create() failed", fd_timer);
tspec.it_interval.tv_sec = 1;
tspec.it_interval.tv_nsec = 0;
tspec.it_value.tv_sec = 1;
tspec.it_value.tv_nsec = 0;
rc = timerfd_settime(fd_timer, 0, &tspec, NULL);
if (rc<0) bad_syscall_exit("timerfd_settime() failed", rc);
pollfd_fds[0].fd = fd_timer;
pollfd_fds[0].events = POLLIN;
pollfd_fds[0].revents = 0;
pollfd_nfds = 1;
 
pollfd_init();
 
/* setup loop */
if (par_nwmsg > 0) {
dsc_rx.par_nfrm = 0;
dsc_rx.par_nque = 0;
if (dsc_tx1.par_nfrm == 0) dsc_tx1.par_nfrm = 1;
if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1;
 
tx_pipe_drain(6); /* drain tx1 */
for (i = 0; i < dsc_tx1.par_nque; i++) /* prime tx1 */
que_read(6, dsc_tx1.par_nfrm, cb_txloop);
send_msg();
}
 
/* setup rxblast */
if (dsc_rx.par_nfrm > 0) {
int i;
if (dsc_rx.par_nque == 0) dsc_rx.par_nque = 1;
for (i = 0; i < dsc_rx.par_nque; i++) que_write();
}
 
/* setup txblast */
if (par_nwmsg==0 && dsc_tx1.par_nfrm>0) {
int i;
if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1;
for (i = 0; i < dsc_tx1.par_nque; i++)
que_read(6, dsc_tx1.par_nfrm, cb_tx1blast);
}
 
/* setup tx2blast */
if (dsc_tx2.par_nfrm > 0) {
int i;
if (dsc_tx2.par_nque == 0) dsc_tx2.par_nque = 1;
for (i = 0; i < dsc_tx2.par_nque; i++)
que_read(8, dsc_tx2.par_nfrm, cb_tx2blast);
}
 
t_start = get_time();
 
while(nreq>0 && endpoll==0) {
uint64_t tbuf;
rc = poll(pollfd_fds, pollfd_nfds, 2000);
if (rc==-1 && errno==EINTR) continue;
if (rc < 0) bad_syscall_exit("poll() failed", rc);
if (rc == 0) fprintf(stderr, "tst_fx2loop-I: poll() timeout\n");
 
if (par_trace) {
int i;
prt_time();
printf("poll: rc=%d:", rc);
for (i = 0; i < pollfd_nfds; i++) {
printf(" %d,%2.2x", pollfd_fds[i].fd, pollfd_fds[i].revents);
}
printf("\n");
}
 
if (pollfd_fds[0].revents == POLLIN) {
errno = EBADMSG; /* to be reported on short read */
rc = read(fd_timer, &tbuf, sizeof(tbuf));
if (rc != sizeof(tbuf)) bad_syscall_exit("read(fd_timer,...) failed", rc);
if (par_stat) {
prt_time();
if (par_nwmsg>0 || dsc_rx.par_nque>0) {
double nbuf = dsc_rx.stat_nbuf - dsc_rx_last.stat_nbuf;
double nbyt = dsc_rx.stat_nbyt - dsc_rx_last.stat_nbyt;
printf("rx: %5.0f,%7.1f ", nbuf, nbyt/1000.);
}
if (dsc_tx1.par_nque > 0 ) {
double nbuf = dsc_tx1.stat_nbuf - dsc_tx1_last.stat_nbuf;
double nbyt = dsc_tx1.stat_nbyt - dsc_tx1_last.stat_nbyt;
printf("tx1: %5.0f,%7.1f ", nbuf, nbyt/1000.);
}
if (dsc_tx2.par_nque > 0 ) {
double nbuf = dsc_tx2.stat_nbuf - dsc_tx2_last.stat_nbuf;
double nbyt = dsc_tx2.stat_nbyt - dsc_tx2_last.stat_nbyt;
printf("tx2: %5.0f,%7.1f ", nbuf, nbyt/1000.);
}
printf("\n");
dsc_rx_last = dsc_rx;
dsc_tx1_last = dsc_tx1;
dsc_tx2_last = dsc_tx2;
}
} else {
struct timeval tv;
tv.tv_sec = 0;
tv.tv_usec = 0;
rc = libusb_handle_events_timeout(pUsbContext, &tv);
//setting the timeval pointer to NULL should work, but doesn't (in 1.0.6)
//rc = libusb_handle_events_timeout(pUsbContext, 0);
if (rc) bad_usbcall_exit("libusb_handle_events_timeout()", rc);
}
}
 
return;
}
 
/*--------------------------------------------------------------------------*/
 
void do_stat()
{
printf("run statistics:\n");
printf("runtime : %13.3f\n", get_time()-t_start);
printf("nbuf_rx : %13.0f\n", dsc_rx.stat_nbuf);
printf("nbyt_rx : %13.0f\n", dsc_rx.stat_nbyt);
printf("nbuf_tx1 : %13.0f\n", dsc_tx1.stat_nbuf);
printf("nbyt_tx1 : %13.0f\n", dsc_tx1.stat_nbyt);
printf("npt_tx1 : %13.0f\n", dsc_tx1.stat_npt);
printf("nbuf_tx2 : %13.0f\n", dsc_tx2.stat_nbuf);
printf("nbyt_tx2 : %13.0f\n", dsc_tx2.stat_nbyt);
printf("npt_tx2 : %13.0f\n", dsc_tx2.stat_npt);
printf("nmsg : %13.0f\n", stat_nmsg);
return;
}
 
/*--------------------------------------------------------------------------*/
 
void usb_claim()
{
int rc = libusb_claim_interface(pUsbDevHdl, 0);
if (rc) bad_usbcall_exit("libusb_claim_interface()", rc);
return;
}
 
/*--------------------------------------------------------------------------*/
 
void usb_release()
{
int rc = libusb_release_interface(pUsbDevHdl, 0);
if (rc) bad_usbcall_exit("libusb_release_interface()", rc);
return;
}
 
/*--------------------------------------------------------------------------*/
 
char* usb_strerror(int rc)
{
switch(rc) {
case LIBUSB_SUCCESS:
return "";
case LIBUSB_ERROR_IO:
return "Input/output error";
case LIBUSB_ERROR_INVALID_PARAM:
return "Invalid parameter";
case LIBUSB_ERROR_ACCESS:
return "Access denied";
case LIBUSB_ERROR_NO_DEVICE:
return "No such device";
case LIBUSB_ERROR_NOT_FOUND:
return "Entity not found";
case LIBUSB_ERROR_BUSY:
return "Resource busy";
case LIBUSB_ERROR_TIMEOUT:
return "Operation timed out";
case LIBUSB_ERROR_OVERFLOW:
return "Overflow";
case LIBUSB_ERROR_PIPE:
return "Pipe error";
case LIBUSB_ERROR_INTERRUPTED:
return "System call interrupted";
case LIBUSB_ERROR_NO_MEM:
return "Insufficient memory";
case LIBUSB_ERROR_NOT_SUPPORTED:
return "Operation not supported";
case LIBUSB_ERROR_OTHER:
return "Other error";
default:
return "Unknown libusb error code";
}
}
 
/*--------------------------------------------------------------------------*/
 
void prt_time(void)
{
struct timeval tv;
struct timezone tz;
struct tm tmval;
 
gettimeofday(&tv, &tz);
localtime_r(&tv.tv_sec, &tmval);
printf("%02d:%02d:%02d.%06d: ", tmval.tm_hour, tmval.tm_min, tmval.tm_sec,
(int) tv.tv_usec);
}
 
/*--------------------------------------------------------------------------*/
 
double get_time(void)
{
struct timeval tv;
struct timezone tz;
gettimeofday(&tv, &tz);
return (double)tv.tv_sec + 1.e-6 * (double)tv.tv_usec;
}
 
/*--------------------------------------------------------------------------*/
 
void bad_syscall_exit(const char* text, int rc)
{
fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d errno=%d : %s\n",
text, rc, errno, strerror(errno));
exit(EXIT_FAILURE);
}
 
/*--------------------------------------------------------------------------*/
 
void bad_usbcall_exit(const char* text, int rc)
{
fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d: %s\n",
text, rc, usb_strerror(rc));
exit(EXIT_FAILURE);
}
 
/*--------------------------------------------------------------------------*/
 
void bad_transfer_exit(struct libusb_transfer *t, const char* text)
{
const char* etext = 0;
 
if (t->status == LIBUSB_TRANSFER_ERROR) etext = "ERROR";
if (t->status == LIBUSB_TRANSFER_STALL) etext = "STALL";
if (t->status == LIBUSB_TRANSFER_NO_DEVICE) etext = "NO_DEVICE";
if (t->status == LIBUSB_TRANSFER_OVERFLOW) etext = "OVERFLOW";
 
if (etext == 0) return;
fprintf(stderr, "tst_fx2loop-F: transfer failure in %s on ep=%d: %s\n",
text, (int)(t->endpoint&(~0x80)), etext);
exit(EXIT_FAILURE);
}
 
/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd
0,0 → 1,369
-- $Id: sys_tst_fx2loop_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n3 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100
--
-- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100
--
-- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100
-- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk
-- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
 
-- ----------------------------------------------------------------------------
 
entity sys_tst_fx2loop_n3 is -- top level
-- implements nexys3_aif + fx2 pins
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n3;
 
architecture syn of sys_tst_fx2loop_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
 
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
 
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
 
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
 
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
 
begin
 
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
 
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 8, -- good for up to 255 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
 
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
 
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
 
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
 
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
 
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
 
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
 
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
 
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;
 
/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom
0,0 → 1,30
# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./as/sys_tst_fx2loop_as_n3
# ./ic/sys_tst_fx2loop_ic_n3
# ./ic3/sys_tst_fx2loop_ic3_n3
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../tst_fx2looplib.vbom
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_fx2loop_hiomap.vbom
../tst_fx2loop.vbom
../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_fx2loop_n3.vhd
## no @ucf_cpp
 
/tst_fx2loop/nexys3/ic/sys_conf.vhd
0,0 → 1,63
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk
-- 2012-04-09 461 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package sys_conf is
 
constant sys_conf_clksys_vcodivide : positive := 2;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
constant sys_conf_clksys_gentype : string := "DCM";
 
constant sys_conf_fx2_type : string := "ic2";
 
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
 
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
 
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
 
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
end package sys_conf;
/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp
0,0 → 1,48
## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints
## 2012-04-09 461 1.0 Initial version
##
 
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
 
## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
 
## constrain async pad->pad delays
TIMEGRP TG_SLOW_INS = PADS(I_RXD);
TIMEGRP TG_SLOW_OUTS = PADS(O_TXD);
TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns;
 
## FX2 controller specific constraints
## constrain cdc path in fifos and reset
TIMESPEC TS_CDC_FIFO =
FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*
*FIFO/R_REG?_rst?
*FIFO/R_REG?_rst?_s)
TO FFS(*FIFO/R_REG?_?addr_c*
*FIFO/R_REG?_rst?_c
*FIFO/R_REG?_rst?_sc)
5 ns DATAPATHONLY;
 
## constrain cdc path in monitor
TIMESPEC TS_CDC_FX2MONI = FROM FFS
TO FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY;
 
##
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## FX2 interface
##
#include "bplib/nexys3/nexys3_pins_fx2.ucf"
#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"
/tst_fx2loop/nexys3/ic/Makefile
0,0 → 1,30
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-04-09 461 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
FX2_FILE = nexys3_jtag_2fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#
/tst_fx2loop/nexys3/ic/.cvsignore
0,0 → 1,4
_impactbatch.log
sys_tst_fx2loop_ic_n3.ucf
*.dep_ucf_cpp
*.svf
/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom
0,0 → 1,8
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_fx2loop_n3.vbom
@ucf_cpp: sys_tst_fx2loop_ic_n3.ucf
@top: sys_tst_fx2loop_n3
/tst_fx2loop/nexys3/ic
tst_fx2loop/nexys3/ic Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_fx2loop_ic_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_fx2loop/nexys3/ic3/sys_conf.vhd =================================================================== --- tst_fx2loop/nexys3/ic3/sys_conf.vhd (nonexistent) +++ tst_fx2loop/nexys3/ic3/sys_conf.vhd (revision 24) @@ -0,0 +1,63 @@ +-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2012-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect +-- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk +-- 2012-04-09 461 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 2; + constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_fx2_type : string := "ic3"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom =================================================================== --- tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (nonexistent) +++ tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (revision 24) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_fx2loop_n3.vbom +@ucf_cpp: sys_tst_fx2loop_ic3_n3.ucf +@top: sys_tst_fx2loop_n3 Index: tst_fx2loop/nexys3/ic3/.cvsignore =================================================================== --- tst_fx2loop/nexys3/ic3/.cvsignore (nonexistent) +++ tst_fx2loop/nexys3/ic3/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_fx2loop_ic3_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_fx2loop/nexys3/ic3/Makefile =================================================================== --- tst_fx2loop/nexys3/ic3/Makefile (nonexistent) +++ tst_fx2loop/nexys3/ic3/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-04-09 461 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +FX2_FILE = nexys3_jtag_3fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp =================================================================== --- tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (nonexistent) +++ tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (revision 24) @@ -0,0 +1,20 @@ +## $Id: sys_tst_fx2loop_ic3_n3.ucf_cpp 461 2012-04-09 21:17:54Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2012-04-09 461 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## FX2 interface +## +#include "bplib/nexys3/nexys3_pins_fx2.ucf" +#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" Index: tst_fx2loop/nexys3/ic3 =================================================================== --- tst_fx2loop/nexys3/ic3 (nonexistent) +++ tst_fx2loop/nexys3/ic3 (revision 24)
tst_fx2loop/nexys3/ic3 Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_fx2loop_ic3_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_fx2loop/nexys3 =================================================================== --- tst_fx2loop/nexys3 (nonexistent) +++ tst_fx2loop/nexys3 (revision 24)
tst_fx2loop/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_fx2loop/tst_fx2loop.vhd =================================================================== --- tst_fx2loop/tst_fx2loop.vhd (nonexistent) +++ tst_fx2loop/tst_fx2loop.vhd (revision 24) @@ -0,0 +1,267 @@ +-- $Id: tst_fx2loop.vhd 510 2013-04-26 16:14:57Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_fx2loop - syn +-- Description: simple stand-alone tester for fx2lib components +-- +-- Dependencies: comlib/byte2word +-- comlib/word2byte +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next +-- 2012-01-15 453 1.0 Initial version +-- 2011-12-26 445 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.comlib.all; +use work.fx2lib.all; +use work.tst_fx2looplib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_fx2loop is -- tester for fx2lib components + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + HIO_CNTL : in hio_cntl_type; -- humanio controls + HIO_STAT : out hio_stat_type; -- humanio status + FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor + RXDATA : in slv8; -- receiver data out + RXVAL : in slbit; -- receiver data valid + RXHOLD : out slbit; -- receiver data hold + TXDATA : out slv8; -- transmit data in + TXENA : out slbit; -- transmit data enable + TXBUSY : in slbit; -- transmit busy + TX2DATA : out slv8; -- transmit 2 data in + TX2ENA : out slbit; -- transmit 2 data enable + TX2BUSY : in slbit -- transmit 2 busy + ); +end tst_fx2loop; + +architecture syn of tst_fx2loop is + + type regs_type is record + rxdata : slv16; -- next rx word + txdata : slv16; -- next tx word + tx2data : slv16; -- next tx2 word + rxsecnt : slv16; -- rx sequence error counter + rxcnt : slv32; -- rx word counter + txcnt : slv32; -- tx word counter + tx2cnt : slv32; -- tx2 word counter + rxthrottle : slbit; -- rx throttle flag + end record regs_type; + + constant regs_init : regs_type := ( + (others=>'0'), -- rxdata + (others=>'0'), -- txdata + (others=>'0'), -- tx2data + (others=>'0'), -- rxsecnt + (others=>'0'), -- rxcnt + (others=>'0'), -- txcnt + (others=>'0'), -- tx2cnt + '0' -- rxthrottle + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal RXWDATA : slv16 := (others=>'0'); + signal RXWVAL : slbit := '0'; + signal RXWHOLD : slbit := '0'; + signal RXODD : slbit := '0'; + + signal TXWDATA : slv16 := (others=>'0'); + signal TXWENA : slbit := '0'; + signal TXWBUSY : slbit := '0'; + signal TXODD : slbit := '0'; + signal TX2WDATA : slv16 := (others=>'0'); + signal TX2WENA : slbit := '0'; + signal TX2WBUSY : slbit := '0'; + signal TX2ODD : slbit := '0'; + + signal RXHOLD_L : slbit := '0'; -- local copy of out port signal + signal TXENA_L : slbit := '0'; -- local copy of out port signal + signal TX2ENA_L : slbit := '0'; -- local copy of out port signal + signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal + +begin + + CNTL_RESET_L <= '0'; -- so far unused + + RXB2W : byte2word + port map ( + CLK => CLK, + RESET => CNTL_RESET_L, + DI => RXDATA, + ENA => RXVAL, + BUSY => RXHOLD_L, + DO => RXWDATA, + VAL => RXWVAL, + HOLD => RXWHOLD, + ODD => RXODD + ); + + TX1W2B : word2byte + port map ( + CLK => CLK, + RESET => CNTL_RESET_L, + DI => TXWDATA, + ENA => TXWENA, + BUSY => TXWBUSY, + DO => TXDATA, + VAL => TXENA_L, + HOLD => TXBUSY, + ODD => TXODD + ); + + TX2W2B : word2byte + port map ( + CLK => CLK, + RESET => CNTL_RESET_L, + DI => TX2WDATA, + ENA => TX2WENA, + BUSY => TX2WBUSY, + DO => TX2DATA, + VAL => TX2ENA_L, + HOLD => TX2BUSY, + ODD => TX2ODD + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI, + RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY, + RXHOLD_L, TXBUSY, TX2BUSY) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irxwhold : slbit := '1'; + variable itxwena : slbit := '0'; + variable itxwdata : slv16 := (others=>'0'); + variable itx2wena : slbit := '0'; + + begin + r := R_REGS; + n := R_REGS; + + irxwhold := '1'; + itxwena := '0'; + itxwdata := RXWDATA; + itx2wena := '0'; + + if HIO_CNTL.throttle = '1' then + if CE_MSEC = '1' then + n.rxthrottle := not r.rxthrottle; + end if; + else + n.rxthrottle := '0'; + end if; + + + case HIO_CNTL.mode is + when c_mode_idle => + null; + + when c_mode_rxblast => + if RXWVAL='1' and r.rxthrottle='0' then + irxwhold := '0'; + if RXWDATA /= r.rxdata then + n.rxsecnt := slv(unsigned(r.rxsecnt) + 1); + end if; + n.rxdata := slv(unsigned(RXWDATA) + 1); + end if; + + when c_mode_txblast => + itxwdata := r.txdata; + if TXWBUSY = '0' then + itxwena := '1'; + n.txdata := slv(unsigned(r.txdata) + 1); + end if; + irxwhold := '0'; + + when c_mode_loop => + itxwdata := RXWDATA; + if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then + irxwhold := '0'; + itxwena := '1'; + end if; + + when others => null; + end case; + + if HIO_CNTL.tx2blast = '1' then + if TX2WBUSY = '0' then + itx2wena := '1'; + n.tx2data := slv(unsigned(r.tx2data) + 1); + end if; + end if; + + if RXWVAL='1' and irxwhold='0' then + n.rxcnt := slv(unsigned(r.rxcnt) + 1); + end if; + + if itxwena = '1' then + n.txcnt := slv(unsigned(r.txcnt) + 1); + end if; + + if itx2wena = '1' then + n.tx2cnt := slv(unsigned(r.tx2cnt) + 1); + end if; + + N_REGS <= n; + + RXWHOLD <= irxwhold; + TXWENA <= itxwena; + TXWDATA <= itxwdata; + TX2WENA <= itx2wena; + TX2WDATA <= r.tx2data; + + HIO_STAT.rxhold <= RXHOLD_L; + HIO_STAT.txbusy <= TXBUSY; + HIO_STAT.tx2busy <= TX2BUSY; + HIO_STAT.rxsecnt <= r.rxsecnt; + HIO_STAT.rxcnt <= r.rxcnt; + HIO_STAT.txcnt <= r.txcnt; + HIO_STAT.tx2cnt <= r.tx2cnt; + + end process proc_next; + + RXHOLD <= RXHOLD_L; + TXENA <= TXENA_L; + TX2ENA <= TX2ENA_L; + +end syn; Index: tst_fx2loop/nexys2/ic/Makefile =================================================================== --- tst_fx2loop/nexys2/ic/Makefile (nonexistent) +++ tst_fx2loop/nexys2/ic/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-01-15 453 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +FX2_FILE = nexys2_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_fx2loop/nexys2/ic/sys_conf.vhd =================================================================== --- tst_fx2loop/nexys2/ic/sys_conf.vhd (nonexistent) +++ tst_fx2loop/nexys2/ic/sys_conf.vhd (revision 24) @@ -0,0 +1,58 @@ +-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2012- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-15 453 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 2; + + constant sys_conf_fx2_type : string := "ic2"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset =================================================================== --- tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset (nonexistent) +++ tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset (revision 24) @@ -0,0 +1,63 @@ +# $Id: sys_tst_fx2loop_ic_n2.mfset 453 2012-01-15 17:51:18Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Signal is assigned but never used + +Input is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +# +# ---------------------------------------------------------------------------- +[tra] +INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP +The Offset constraint .*, is specified without a duration + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +A clock IOB / clock component pair have been found that are not placed at +The Offset constraint .*, is specified without a duration +The signal I_MEM_WAIT_IBUF has no load +The signal I_BTN<1>_IBUF has no load +The signal I_BTN<2>_IBUF has no load +The signal I_BTN<3>_IBUF has no load +There are 4 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +To achieve optimal frequency synthesis performance .* consult +The signal is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete Index: tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp =================================================================== --- tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp (nonexistent) +++ tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp (revision 24) @@ -0,0 +1,15 @@ +## $Id: sys_tst_fx2loop_ic_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-26 445 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +#include "bplib/nexys2/nexys2_pins.ucf" +#include "bplib/nexys2/nexys2_pins_fx2.ucf" +#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom =================================================================== --- tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom (nonexistent) +++ tst_fx2loop/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom (revision 24) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_fx2loop_n2.vbom +@ucf_cpp: sys_tst_fx2loop_ic_n2.ucf +@top: sys_tst_fx2loop_n2 Index: tst_fx2loop/nexys2/ic/.cvsignore =================================================================== --- tst_fx2loop/nexys2/ic/.cvsignore (nonexistent) +++ tst_fx2loop/nexys2/ic/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_fx2loop_ic_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_fx2loop/nexys2/ic =================================================================== --- tst_fx2loop/nexys2/ic (nonexistent) +++ tst_fx2loop/nexys2/ic (revision 24)
tst_fx2loop/nexys2/ic Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_fx2loop_ic_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_fx2loop/nexys2/ic3/Makefile =================================================================== --- tst_fx2loop/nexys2/ic3/Makefile (nonexistent) +++ tst_fx2loop/nexys2/ic3/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-01-15 453 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +FX2_FILE = nexys2_jtag_3fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom =================================================================== --- tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (nonexistent) +++ tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (revision 24) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_fx2loop_n2.vbom +@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf +@top: sys_tst_fx2loop_n2 Index: tst_fx2loop/nexys2/ic3/sys_conf.vhd =================================================================== --- tst_fx2loop/nexys2/ic3/sys_conf.vhd (nonexistent) +++ tst_fx2loop/nexys2/ic3/sys_conf.vhd (revision 24) @@ -0,0 +1,58 @@ +-- $Id: sys_conf.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2012- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-15 453 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 2; + + constant sys_conf_fx2_type : string := "ic3"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset =================================================================== --- tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (nonexistent) +++ tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (revision 24) @@ -0,0 +1,58 @@ +# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' + +Node of sequential type is unconnected +Node of sequential type is unconnected + +Input is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +# +# ---------------------------------------------------------------------------- +[tra] +INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP +The Offset constraint .*, is specified without a duration + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +A clock IOB / clock component pair have been found that are not placed at +The Offset constraint .*, is specified without a duration +The signal I_MEM_WAIT_IBUF has no load +The signal I_BTN<1>_IBUF has no load +The signal I_BTN<2>_IBUF has no load +The signal I_BTN<3>_IBUF has no load +There are 4 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +To achieve optimal frequency synthesis performance .* consult +The signal is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete +The signal _IBUF> is incomplete Index: tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp =================================================================== --- tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (nonexistent) +++ tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (revision 24) @@ -0,0 +1,15 @@ +## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-26 445 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +#include "bplib/nexys2/nexys2_pins.ucf" +#include "bplib/nexys2/nexys2_pins_fx2.ucf" +#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: tst_fx2loop/nexys2/ic3/.cvsignore =================================================================== --- tst_fx2loop/nexys2/ic3/.cvsignore (nonexistent) +++ tst_fx2loop/nexys2/ic3/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_fx2loop_ic3_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_fx2loop/nexys2/ic3 =================================================================== --- tst_fx2loop/nexys2/ic3 (nonexistent) +++ tst_fx2loop/nexys2/ic3 (revision 24)
tst_fx2loop/nexys2/ic3 Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_fx2loop_ic3_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd =================================================================== --- tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd (nonexistent) +++ tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd (revision 24) @@ -0,0 +1,354 @@ +-- $Id: sys_tst_fx2loop_n2.vhd 461 2012-04-09 21:17:54Z mueller $ +-- +-- Copyright 2011-2012 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_fx2loop_n2 - syn +-- Description: test of Cypress EZ-USB FX2 controller +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- vlib/genlib/clkdivce +-- bpgen/sn_humanio +-- tst_fx2loop_hiomap +-- tst_fx2loop +-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] +-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] +-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] +-- bplib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz +-- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100 +-- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100 +-- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers +-- 2011-12-26 445 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_fx2looplib.all; +use work.fx2lib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_fx2loop_n2 is -- top level + -- implements nexys2_aif + fx2 pins + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end sys_tst_fx2loop_n2; + +architecture syn of sys_tst_fx2loop_n2 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal LED_MAP : slv8 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal FX2_RXDATA : slv8 := (others=>'0'); + signal FX2_RXVAL : slbit := '0'; + signal FX2_RXHOLD : slbit := '0'; + signal FX2_RXAEMPTY : slbit := '0'; + signal FX2_TXDATA : slv8 := (others=>'0'); + signal FX2_TXENA : slbit := '0'; + signal FX2_TXBUSY : slbit := '0'; + signal FX2_TXAFULL : slbit := '0'; + signal FX2_TX2DATA : slv8 := (others=>'0'); + signal FX2_TX2ENA : slbit := '0'; + signal FX2_TX2BUSY : slbit := '1'; + signal FX2_TX2AFULL : slbit := '0'; + signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + DCM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, -- good for up to 127 MHz ! + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_fx2loop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + FX2_MONI => FX2_MONI, + SWI => SWI, + BTN => BTN, + LED => LED_MAP, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA, + FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL) + begin + + if SWI(4) = '1' then + LED(7) <= '0'; + LED(6) <= '0'; + LED(5) <= FX2_TX2BUSY; + LED(4) <= FX2_TX2ENA; + LED(3) <= FX2_TXBUSY; + LED(2) <= FX2_TXENA; + LED(1) <= FX2_RXHOLD; + LED(0) <= FX2_RXVAL; + else + LED <= LED_MAP; + end if; + + end process proc_led; + + + TST : tst_fx2loop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + FX2_MONI => FX2_MONI, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TX2DATA => FX2_TX2DATA, + TX2ENA => FX2_TX2ENA, + TX2BUSY => FX2_TX2BUSY + ); + + FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate + CNTL : fx2_2fifoctl_as + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + PETOWIDTH => sys_conf_fx2_petowidth, + RDPWLDELAY => sys_conf_fx2_rdpwldelay, + RDPWHDELAY => sys_conf_fx2_rdpwhdelay, + WRPWLDELAY => sys_conf_fx2_wrpwldelay, + WRPWHDELAY => sys_conf_fx2_wrpwhdelay, + FLAGDELAY => sys_conf_fx2_flagdelay) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_AS; + + FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate + CNTL : fx2_2fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC; + + FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate + CNTL : fx2_3fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + TX2AFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + TX2DATA => FX2_TX2DATA, + TX2ENA => FX2_TX2ENA, + TX2BUSY => FX2_TX2BUSY, + TX2AFULL => FX2_TX2AFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC3; + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + + O_TXD <= I_RXD; -- loop-back in serial port... + +end syn; + Index: tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom =================================================================== --- tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom (nonexistent) +++ tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom (revision 24) @@ -0,0 +1,30 @@ +# this is the vbom for the 'generic' top level entity +# to be referenced in the vbom's of the specific systems +# ./as/sys_tst_fx2loop_as_n2 +# ./ic/sys_tst_fx2loop_ic_n2 +# ./ic3/sys_tst_fx2loop_ic3_n2 +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_fx2looplib.vbom +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf} +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_fx2loop_hiomap.vbom +../tst_fx2loop.vbom +../../../bplib/fx2lib/fx2_2fifoctl_as.vbom +../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom +../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_fx2loop_n2.vhd +## no @ucf_cpp + Index: tst_fx2loop/nexys2 =================================================================== --- tst_fx2loop/nexys2 (nonexistent) +++ tst_fx2loop/nexys2 (revision 24)
tst_fx2loop/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_fx2loop/Makefile =================================================================== --- tst_fx2loop/Makefile (nonexistent) +++ tst_fx2loop/Makefile (revision 24) @@ -0,0 +1,40 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-01-05 470 1.2 fix LDLIBS (must come after objs) +# 2012-02-26 458 1.1 add tst_fx2loop_si +# 2011-12-26 445 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean realclean +# +all : tst_fx2loop tst_fx2loop_si +# +clean : ise_clean + rm -f tst_fx2loop + rm -f tst_fx2loop_si +# +realclean : + rm -f tst_fx2loop tst_fx2loop_si +# +CFLAGS = -Wall -O2 -g +LDLIBS = -lusb-1.0 +# +tst_fx2loop : tst_fx2loop.c + ${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS} +tst_fx2loop_si : tst_fx2loop_si.c + ${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS} +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: tst_fx2loop/tst_fx2loop_hiomap.vhd =================================================================== --- tst_fx2loop/tst_fx2loop_hiomap.vhd (nonexistent) +++ tst_fx2loop/tst_fx2loop_hiomap.vhd (revision 24) @@ -0,0 +1,194 @@ +-- $Id: tst_fx2loop_hiomap.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2011-2012 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_fx2loop_hiomap - syn +-- Description: default human I/O mapper +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage +-- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout +-- 2011-12-26 445 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- Usage of Switches, Buttons, LEDs: +-- +-- BTN(3) -- unused -- +-- (2) -- unused -- +-- (1) -- unused -- +-- (0) reset state [!! decoded by top level design !!] +-- +-- SWI(7:5) select display +-- (4) -- unused -- +-- (3) throttle +-- (2) tx2blast +-- (1:0) mode 00 idle +-- 01 rxblast +-- 10 txblast +-- 11 loop +-- +-- LED(7) MONI.fifo_ep4 +-- (6) MONI.fifo_ep6 +-- (5) MONI.fifo_ep8 +-- (4) MONI.flag_ep4_empty +-- (3) MONI.flag_ep4_almost +-- (2) MONI.flag_ep6_full +-- (1) MONI.flag_ep6_almost +-- (0) rxsecnt > 0 (sequence error) +-- +-- DSP data as selected by SWI(7:5) +-- 000 -> rxsecnt +-- 001 -> -- unused -- (display ffff) +-- 010 -> rxcnt.l +-- 011 -> rxcnt.h +-- 100 -> txcnt.l +-- 101 -> txcnt.h +-- 110 -> tx2cnt.l +-- 111 -> tx2cnt.h +-- +-- DP(3) FX2_TXBUSY (shows tx back preasure) +-- (2) FX2_MONI.slwr (shows tx activity) +-- (1) FX2_RXHOLD (shows rx back preasure) +-- (0) FX2_MONI.slrd (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.fx2lib.all; +use work.tst_fx2looplib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_fx2loop_hiomap is -- default human I/O mapper + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + HIO_CNTL : out hio_cntl_type; -- tester controls from hio + HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio + FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio + SWI : in slv8; -- switch settings + BTN : in slv4; -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end tst_fx2loop_hiomap; + +architecture syn of tst_fx2loop_hiomap is + + type regs_type is record + dspdat : slv16; -- display data + dummy : slbit; -- + end record regs_type; + + constant regs_init : regs_type := ( + (others=>'0'), -- dspdat + '0' + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable icntl : hio_cntl_type := hio_cntl_init; + variable iled : slv8 := (others=>'0'); + variable idat : slv16 := (others=>'0'); + variable idp : slv4 := (others=>'0'); + + begin + + r := R_REGS; + n := R_REGS; + + icntl := hio_cntl_init; + iled := (others=>'0'); + idat := (others=>'0'); + idp := (others=>'0'); + + -- setup tester controls + + icntl.mode := SWI(1 downto 0); + icntl.tx2blast := SWI(2); + icntl.throttle := SWI(3); + + -- setup leds + iled(7) := FX2_MONI.fifo_ep4; + iled(6) := FX2_MONI.fifo_ep6; + iled(5) := FX2_MONI.fifo_ep8; + iled(4) := FX2_MONI.flag_ep4_empty; + iled(3) := FX2_MONI.flag_ep4_almost; + iled(2) := FX2_MONI.flag_ep6_full; + iled(1) := FX2_MONI.flag_ep6_almost; + if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if; + + -- setup display data + + case SWI(7 downto 5) is + when "000" => idat := HIO_STAT.rxsecnt; + when "001" => idat := (others=>'1'); + when "010" => idat := HIO_STAT.rxcnt(15 downto 0); + when "011" => idat := HIO_STAT.rxcnt(31 downto 16); + when "100" => idat := HIO_STAT.txcnt(15 downto 0); + when "101" => idat := HIO_STAT.txcnt(31 downto 16); + when "110" => idat := HIO_STAT.tx2cnt(15 downto 0); + when "111" => idat := HIO_STAT.tx2cnt(31 downto 16); + when others => null; + end case; + n.dspdat := idat; + + -- setup display decimal points + + idp(3) := HIO_STAT.txbusy; -- tx back preasure + idp(2) := FX2_MONI.slwr; -- tx activity + idp(1) := HIO_STAT.rxhold; -- rx back preasure + idp(0) := FX2_MONI.slrd; -- rx activity + + N_REGS <= n; + + HIO_CNTL <= icntl; + LED <= iled; + DSP_DAT <= r.dspdat; + DSP_DP <= idp; + + end process proc_next; + +end syn; Index: tst_fx2loop/tst_fx2loop_hiomap.vbom =================================================================== --- tst_fx2loop/tst_fx2loop_hiomap.vbom (nonexistent) +++ tst_fx2loop/tst_fx2loop_hiomap.vbom (revision 24) @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +../../bplib/fx2lib/fx2lib.vhd +tst_fx2looplib.vbom +# components +# design +tst_fx2loop_hiomap.vhd Index: tst_fx2loop/tst_fx2loop.vbom =================================================================== --- tst_fx2loop/tst_fx2loop.vbom (nonexistent) +++ tst_fx2loop/tst_fx2loop.vbom (revision 24) @@ -0,0 +1,10 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/comlib/comlib.vhd +../../bplib/fx2lib/fx2lib.vhd +tst_fx2looplib.vhd +# components +../../vlib/comlib/byte2word.vbom +../../vlib/comlib/word2byte.vbom +# design +tst_fx2loop.vhd Index: tst_fx2loop/tst_fx2looplib.vhd =================================================================== --- tst_fx2loop/tst_fx2looplib.vhd (nonexistent) +++ tst_fx2loop/tst_fx2looplib.vhd (revision 24) @@ -0,0 +1,109 @@ +-- $Id: tst_fx2looplib.vhd 453 2012-01-15 17:51:18Z mueller $ +-- +-- Copyright 2011-2012 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: tst_fx2looplib +-- Description: Definitions for tst_fx2loop records and helpers +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat +-- 2011-12-26 445 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.fx2lib.all; + +package tst_fx2looplib is + + constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as + constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic + constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic + + constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity) + constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity) + constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx) + constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back) + + type hio_cntl_type is record -- humanio controls + mode : slv2; -- mode (idle,(tx|tx)blast,loop) + tx2blast : slbit; -- enable tx2 blast + throttle : slbit; -- enable 1 msec tx throttling + end record hio_cntl_type; + + constant hio_cntl_init : hio_cntl_type := ( + c_mode_idle, -- mode + '0','0' -- tx2blast,throttle + ); + + type hio_stat_type is record -- humanio status + rxhold : slbit; -- rx hold + txbusy : slbit; -- tx busy + tx2busy : slbit; -- tx2 busy + rxsecnt : slv16; -- rx sequence error counter + rxcnt : slv32; -- rx word counter + txcnt : slv32; -- tx word counter + tx2cnt : slv32; -- tx2 word counter + end record hio_stat_type; + + constant hio_stat_init : hio_stat_type := ( + '0','0','0', -- rxhold,txbusy,tx2busy + (others=>'0'), -- rxsecnt + (others=>'0'), -- rxcnt + (others=>'0'), -- txcnt + (others=>'0') -- tx2cnt + ); + +-- ------------------------------------- + +component tst_fx2loop is -- tester for serport components + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + HIO_CNTL : in hio_cntl_type; -- humanio controls + HIO_STAT : out hio_stat_type; -- humanio status + FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor + RXDATA : in slv8; -- receiver data out + RXVAL : in slbit; -- receiver data valid + RXHOLD : out slbit; -- receiver data hold + TXDATA : out slv8; -- transmit data in + TXENA : out slbit; -- transmit data enable + TXBUSY : in slbit; -- transmit busy + TX2DATA : out slv8; -- transmit 2 data in + TX2ENA : out slbit; -- transmit 2 data enable + TX2BUSY : in slbit -- transmit 2 busy + ); +end component; + +component tst_fx2loop_hiomap is -- default human I/O mapper + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + HIO_CNTL : out hio_cntl_type; -- tester controls from hio + HIO_STAT : in hio_stat_type; -- tester status to display by hio + FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio + SWI : in slv8; -- switch settings + BTN : in slv4; -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end component; + +end package tst_fx2looplib; Index: tst_fx2loop/tst_fx2looplib.vbom =================================================================== --- tst_fx2loop/tst_fx2looplib.vbom (nonexistent) +++ tst_fx2loop/tst_fx2looplib.vbom (revision 24) @@ -0,0 +1,4 @@ +# libs +../../vlib/slvtypes.vhd +../../bplib/fx2lib/fx2lib.vhd +tst_fx2looplib.vhd Index: tst_fx2loop/.cvsignore =================================================================== --- tst_fx2loop/.cvsignore (nonexistent) +++ tst_fx2loop/.cvsignore (revision 24) @@ -0,0 +1,2 @@ +tst_fx2loop +tst_fx2loop_si Index: tst_fx2loop =================================================================== --- tst_fx2loop (nonexistent) +++ tst_fx2loop (revision 24)
tst_fx2loop Property changes : Added: svn:ignore ## -0,0 +1,34 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tst_fx2loop +tst_fx2loop_si Index: tst_rlink/nexys3/sys_conf.vhd =================================================================== --- tst_rlink/nexys3/sys_conf.vhd (nonexistent) +++ tst_rlink/nexys3/sys_conf.vhd (revision 24) @@ -0,0 +1,53 @@ +-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2011-11-26 433 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + Index: tst_rlink/nexys3/tb/sys_conf_sim.vhd =================================================================== --- tst_rlink/nexys3/tb/sys_conf_sim.vhd (nonexistent) +++ tst_rlink/nexys3/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,49 @@ +-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2011-11-26 433 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom =================================================================== --- tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom (nonexistent) +++ tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_n3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys3_fusp_aif = sys_tst_rlink_n3_ssim.vhd +tb_tst_rlink_n3.vbom +@top:tb_tst_rlink_n3 Index: tst_rlink/nexys3/tb/Makefile =================================================================== --- tst_rlink/nexys3/tb/Makefile (nonexistent) +++ tst_rlink/nexys3/tb/Makefile (revision 24) @@ -0,0 +1,32 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-26 433 1.0 Initial version +# +EXE_all = tb_tst_rlink_n3 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_rlink_n3.ucf +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_rlink/nexys3/tb/tb_tst_rlink_n3.vbom =================================================================== --- tst_rlink/nexys3/tb/tb_tst_rlink_n3.vbom (nonexistent) +++ tst_rlink/nexys3/tb/tb_tst_rlink_n3.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_nexsy3_fusp with sys_tst_rlink_n3 target; +# use vhdl configure file (tb_tst_rlink_n3.vhd) to allow +# that all configurations will co-exist in work library +${nexys3_fusp_aif := ../sys_tst_rlink_n3.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys3/tb/tb_nexys3_fusp.vbom +tb_tst_rlink_n3.vhd Index: tst_rlink/nexys3/tb/tbw.dat =================================================================== --- tst_rlink/nexys3/tb/tbw.dat (nonexistent) +++ tst_rlink/nexys3/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 433 2011-11-27 22:04:39Z mueller $ +# +[tb_tst_rlink_n3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: tst_rlink/nexys3/tb/sys_tst_rlink_n3.ucf_cpp =================================================================== --- tst_rlink/nexys3/tb/sys_tst_rlink_n3.ucf_cpp (nonexistent) +++ tst_rlink/nexys3/tb/sys_tst_rlink_n3.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_rlink_n3.ucf_cpp \ No newline at end of file
tst_rlink/nexys3/tb/sys_tst_rlink_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_rlink/nexys3/tb/.cvsignore =================================================================== --- tst_rlink/nexys3/tb/.cvsignore (nonexistent) +++ tst_rlink/nexys3/tb/.cvsignore (revision 24) @@ -0,0 +1,7 @@ +tb_tst_rlink_n3 +tb_tst_rlink_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_n3.ucf +*.dep_ucf_cpp Index: tst_rlink/nexys3/tb/tb_tst_rlink_n3.vhd =================================================================== --- tst_rlink/nexys3/tb/tb_tst_rlink_n3.vhd (nonexistent) +++ tst_rlink/nexys3/tb/tb_tst_rlink_n3.vhd (revision 24) @@ -0,0 +1,39 @@ +-- $Id: tb_tst_rlink_n3.vhd 435 2011-12-04 20:15:25Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_n3 +-- Description: Configuration for tb_tst_rlink_n3 for tb_nexys3_fusp +-- +-- Dependencies: sys_tst_rlink_n3 +-- +-- To test: sys_tst_rlink_n3 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-xx xxx - 0.29 13.1 O40d xc6slx16-2 u:??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-26 433 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_n3 of tb_nexys3_fusp is + + for sim + for all : nexys3_fusp_aif + use entity work.sys_tst_rlink_n3; + end for; + end for; + +end tb_tst_rlink_n3; Index: tst_rlink/nexys3/tb =================================================================== --- tst_rlink/nexys3/tb (nonexistent) +++ tst_rlink/nexys3/tb (revision 24)
tst_rlink/nexys3/tb Property changes : Added: svn:ignore ## -0,0 +1,39 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_rlink_n3 +tb_tst_rlink_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_n3.ucf +*.dep_ucf_cpp Index: tst_rlink/nexys3/sys_tst_rlink_n3.vhd =================================================================== --- tst_rlink/nexys3/sys_tst_rlink_n3.vhd (nonexistent) +++ tst_rlink/nexys3/sys_tst_rlink_n3.vhd (revision 24) @@ -0,0 +1,297 @@ +-- $Id: sys_tst_rlink_n3.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_n3 - syn +-- Description: rlink tester design for nexys3 +-- +-- Dependencies: vlib/xlib/s6_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: tb/tb_tst_rlink_n3 +-- +-- Target Devices: generic +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-18 440 13.1 O40d xc6slx16-2 752 1258 48 439 t 7.9 +-- 2011-11-26 433 13.1 O40d xc6slx16-2 722 1199 36 423 t 9.7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect +-- 2011-12-18 440 1.1.1 use [rt]xok for DSP_DP +-- 2011-12-11 438 1.1 use now rbd_tst_rlink and rlink_sp1c +-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2) +------------------------------------------------------------------------------ +-- Usage of Nexys 3 Switches, Buttons, LEDs: +-- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON +-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- +-- LED(7): SER_MONI.abact +-- LED(6:2): no function (only connected to sn_humanio_rbus) +-- LED(0): timer 0 busy +-- LED(1): timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_n3 is -- top level + -- implements nexys3_fusp_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_rlink_n3; + +architecture syn of sys_tst_rlink_n3 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + + GEN_CLKSYS : s6_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + ATOWIDTH => 6, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + + DSP_DAT <= SER_MONI.abclkdiv; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + +end syn; Index: tst_rlink/nexys3/sys_tst_rlink_n3.vbom =================================================================== --- tst_rlink/nexys3/sys_tst_rlink_n3.vbom (nonexistent) +++ tst_rlink/nexys3/sys_tst_rlink_n3.vbom (revision 24) @@ -0,0 +1,24 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf.vhd} +# components +[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_rlink_n3.vhd +@ucf_cpp: sys_tst_rlink_n3.ucf Index: tst_rlink/nexys3/Makefile =================================================================== --- tst_rlink/nexys3/Makefile (nonexistent) +++ tst_rlink/nexys3/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-26 433 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_rlink/nexys3/sys_tst_rlink_n3.ucf_cpp =================================================================== --- tst_rlink/nexys3/sys_tst_rlink_n3.ucf_cpp (nonexistent) +++ tst_rlink/nexys3/sys_tst_rlink_n3.ucf_cpp (revision 24) @@ -0,0 +1,19 @@ +## $Id: sys_tst_rlink_n3.ucf_cpp 433 2011-11-27 22:04:39Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-11-26 433 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" Index: tst_rlink/nexys3/.cvsignore =================================================================== --- tst_rlink/nexys3/.cvsignore (nonexistent) +++ tst_rlink/nexys3/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink/nexys3 =================================================================== --- tst_rlink/nexys3 (nonexistent) +++ tst_rlink/nexys3 (revision 24)
tst_rlink/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink/nexys2/tb/Makefile =================================================================== --- tst_rlink/nexys2/tb/Makefile (nonexistent) +++ tst_rlink/nexys2/tb/Makefile (revision 24) @@ -0,0 +1,33 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-12-29 351 1.0 Initial version +# +EXE_all = tb_tst_rlink_n2 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_rlink_n2.ucf +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom =================================================================== --- tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom (nonexistent) +++ tst_rlink/nexys2/tb/tb_tst_rlink_n2.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_nexsy2_fusp with sys_tst_rlink_n2 target; +# use vhdl configure file (tb_tst_rlink_n2.vhd) to allow +# that all configurations will co-exist in work library +${nexys2_aif := ../sys_tst_rlink_n2.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys2/tb/tb_nexys2_fusp.vbom +tb_tst_rlink_n2.vhd Index: tst_rlink/nexys2/tb/tb_tst_rlink_n2.vhd =================================================================== --- tst_rlink/nexys2/tb/tb_tst_rlink_n2.vhd (nonexistent) +++ tst_rlink/nexys2/tb/tb_tst_rlink_n2.vhd (revision 24) @@ -0,0 +1,39 @@ +-- $Id: tb_tst_rlink_n2.vhd 437 2011-12-09 19:38:07Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_n2 +-- Description: Configuration for tb_tst_rlink_n2 for tb_nexys2_fusp +-- +-- Dependencies: sys_tst_rlink_n2 +-- +-- To test: sys_tst_rlink_n2 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2010-12-xx xxx - 0.29 12.1 M53d xc3s1200e u:??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_n2 of tb_nexys2_fusp is + + for sim + for all : nexys2_fusp_aif + use entity work.sys_tst_rlink_n2; + end for; + end for; + +end tb_tst_rlink_n2; Index: tst_rlink/nexys2/tb/tbw.dat =================================================================== --- tst_rlink/nexys2/tb/tbw.dat (nonexistent) +++ tst_rlink/nexys2/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $ +# +[tb_tst_rlink_n2] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: tst_rlink/nexys2/tb/sys_tst_rlink_n2.ucf_cpp =================================================================== --- tst_rlink/nexys2/tb/sys_tst_rlink_n2.ucf_cpp (nonexistent) +++ tst_rlink/nexys2/tb/sys_tst_rlink_n2.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_rlink_n2.ucf_cpp \ No newline at end of file
tst_rlink/nexys2/tb/sys_tst_rlink_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_rlink/nexys2/tb/tb_tst_rlink_n2_ssim.vbom =================================================================== --- tst_rlink/nexys2/tb/tb_tst_rlink_n2_ssim.vbom (nonexistent) +++ tst_rlink/nexys2/tb/tb_tst_rlink_n2_ssim.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_n2.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys2_aif = sys_tst_rlink_n2_ssim.vhd +tb_tst_rlink_n2.vbom +@top:tb_tst_rlink_n2 Index: tst_rlink/nexys2/tb/sys_conf_sim.vhd =================================================================== --- tst_rlink/nexys2/tb/sys_conf_sim.vhd (nonexistent) +++ tst_rlink/nexys2/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,45 @@ +-- $Id: sys_conf_sim.vhd 351 2010-12-30 21:50:54Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n2 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 12.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 1; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_rlink/nexys2/tb/.cvsignore =================================================================== --- tst_rlink/nexys2/tb/.cvsignore (nonexistent) +++ tst_rlink/nexys2/tb/.cvsignore (revision 24) @@ -0,0 +1,7 @@ +tb_tst_rlink_n2 +tb_tst_rlink_n2_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_n2.ucf +*.dep_ucf_cpp Index: tst_rlink/nexys2/tb =================================================================== --- tst_rlink/nexys2/tb (nonexistent) +++ tst_rlink/nexys2/tb (revision 24)
tst_rlink/nexys2/tb Property changes : Added: svn:ignore ## -0,0 +1,39 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_rlink_n2 +tb_tst_rlink_n2_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_n2.ucf +*.dep_ucf_cpp Index: tst_rlink/nexys2/sys_tst_rlink_n2.vhd =================================================================== --- tst_rlink/nexys2/sys_tst_rlink_n2.vhd (nonexistent) +++ tst_rlink/nexys2/sys_tst_rlink_n2.vhd (revision 24) @@ -0,0 +1,298 @@ +-- $Id: sys_tst_rlink_n2.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2010-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_n2 - syn +-- Description: rlink tester design for nexys2 +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: tb/tb_tst_rlink_n2 +-- +-- Target Devices: generic +-- Tool versions: xst 12.1, 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2012-12-27 453 13.3 O76d xc3s1200e-4 754 1605 96 1057 t 14.5 +-- 2011-12-18 440 13.1 O40d xc3s1200e-4 754 1605 96 1057 t 16.8 +-- 2011-06-26 385 12.1 M53d xc3s1200e-4 688 1500 68 993 t 16.2 +-- 2011-04-02 375 12.1 M53d xc3s1200e-4 688 1572 68 994 t 13.8 +-- 2010-12-29 351 12.1 M53d xc3s1200e-4 604 1298 68 851 t 14.7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.2 remove clksys output hack +-- 2011-12-18 440 1.1.6 use now rbd_tst_rlink and rlink_sp1c +-- 2011-11-26 433 1.1.5 use nx_cram_dummy now +-- 2011-11-23 432 1.1.4 update O_FLA_CE_N usage +-- 2011-11-17 426 1.1.3 use dcm_sfs now +-- 2011-07-09 391 1.1.2 use now bp_rs232_2l4l_iob +-- 2011-07-08 390 1.1.1 use now sn_humanio +-- 2011-06-26 385 1.1 move s3_humanio_rbus from tst_rlink to top level +-- 2010-12-29 351 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Nexys 2 Switches, Buttons, LEDs: +-- +-- SWI(7:2) no function (only connected to sn_humanio_rbus) +-- (1) 1 enable XON +-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- +-- LED(7) SER_MONI.abact +-- (6:2) no function (only connected to sn_humanio_rbus) +-- (0) timer 0 busy +-- (1) timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- DP(3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_n2 is -- top level + -- implements nexys2_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_rlink_n2; + +architecture syn of sys_tst_rlink_n2 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + + DCM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + ATOWIDTH => 6, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + + DSP_DAT <= SER_MONI.abclkdiv; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + +end syn; Index: tst_rlink/nexys2/sys_tst_rlink_n2.vbom =================================================================== --- tst_rlink/nexys2/sys_tst_rlink_n2.vbom (nonexistent) +++ tst_rlink/nexys2/sys_tst_rlink_n2.vbom (revision 24) @@ -0,0 +1,24 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf.vhd} +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_rlink_n2.vhd +@ucf_cpp: sys_tst_rlink_n2.ucf Index: tst_rlink/nexys2/Makefile =================================================================== --- tst_rlink/nexys2/Makefile (nonexistent) +++ tst_rlink/nexys2/Makefile (revision 24) @@ -0,0 +1,29 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-12-29 351 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_rlink/nexys2/sys_tst_rlink_n2.mfset =================================================================== --- tst_rlink/nexys2/sys_tst_rlink_n2.mfset (nonexistent) +++ tst_rlink/nexys2/sys_tst_rlink_n2.mfset (revision 24) @@ -0,0 +1,60 @@ +# $Id: sys_tst_rlink_n2.mfset 440 2011-12-18 20:08:09Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Unconnected output port 'SIZE' of component 'fifo_1c_dram' +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' +Unconnected output port 'RL_MONI' of component 'rlink_sp1c' + +Input is never used +Input > is never used +Input is never used +Input is never used + +Signal > is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used + +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +Logical network I_MEM_WAIT_IBUF has no load +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete \ No newline at end of file Index: tst_rlink/nexys2/sys_tst_rlink_n2.ucf_cpp =================================================================== --- tst_rlink/nexys2/sys_tst_rlink_n2.ucf_cpp (nonexistent) +++ tst_rlink/nexys2/sys_tst_rlink_n2.ucf_cpp (revision 24) @@ -0,0 +1,19 @@ +## $Id: sys_tst_rlink_n2.ucf_cpp 403 2011-08-06 17:36:22Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-12-29 351 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" Index: tst_rlink/nexys2/.cvsignore =================================================================== --- tst_rlink/nexys2/.cvsignore (nonexistent) +++ tst_rlink/nexys2/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink/nexys2/sys_conf.vhd =================================================================== --- tst_rlink/nexys2/sys_conf.vhd (nonexistent) +++ tst_rlink/nexys2/sys_conf.vhd (revision 24) @@ -0,0 +1,49 @@ +-- $Id: sys_conf.vhd 351 2010-12-30 21:50:54Z mueller $ +-- +-- Copyright 2010- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 12.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2010-12-29 351 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 1; -- + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + Index: tst_rlink/nexys2 =================================================================== --- tst_rlink/nexys2 (nonexistent) +++ tst_rlink/nexys2 (revision 24)
tst_rlink/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink/Makefile =================================================================== --- tst_rlink/Makefile (nonexistent) +++ tst_rlink/Makefile (revision 24) @@ -0,0 +1,26 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-11 438 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean realclean +# +all : $(NGC_all) +# +clean : ise_clean +# +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: tst_rlink/s3board/tb/Makefile =================================================================== --- tst_rlink/s3board/tb/Makefile (nonexistent) +++ tst_rlink/s3board/tb/Makefile (revision 24) @@ -0,0 +1,32 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-22 442 1.0 Initial version +# +EXE_all = tb_tst_rlink_s3 +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_rlink_s3.ucf +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_rlink/s3board/tb/tb_tst_rlink_s3.vbom =================================================================== --- tst_rlink/s3board/tb/tb_tst_rlink_s3.vbom (nonexistent) +++ tst_rlink/s3board/tb/tb_tst_rlink_s3.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_s3board_fusp with sys_tst_rlink_s3 target; +# use vhdl configure file (tb_tst_rlink_s3.vhd) to allow +# that all configurations will co-exist in work library +${s3board_aif := ../sys_tst_rlink_s3.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/s3board/tb/tb_s3board_fusp.vbom +tb_tst_rlink_s3.vhd Index: tst_rlink/s3board/tb/tbw.dat =================================================================== --- tst_rlink/s3board/tb/tbw.dat (nonexistent) +++ tst_rlink/s3board/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 442 2011-12-23 10:03:28Z mueller $ +# +[tb_tst_rlink_s3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: tst_rlink/s3board/tb/tb_tst_rlink_s3.vhd =================================================================== --- tst_rlink/s3board/tb/tb_tst_rlink_s3.vhd (nonexistent) +++ tst_rlink/s3board/tb/tb_tst_rlink_s3.vhd (revision 24) @@ -0,0 +1,39 @@ +-- $Id: tb_tst_rlink_s3.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_s3 +-- Description: Configuration for tb_tst_rlink_s3 for tb_s3board_fusp +-- +-- Dependencies: sys_tst_rlink_s3 +-- +-- To test: sys_tst_rlink_s3 +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2011-12-22 442 - 0.29 13.1 O40d xc3s1000 u:ok +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_s3 of tb_s3board_fusp is + + for sim + for all : s3board_fusp_aif + use entity work.sys_tst_rlink_s3; + end for; + end for; + +end tb_tst_rlink_s3; Index: tst_rlink/s3board/tb/sys_tst_rlink_s3.ucf_cpp =================================================================== --- tst_rlink/s3board/tb/sys_tst_rlink_s3.ucf_cpp (nonexistent) +++ tst_rlink/s3board/tb/sys_tst_rlink_s3.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_rlink_s3.ucf_cpp \ No newline at end of file
tst_rlink/s3board/tb/sys_tst_rlink_s3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_rlink/s3board/tb/sys_conf_sim.vhd =================================================================== --- tst_rlink/s3board/tb/sys_conf_sim.vhd (nonexistent) +++ tst_rlink/s3board/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,41 @@ +-- $Id: sys_conf_sim.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_s3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- derived constants + + constant sys_conf_clksys : integer := 50000000; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_rlink/s3board/tb/.cvsignore =================================================================== --- tst_rlink/s3board/tb/.cvsignore (nonexistent) +++ tst_rlink/s3board/tb/.cvsignore (revision 24) @@ -0,0 +1,7 @@ +tb_tst_rlink_s3 +tb_tst_rlink_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp Index: tst_rlink/s3board/tb =================================================================== --- tst_rlink/s3board/tb (nonexistent) +++ tst_rlink/s3board/tb (revision 24)
tst_rlink/s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,39 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_rlink_s3 +tb_tst_rlink_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp Index: tst_rlink/s3board/sys_tst_rlink_s3.vhd =================================================================== --- tst_rlink/s3board/sys_tst_rlink_s3.vhd (nonexistent) +++ tst_rlink/s3board/sys_tst_rlink_s3.vhd (revision 24) @@ -0,0 +1,263 @@ +-- $Id: sys_tst_rlink_s3.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_s3 - syn +-- Description: rlink tester design for s3board +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rlink/rlink_sp1c +-- rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- bplib/s3board/s3_sram_dummy +-- +-- Test bench: tb/tb_tst_rlink_s3 +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2) +------------------------------------------------------------------------------ +-- Usage of S3board switches, Buttons, LEDs: +-- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON +-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- +-- LED(7): SER_MONI.abact +-- LED(6:2): no function (only connected to sn_humanio_rbus) +-- LED(0): timer 0 busy +-- LED(1): timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.s3boardlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_s3 is -- top level + -- implements s3board_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_rlink_s3; + +architecture syn of sys_tst_rlink_s3 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + RESET <= '0'; -- so far not used + CLK <= I_CLK50; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + ATOWIDTH => 6, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + IFAWIDTH => 5, + OFAWIDTH => 5, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_HIO, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + SRAM : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + DSP_DAT <= SER_MONI.abclkdiv; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + +end syn; Index: tst_rlink/s3board/Makefile =================================================================== --- tst_rlink/s3board/Makefile (nonexistent) +++ tst_rlink/s3board/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-22 442 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_rlink/s3board/sys_tst_rlink_s3.vbom =================================================================== --- tst_rlink/s3board/sys_tst_rlink_s3.vbom (nonexistent) +++ tst_rlink/s3board/sys_tst_rlink_s3.vbom (revision 24) @@ -0,0 +1,21 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/s3board/s3boardlib.vbom +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../rbd_tst_rlink.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +../../../bplib/s3board/s3_sram_dummy.vbom +# design +sys_tst_rlink_s3.vhd +@ucf_cpp: sys_tst_rlink_s3.ucf Index: tst_rlink/s3board/sys_conf.vhd =================================================================== --- tst_rlink/s3board/sys_conf.vhd (nonexistent) +++ tst_rlink/s3board/sys_conf.vhd (revision 24) @@ -0,0 +1,44 @@ +-- $Id: sys_conf.vhd 442 2011-12-23 10:03:28Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_s3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-22 442 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- derived constants + + constant sys_conf_clksys : integer := 50000000; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: tst_rlink/s3board/sys_tst_rlink_s3.ucf_cpp =================================================================== --- tst_rlink/s3board/sys_tst_rlink_s3.ucf_cpp (nonexistent) +++ tst_rlink/s3board/sys_tst_rlink_s3.ucf_cpp (revision 24) @@ -0,0 +1,19 @@ +## $Id: sys_tst_rlink_s3.ucf_cpp 442 2011-12-23 10:03:28Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-22 442 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" +## +## Pmod1-RS232 on A2 connector +## +#include "bplib/s3board/s3board_a2_pm1_rs232.ucf" Index: tst_rlink/s3board/.cvsignore =================================================================== --- tst_rlink/s3board/.cvsignore (nonexistent) +++ tst_rlink/s3board/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink/s3board =================================================================== --- tst_rlink/s3board (nonexistent) +++ tst_rlink/s3board (revision 24)
tst_rlink/s3board Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_s3.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink/rbd_tst_rlink.vhd =================================================================== --- tst_rlink/rbd_tst_rlink.vhd (nonexistent) +++ tst_rlink/rbd_tst_rlink.vhd (revision 24) @@ -0,0 +1,191 @@ +-- $Id: rbd_tst_rlink.vhd 438 2011-12-11 23:40:52Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: rbd_tst_rlink - syn +-- Description: rbus device for tst_rlink +-- +-- Dependencies: rbus/rbd_tester +-- rbus/rbd_bram +-- rbus/rbd_rbmon +-- rbus/rbd_eyemon +-- rbus/rbd_timer +-- rbus/rb_sres_or_3 +-- rbus/rb_sres_or_4 +-- +-- Test bench: nexys3/tb/tb_tst_rlink_n3 +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-11 351 1.0 Initial version (derived from tst_rlink) +------------------------------------------------------------------------------ +-- Usage of STAT signal: +-- STAT(0): timer 0 busy +-- STAT(1): timer 1 busy +-- STAT(2:7): unused + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.rblib.all; +use work.rbdlib.all; + +-- ---------------------------------------------------------------------------- + +entity rbd_tst_rlink is -- rbus device for tst_rlink + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_USEC : in slbit; -- usec pulse + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + RB_LAM : out slv16; -- rbus: look at me + RB_STAT : out slv3; -- rbus: status flags + RB_SRES_TOP : in rb_sres_type; -- top-level rb_sres, for rbd_mon + RXSD : in slbit; -- serport rxsd, for rbd_emon + RXACT : in slbit; -- serport rxact, for rbd_emon + STAT : out slv8 -- status flags + + ); +end rbd_tst_rlink; + +architecture syn of rbd_tst_rlink is + + signal RB_SRES_TEST : rb_sres_type := rb_sres_init; + signal RB_SRES_BRAM : rb_sres_type := rb_sres_init; + signal RB_SRES_MON : rb_sres_type := rb_sres_init; + signal RB_SRES_EMON : rb_sres_type := rb_sres_init; + signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init; + signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init; + signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init; + + signal RB_LAM_TEST : slv16 := (others=>'0'); + + signal TIM0_DONE : slbit := '0'; + signal TIM0_BUSY : slbit := '0'; + signal TIM1_DONE : slbit := '0'; + signal TIM1_BUSY : slbit := '0'; + + constant rbaddr_mon : slv8 := "11111100"; -- 111111xx + constant rbaddr_emon : slv8 := "11111000"; -- 111110xx + constant rbaddr_bram : slv8 := "11110100"; -- 111101xx + constant rbaddr_test : slv8 := "11110000"; -- 111100xx + constant rbaddr_tim1 : slv8 := "11100001"; -- 11100001 + constant rbaddr_tim0 : slv8 := "11100000"; -- 11100000 + +begin + + TEST : rbd_tester + generic map ( + RB_ADDR => rbaddr_test) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TEST, + RB_LAM => RB_LAM_TEST, + RB_STAT => RB_STAT + ); + + BRAM : rbd_bram + generic map ( + RB_ADDR => rbaddr_bram) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_BRAM + ); + + MON : rbd_rbmon + generic map ( + RB_ADDR => rbaddr_mon, + AWIDTH => 9) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_MON, + RB_SRES_SUM => RB_SRES_TOP + ); + + EMON : rbd_eyemon + generic map ( + RB_ADDR => rbaddr_emon, + RDIV => slv(to_unsigned(0,8))) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_EMON, + RXSD => RXSD, + RXACT => RXACT + ); + + TIM0 : rbd_timer + generic map ( + RB_ADDR => rbaddr_tim0) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TIM0, + DONE => TIM0_DONE, + BUSY => TIM0_BUSY + ); + + TIM1 : rbd_timer + generic map ( + RB_ADDR => rbaddr_tim1) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TIM1, + DONE => TIM1_DONE, + BUSY => TIM1_BUSY + ); + + RB_SRES_OR1 : rb_sres_or_3 + port map ( + RB_SRES_1 => RB_SRES_TEST, + RB_SRES_2 => RB_SRES_BRAM, + RB_SRES_3 => RB_SRES_MON, + RB_SRES_OR => RB_SRES_SUM1 + ); + + RB_SRES_OR : rb_sres_or_4 + port map ( + RB_SRES_1 => RB_SRES_SUM1, + RB_SRES_2 => RB_SRES_EMON, + RB_SRES_3 => RB_SRES_TIM0, + RB_SRES_4 => RB_SRES_TIM1, + RB_SRES_OR => RB_SRES + ); + + RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2); + RB_LAM(1) <= TIM1_DONE; + RB_LAM(0) <= TIM0_DONE; + + STAT(0) <= TIM0_BUSY; + STAT(1) <= TIM1_BUSY; + STAT(7 downto 2) <= (others=>'0'); + +end syn; Index: tst_rlink/rbd_tst_rlink.vbom =================================================================== --- tst_rlink/rbd_tst_rlink.vbom (nonexistent) +++ tst_rlink/rbd_tst_rlink.vbom (revision 24) @@ -0,0 +1,14 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +../../vlib/rbus/rbdlib.vhd +# components +../../vlib/rbus/rbd_tester.vbom +../../vlib/rbus/rbd_bram.vbom +../../vlib/rbus/rbd_rbmon.vbom +../../vlib/rbus/rbd_eyemon.vbom +../../vlib/rbus/rbd_timer.vbom +../../vlib/rbus/rb_sres_or_3.vbom +../../vlib/rbus/rb_sres_or_4.vbom +# design +rbd_tst_rlink.vhd Index: tst_rlink =================================================================== --- tst_rlink (nonexistent) +++ tst_rlink (revision 24)
tst_rlink Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: w11a/nexys2/sys_w11a_n2.ucf_cpp =================================================================== --- w11a/nexys2/sys_w11a_n2.ucf_cpp (nonexistent) +++ w11a/nexys2/sys_w11a_n2.ucf_cpp (revision 24) @@ -0,0 +1,33 @@ +## $Id: sys_w11a_n2.ucf_cpp 540 2013-10-13 18:42:50Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-13 540 1.1 add pad->clk constraints +## 2013-04-20 509 1.1 add fx2 support +## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 +## 2010-05-26 295 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## constrain pad->net clock delay +NET CLK TNM = TNM_CLK; +TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK50) TO TNM_CLK 10 ns; +NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK; +TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" +## +## Cypress FX2 +## +#include "bplib/nexys2/nexys2_pins_fx2.ucf" +#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: w11a/nexys2/sys_conf.vhd =================================================================== --- w11a/nexys2/sys_conf.vhd (nonexistent) +++ w11a/nexys2/sys_conf.vhd (revision 24) @@ -0,0 +1,88 @@ +-- $Id: sys_conf.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2010-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-21 509 1.2 add fx2 settings +-- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...) +-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58) +-- 2010-05-05 295 1.0 Initial version (derived from _s3 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +-- valid system clock / delay combinations: +-- div mul clksys read0 read1 write +-- 1 1 50.0 2 2 3 +-- 25 27 54.0 3 3 3 +-- 25 29 58.0 3 3 4 + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 25; + constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz + + constant sys_conf_memctl_read0delay : positive := 3; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 4; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec + constant sys_conf_fx2_petowidth : positive := 10; + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_bram : integer := 0; -- no bram, use cache + constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + +-- constant sys_conf_bram : integer := 1; -- bram only +-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) +-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB Index: w11a/nexys2/tb/tb_w11a_n2.vbom =================================================================== --- w11a/nexys2/tb/tb_w11a_n2.vbom (nonexistent) +++ w11a/nexys2/tb/tb_w11a_n2.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_nexys2_fusp_cuff with sys_w11a_n2 target; +# use vhdl configure file (tb_w11a_n2.vhd) to allow +# that all configurations will co-exist in work library +nexys2_fusp_cuff_aif = ../sys_w11a_n2.vbom +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom +tb_w11a_n2.vhd Index: w11a/nexys2/tb/sys_conf_sim.vhd =================================================================== --- w11a/nexys2/tb/sys_conf_sim.vhd (nonexistent) +++ w11a/nexys2/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,81 @@ +-- $Id: sys_conf_sim.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2010-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n2 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-21 509 1.2 add fx2 settings +-- 2011-11-27 433 1.1.1 use /1*1 to skip dcm in sim, _ssim fails with dcm +-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58) +-- 2010-05-28 295 1.0 Initial version (cloned from _s3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim... +-- constant sys_conf_clkfx_divide : positive := 25; +-- constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz + + constant sys_conf_memctl_read0delay : positive := 3; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 4; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec + constant sys_conf_fx2_petowidth : positive := 10; + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + constant sys_conf_bram : integer := 0; -- no bram, use cache + constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + +-- constant sys_conf_bram : integer := 1; -- bram only +-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) +-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB Index: w11a/nexys2/tb/tb_w11a_n2.vhd =================================================================== --- w11a/nexys2/tb/tb_w11a_n2.vhd (nonexistent) +++ w11a/nexys2/tb/tb_w11a_n2.vhd (revision 24) @@ -0,0 +1,41 @@ +-- $Id: tb_w11a_n2.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2010-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_n2 +-- Description: Configuration for tb_w11a_n2 for tb_nexys2_fusp_cuff +-- +-- Dependencies: sys_w11a_n2 +-- +-- To test: sys_w11a_n2 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2010-05-28 295 - -.-- - - -:-- +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-21 509 1.1 now based on tb_nexys2_fusp_cuff +-- 2010-05-26 295 1.0 Initial version (cloned from _s3) +------------------------------------------------------------------------------ + +configuration tb_w11a_n2 of tb_nexys2_fusp_cuff is + + for sim + for all : nexys2_fusp_cuff_aif + use entity work.sys_w11a_n2; + end for; + end for; + +end tb_w11a_n2; Index: w11a/nexys2/tb/Makefile =================================================================== --- w11a/nexys2/tb/Makefile (nonexistent) +++ w11a/nexys2/tb/Makefile (revision 24) @@ -0,0 +1,32 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-05-26 295 1.0 Initial version +# +EXE_all = tb_w11a_n2 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: w11a/nexys2/tb/tbw.dat =================================================================== --- w11a/nexys2/tb/tbw.dat (nonexistent) +++ w11a/nexys2/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $ +# +[tb_w11a_n2] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: w11a/nexys2/tb/tb_w11a_n2_ssim.vbom =================================================================== --- w11a/nexys2/tb/tb_w11a_n2_ssim.vbom (nonexistent) +++ w11a/nexys2/tb/tb_w11a_n2_ssim.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_n2.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys2_fusp_aif = sys_w11a_n2_ssim.vhd +tb_w11a_n2.vbom +@top:tb_w11a_n2 Index: w11a/nexys2/tb/.cvsignore =================================================================== --- w11a/nexys2/tb/.cvsignore (nonexistent) +++ w11a/nexys2/tb/.cvsignore (revision 24) @@ -0,0 +1,8 @@ +tb_w11a_n2 +tb_w11a_n2_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n2.ucf +*.dep_ucf_cpp Index: w11a/nexys2/tb/sys_w11a_n2.ucf_cpp =================================================================== --- w11a/nexys2/tb/sys_w11a_n2.ucf_cpp (nonexistent) +++ w11a/nexys2/tb/sys_w11a_n2.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_w11a_n2.ucf_cpp \ No newline at end of file
w11a/nexys2/tb/sys_w11a_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: w11a/nexys2/tb =================================================================== --- w11a/nexys2/tb (nonexistent) +++ w11a/nexys2/tb (revision 24)
w11a/nexys2/tb Property changes : Added: svn:ignore ## -0,0 +1,40 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_n2 +tb_w11a_n2_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n2.ucf +*.dep_ucf_cpp Index: w11a/nexys2/sys_w11a_n2.vhd =================================================================== --- w11a/nexys2/sys_w11a_n2.vhd (nonexistent) +++ w11a/nexys2/sys_w11a_n2.vhd (revision 24) @@ -0,0 +1,658 @@ +-- $Id: sys_w11a_n2.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2010-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_n2 - syn +-- Description: w11a test design for nexys2 +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- bplib/fx2rlink/rlink_sp1c_fx2 +-- bplib/fx2rlink/ioleds_sp1c_fx2 +-- vlib/rri/rb_sres_or_3 +-- w11a/pdp11_core_rbus +-- w11a/pdp11_core +-- w11a/pdp11_bram +-- vlib/nxcramlib/nx_cram_dummy +-- w11a/pdp11_cache +-- w11a/pdp11_mem70 +-- bplib/nxcramlib/nx_cram_memctl_as +-- ibus/ib_sres_or_2 +-- ibus/ibdr_minisys +-- ibus/ibdr_maxisys +-- w11a/pdp11_tmu_sb [sim only] +-- +-- Test bench: tb/tb_sys_w11a_n2 +-- +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.26-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2013-04-20 509 13.3 O76d xc3s1200e-4 1541 4598 334 2889 ok: now + FX2 ! +-- 2011-12-18 440 13.1 O40d xc3s1200e-4 1450 4439 270 2740 ok: LP+PC+DL+II +-- 2011-11-18 427 13.1 O40d xc3s1200e-4 1433 4374 242 2680 ok: LP+PC+DL+II +-- 2010-12-30 351 12.1 M53d xc3s1200e-4 1389 4368 242 2674 ok: LP+PC+DL+II +-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II +-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II +-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II +-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II +-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II +-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II +-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II +-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II +-- " 306 10.1.02 K39 xc3s1200e-4 1309 4311 242 2665 ok: LP+PC+DL+II +-- " 306 9.2.02 J40 xc3s1200e-4 1316 4259 242 2656 ok: LP+PC+DL+II +-- " 306 9.1 J30 xc3s1200e-4 1311 4260 242 2643 ok: LP+PC+DL+II +-- " 306 8.2.03 I34 xc3s1200e-4 1371 4394 242 2765 ok: LP+PC+DL+II +-- 2010-06-13 305 11.4 L68 xc3s1200e-4 1318 4360 242 2629 ok: LP+PC+DL+II +-- 2010-06-12 304 11.4 L68 xc3s1200e-4 1323 4201 242 2574 ok: LP+PC+DL+II +-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II +-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II +-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II +-- Note: till 2010-10-24 lutm included 'route-thru', after only logic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-20 509 1.4 added fx2 (cuff) support; ATOWIDTH=7 +-- 2011-12-23 444 1.3 remove clksys output hack +-- 2011-12-18 440 1.2.7 use rlink_sp1c +-- 2011-11-26 433 1.2.6 use nx_cram_(dummy|memctl_as) now +-- 2011-11-23 432 1.2.5 update O_FLA_CE_N usage +-- 2011-11-19 427 1.2.4 now numeric_std clean +-- 2011-11-17 426 1.2.3 use dcm_sfs now +-- 2011-07-09 391 1.2.2 use now bp_rs232_2l4l_iob +-- 2011-07-08 390 1.2.1 use now sn_humanio +-- 2010-12-30 351 1.2 ported to rbv3 +-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv +-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock) +-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50 +-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM; +-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...) +-- BUGFIX: resolve rbus address clash hio<->ibr +-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn; +-- rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS; +-- remove pdp11_ibdr_rri +-- 2010-06-13 305 1.1.2 add CP_ADDR, wire up pdp11_core_rri->pdp11_core +-- 2010-06-12 304 1.1.1 re-do LED driver logic (show cpu modes or cpurust) +-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ +-- 2010-06-03 300 1.0.2 use default FAWIDTH for rri_core_serport +-- use s3_humanio_rri +-- 2010-05-30 297 1.0.1 put MEM_ACT_(R|W) on LED 6,7 +-- 2010-05-28 295 1.0 Initial version (derived from sys_w11a_s3) +------------------------------------------------------------------------------ +-- +-- w11a test design for nexys2 +-- w11a + rlink + serport + cuff +-- +-- Usage of Nexys 2 Switches, Buttons, LEDs: +-- +-- SWI(7:3): no function (only connected to sn_humanio_rbus) +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- (1): 1 enable XON +-- (0): 0 -> main board RS232 port +-- 1 -> Pmod B/top RS232 port +-- +-- LED(7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0): if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (3:0) cpurust code +-- (4) '1' +-- +-- DP(3:0) shows IO activity +-- if SWI(2)=0 (serport) +-- (3): not SER_MONI.txok (shows tx back preasure) +-- (2): SER_MONI.txact (shows tx activity) +-- (1): not SER_MONI.rxok (shows rx back preasure) +-- (0): SER_MONI.rxact (shows rx activity) +-- if SWI(2)=1 (fx2-usb) +-- (3): RB_SRES.busy (shows rbus back preasure) +-- (2): RLB_TXBUSY (shows tx back preasure) +-- (1): RLB_TXENA (shows tx activity) +-- (0): RLB_RXVAL (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.fx2lib.all; +use work.fx2rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.nxcramlib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_n2 is -- top level + -- implements nexys2_fusp_cuff_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end sys_w11a_n2; + +architecture syn of sys_w11a_n2 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal RLB_MONI : rlb_moni_type := rlb_moni_init; + signal SER_MONI : serport_moni_type := serport_moni_init; + signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_IBD : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CPU_RESET : slbit := '0'; + signal CP_CNTL : cp_cntl_type := cp_cntl_init; + signal CP_ADDR : cp_addr_type := cp_addr_init; + signal CP_DIN : slv16 := (others=>'0'); + signal CP_STAT : cp_stat_type := cp_stat_init; + signal CP_DOUT : slv16 := (others=>'0'); + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal EM_MREQ : em_mreq_type := em_mreq_init; + signal EM_SRES : em_sres_type := em_sres_init; + + signal HM_ENA : slbit := '0'; + signal MEM70_FMISS : slbit := '0'; + signal CACHE_FMISS : slbit := '0'; + signal CACHE_CHIT : slbit := '0'; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MEM_ADDR_EXT : slv22 := (others=>'0'); + + signal BRESET : slbit := '0'; + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES : ib_sres_type := ib_sres_init; + + signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; + signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; + signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + + signal DISPREG : slv16 := (others=>'0'); + + constant rbaddr_core0 : slv8 := "00000000"; + constant rbaddr_ibus : slv8 := "10000000"; + constant rbaddr_hio : slv8 := "11000000"; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + DCM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c_fx2 + generic map ( + ATOWIDTH => 7, -- 128 cycles access timeout + ITOWIDTH => 6, -- 64 periods max idle timeout + CPREF => c_rlink_cpref, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + ENAFX2 => SWI(2), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + RLB_MONI => RLB_MONI, + SER_MONI => SER_MONI, + FX2_MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + + RB_SRES_OR : rb_sres_or_3 + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_IBD, + RB_SRES_3 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + + RB2CP : pdp11_core_rbus + generic map ( + RB_ADDR_CORE => rbaddr_core0, + RB_ADDR_IBUS => rbaddr_ibus) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM(0), + CPU_RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT + ); + + CORE : pdp11_core + port map ( + CLK => CLK, + RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + BRESET => BRESET, + IB_MREQ_M => IB_MREQ, + IB_SRES_M => IB_SRES, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO + ); + + MEM_BRAM: if sys_conf_bram > 0 generate + signal HM_VAL_BRAM : slbit := '0'; + begin + + MEM : pdp11_bram + generic map ( + AWIDTH => sys_conf_bram_awidth) + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES + ); + + HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => EM_MREQ.req, + HM_VAL => HM_VAL_BRAM, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + + end generate MEM_BRAM; + + MEM_SRAM: if sys_conf_bram = 0 generate + + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) + + SRAM_CTL: nx_cram_memctl_as + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => CPU_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + + end generate MEM_SRAM; + + IB_SRES_OR : ib_sres_or_2 + port map ( + IB_SRES_1 => IB_SRES_MEM70, + IB_SRES_2 => IB_SRES_IBDR, + IB_SRES_OR => IB_SRES + ); + + IBD_MINI : if false generate + begin + IBDR_SYS : ibdr_minisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + end generate IBD_MINI; + + IBD_MAXI : if true generate + begin + IBDR_SYS : ibdr_maxisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + end generate IBD_MAXI; + + IOLEDS : ioleds_sp1c_fx2 + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => CPU_RESET, + ENAFX2 => SWI(2), + RB_SRES => RB_SRES, + RLB_MONI => RLB_MONI, + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + DSP_DAT(15 downto 0) <= DISPREG; + + proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) + variable iled : slv8 := (others=>'0'); + begin + iled := (others=>'0'); + iled(7) := MEM_ACT_W; + iled(6) := MEM_ACT_R; + iled(5) := CP_STAT.cmdbusy; + if CP_STAT.cpugo = '1' then + case DM_STAT_DP.psw.cmode is + when c_psw_kmode => + if CP_STAT.cpuwait = '1' then + iled(2) := '1'; + elsif unsigned(DM_STAT_DP.psw.pri) = 0 then + iled(3) := '1'; + else + iled(4) := '1'; + end if; + when c_psw_smode => + iled(1) := '1'; + when c_psw_umode => + iled(0) := '1'; + when others => null; + end case; + else + iled(4) := '1'; + iled(3 downto 0) := CP_STAT.cpurust; + end if; + LED <= iled; + end process; + +-- synthesis translate_off + DM_STAT_SY.emmreq <= EM_MREQ; + DM_STAT_SY.emsres <= EM_SRES; + DM_STAT_SY.chit <= CACHE_CHIT; + + TMU : pdp11_tmu_sb + generic map ( + ENAPIN => 13) + port map ( + CLK => CLK, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO, + DM_STAT_SY => DM_STAT_SY + ); +-- synthesis translate_on + +end syn; Index: w11a/nexys2/sys_w11a_n2.vbom =================================================================== --- w11a/nexys2/sys_w11a_n2.vbom (nonexistent) +++ w11a/nexys2/sys_w11a_n2.vbom (revision 24) @@ -0,0 +1,39 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/fx2rlink/fx2rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom +../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom +../../../vlib/rbus/rb_sres_or_3.vbom +../../../w11a/pdp11_core_rbus.vbom +../../../w11a/pdp11_core.vbom +../../../w11a/pdp11_bram.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +../../../w11a/pdp11_cache.vbom +../../../w11a/pdp11_mem70.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +../../../ibus/ib_sres_or_2.vbom +../../../ibus/ibdr_minisys.vbom +../../../ibus/ibdr_maxisys.vbom +[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom +# design +sys_w11a_n2.vhd +@ucf_cpp: sys_w11a_n2.ucf Index: w11a/nexys2/.cvsignore =================================================================== --- w11a/nexys2/.cvsignore (nonexistent) +++ w11a/nexys2/.cvsignore (revision 24) @@ -0,0 +1,5 @@ +sys_w11a_n2.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: w11a/nexys2/Makefile =================================================================== --- w11a/nexys2/Makefile (nonexistent) +++ w11a/nexys2/Makefile (revision 24) @@ -0,0 +1,36 @@ +# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-04-20 509 1.2 add fx2 support +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-05-28 295 1.0 Initial version (derived from _s3 version) +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +FX2_FILE = nexys2_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +sys_w11a_n2.mcs : sys_w11a_n2.bit + promgen -w -x xcf04s -p mcs -u 0 sys_w11a_n2 + mv sys_w11a_n2.prm sys_w11a_n2_prm.log + mv sys_w11a_n2.cfi sys_w11a_n2_cfi.log +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: w11a/nexys2/sys_w11a_n2.mfset =================================================================== --- w11a/nexys2/sys_w11a_n2.mfset (nonexistent) +++ w11a/nexys2/sys_w11a_n2.mfset (revision 24) @@ -0,0 +1,148 @@ +# $Id: sys_w11a_n2.mfset 427 2011-11-19 21:04:11Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded +INFO:.*You can improve the performance of the multiplier + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'RL_MONI' of component 'rlink_base_serport' +Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport' +Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as' +Unconnected output port 'OFIFO_SIZE' of component 'rlink_base' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen' + +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input > is never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used + +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used + +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +# +# ---------------------------------------------------------------------------- +[tra] +INFO:.*TNM.*used in period specification.*was traced into DCM_SP + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +Logical network I_MEM_WAIT_IBUF has no load +There is a dangling output parity pin +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete +There is a dangling output parity pin +INFO:.*To achieve optimal frequency synthesis performance \ No newline at end of file Index: w11a/nexys2 =================================================================== --- w11a/nexys2 (nonexistent) +++ w11a/nexys2 (revision 24)
w11a/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +sys_w11a_n2.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: w11a/nexys3/sys_conf.vhd =================================================================== --- w11a/nexys3/sys_conf.vhd (nonexistent) +++ w11a/nexys3/sys_conf.vhd (revision 24) @@ -0,0 +1,95 @@ +-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect +-- 2013-10-05 537 1.1.1 use 72 MHz, no closure w/ ISE 14.x for 80 anymore +-- 2013-04-21 509 1.1 add fx2 settings +-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432) +-- 2011-11-20 430 1.0 Initial version (derived from _n2 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd): +-- div mul clksys read0 read1 write +-- 2 1 50.0 2 2 3 +-- 4 3 75.0 4 4 5 (also 70 MHz) +-- 5 4 80.0 5 5 5 +-- 20 17 85.0 5 5 6 +-- 10 9 90.0 6 6 6 (also 95 MHz) +-- 1 1 100.0 6 6 7 + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 25; + constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_memctl_read0delay : positive := 4; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + + -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec + constant sys_conf_fx2_petowidth : positive := 10; + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_bram : integer := 0; -- no bram, use cache + constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + +-- constant sys_conf_bram : integer := 1; -- bram only +-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) +-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB Index: w11a/nexys3/sys_w11a_n3.ucf_cpp =================================================================== --- w11a/nexys3/sys_w11a_n3.ucf_cpp (nonexistent) +++ w11a/nexys3/sys_w11a_n3.ucf_cpp (revision 24) @@ -0,0 +1,39 @@ +## $Id: sys_w11a_n3.ucf_cpp 540 2013-10-13 18:42:50Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints +## 2013-04-21 509 1.1 add fx2 support +## 2011-11-20 430 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## constrain pad->net clock delay +NET CLK TNM = TNM_CLK; +TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns; +NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK; +TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns; + +## FX2 controller specific constraints +## constrain cdc path in fifos and reset +TIMESPEC TS_CDC_FIFO = + FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*) + TO FFS(*FIFO/R_REG?_?addr_c*) + 5 ns DATAPATHONLY; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" +## +## Cypress FX2 +## +#include "bplib/nexys3/nexys3_pins_fx2.ucf" +#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" Index: w11a/nexys3/tb/sys_conf_sim.vhd =================================================================== --- w11a/nexys3/tb/sys_conf_sim.vhd (nonexistent) +++ w11a/nexys3/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,81 @@ +-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.3 pll support, use clksys_vcodivide ect +-- 2013-04-21 509 1.2 add fx2 settings +-- 2011-11-25 432 1.0 Initial version (cloned from _n3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 25; + constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec + constant sys_conf_fx2_petowidth : positive := 10; + constant sys_conf_fx2_ccwidth : positive := 5; + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + constant sys_conf_bram : integer := 0; -- no bram, use cache + constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + +-- constant sys_conf_bram : integer := 1; -- bram only +-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) +-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB Index: w11a/nexys3/tb/tb_w11a_n3.vbom =================================================================== --- w11a/nexys3/tb/tb_w11a_n3.vbom (nonexistent) +++ w11a/nexys3/tb/tb_w11a_n3.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_nexys3_fusp with sys_w11a_n3 target; +# use vhdl configure file (tb_w11a_n3.vhd) to allow +# that all configurations will co-exist in work library +nexys3_fusp_cuff_aif = ../sys_w11a_n3.vbom +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom +tb_w11a_n3.vhd Index: w11a/nexys3/tb/tb_w11a_n3.vhd =================================================================== --- w11a/nexys3/tb/tb_w11a_n3.vhd (nonexistent) +++ w11a/nexys3/tb/tb_w11a_n3.vhd (revision 24) @@ -0,0 +1,41 @@ +-- $Id: tb_w11a_n3.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_n3 +-- Description: Configuration for tb_w11a_n3 for tb_nexys3_fusp_cuff +-- +-- Dependencies: sys_w11a_n3 +-- +-- To test: sys_w11a_n3 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-25 295 - -.-- - - -:-- +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-21 509 1.1 now based on tb_nexys3_fusp_cuff +-- 2011-11-25 432 1.0 Initial version (cloned from _n2) +------------------------------------------------------------------------------ + +configuration tb_w11a_n3 of tb_nexys3_fusp_cuff is + + for sim + for all : nexys3_fusp_cuff_aif + use entity work.sys_w11a_n3; + end for; + end for; + +end tb_w11a_n3; Index: w11a/nexys3/tb/Makefile =================================================================== --- w11a/nexys3/tb/Makefile (nonexistent) +++ w11a/nexys3/tb/Makefile (revision 24) @@ -0,0 +1,31 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-25 432 1.0 Initial version +# +EXE_all = tb_w11a_n3 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: w11a/nexys3/tb/tbw.dat =================================================================== --- w11a/nexys3/tb/tbw.dat (nonexistent) +++ w11a/nexys3/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 432 2011-11-25 20:16:28Z mueller $ +# +[tb_w11a_n3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: w11a/nexys3/tb/sys_w11a_n3.ucf_cpp =================================================================== --- w11a/nexys3/tb/sys_w11a_n3.ucf_cpp (nonexistent) +++ w11a/nexys3/tb/sys_w11a_n3.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_w11a_n3.ucf_cpp \ No newline at end of file
w11a/nexys3/tb/sys_w11a_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: w11a/nexys3/tb/tb_w11a_n3_ssim.vbom =================================================================== --- w11a/nexys3/tb/tb_w11a_n3_ssim.vbom (nonexistent) +++ w11a/nexys3/tb/tb_w11a_n3_ssim.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_n3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys3_fusp_aif = sys_w11a_n3_ssim.vhd +tb_w11a_n3.vbom +@top:tb_w11a_n3 Index: w11a/nexys3/tb/.cvsignore =================================================================== --- w11a/nexys3/tb/.cvsignore (nonexistent) +++ w11a/nexys3/tb/.cvsignore (revision 24) @@ -0,0 +1,8 @@ +tb_w11a_n3 +tb_w11a_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n3.ucf +*.dep_ucf_cpp Index: w11a/nexys3/tb =================================================================== --- w11a/nexys3/tb (nonexistent) +++ w11a/nexys3/tb (revision 24)
w11a/nexys3/tb Property changes : Added: svn:ignore ## -0,0 +1,40 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_n3 +tb_w11a_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n3.ucf +*.dep_ucf_cpp Index: w11a/nexys3/sys_w11a_n3.vhd =================================================================== --- w11a/nexys3/sys_w11a_n3.vhd (nonexistent) +++ w11a/nexys3/sys_w11a_n3.vhd (revision 24) @@ -0,0 +1,628 @@ +-- $Id: sys_w11a_n3.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_n3 - syn +-- Description: w11a test design for nexys3 +-- +-- Dependencies: vlib/xlib/s6_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- bplib/fx2rlink/rlink_sp1c_fx2 +-- bplib/fx2rlink/ioleds_sp1c_fx2 +-- vlib/rri/rb_sres_or_3 +-- w11a/pdp11_core_rbus +-- w11a/pdp11_core +-- w11a/pdp11_bram +-- vlib/nxcramlib/nx_cram_dummy +-- w11a/pdp11_cache +-- w11a/pdp11_mem70 +-- bplib/nxcramlib/nx_cram_memctl_as +-- ibus/ib_sres_or_2 +-- ibus/ibdr_minisys +-- ibus/ibdr_maxisys +-- w11a/pdp11_tmu_sb [sim only] +-- +-- Test bench: tb/tb_sys_w11a_n3 +-- +-- Target Devices: generic +-- Tool versions: xst 13.1, 14.6; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 ! +-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II +-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect +-- 2013-04-21 509 1.4 added fx2 (cuff) support +-- 2011-12-18 440 1.0.4 use rlink_sp1c +-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks) +-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now +-- 2011-11-23 432 1.0.1 fixup PPCM handling +-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2) +------------------------------------------------------------------------------ +-- +-- w11a test design for nexys3 +-- w11a + rlink + serport +-- +-- Usage of Nexys 3 Switches, Buttons, LEDs: +-- +-- SWI(7:3): no function (only connected to sn_humanio_rbus) +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- SWI(1): 1 enable XON +-- SWI(0): 0 -> main board RS232 port +-- 1 -> Pmod B/top RS232 port +-- +-- LED(7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0): if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (3:0) cpurust code +-- (4) '1' +-- +-- DP(3:0) shows IO activity +-- if SWI(2)=0 (serport) +-- (3): not SER_MONI.txok (shows tx back preasure) +-- (2): SER_MONI.txact (shows tx activity) +-- (1): not SER_MONI.rxok (shows rx back preasure) +-- (0): SER_MONI.rxact (shows rx activity) +-- if SWI(2)=1 (fx2-usb) +-- (3): RB_SRES.busy (shows rbus back preasure) +-- (2): RLB_TXBUSY (shows tx back preasure) +-- (1): RLB_TXENA (shows tx activity) +-- (0): RLB_RXVAL (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.fx2lib.all; +use work.fx2rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.nxcramlib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_n3 is -- top level + -- implements nexys3_fusp_cuff_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end sys_w11a_n3; + +architecture syn of sys_w11a_n3 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal RLB_MONI : rlb_moni_type := rlb_moni_init; + signal SER_MONI : serport_moni_type := serport_moni_init; + signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_IBD : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CPU_RESET : slbit := '0'; + signal CP_CNTL : cp_cntl_type := cp_cntl_init; + signal CP_ADDR : cp_addr_type := cp_addr_init; + signal CP_DIN : slv16 := (others=>'0'); + signal CP_STAT : cp_stat_type := cp_stat_init; + signal CP_DOUT : slv16 := (others=>'0'); + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal EM_MREQ : em_mreq_type := em_mreq_init; + signal EM_SRES : em_sres_type := em_sres_init; + + signal HM_ENA : slbit := '0'; + signal MEM70_FMISS : slbit := '0'; + signal CACHE_FMISS : slbit := '0'; + signal CACHE_CHIT : slbit := '0'; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MEM_ADDR_EXT : slv22 := (others=>'0'); + + signal BRESET : slbit := '0'; + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES : ib_sres_type := ib_sres_init; + + signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; + signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; + signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + + signal DISPREG : slv16 := (others=>'0'); + + constant rbaddr_core0 : slv8 := "00000000"; + constant rbaddr_ibus : slv8 := "10000000"; + constant rbaddr_hio : slv8 := "11000000"; + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s6_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c_fx2 + generic map ( + ATOWIDTH => 7, -- 128 cycles access timeout + ITOWIDTH => 6, -- 64 periods max idle timeout + CPREF => c_rlink_cpref, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + ENAFX2 => SWI(2), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + RLB_MONI => RLB_MONI, + SER_MONI => SER_MONI, + FX2_MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + + RB_SRES_OR : rb_sres_or_3 + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_IBD, + RB_SRES_3 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + + RB2CP : pdp11_core_rbus + generic map ( + RB_ADDR_CORE => rbaddr_core0, + RB_ADDR_IBUS => rbaddr_ibus) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM(0), + CPU_RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT + ); + + CORE : pdp11_core + port map ( + CLK => CLK, + RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + BRESET => BRESET, + IB_MREQ_M => IB_MREQ, + IB_SRES_M => IB_SRES, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO + ); + + MEM_BRAM: if sys_conf_bram > 0 generate + signal HM_VAL_BRAM : slbit := '0'; + begin + + MEM : pdp11_bram + generic map ( + AWIDTH => sys_conf_bram_awidth) + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES + ); + + HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => EM_MREQ.req, + HM_VAL => HM_VAL_BRAM, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + + end generate MEM_BRAM; + + MEM_SRAM: if sys_conf_bram = 0 generate + + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) + + SRAM_CTL: nx_cram_memctl_as + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => CPU_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + + end generate MEM_SRAM; + + IB_SRES_OR : ib_sres_or_2 + port map ( + IB_SRES_1 => IB_SRES_MEM70, + IB_SRES_2 => IB_SRES_IBDR, + IB_SRES_OR => IB_SRES + ); + + IBD_MINI : if false generate + begin + IBDR_SYS : ibdr_minisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + end generate IBD_MINI; + + IBD_MAXI : if true generate + begin + IBDR_SYS : ibdr_maxisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + end generate IBD_MAXI; + + IOLEDS : ioleds_sp1c_fx2 + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => CPU_RESET, + ENAFX2 => SWI(2), + RB_SRES => RB_SRES, + RLB_MONI => RLB_MONI, + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + DSP_DAT(15 downto 0) <= DISPREG; + + proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) + variable iled : slv8 := (others=>'0'); + begin + iled := (others=>'0'); + iled(7) := MEM_ACT_W; + iled(6) := MEM_ACT_R; + iled(5) := CP_STAT.cmdbusy; + if CP_STAT.cpugo = '1' then + case DM_STAT_DP.psw.cmode is + when c_psw_kmode => + if CP_STAT.cpuwait = '1' then + iled(2) := '1'; + elsif unsigned(DM_STAT_DP.psw.pri) = 0 then + iled(3) := '1'; + else + iled(4) := '1'; + end if; + when c_psw_smode => + iled(1) := '1'; + when c_psw_umode => + iled(0) := '1'; + when others => null; + end case; + else + iled(4) := '1'; + iled(3 downto 0) := CP_STAT.cpurust; + end if; + LED <= iled; + end process; + +-- synthesis translate_off + DM_STAT_SY.emmreq <= EM_MREQ; + DM_STAT_SY.emsres <= EM_SRES; + DM_STAT_SY.chit <= CACHE_CHIT; + + TMU : pdp11_tmu_sb + generic map ( + ENAPIN => 13) + port map ( + CLK => CLK, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO, + DM_STAT_SY => DM_STAT_SY + ); +-- synthesis translate_on + +end syn; Index: w11a/nexys3/sys_w11a_n3.vbom =================================================================== --- w11a/nexys3/sys_w11a_n3.vbom (nonexistent) +++ w11a/nexys3/sys_w11a_n3.vbom (revision 24) @@ -0,0 +1,39 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/fx2rlink/fx2rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom +../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom +../../../vlib/rbus/rb_sres_or_3.vbom +../../../w11a/pdp11_core_rbus.vbom +../../../w11a/pdp11_core.vbom +../../../w11a/pdp11_bram.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +../../../w11a/pdp11_cache.vbom +../../../w11a/pdp11_mem70.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +../../../ibus/ib_sres_or_2.vbom +../../../ibus/ibdr_minisys.vbom +../../../ibus/ibdr_maxisys.vbom +[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom +# design +sys_w11a_n3.vhd +@ucf_cpp: sys_w11a_n3.ucf Index: w11a/nexys3/.cvsignore =================================================================== --- w11a/nexys3/.cvsignore (nonexistent) +++ w11a/nexys3/.cvsignore (revision 24) @@ -0,0 +1,5 @@ +sys_w11a_n3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: w11a/nexys3/Makefile =================================================================== --- w11a/nexys3/Makefile (nonexistent) +++ w11a/nexys3/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 509 2013-04-21 20:46:20Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-04-20 509 1.2 add fx2 support +# 2011-11-20 430 1.0 Initial version (derived from _n2 version) +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +FX2_FILE = nexys3_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: w11a/nexys3/sys_w11a_n3.mfset =================================================================== --- w11a/nexys3/sys_w11a_n3.mfset (nonexistent) +++ w11a/nexys3/sys_w11a_n3.mfset (revision 24) @@ -0,0 +1,35 @@ +# $Id: sys_w11a_n3.mfset 440 2011-12-18 20:08:09Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Case statement is complete. others clause is never selected +INFO:.*The small RAM <.*> will be implemented on LUTs + +sys_w11a_n3\..*Output port of the instance is unconnected +sys_w11a_n3\..*Output port of the instance is unconnected +sys_w11a_n3\..*Output port of the instance is unconnected +sys_w11a_n3\..*Output port of the instance is unconnected +# +# ---------------------------------------------------------------------------- +[tra] +INFO:.*TNM 'I_CLK100'.*was traced into DCM_SP +INFO:.*Setting CLKIN_PERIOD attribute associated with DCM instance +# +# ---------------------------------------------------------------------------- +[map] +WARNING:.*has the attribute CLK_FEEDBACK set to NONE +WARNING:.*The signal is incomplete +WARNING:.*to use input parity pin.*dangling output for parity pin +INFO:.* +# +# ---------------------------------------------------------------------------- +[par] +WARNING:.*has the attribute CLK_FEEDBACK set to NONE +WARNING:.*The signal I_MEM_WAIT_IBUF has no load +WARNING:.*There are 1 loadless signals in this design +# +# ---------------------------------------------------------------------------- +[bgn] +WARNING:.*The signal is incomplete +WARNING:.*to use input parity pin.*dangling output for parity pin +INFO:.*To achieve optimal frequency synthesis performance Index: w11a/nexys3 =================================================================== --- w11a/nexys3 (nonexistent) +++ w11a/nexys3 (revision 24)
w11a/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +sys_w11a_n3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: w11a/tb/.cvsignore =================================================================== --- w11a/tb/.cvsignore (nonexistent) +++ w11a/tb/.cvsignore (revision 24) @@ -0,0 +1,14 @@ +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +to_ptp +to_lda +tmu_ofile +*.dsk +*.log +*.log.gz +*.lst +*.lda +lpt.dat +ptp.dat +*.LOG Index: w11a/tb =================================================================== --- w11a/tb (nonexistent) +++ w11a/tb (revision 24)
w11a/tb Property changes : Added: svn:ignore ## -0,0 +1,46 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +to_ptp +to_lda +tmu_ofile +*.dsk +*.log +*.log.gz +*.lst +*.lda +lpt.dat +ptp.dat +*.LOG Index: w11a/s3board/.cvsignore =================================================================== --- w11a/s3board/.cvsignore (nonexistent) +++ w11a/s3board/.cvsignore (revision 24) @@ -0,0 +1,5 @@ +sys_w11a_s3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: w11a/s3board/tb/Makefile =================================================================== --- w11a/s3board/tb/Makefile (nonexistent) +++ w11a/s3board/tb/Makefile (revision 24) @@ -0,0 +1,34 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.3 use includes from rtl/make +# 2010-05-26 295 1.2 rename tb_s3board_pdp11core -> tb_w11a_s3 +# 2007-11-26 98 1.1 add all_ssim and all_tsim targets +# 2007-09-23 84 1.0 Initial version +# +EXE_all = tb_w11a_s3 +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: w11a/s3board/tb/tb_w11a_s3_ssim.vbom =================================================================== --- w11a/s3board/tb/tb_w11a_s3_ssim.vbom (nonexistent) +++ w11a/s3board/tb/tb_w11a_s3_ssim.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_s3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +s3board_fusp_aif = sys_w11a_s3_ssim.vhd +tb_w11a_s3.vbom +@top:tb_w11a_s3 Index: w11a/s3board/tb/tbw.dat =================================================================== --- w11a/s3board/tb/tbw.dat (nonexistent) +++ w11a/s3board/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $ +# +[tb_w11a_s3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: w11a/s3board/tb/.cvsignore =================================================================== --- w11a/s3board/tb/.cvsignore (nonexistent) +++ w11a/s3board/tb/.cvsignore (revision 24) @@ -0,0 +1,8 @@ +tb_w11a_s3 +tb_w11a_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_s3.ucf +*.dep_ucf_cpp Index: w11a/s3board/tb/tb_w11a_s3.vhd =================================================================== --- w11a/s3board/tb/tb_w11a_s3.vhd (nonexistent) +++ w11a/s3board/tb/tb_w11a_s3.vhd (revision 24) @@ -0,0 +1,49 @@ +-- $Id: tb_w11a_s3.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_s3 +-- Description: Configuration for tb_w11a_s3 for tb_s3board_fusp +-- +-- Dependencies: sys_w11a_s3 +-- +-- To test: sys_w11a_s3 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#2) 91497s; 632m +-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#1) 3356s; 632m +-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#2) 2227s +-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#1) 82s +-- 2007-10-21 91 - 0.26 - - d:ok (#2) +-- 2007-10-19 90 - 0.26 - - d:ok (#2) +-- 2007-10-19 90 - 0.26 - - d:ok (#1) +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-05-26 295 1.1.2 rename tb_s3board_pdp11core -> tb_w11a_s3 +-- 2010-05-16 291 1.1.1 use now tb_s3board_fusp +-- 2010-05-02 287 1.1 use now tb_s3board_usp +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_w11a_s3 of tb_s3board_fusp is + + for sim + for all : s3board_fusp_aif + use entity work.sys_w11a_s3; + end for; + end for; + +end tb_w11a_s3; Index: w11a/s3board/tb/tb_w11a_s3.vbom =================================================================== --- w11a/s3board/tb/tb_w11a_s3.vbom (nonexistent) +++ w11a/s3board/tb/tb_w11a_s3.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_s3board_fusp with sys_w11a_s3 target; +# use vhdl configure file (tb_w11a_s3.vhd) to allow +# that all configurations will co-exist in work library +s3board_fusp_aif = ../sys_w11a_s3.vbom +sys_conf = sys_conf_sim.vhd +../../../../bplib/s3board/tb/tb_s3board_fusp.vbom +tb_w11a_s3.vhd Index: w11a/s3board/tb/sys_w11a_s3.ucf_cpp =================================================================== --- w11a/s3board/tb/sys_w11a_s3.ucf_cpp (nonexistent) +++ w11a/s3board/tb/sys_w11a_s3.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_w11a_s3.ucf_cpp \ No newline at end of file
w11a/s3board/tb/sys_w11a_s3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: w11a/s3board/tb/sys_conf_sim.vhd =================================================================== --- w11a/s3board/tb/sys_conf_sim.vhd (nonexistent) +++ w11a/s3board/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,60 @@ +-- $Id: sys_conf_sim.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007-2008 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_s3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce +-- 2008-02-23 118 1.1 add memory config +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_bram : integer := 0; -- no bram, use cache + constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + +-- constant sys_conf_bram : integer := 1; -- bram only +-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) +-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB Index: w11a/s3board/tb =================================================================== --- w11a/s3board/tb (nonexistent) +++ w11a/s3board/tb (revision 24)
w11a/s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,40 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_s3 +tb_w11a_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_s3.ucf +*.dep_ucf_cpp Index: w11a/s3board/sys_w11a_s3.vhd =================================================================== --- w11a/s3board/sys_w11a_s3.vhd (nonexistent) +++ w11a/s3board/sys_w11a_s3.vhd (revision 24) @@ -0,0 +1,595 @@ +-- $Id: sys_w11a_s3.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_s3 - syn +-- Description: w11a test design for s3board +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio +-- vlib/rlink/rlink_sp1c +-- vlib/rbus/rb_sres_or_2 +-- w11a/pdp11_core_rbus +-- w11a/pdp11_core +-- w11a/pdp11_bram +-- vlib/s3board/s3_sram_dummy +-- w11a/pdp11_cache +-- w11a/pdp11_mem70 +-- bplib/s3board/s3_sram_memctl +-- ibus/ib_sres_or_2 +-- ibus/ibdr_minisys +-- ibus/ibdr_maxisys +-- w11a/pdp11_tmu_sb [sim only] +-- +-- Test bench: tb/tb_sys_w11a_s3 +-- +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1, 13.1; ghdl 0.18-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II +-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II +-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II +-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II +-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II +-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II +-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II +-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II +-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II +-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II +-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK +-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK +-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK +-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK +-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK +-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK +-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK +-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK +-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32 +-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16 +-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK +-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16 +-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK +-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK +-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL +-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK +-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK +-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK +-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8 +-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK +-- Note: till 2010-10-24 lutm included 'route-thru', after only logic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3 +-- 2011-11-19 427 1.4.3 now numeric_std clean +-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob +-- 2011-07-08 390 1.4.1 use now sn_humanio +-- 2010-12-30 351 1.4 ported to rbv3 +-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50 +-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM; +-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...) +-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS; +-- remove pdp11_ibdr_rri +-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core +-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ +-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport +-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3 +-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_ +-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl +-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce +-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT from interfaces; drop RTSFLUSH generic +-- add pm1 rs232 (usp) support +-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport +-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy +-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3) +-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes +-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys +-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu +-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames +-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust +-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg) +-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu +-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys +-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs +-- 2008-02-23 118 1.3.1 add _mem70 +-- 2008-02-17 117 1.3 use ext. memory interface of _core; +-- use _cache + memctl or _bram (configurable) +-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05) +-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET +-- add _ib_mux2 +-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack +-- instanciate all parts directly +-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb +-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO +-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them +-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- w11a test design for s3board +-- w11a + rlink + serport +-- +-- Usage of S3BOARD Switches, Buttons, LEDs: +-- +-- SWI(7:2): no function (only connected to sn_humanio_rbus) +-- SWI(1): 1 enable XON +-- SWI(0): 0 -> main board RS232 port +-- 1 -> Pmod B/top RS232 port +-- +-- LED(7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0): if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (3:0) cpurust code +-- (4) '1' +-- +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.s3boardlib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_s3 is -- top level + -- implements s3board_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_w11a_s3; + +architecture syn of sys_w11a_s3 is + + signal CLK : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_IBD : rb_sres_type := rb_sres_init; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CPU_RESET : slbit := '0'; + signal CP_CNTL : cp_cntl_type := cp_cntl_init; + signal CP_ADDR : cp_addr_type := cp_addr_init; + signal CP_DIN : slv16 := (others=>'0'); + signal CP_STAT : cp_stat_type := cp_stat_init; + signal CP_DOUT : slv16 := (others=>'0'); + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal EM_MREQ : em_mreq_type := em_mreq_init; + signal EM_SRES : em_sres_type := em_sres_init; + + signal HM_ENA : slbit := '0'; + signal MEM70_FMISS : slbit := '0'; + signal CACHE_FMISS : slbit := '0'; + signal CACHE_CHIT : slbit := '0'; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal BRESET : slbit := '0'; + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES : ib_sres_type := ib_sres_init; + + signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; + signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; + signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; + + signal DISPREG : slv16 := (others=>'0'); + + constant rbaddr_core0 : slv8 := "00000000"; + constant rbaddr_ibus : slv8 := "10000000"; + constant rbaddr_hio : slv8 := "11000000"; + +begin + + CLK <= I_CLK50; -- use 50MHz as system clock + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => 50, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RLINK : rlink_sp1c + generic map ( + ATOWIDTH => 6, -- 64 cycles access timeout + ITOWIDTH => 6, -- 64 periods max idle timeout + CPREF => c_rlink_cpref, + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + RB_SRES_OR : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_IBD, + RB_SRES_OR => RB_SRES + ); + + RP2CP : pdp11_core_rbus + generic map ( + RB_ADDR_CORE => rbaddr_core0, + RB_ADDR_IBUS => rbaddr_ibus) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM => RB_LAM(0), + CPU_RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT + ); + + CORE : pdp11_core + port map ( + CLK => CLK, + RESET => CPU_RESET, + CP_CNTL => CP_CNTL, + CP_ADDR => CP_ADDR, + CP_DIN => CP_DIN, + CP_STAT => CP_STAT, + CP_DOUT => CP_DOUT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + BRESET => BRESET, + IB_MREQ_M => IB_MREQ, + IB_SRES_M => IB_SRES, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO + ); + + MEM_BRAM: if sys_conf_bram > 0 generate + signal HM_VAL_BRAM : slbit := '0'; + begin + + MEM : pdp11_bram + generic map ( + AWIDTH => sys_conf_bram_awidth) + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES + ); + + HM_VAL_BRAM <= not EM_MREQ.we; -- assume hit if read, miss if write + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => EM_MREQ.req, + HM_VAL => HM_VAL_BRAM, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + end generate MEM_BRAM; + + MEM_SRAM: if sys_conf_bram = 0 generate + + CACHE: pdp11_cache + port map ( + CLK => CLK, + GRESET => CPU_RESET, + EM_MREQ => EM_MREQ, + EM_SRES => EM_SRES, + FMISS => CACHE_FMISS, + CHIT => CACHE_CHIT, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO + ); + + MEM70: pdp11_mem70 + port map ( + CLK => CLK, + CRESET => BRESET, + HM_ENA => HM_ENA, + HM_VAL => CACHE_CHIT, + CACHE_FMISS => MEM70_FMISS, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_MEM70 + ); + + HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w; + CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss; + + SRAM_CTL: s3_sram_memctl + port map ( + CLK => CLK, + RESET => CPU_RESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR(17 downto 0), + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + end generate MEM_SRAM; + + IB_SRES_OR : ib_sres_or_2 + port map ( + IB_SRES_1 => IB_SRES_MEM70, + IB_SRES_2 => IB_SRES_IBDR, + IB_SRES_OR => IB_SRES); + + IBD_MINI : if false generate + begin + IBDR_SYS : ibdr_minisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG); + end generate IBD_MINI; + + IBD_MAXI : if true generate + begin + IBDR_SYS : ibdr_maxisys + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => CPU_RESET, + BRESET => BRESET, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG); + end generate IBD_MAXI; + + DSP_DAT(15 downto 0) <= DISPREG; + + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + + proc_led: process (MEM_ACT_W, MEM_ACT_R, CP_STAT, DM_STAT_DP.psw) + variable iled : slv8 := (others=>'0'); + begin + iled := (others=>'0'); + iled(7) := MEM_ACT_W; + iled(6) := MEM_ACT_R; + iled(5) := CP_STAT.cmdbusy; + if CP_STAT.cpugo = '1' then + case DM_STAT_DP.psw.cmode is + when c_psw_kmode => + if CP_STAT.cpuwait = '1' then + iled(2) := '1'; + elsif unsigned(DM_STAT_DP.psw.pri) = 0 then + iled(3) := '1'; + else + iled(4) := '1'; + end if; + when c_psw_smode => + iled(1) := '1'; + when c_psw_umode => + iled(0) := '1'; + when others => null; + end case; + else + iled(4) := '1'; + iled(3 downto 0) := CP_STAT.cpurust; + end if; + LED <= iled; + end process; + +-- synthesis translate_off + DM_STAT_SY.emmreq <= EM_MREQ; + DM_STAT_SY.emsres <= EM_SRES; + DM_STAT_SY.chit <= CACHE_CHIT; + + TMU : pdp11_tmu_sb + generic map ( + ENAPIN => 13) + port map ( + CLK => CLK, + DM_STAT_DP => DM_STAT_DP, + DM_STAT_VM => DM_STAT_VM, + DM_STAT_CO => DM_STAT_CO, + DM_STAT_SY => DM_STAT_SY + ); +-- synthesis translate_on + +end syn; Index: w11a/s3board/Makefile =================================================================== --- w11a/s3board/Makefile (nonexistent) +++ w11a/s3board/Makefile (revision 24) @@ -0,0 +1,39 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.2 use includes from rtl/make +# 2010-05-28 295 1.1.4 rename sys_pdp11core -> sys_w11a_s3 +# 2010-04-24 282 1.1.3 use %.impact rule, all=BIT_all now +# 2009-11-20 251 1.1.2 add .mcs rule +# 2009-07-26 236 1.1.1 add program: rule +# 2007-11-26 98 1.1 include $(RETROBASE)/vlib/Makefile.(ghdl|xflow) +# 2007-07-08 65 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +sys_w11a_s3.mcs : sys_w11a_s3.bit + promgen -w -x xcf04s -p mcs -u 0 sys_w11a_s3 + mv sys_w11a_s3.prm sys_w11a_s3_prm.log + mv sys_w11a_s3.cfi sys_w11a_s3_cfi.log +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: w11a/s3board/sys_w11a_s3.vbom =================================================================== --- w11a/s3board/sys_w11a_s3.vbom (nonexistent) +++ w11a/s3board/sys_w11a_s3.vbom (revision 24) @@ -0,0 +1,32 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/s3board/s3boardlib.vbom +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +../../../w11a/pdp11_core_rbus.vbom +../../../w11a/pdp11_core.vbom +../../../w11a/pdp11_bram.vbom +../../../bplib/s3board/s3_sram_dummy.vbom +../../../w11a/pdp11_cache.vbom +../../../w11a/pdp11_mem70.vbom +../../../bplib/s3board/s3_sram_memctl.vbom +../../../ibus/ib_sres_or_2.vbom +../../../ibus/ibdr_minisys.vbom +../../../ibus/ibdr_maxisys.vbom +[ghdl,isim]../../../w11a/pdp11_tmu_sb.vbom +# design +sys_w11a_s3.vhd +@ucf_cpp: sys_w11a_s3.ucf Index: w11a/s3board/sys_w11a_s3.mfset =================================================================== --- w11a/s3board/sys_w11a_s3.mfset (nonexistent) +++ w11a/s3board/sys_w11a_s3.mfset (revision 24) @@ -0,0 +1,120 @@ +# $Id: sys_w11a_s3.mfset 442 2011-12-23 10:03:28Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen' +Unconnected output port 'ACK_W' of component 's3_sram_memctl' + +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input is never used +Input > is never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used + +Signal > is assigned but never used + +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +There is a dangling output parity pin +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] +There is a dangling output parity pin Index: w11a/s3board/sys_w11a_s3.ucf_cpp =================================================================== --- w11a/s3board/sys_w11a_s3.ucf_cpp (nonexistent) +++ w11a/s3board/sys_w11a_s3.ucf_cpp (revision 24) @@ -0,0 +1,22 @@ +## $Id: sys_w11a_s3.ucf_cpp 336 2010-11-06 18:28:27Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-11-06 336 2.0.1 rename input pin CLK -> I_CLK50 +## 2010-05-02 287 2.0 added defs for pm1 rs232 +## 2007-12-16 101 1.1 converted to ucf_cpp, factor out std pins +## 2007-12-09 100 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" +## +## Pmod1-RS232 on A2 connector +## +#include "bplib/s3board/s3board_a2_pm1_rs232.ucf" Index: w11a/s3board/sys_conf.vhd =================================================================== --- w11a/s3board/sys_conf.vhd (nonexistent) +++ w11a/s3board/sys_conf.vhd (revision 24) @@ -0,0 +1,60 @@ +-- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007-2008 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_s3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25 +-- Revision History: +-- Date Rev Version Comment +-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce +-- 2008-02-23 118 1.1 add memory config +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200 + + constant sys_conf_bram : integer := 0; -- no bram, use cache + constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + +-- constant sys_conf_bram : integer := 1; -- bram only +-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB) +-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + +end package sys_conf; + +-- Note: mem_losize holds 16 MSB of the PA of the addressable memory +-- 2 211 111 111 110 000 000 000 +-- 1 098 765 432 109 876 543 210 +-- +-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte +-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte +-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte +-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte +-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte +-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte +-- upper 256 kB excluded for 11/70 UB Index: w11a/s3board =================================================================== --- w11a/s3board (nonexistent) +++ w11a/s3board (revision 24)
w11a/s3board Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +sys_w11a_s3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: w11a =================================================================== --- w11a (nonexistent) +++ w11a (revision 24)
w11a Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd =================================================================== --- tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd (nonexistent) +++ tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd (revision 24) @@ -0,0 +1,388 @@ +-- $Id: sys_tst_rlink_cuff_n3.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_cuff_n3 - syn +-- Description: rlink tester design for nexys3 with fx2 interface +-- +-- Dependencies: vlib/xlib/s6_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] +-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] +-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] +-- tst_rlink_cuff +-- bplib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3, 14.6; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz +-- 2013-01-04 469 13.3 O76d xc6slx16-2 ??? ???? ??? ???? p ??.? ic2/ 50 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_rlink_cuff_n2 +-- and sys_tst_fx2loop_n3 +------------------------------------------------------------------------------ +-- Usage of Nexys 3 Switches, Buttons, LEDs: +-- +-- SWI(7:3) no function (only connected to sn_humanio_rbus) +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- (1) 1 enable XON +-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- +-- LED(7) SER_MONI.abact +-- (6:2) no function (only connected to sn_humanio_rbus) +-- (0) timer 0 busy +-- (1) timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- for SWI(2)='0' (serport) +-- DP(3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- for SWI(2)='1' (fx2) +-- DP(3) FX2_TX2BUSY (shows tx2 back preasure) +-- (2) FX2_TX2ENA(stretched) (shows tx2 activity) +-- (1) FX2_TXENA(streched) (shows tx activity) +-- (0) FX2_RXVAL(stretched) (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.rblib.all; +use work.fx2lib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_cuff_n3 is -- top level + -- implements nexys3_fusp_cuff_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end sys_tst_rlink_cuff_n3; + +architecture syn of sys_tst_rlink_cuff_n3 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXSD : slbit := '0'; + signal TXSD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal FX2_RXDATA : slv8 := (others=>'0'); + signal FX2_RXVAL : slbit := '0'; + signal FX2_RXHOLD : slbit := '0'; + signal FX2_RXAEMPTY : slbit := '0'; + signal FX2_TXDATA : slv8 := (others=>'0'); + signal FX2_TXENA : slbit := '0'; + signal FX2_TXBUSY : slbit := '0'; + signal FX2_TXAFULL : slbit := '0'; + signal FX2_TX2DATA : slv8 := (others=>'0'); + signal FX2_TX2ENA : slbit := '0'; + signal FX2_TX2BUSY : slbit := '0'; + signal FX2_TX2AFULL : slbit := '0'; + signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s6_cmt_sfs + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, -- good for up to 127 MHz ! + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXSD, + TXD => TXSD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate + CNTL : fx2_2fifoctl_as + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + PETOWIDTH => sys_conf_fx2_petowidth, + RDPWLDELAY => sys_conf_fx2_rdpwldelay, + RDPWHDELAY => sys_conf_fx2_rdpwhdelay, + WRPWLDELAY => sys_conf_fx2_wrpwldelay, + WRPWHDELAY => sys_conf_fx2_wrpwhdelay, + FLAGDELAY => sys_conf_fx2_flagdelay) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_AS; + + FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate + CNTL : fx2_2fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC; + + FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate + CNTL : fx2_3fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + TX2AFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + TX2DATA => FX2_TX2DATA, + TX2ENA => FX2_TX2ENA, + TX2BUSY => FX2_TX2BUSY, + TX2AFULL => FX2_TX2AFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC3; + + TST : entity work.tst_rlink_cuff + port map ( + CLK => CLK, + RESET => '0', + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RB_MREQ_TOP => RB_MREQ, + RB_SRES_TOP => RB_SRES_HIO, + SWI => SWI, + BTN => BTN(3 downto 0), + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + RXSD => RXSD, + TXSD => TXSD, + RTS_N => RTS_N, + CTS_N => CTS_N, + FX2_RXDATA => FX2_RXDATA, + FX2_RXVAL => FX2_RXVAL, + FX2_RXHOLD => FX2_RXHOLD, + FX2_TXDATA => FX2_TXDATA, + FX2_TXENA => FX2_TXENA, + FX2_TXBUSY => FX2_TXBUSY, + FX2_TX2DATA => FX2_TX2DATA, + FX2_TX2ENA => FX2_TX2ENA, + FX2_TX2BUSY => FX2_TX2BUSY, + FX2_MONI => FX2_MONI + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + +end syn; + Index: tst_rlink_cuff/nexys3/ic/sys_conf.vhd =================================================================== --- tst_rlink_cuff/nexys3/ic/sys_conf.vhd (nonexistent) +++ tst_rlink_cuff/nexys3/ic/sys_conf.vhd (revision 24) @@ -0,0 +1,66 @@ +-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3, 14.6; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2013-01-04 469 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_fx2_type : string := "ic2"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + -- derived constants + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: tst_rlink_cuff/nexys3/ic/tb/tbw.dat =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/tbw.dat (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 538 2013-10-06 17:21:25Z mueller $ +# +[tb_tst_rlink_cuff_ic_n3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,64 @@ +-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.3, 14.6; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect +-- 2013-04-27 512 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + constant sys_conf_fx2_type : string := "ic2"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_fx2_ccwidth : positive := 5; + + -- derived constants + + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_rlink_cuff/nexys3/ic/tb/sys_tst_rlink_cuff_ic_n3.ucf_cpp =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/sys_tst_rlink_cuff_ic_n3.ucf_cpp (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/sys_tst_rlink_cuff_ic_n3.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_rlink_cuff_ic_n3.ucf_cpp \ No newline at end of file
tst_rlink_cuff/nexys3/ic/tb/sys_tst_rlink_cuff_ic_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3_ssim.vbom =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3_ssim.vbom (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3_ssim.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_n3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys3_fusp_cuff_aif = sys_tst_rlink_cuff_ic_n3_ssim.vhd +tb_tst_rlink_cuff_ic_n3.vbom +@top:tb_tst_rlink_cuff_ic_n3 Index: tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vhd =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vhd (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vhd (revision 24) @@ -0,0 +1,40 @@ +-- $Id: tb_tst_rlink_cuff_ic_n3.vhd 512 2013-04-28 07:44:02Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_cuff_ic_n3 +-- Description: Configuration for tb_tst_rlink_cuff_ic_n3 for +-- tb_nexys3_fusp_cuff +-- +-- Dependencies: sys_tst_rlink_cuff_n3 (fx2_type = 'ic2') +-- +-- To test: sys_tst_rlink_cuff_n3 (fx2_type = 'ic2') +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2013-01-xx xxx - 0.29 13.3 O76d xc6slx16-2 u:??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-27 512 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_cuff_ic_n3 of tb_nexys3_fusp_cuff is + + for sim + for all : nexys3_fusp_cuff_aif + use entity work.sys_tst_rlink_cuff_n3; + end for; + end for; + +end tb_tst_rlink_cuff_ic_n3; Index: tst_rlink_cuff/nexys3/ic/tb/Makefile =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/Makefile (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/Makefile (revision 24) @@ -0,0 +1,32 @@ +# $Id: Makefile 512 2013-04-28 07:44:02Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-04-27 512 1.0 Initial version +# +EXE_all = tb_tst_rlink_cuff_ic_n3 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_rlink_cuff_ic_n3.ucf +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_rlink_cuff/nexys3/ic/tb/.cvsignore =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/.cvsignore (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/.cvsignore (revision 24) @@ -0,0 +1,6 @@ +tb_tst_rlink_cuff_ic_n3 +tb_tst_rlink_cuff_ic_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_ucf_cpp Index: tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vbom =================================================================== --- tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vbom (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_nexsy3_fusp_cuff with sys_tst_rlink_cuff_n3 target; +# use vhdl configure file (tb_tst_rlink_cuff_ic_n3.vhd) to allow +# that all configurations will co-exist in work library +${nexys3_fusp_cuff_aif := ../sys_tst_rlink_cuff_ic_n3.vbom} +sys_conf = sys_conf_sim.vhd +../../../../../bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom +tb_tst_rlink_cuff_ic_n3.vhd Index: tst_rlink_cuff/nexys3/ic/tb =================================================================== --- tst_rlink_cuff/nexys3/ic/tb (nonexistent) +++ tst_rlink_cuff/nexys3/ic/tb (revision 24)
tst_rlink_cuff/nexys3/ic/tb Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_rlink_cuff_ic_n3 +tb_tst_rlink_cuff_ic_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_ucf_cpp Index: tst_rlink_cuff/nexys3/ic/Makefile =================================================================== --- tst_rlink_cuff/nexys3/ic/Makefile (nonexistent) +++ tst_rlink_cuff/nexys3/ic/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-01-04 469 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +FX2_FILE = nexys3_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset =================================================================== --- tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset (nonexistent) +++ tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset (revision 24) @@ -0,0 +1,100 @@ +# $Id: sys_tst_rlink_cuff_ic_n3.mfset 472 2013-01-06 14:39:10Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +Case statement is complete. others clause is never selected +Using initial value '0' for reset since it is never assigned +Using initial value '0' for fx2_tx2ena_l since it is never assigned + +Net does not have a driver. + +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected + +Signal is used but never assigned + +Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_n3' + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +ode of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Input is never used +Input > is never used +Input is never used +Input > is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used + +FF/Latch has a constant value of 0 +FF/Latch has a constant value +FF/Latch has a constant value + +of type RAMB16_S18 has been replaced by RAMB16BWER +of type RAMB16_S36 has been replaced by RAMB16BWER +of type RAMB16_S36_S36 has been replaced by RAMB16BWER + +FF/Latch has a constant value of 0 +FF/Latch has a constant value + +The FF/Latch .* is equivalent +The FF/Latch .* is equivalent +The FF/Latch .* is the opposite + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +The signal I_FX2_FLAG<3>_IBUF has no load +There are 2 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] Index: tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.ucf_cpp =================================================================== --- tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.ucf_cpp (nonexistent) +++ tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.ucf_cpp (revision 24) @@ -0,0 +1,24 @@ +## $Id: sys_tst_rlink_cuff_ic_n3.ucf_cpp 469 2013-01-05 12:29:44Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-01-04 469 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" +## +## FX2 interface +## +#include "bplib/nexys3/nexys3_pins_fx2.ucf" +#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" Index: tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.vbom =================================================================== --- tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.vbom (nonexistent) +++ tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.vbom (revision 24) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_rlink_cuff_n3.vbom +@ucf_cpp: sys_tst_rlink_cuff_ic_n3.ucf +@top: sys_tst_rlink_cuff_n3 Index: tst_rlink_cuff/nexys3/ic/.cvsignore =================================================================== --- tst_rlink_cuff/nexys3/ic/.cvsignore (nonexistent) +++ tst_rlink_cuff/nexys3/ic/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_cuff_ic_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/nexys3/ic =================================================================== --- tst_rlink_cuff/nexys3/ic (nonexistent) +++ tst_rlink_cuff/nexys3/ic (revision 24)
tst_rlink_cuff/nexys3/ic Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_cuff_ic_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom =================================================================== --- tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom (nonexistent) +++ tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom (revision 24) @@ -0,0 +1,31 @@ +# this is the vbom for the 'generic' top level entity +# to be referenced in the vbom's of the specific systems +# ./as/sys_tst_rlink_cuff_as_n3 +# ./ic/sys_tst_rlink_cuff_ic_n3 +# ./ic3/sys_tst_rlink_cuff_ic3_n3 +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../vlib/rbus/rblib.vhd +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf} +# components +[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../bplib/fx2lib/fx2_2fifoctl_as.vbom +../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom +../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom +../tst_rlink_cuff.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_rlink_cuff_n3.vhd +## no @ucf_cpp + Index: tst_rlink_cuff/nexys3 =================================================================== --- tst_rlink_cuff/nexys3 (nonexistent) +++ tst_rlink_cuff/nexys3 (revision 24)
tst_rlink_cuff/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vbom =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vbom (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vbom (revision 24) @@ -0,0 +1,7 @@ +# configure tb_nexsy2_fusp_cuff with sys_tst_rlink_cuff_n2 target; +# use vhdl configure file (tb_tst_rlink_cuff_ic_n2.vhd) to allow +# that all configurations will co-exist in work library +${nexys2_fusp_cuff_aif := ../sys_tst_rlink_cuff_ic_n2.vbom} +sys_conf = sys_conf_sim.vhd +../../../../../bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom +tb_tst_rlink_cuff_ic_n2.vhd Index: tst_rlink_cuff/nexys2/ic/tb/Makefile =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/Makefile (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/Makefile (revision 24) @@ -0,0 +1,32 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-01-01 467 1.0 Initial version +# +EXE_all = tb_tst_rlink_cuff_ic_n2 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean + rm -f sys_tst_rlink_cuff_ic_n2.ucf +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_rlink_cuff/nexys2/ic/tb/sys_tst_rlink_cuff_ic_n2.ucf_cpp =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/sys_tst_rlink_cuff_ic_n2.ucf_cpp (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/sys_tst_rlink_cuff_ic_n2.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_rlink_cuff_ic_n2.ucf_cpp \ No newline at end of file
tst_rlink_cuff/nexys2/ic/tb/sys_tst_rlink_cuff_ic_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_rlink_cuff/nexys2/ic/tb/tbw.dat =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/tbw.dat (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 467 2013-01-02 19:49:05Z mueller $ +# +[tb_tst_rlink_cuff_ic_n2] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2_ssim.vbom =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2_ssim.vbom (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2_ssim.vbom (revision 24) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_tst_rlink_n2.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys2_aif = sys_tst_rlink_cuff_ic_n2_ssim.vhd +tb_tst_rlink_cuff_ic_n2.vbom +@top:tb_tst_rlink_cuff_ic_n2 Index: tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vhd =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vhd (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vhd (revision 24) @@ -0,0 +1,40 @@ +-- $Id: tb_tst_rlink_cuff_ic_n2.vhd 467 2013-01-02 19:49:05Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_rlink_cuff_ic_n2 +-- Description: Configuration for tb_tst_rlink_cuff_ic_n2 for +-- tb_nexys2_fusp_cuff +-- +-- Dependencies: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2') +-- +-- To test: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2') +-- +-- Verified: +-- Date Rev Code ghdl ise Target Comment +-- 2013-01-xx xxx - 0.29 12.1 M53d xc3s1200e u:??? +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-01 467 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_tst_rlink_cuff_ic_n2 of tb_nexys2_fusp_cuff is + + for sim + for all : nexys2_fusp_cuff_aif + use entity work.sys_tst_rlink_cuff_n2; + end for; + end for; + +end tb_tst_rlink_cuff_ic_n2; Index: tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,60 @@ +-- $Id: sys_conf_sim.vhd 467 2013-01-02 19:49:05Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-01 467 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 1; + + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + constant sys_conf_fx2_type : string := "ic2"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: tst_rlink_cuff/nexys2/ic/tb/.cvsignore =================================================================== --- tst_rlink_cuff/nexys2/ic/tb/.cvsignore (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb/.cvsignore (revision 24) @@ -0,0 +1,6 @@ +tb_tst_rlink_cuff_ic_n2 +tb_tst_rlink_cuff_ic_n2_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_ucf_cpp Index: tst_rlink_cuff/nexys2/ic/tb =================================================================== --- tst_rlink_cuff/nexys2/ic/tb (nonexistent) +++ tst_rlink_cuff/nexys2/ic/tb (revision 24)
tst_rlink_cuff/nexys2/ic/tb Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_rlink_cuff_ic_n2 +tb_tst_rlink_cuff_ic_n2_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_ucf_cpp Index: tst_rlink_cuff/nexys2/ic/Makefile =================================================================== --- tst_rlink_cuff/nexys2/ic/Makefile (nonexistent) +++ tst_rlink_cuff/nexys2/ic/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-12-29 466 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +FX2_FILE = nexys2_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset =================================================================== --- tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset (nonexistent) +++ tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset (revision 24) @@ -0,0 +1,104 @@ +# $Id: sys_tst_rlink_cuff_ic_n2.mfset 466 2012-12-30 13:26:55Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value +Register in unit has a constant value + +Unconnected output port 'SIZE' of component 'fifo_1c_dram' +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' +Unconnected output port 'RL_MONI' of component 'rlink_core8' + +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used + +Output is never assigned + +Signal > is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is used but never assigned +Signal is used but never assigned +Signal is used but never assigned + +Signal is never used or assigned + +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Node of sequential type is unconnected +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +Signal I_FX2_FLAG<3> connected to top level port I_FX2_FLAG<3> has been removed +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design +This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete Index: tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.ucf_cpp =================================================================== --- tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.ucf_cpp (nonexistent) +++ tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.ucf_cpp (revision 24) @@ -0,0 +1,22 @@ +## $Id: sys_tst_rlink_cuff_ic_n2.ucf_cpp 466 2012-12-30 13:26:55Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2012-12-29 466 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" +## +## Cypress FX2 +## +#include "bplib/nexys2/nexys2_pins_fx2.ucf" +#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: tst_rlink_cuff/nexys2/ic/sys_conf.vhd =================================================================== --- tst_rlink_cuff/nexys2/ic/sys_conf.vhd (nonexistent) +++ tst_rlink_cuff/nexys2/ic/sys_conf.vhd (revision 24) @@ -0,0 +1,62 @@ +-- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $ +-- +-- Copyright 2012- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2012-12-29 466 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 1; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_fx2_type : string := "ic2"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.vbom =================================================================== --- tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.vbom (nonexistent) +++ tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.vbom (revision 24) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_rlink_cuff_n2.vbom +@ucf_cpp: sys_tst_rlink_cuff_ic_n2.ucf +@top: sys_tst_rlink_cuff_n2 Index: tst_rlink_cuff/nexys2/ic/.cvsignore =================================================================== --- tst_rlink_cuff/nexys2/ic/.cvsignore (nonexistent) +++ tst_rlink_cuff/nexys2/ic/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_cuff_ic_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/nexys2/ic =================================================================== --- tst_rlink_cuff/nexys2/ic (nonexistent) +++ tst_rlink_cuff/nexys2/ic (revision 24)
tst_rlink_cuff/nexys2/ic Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_cuff_ic_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd =================================================================== --- tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd (nonexistent) +++ tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd (revision 24) @@ -0,0 +1,383 @@ +-- $Id: sys_tst_rlink_cuff_n2.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2012-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_cuff_n2 - syn +-- Description: rlink tester design for nexys2 with fx2 interface +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_rbus +-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] +-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] +-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] +-- tst_rlink_cuff +-- bplib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz +-- 2013-01-04 469 13.3 O76d xc3s1200e-4 846 1798 160 1215 p 16.3 ic2/ 50 +-- 2012-12-29 466 13.3 O76d xc3s1200e-4 808 1739 160 1172 p 16.3 as2/ 50 +-- 2013-01-02 467 13.3 O76d xc3s1200e-4 843 1792 160 1209 p 15.2 ic2/ 50 +-- 2012-12-29 466 13.3 O76d xc3s1200e-4 863 1850 192 1266 p 13.6 ic3/ 50 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_fx2loop_n2 +-- the now obsoleted sys_tst_rlink_n2_cuff design +------------------------------------------------------------------------------ +-- Usage of Nexys 2 Switches, Buttons, LEDs: +-- +-- SWI(7:3) no function (only connected to sn_humanio_rbus) +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- (1) 1 enable XON +-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- +-- LED(7) SER_MONI.abact +-- (6:2) no function (only connected to sn_humanio_rbus) +-- (0) timer 0 busy +-- (1) timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- for SWI(2)='0' (serport) +-- DP(3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- for SWI(2)='1' (fx2) +-- DP(3) FX2_TX2BUSY (shows tx2 back preasure) +-- (2) FX2_TX2ENA(stretched) (shows tx2 activity) +-- (1) FX2_TXENA(streched) (shows tx activity) +-- (0) FX2_RXVAL(stretched) (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.rblib.all; +use work.fx2lib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_cuff_n2 is -- top level + -- implements nexys2_fusp_cuff_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end sys_tst_rlink_cuff_n2; + +architecture syn of sys_tst_rlink_cuff_n2 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXSD : slbit := '0'; + signal TXSD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal FX2_RXDATA : slv8 := (others=>'0'); + signal FX2_RXVAL : slbit := '0'; + signal FX2_RXHOLD : slbit := '0'; + signal FX2_RXAEMPTY : slbit := '0'; + signal FX2_TXDATA : slv8 := (others=>'0'); + signal FX2_TXENA : slbit := '0'; + signal FX2_TXBUSY : slbit := '0'; + signal FX2_TXAFULL : slbit := '0'; + signal FX2_TX2DATA : slv8 := (others=>'0'); + signal FX2_TX2ENA : slbit := '0'; + signal FX2_TX2BUSY : slbit := '0'; + signal FX2_TX2AFULL : slbit := '0'; + signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + DCM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, -- good for up to 127 MHz ! + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXSD, + TXD => TXSD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_rbus + generic map ( + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate + CNTL : fx2_2fifoctl_as + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + PETOWIDTH => sys_conf_fx2_petowidth, + RDPWLDELAY => sys_conf_fx2_rdpwldelay, + RDPWHDELAY => sys_conf_fx2_rdpwhdelay, + WRPWLDELAY => sys_conf_fx2_wrpwldelay, + WRPWHDELAY => sys_conf_fx2_wrpwhdelay, + FLAGDELAY => sys_conf_fx2_flagdelay) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_AS; + + FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate + CNTL : fx2_2fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC; + + FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate + CNTL : fx2_3fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + TX2AFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + TX2DATA => FX2_TX2DATA, + TX2ENA => FX2_TX2ENA, + TX2BUSY => FX2_TX2BUSY, + TX2AFULL => FX2_TX2AFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC3; + + TST : entity work.tst_rlink_cuff + port map ( + CLK => CLK, + RESET => '0', + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RB_MREQ_TOP => RB_MREQ, + RB_SRES_TOP => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + RXSD => RXSD, + TXSD => TXSD, + RTS_N => RTS_N, + CTS_N => CTS_N, + FX2_RXDATA => FX2_RXDATA, + FX2_RXVAL => FX2_RXVAL, + FX2_RXHOLD => FX2_RXHOLD, + FX2_TXDATA => FX2_TXDATA, + FX2_TXENA => FX2_TXENA, + FX2_TXBUSY => FX2_TXBUSY, + FX2_TX2DATA => FX2_TX2DATA, + FX2_TX2ENA => FX2_TX2ENA, + FX2_TX2BUSY => FX2_TX2BUSY, + FX2_MONI => FX2_MONI + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; + Index: tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom =================================================================== --- tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom (nonexistent) +++ tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vbom (revision 24) @@ -0,0 +1,31 @@ +# this is the vbom for the 'generic' top level entity +# to be referenced in the vbom's of the specific systems +# ./as/sys_tst_rlink_cuff_as_n2 +# ./ic/sys_tst_rlink_cuff_ic_n2 +# ./ic3/sys_tst_rlink_cuff_ic3_n2 +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../vlib/rbus/rblib.vhd +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf} +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../bplib/fx2lib/fx2_2fifoctl_as.vbom +../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom +../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom +../tst_rlink_cuff.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_rlink_cuff_n2.vhd +## no @ucf_cpp + Index: tst_rlink_cuff/nexys2/ic3/Makefile =================================================================== --- tst_rlink_cuff/nexys2/ic3/Makefile (nonexistent) +++ tst_rlink_cuff/nexys2/ic3/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-12-29 466 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +FX2_FILE = nexys2_jtag_3fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_rlink_cuff/nexys2/ic3/sys_conf.vhd =================================================================== --- tst_rlink_cuff/nexys2/ic3/sys_conf.vhd (nonexistent) +++ tst_rlink_cuff/nexys2/ic3/sys_conf.vhd (revision 24) @@ -0,0 +1,62 @@ +-- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $ +-- +-- Copyright 2012- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_cuff_ic3_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2012-12-29 466 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 1; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_fx2_type : string := "ic3"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + -- derived constants + + constant sys_conf_clksys : integer := + (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset =================================================================== --- tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset (nonexistent) +++ tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset (revision 24) @@ -0,0 +1,97 @@ +# $Id: sys_tst_rlink_cuff_ic3_n2.mfset 469 2013-01-05 12:29:44Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'SIZE' of component 'fifo_1c_dram' +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' +Unconnected output port 'RL_MONI' of component 'rlink_core8' + +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used + +Output is never assigned + +Signal > is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is used but never assigned +Signal is used but never assigned + +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value +FF/Latch has a constant value + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Node of sequential type is unconnected + +RAMs , are equivalent +RAMs , are equivalent + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design +This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete Index: tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp =================================================================== --- tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp (nonexistent) +++ tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp (revision 24) @@ -0,0 +1,22 @@ +## $Id: sys_tst_rlink_cuff_ic3_n2.ucf_cpp 466 2012-12-30 13:26:55Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2012-12-29 466 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" +## +## Cypress FX2 +## +#include "bplib/nexys2/nexys2_pins_fx2.ucf" +#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom =================================================================== --- tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom (nonexistent) +++ tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom (revision 24) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_rlink_cuff_n2.vbom +@ucf_cpp: sys_tst_rlink_cuff_ic3_n2.ucf +@top: sys_tst_rlink_cuff_n2 Index: tst_rlink_cuff/nexys2/ic3/.cvsignore =================================================================== --- tst_rlink_cuff/nexys2/ic3/.cvsignore (nonexistent) +++ tst_rlink_cuff/nexys2/ic3/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_cuff_ic3_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/nexys2/ic3 =================================================================== --- tst_rlink_cuff/nexys2/ic3 (nonexistent) +++ tst_rlink_cuff/nexys2/ic3 (revision 24)
tst_rlink_cuff/nexys2/ic3 Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_cuff_ic3_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/nexys2 =================================================================== --- tst_rlink_cuff/nexys2 (nonexistent) +++ tst_rlink_cuff/nexys2 (revision 24)
tst_rlink_cuff/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd =================================================================== --- tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd (nonexistent) +++ tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd (revision 24) @@ -0,0 +1,347 @@ +-- $Id: sys_tst_rlink_cuff_atlys.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_rlink_cuff_atlys - syn +-- Description: rlink tester design for atlys with fx2 interface +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/bpgen/sn_humanio_demu_rbus +-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"] +-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] +-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] +-- tst_rlink_cuff +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz +-- 2013-01-06 472 13.3 O76d xc6slx45 ??? ???? ??? ???? p ??.? ic2/100 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-06 472 1.0 Initial version; derived from sys_tst_rlink_cuff_n3 +-- and sys_tst_fx2loop_atlys +------------------------------------------------------------------------------ +-- Usage of Atlys Switches, Buttons, LEDs: +-- +-- SWI(7:3) no function (only connected to sn_humanio_demu_rbus) +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- (1) 1 enable XON +-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob +-- 1 -> Pmod B/top RS232 port / +-- +-- LED(7) SER_MONI.abact +-- (6:2) no function (only connected to sn_humanio_demu_rbus) +-- (0) timer 0 busy +-- (1) timer 1 busy +-- +-- DSP: SER_MONI.clkdiv (from auto bauder) +-- for SWI(2)='0' (serport) +-- DP(3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- for SWI(2)='1' (fx2) +-- DP(3) FX2_TX2BUSY (shows tx2 back preasure) +-- (2) FX2_TX2ENA(stretched) (shows tx2 activity) +-- (1) FX2_TXENA(streched) (shows tx activity) +-- (0) FX2_RXVAL(stretched) (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.rblib.all; +use work.fx2lib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_rlink_cuff_atlys is -- top level + -- implements atlys_fusp_cuff_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_USB_RXD : in slbit; -- USB UART receive data (board view) + O_USB_TXD : out slbit; -- USB UART transmit data (board view) + I_HIO_SWI : in slv8; -- atlys hio switches + I_HIO_BTN : in slv6; -- atlys hio buttons + O_HIO_LED: out slv8; -- atlys hio leds + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end sys_tst_rlink_cuff_atlys; + +architecture syn of sys_tst_rlink_cuff_atlys is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXSD : slbit := '0'; + signal TXSD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal FX2_RXDATA : slv8 := (others=>'0'); + signal FX2_RXVAL : slbit := '0'; + signal FX2_RXHOLD : slbit := '0'; + signal FX2_RXAEMPTY : slbit := '0'; + signal FX2_TXDATA : slv8 := (others=>'0'); + signal FX2_TXENA : slbit := '0'; + signal FX2_TXBUSY : slbit := '0'; + signal FX2_TXAFULL : slbit := '0'; + signal FX2_TX2DATA : slv8 := (others=>'0'); + signal FX2_TX2ENA : slbit := '0'; + signal FX2_TX2BUSY : slbit := '0'; + signal FX2_TX2AFULL : slbit := '0'; + signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; + + constant rbaddr_hio : slv8 := "11000000"; -- 110000xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + DCM : dcm_sfs + generic map ( + CLKFX_DIVIDE => sys_conf_clkfx_divide, + CLKFX_MULTIPLY => sys_conf_clkfx_multiply, + CLKIN_PERIOD => 10.0) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, -- good for up to 127 MHz ! + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXSD, + TXD => TXSD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_USB_RXD, + O_TXD0 => O_USB_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + HIO : sn_humanio_demu_rbus + generic map ( + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_HIO_SWI, + I_BTN => I_HIO_BTN, + O_LED => O_HIO_LED + ); + + FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate + CNTL : fx2_2fifoctl_as + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + PETOWIDTH => sys_conf_fx2_petowidth, + RDPWLDELAY => sys_conf_fx2_rdpwldelay, + RDPWHDELAY => sys_conf_fx2_rdpwhdelay, + WRPWLDELAY => sys_conf_fx2_wrpwldelay, + WRPWHDELAY => sys_conf_fx2_wrpwhdelay, + FLAGDELAY => sys_conf_fx2_flagdelay) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_AS; + + FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate + CNTL : fx2_2fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC; + + FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate + CNTL : fx2_3fifoctl_ic + generic map ( + RXFAWIDTH => 5, + TXFAWIDTH => 5, + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + RXAEMPTY_THRES => 1, + TXAFULL_THRES => 1, + TX2AFULL_THRES => 1) + port map ( + CLK => CLK, + RESET => RESET, + RXDATA => FX2_RXDATA, + RXVAL => FX2_RXVAL, + RXHOLD => FX2_RXHOLD, + RXAEMPTY => FX2_RXAEMPTY, + TXDATA => FX2_TXDATA, + TXENA => FX2_TXENA, + TXBUSY => FX2_TXBUSY, + TXAFULL => FX2_TXAFULL, + TX2DATA => FX2_TX2DATA, + TX2ENA => FX2_TX2ENA, + TX2BUSY => FX2_TX2BUSY, + TX2AFULL => FX2_TX2AFULL, + MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + end generate FX2_CNTL_IC3; + + TST : entity work.tst_rlink_cuff + port map ( + CLK => CLK, + RESET => '0', + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RB_MREQ_TOP => RB_MREQ, + RB_SRES_TOP => RB_SRES_HIO, + SWI => SWI, + BTN => BTN(3 downto 0), + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + RXSD => RXSD, + TXSD => TXSD, + RTS_N => RTS_N, + CTS_N => CTS_N, + FX2_RXDATA => FX2_RXDATA, + FX2_RXVAL => FX2_RXVAL, + FX2_RXHOLD => FX2_RXHOLD, + FX2_TXDATA => FX2_TXDATA, + FX2_TXENA => FX2_TXENA, + FX2_TXBUSY => FX2_TXBUSY, + FX2_TX2DATA => FX2_TX2DATA, + FX2_TX2ENA => FX2_TX2ENA, + FX2_TX2BUSY => FX2_TX2BUSY, + FX2_MONI => FX2_MONI + ); + +end syn; + Index: tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom =================================================================== --- tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom (nonexistent) +++ tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom (revision 24) @@ -0,0 +1,28 @@ +# this is the vbom for the 'generic' top level entity +# to be referenced in the vbom's of the specific systems +# ./as/sys_tst_rlink_cuff_as_atlys +# ./ic/sys_tst_rlink_cuff_ic_atlys +# ./ic3/sys_tst_rlink_cuff_ic3_atlys +# +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../vlib/rbus/rblib.vhd +../../../bplib/fx2lib/fx2lib.vhd +${sys_conf} +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio_demu_rbus.vbom +../../../bplib/fx2lib/fx2_2fifoctl_as.vbom +../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom +../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom +../tst_rlink_cuff.vbom +# design +sys_tst_rlink_cuff_atlys.vhd +## no @ucf_cpp Index: tst_rlink_cuff/atlys/ic/Makefile =================================================================== --- tst_rlink_cuff/atlys/ic/Makefile (nonexistent) +++ tst_rlink_cuff/atlys/ic/Makefile (revision 24) @@ -0,0 +1,30 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-01-06 472 1.0 Initial version +# +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_atlys.mk +FX2_FILE = nexys3_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.ucf_cpp =================================================================== --- tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.ucf_cpp (nonexistent) +++ tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.ucf_cpp (revision 24) @@ -0,0 +1,24 @@ +## $Id: sys_tst_rlink_cuff_ic_atlys.ucf_cpp 472 2013-01-06 14:39:10Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-01-06 472 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/atlys/atlys_pins.ucf" +## +## Pmod A0 - RS232 +## +#include "bplib/atlys/atlys_pins_pma0_rs232.ucf" +## +## FX2 interface +## +#include "bplib/atlys/atlys_pins_fx2.ucf" +#include "bplib/atlys/atlys_time_fx2_ic.ucf" Index: tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.vbom =================================================================== --- tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.vbom (nonexistent) +++ tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.vbom (revision 24) @@ -0,0 +1,8 @@ +# conf +sys_conf = sys_conf.vhd +# libs +# components +# design +../sys_tst_rlink_cuff_atlys.vbom +@ucf_cpp: sys_tst_rlink_cuff_ic_atlys.ucf +@top: sys_tst_rlink_cuff_atlys Index: tst_rlink_cuff/atlys/ic/sys_conf.vhd =================================================================== --- tst_rlink_cuff/atlys/ic/sys_conf.vhd (nonexistent) +++ tst_rlink_cuff/atlys/ic/sys_conf.vhd (revision 24) @@ -0,0 +1,62 @@ +-- $Id: sys_conf.vhd 472 2013-01-06 14:39:10Z mueller $ +-- +-- Copyright 2013- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_rlink_cuff_ic_atlys (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.3; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-06 472 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkfx_divide : positive := 1; + constant sys_conf_clkfx_multiply : positive := 1; + + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + constant sys_conf_fx2_type : string := "ic2"; + + -- dummy values defs for generic parameters of as controller + constant sys_conf_fx2_rdpwldelay : positive := 1; + constant sys_conf_fx2_rdpwhdelay : positive := 1; + constant sys_conf_fx2_wrpwldelay : positive := 1; + constant sys_conf_fx2_wrpwhdelay : positive := 1; + constant sys_conf_fx2_flagdelay : positive := 1; + + -- pktend timer setting + -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) + constant sys_conf_fx2_petowidth : positive := 10; + + constant sys_conf_fx2_ccwidth : positive := 5; + + -- derived constants + + constant sys_conf_clksys : integer := + (100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: tst_rlink_cuff/atlys/ic/.cvsignore =================================================================== --- tst_rlink_cuff/atlys/ic/.cvsignore (nonexistent) +++ tst_rlink_cuff/atlys/ic/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_rlink_cuff_ic_atlys.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset =================================================================== --- tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset (nonexistent) +++ tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset (revision 24) @@ -0,0 +1,97 @@ +# $Id: sys_tst_rlink_cuff_ic_atlys.mfset 472 2013-01-06 14:39:10Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +Case statement is complete. others clause is never selected +Using initial value '0' for reset since it is never assigned +Using initial value '0' for fx2_tx2ena_l since it is never assigned + +Net does not have a driver. + +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected or connected +Output port of the instance is unconnected + +Signal is used but never assigned + +Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_atlys' + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +ode of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Input is never used +Input > is never used +Input > is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used + +FF/Latch has a constant value of 0 +FF/Latch has a constant value +FF/Latch has a constant value + +of type RAMB16_S18 has been replaced by RAMB16BWER +of type RAMB16_S36 has been replaced by RAMB16BWER +of type RAMB16_S36_S36 has been replaced by RAMB16BWER + +FF/Latch has a constant value of 0 +FF/Latch has a constant value + +The FF/Latch .* is equivalent +The FF/Latch .* is equivalent + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_FX2_FLAG<3>_IBUF has no load +There are 1 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] Index: tst_rlink_cuff/atlys/ic =================================================================== --- tst_rlink_cuff/atlys/ic (nonexistent) +++ tst_rlink_cuff/atlys/ic (revision 24)
tst_rlink_cuff/atlys/ic Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_rlink_cuff_ic_atlys.ucf +*.dep_ucf_cpp +*.svf Index: tst_rlink_cuff/atlys =================================================================== --- tst_rlink_cuff/atlys (nonexistent) +++ tst_rlink_cuff/atlys (revision 24)
tst_rlink_cuff/atlys Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_rlink_cuff/tst_rlink_cuff.vhd =================================================================== --- tst_rlink_cuff/tst_rlink_cuff.vhd (nonexistent) +++ tst_rlink_cuff/tst_rlink_cuff.vhd (revision 24) @@ -0,0 +1,281 @@ +-- $Id: tst_rlink_cuff.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2012-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_rlink_cuff - syn +-- Description: tester for rlink over cuff +-- +-- Dependencies: vlib/rlink/rlink_core8 +-- vlib/rlink/rlink_rlbmux +-- vlib/serport/serport_1clock +-- ../tst_rlink/rbd_tst_rlink +-- vlib/rbus/rb_sres_or_2 +-- vlib/genlib/led_pulse_stretch +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.3; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-02 467 1.0.1 use 64 usec led pulse width +-- 2012-12-29 466 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.serportlib.all; +use work.fx2lib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity tst_rlink_cuff is -- tester for rlink over cuff + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_USEC : in slbit; -- usec pulse + CE_MSEC : in slbit; -- msec pulse + RB_MREQ_TOP : out rb_mreq_type; -- rbus: request + RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level + SWI : in slv8; -- hio: switches + BTN : in slv4; -- hio: buttons + LED : out slv8; -- hio: leds + DSP_DAT : out slv16; -- hio: display data + DSP_DP : out slv4; -- hio: display decimal points + RXSD : in slbit; -- receive serial data (uart view) + TXSD : out slbit; -- transmit serial data (uart view) + RTS_N : out slbit; -- receive rts (uart view, act.low) + CTS_N : in slbit; -- transmit cts (uart view, act.low) + FX2_RXDATA : in slv8; -- fx2: receiver data out + FX2_RXVAL : in slbit; -- fx2: receiver data valid + FX2_RXHOLD : out slbit; -- fx2: receiver data hold + FX2_TXDATA : out slv8; -- fx2: transmit data in + FX2_TXENA : out slbit; -- fx2: transmit data enable + FX2_TXBUSY : in slbit; -- fx2: transmit busy + FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in + FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable + FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy + FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor + ); +end tst_rlink_cuff; + +architecture syn of tst_rlink_cuff is + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_TST : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv3 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + signal STAT : slv8 := (others=>'0'); + + signal RLB_DI : slv8 := (others=>'0'); + signal RLB_ENA : slbit := '0'; + signal RLB_BUSY : slbit := '0'; + signal RLB_DO : slv8 := (others=>'0'); + signal RLB_VAL : slbit := '0'; + signal RLB_HOLD : slbit := '0'; + + signal SER_RXDATA : slv8 := (others=>'0'); + signal SER_RXVAL : slbit := '0'; + signal SER_RXHOLD : slbit := '0'; + signal SER_TXDATA : slv8 := (others=>'0'); + signal SER_TXENA : slbit := '0'; + signal SER_TXBUSY : slbit := '0'; + + signal FX2_TX2ENA_L : slbit := '0'; + signal FX2_TXENA_L : slbit := '0'; + + signal FX2_TX2ENA_LED : slbit := '0'; + signal FX2_TXENA_LED : slbit := '0'; + signal FX2_RXVAL_LED : slbit := '0'; + + signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses + signal R_LEDCE : slbit := '0'; -- ce every 64 usec + +begin + + RLCORE : rlink_core8 + generic map ( + ATOWIDTH => 6, + ITOWIDTH => 6, + CPREF => c_rlink_cpref, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon) + port map ( + CLK => CLK, + CE_INT => CE_MSEC, + RESET => RESET, + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + RL_MONI => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT + ); + + RLBMUX : rlink_rlbmux + port map ( + SEL => SWI(2), + RLB_DI => RLB_DI, + RLB_ENA => RLB_ENA, + RLB_BUSY => RLB_BUSY, + RLB_DO => RLB_DO, + RLB_VAL => RLB_VAL, + RLB_HOLD => RLB_HOLD, + P0_RXDATA => SER_RXDATA, + P0_RXVAL => SER_RXVAL, + P0_RXHOLD => SER_RXHOLD, + P0_TXDATA => SER_TXDATA, + P0_TXENA => SER_TXENA, + P0_TXBUSY => SER_TXBUSY, + P1_RXDATA => FX2_RXDATA, + P1_RXVAL => FX2_RXVAL, + P1_RXHOLD => FX2_RXHOLD, + P1_TXDATA => FX2_TXDATA, + P1_TXENA => FX2_TXENA_L, + P1_TXBUSY => FX2_TXBUSY + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_ser2rri_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAESC => SWI(1), + RXDATA => SER_RXDATA, + RXVAL => SER_RXVAL, + RXHOLD => SER_RXHOLD, + TXDATA => SER_TXDATA, + TXENA => SER_TXENA, + TXBUSY => SER_TXBUSY, + MONI => SER_MONI, + RXSD => RXSD, + TXSD => TXSD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + RBDTST : entity work.rbd_tst_rlink + port map ( + CLK => CLK, + RESET => RESET, + CE_USEC => CE_USEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_TST, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RB_SRES_TOP => RB_SRES, + RXSD => RXSD, + RXACT => SER_MONI.rxact, + STAT => STAT + ); + + RB_SRES_OR1 : rb_sres_or_2 + port map ( + RB_SRES_1 => RB_SRES_TOP, + RB_SRES_2 => RB_SRES_TST, + RB_SRES_OR => RB_SRES + ); + + TX2ENA_PSTR : led_pulse_stretch + port map ( + CLK => CLK, + CE_INT => R_LEDCE, + RESET => '0', + DIN => FX2_TX2ENA_L, + POUT => FX2_TX2ENA_LED + ); + TXENA_PSTR : led_pulse_stretch + port map ( + CLK => CLK, + CE_INT => R_LEDCE, + RESET => '0', + DIN => FX2_TXENA_L, + POUT => FX2_TXENA_LED + ); + RXVAL_PSTR : led_pulse_stretch + port map ( + CLK => CLK, + CE_INT => R_LEDCE, + RESET => '0', + DIN => FX2_RXVAL, + POUT => FX2_RXVAL_LED + ); + + proc_clkdiv: process (CLK) + begin + + if rising_edge(CLK) then + R_LEDCE <= '0'; + if CE_USEC = '1' then + R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1); + if unsigned(R_LEDDIV) = 0 then + R_LEDCE <= '1'; + end if; + end if; + end if; + + end process proc_clkdiv; + + proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY, + FX2_TX2ENA_LED, FX2_TXENA_LED, FX2_RXVAL_LED) + begin + + DSP_DAT <= SER_MONI.abclkdiv; + + LED(7) <= SER_MONI.abact; + LED(6 downto 2) <= (others=>'0'); + LED(1) <= STAT(1); + LED(0) <= STAT(0); + + if SWI(2) = '0' then + DSP_DP(3) <= not SER_MONI.txok; + DSP_DP(2) <= SER_MONI.txact; + DSP_DP(1) <= not SER_MONI.rxok; + DSP_DP(0) <= SER_MONI.rxact; + else + DSP_DP(3) <= FX2_TX2BUSY; + DSP_DP(2) <= FX2_TX2ENA_LED; + DSP_DP(1) <= FX2_TXENA_LED; + DSP_DP(0) <= FX2_RXVAL_LED; + end if; + + end process proc_hiomux; + + RB_MREQ_TOP <= RB_MREQ; + FX2_TX2ENA <= FX2_TX2ENA_L; + FX2_TXENA <= FX2_TXENA_L; + +end syn; Index: tst_rlink_cuff/Makefile =================================================================== --- tst_rlink_cuff/Makefile (nonexistent) +++ tst_rlink_cuff/Makefile (revision 24) @@ -0,0 +1,26 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2012-12-29 466 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean realclean +# +all : $(NGC_all) +# +clean : ise_clean +# +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: tst_rlink_cuff/tst_rlink_cuff.vbom =================================================================== --- tst_rlink_cuff/tst_rlink_cuff.vbom (nonexistent) +++ tst_rlink_cuff/tst_rlink_cuff.vbom (revision 24) @@ -0,0 +1,17 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/genlib/genlib.vhd +../../vlib/rbus/rblib.vhd +../../vlib/rlink/rlinklib.vbom +../../vlib/serport/serportlib.vbom +../../bplib/fx2lib/fx2lib.vhd +${sys_conf := nexys2/as/sys_conf.vhd} +# components +../../vlib/rlink/rlink_core8.vbom +../../vlib/rlink/rlink_rlbmux.vbom +../../vlib/serport/serport_1clock.vbom +../tst_rlink/rbd_tst_rlink.vbom +../../vlib/rbus/rb_sres_or_2.vbom +../../vlib/genlib/led_pulse_stretch.vbom +# design +tst_rlink_cuff.vhd Index: tst_rlink_cuff =================================================================== --- tst_rlink_cuff (nonexistent) +++ tst_rlink_cuff (revision 24)
tst_rlink_cuff Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_snhumanio/nexys2/Makefile =================================================================== --- tst_snhumanio/nexys2/Makefile (nonexistent) +++ tst_snhumanio/nexys2/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-09-17 410 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd =================================================================== --- tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd (nonexistent) +++ tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vhd (revision 24) @@ -0,0 +1,161 @@ +-- $Id: sys_tst_snhumanio_n2.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_n2 - syn +-- Description: snhumanio tester design for nexys2 +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-09-17 410 13.1 O40d xc3s1200e-4 149 207 - 144 t 10.2 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 remove clksys output hack +-- 2011-11-26 433 1.0.3 use nx_cram_dummy now +-- 2011-11-23 432 1.0.3 update O_FLA_CE_N usage +-- 2011-10-25 419 1.0.2 get entity name right... +-- 2011-09-17 410 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Nexys 2 Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_n2 is -- top level + -- implements nexys2_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit -- flash ce.. (act.low) + ); +end sys_tst_snhumanio_n2; + +architecture syn of sys_tst_snhumanio_n2 is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK50; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 50, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 4, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 4) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom =================================================================== --- tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom (nonexistent) +++ tst_snhumanio/nexys2/sys_tst_snhumanio_n2.vbom (revision 24) @@ -0,0 +1,14 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_snhumanio_n2.vhd +@ucf_cpp: sys_tst_snhumanio_n2.ucf Index: tst_snhumanio/nexys2/sys_conf.vhd =================================================================== --- tst_snhumanio/nexys2/sys_conf.vhd (nonexistent) +++ tst_snhumanio/nexys2/sys_conf.vhd (revision 24) @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-09-17 410 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + Index: tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset =================================================================== --- tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset (nonexistent) +++ tst_snhumanio/nexys2/sys_tst_snhumanio_n2.mfset (revision 24) @@ -0,0 +1,34 @@ +# $Id: sys_tst_snhumanio_n2.mfset 412 2011-10-08 15:15:20Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'CE_USEC' of component 'clkdivce' + +Input is never used + +FF/Latch has a constant value of 0 +Node of sequential type is unconnected + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design + +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete Index: tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp =================================================================== --- tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp (nonexistent) +++ tst_snhumanio/nexys2/sys_tst_snhumanio_n2.ucf_cpp (revision 24) @@ -0,0 +1,15 @@ +## $Id: sys_tst_snhumanio_n2.ucf_cpp 410 2011-09-18 11:23:09Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-09-17 410 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" Index: tst_snhumanio/nexys2/.cvsignore =================================================================== --- tst_snhumanio/nexys2/.cvsignore (nonexistent) +++ tst_snhumanio/nexys2/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_snhumanio_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_snhumanio/nexys2 =================================================================== --- tst_snhumanio/nexys2 (nonexistent) +++ tst_snhumanio/nexys2 (revision 24)
tst_snhumanio/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_snhumanio_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_snhumanio/nexys3/Makefile =================================================================== --- tst_snhumanio/nexys3/Makefile (nonexistent) +++ tst_snhumanio/nexys3/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-27 433 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vbom =================================================================== --- tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vbom (nonexistent) +++ tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vbom (revision 24) @@ -0,0 +1,14 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_snhumanio_n3.vhd +@ucf_cpp: sys_tst_snhumanio_n3.ucf Index: tst_snhumanio/nexys3/.cvsignore =================================================================== --- tst_snhumanio/nexys3/.cvsignore (nonexistent) +++ tst_snhumanio/nexys3/.cvsignore (revision 24) @@ -0,0 +1,5 @@ +_impactbatch.log +sys_tst_snhumanio_n3.ucf +*.dep_ucf_cpp +_impact* +*.svf Index: tst_snhumanio/nexys3/sys_conf.vhd =================================================================== --- tst_snhumanio/nexys3/sys_conf.vhd (nonexistent) +++ tst_snhumanio/nexys3/sys_conf.vhd (revision 24) @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-27 433 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + Index: tst_snhumanio/nexys3/sys_tst_snhumanio_n3.ucf_cpp =================================================================== --- tst_snhumanio/nexys3/sys_tst_snhumanio_n3.ucf_cpp (nonexistent) +++ tst_snhumanio/nexys3/sys_tst_snhumanio_n3.ucf_cpp (revision 24) @@ -0,0 +1,15 @@ +## $Id: sys_tst_snhumanio_n3.ucf_cpp 433 2011-11-27 22:04:39Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-11-27 433 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" Index: tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd =================================================================== --- tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd (nonexistent) +++ tst_snhumanio/nexys3/sys_tst_snhumanio_n3.vhd (revision 24) @@ -0,0 +1,159 @@ +-- $Id: sys_tst_snhumanio_n3.vhd 433 2011-11-27 22:04:39Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_n3 - syn +-- Description: snhumanio tester design for nexys3 +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-11-27 433 13.1 O40d xc3s1200e-4 151 195 - 65 t 6.1 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-27 433 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Nexys 2 Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_n3 is -- top level + -- implements nexys3_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit -- ppcm: ... + ); +end sys_tst_snhumanio_n3; + +architecture syn of sys_tst_snhumanio_n3 is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 100, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 5) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + +end syn; Index: tst_snhumanio/nexys3 =================================================================== --- tst_snhumanio/nexys3 (nonexistent) +++ tst_snhumanio/nexys3 (revision 24)
tst_snhumanio/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_snhumanio_n3.ucf +*.dep_ucf_cpp +_impact* +*.svf Index: tst_snhumanio/atlys/Makefile =================================================================== --- tst_snhumanio/atlys/Makefile (nonexistent) +++ tst_snhumanio/atlys/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-10-11 414 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_atlys.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom =================================================================== --- tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom (nonexistent) +++ tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vbom (revision 24) @@ -0,0 +1,12 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio_demu.vbom +../tst_snhumanio.vbom +# design +sys_tst_snhumanio_atlys.vhd +@ucf_cpp: sys_tst_snhumanio_atlys.ucf Index: tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd =================================================================== --- tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd (nonexistent) +++ tst_snhumanio/atlys/sys_tst_snhumanio_atlys.vhd (revision 24) @@ -0,0 +1,130 @@ +-- $Id: sys_tst_snhumanio_atlys.vhd 439 2011-12-16 21:56:04Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_atlys - syn +-- Description: snhumanio tester design for atlys +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio_demu +-- tst_snhumanio +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-10-11 414 13.1 O40d xc6slx45 166 196 - 60 t 4.9 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-11 414 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of Atlys Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_atlys is -- top level + -- implements atlys_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock +-- O_CLKSYS : out slbit; -- DCM derived system clock + I_USB_RXD : in slbit; -- USB UART receive data (board view) + O_USB_TXD : out slbit; -- USB UART transmit data (board view) + I_HIO_SWI : in slv8; -- atlys hio switches + I_HIO_BTN : in slv6; -- atlys hio buttons + O_HIO_LED: out slv8; -- atlys hio leds + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_snhumanio_atlys; + +architecture syn of sys_tst_snhumanio_atlys is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 100, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio_demu + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_HIO_SWI, + I_BTN => I_HIO_BTN, + O_LED => O_HIO_LED + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 4) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_USB_TXD <= I_USB_RXD; + O_FUSP_TXD <= I_FUSP_RXD; + O_FUSP_RTS_N <= I_FUSP_CTS_N; + +end syn; Index: tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset =================================================================== --- tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset (nonexistent) +++ tst_snhumanio/atlys/sys_tst_snhumanio_atlys.mfset (revision 24) @@ -0,0 +1,29 @@ +# $Id: sys_tst_snhumanio_atlys.mfset 416 2011-10-15 13:32:57Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Case statement is complete. others clause is never selected + +sys_tst_snhumanio_atlys\..*Output port of the instance is unconnected + +Node of sequential type is unconnected + +The FF/Latch in Unit <.*> is equivalent +The small RAM <.*> will be implemented on LUTs + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] Index: tst_snhumanio/atlys/sys_conf.vhd =================================================================== --- tst_snhumanio/atlys/sys_conf.vhd (nonexistent) +++ tst_snhumanio/atlys/sys_conf.vhd (revision 24) @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 414 2011-10-11 19:38:12Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_atlys (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-11 414 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + Index: tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp =================================================================== --- tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp (nonexistent) +++ tst_snhumanio/atlys/sys_tst_snhumanio_atlys.ucf_cpp (revision 24) @@ -0,0 +1,16 @@ +## $Id: sys_tst_snhumanio_atlys.ucf_cpp 414 2011-10-11 19:38:12Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-10-11 414 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/atlys/atlys_pins.ucf" +#include "bplib/atlys/atlys_pins_pma0_rs232.ucf" Index: tst_snhumanio/atlys/.cvsignore =================================================================== --- tst_snhumanio/atlys/.cvsignore (nonexistent) +++ tst_snhumanio/atlys/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_snhumanio_atlys.ucf +*.dep_ucf_cpp +*.svf Index: tst_snhumanio/atlys =================================================================== --- tst_snhumanio/atlys (nonexistent) +++ tst_snhumanio/atlys (revision 24)
tst_snhumanio/atlys Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_snhumanio_atlys.ucf +*.dep_ucf_cpp +*.svf Index: tst_snhumanio/Makefile =================================================================== --- tst_snhumanio/Makefile (nonexistent) +++ tst_snhumanio/Makefile (revision 24) @@ -0,0 +1,25 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-09-17 410 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: tst_snhumanio/s3board/Makefile =================================================================== --- tst_snhumanio/s3board/Makefile (nonexistent) +++ tst_snhumanio/s3board/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-09-18 410 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom =================================================================== --- tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom (nonexistent) +++ tst_snhumanio/s3board/sys_tst_snhumanio_s3.vbom (revision 24) @@ -0,0 +1,14 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/s3board/s3boardlib.vhd +${sys_conf := sys_conf.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_snhumanio.vbom +../../../bplib/s3board/s3_sram_dummy.vbom +# design +sys_tst_snhumanio_s3.vhd +@ucf_cpp: sys_tst_snhumanio_s3.ucf Index: tst_snhumanio/s3board/sys_conf.vhd =================================================================== --- tst_snhumanio/s3board/sys_conf.vhd (nonexistent) +++ tst_snhumanio/s3board/sys_conf.vhd (revision 24) @@ -0,0 +1,35 @@ +-- $Id: sys_conf.vhd 410 2011-09-18 11:23:09Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_snhumanio_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-09-18 410 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + +end package sys_conf; + Index: tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset =================================================================== --- tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset (nonexistent) +++ tst_snhumanio/s3board/sys_tst_snhumanio_s3.mfset (revision 24) @@ -0,0 +1,27 @@ +# $Id: sys_tst_snhumanio_s3.mfset 417 2011-10-22 10:30:29Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'CE_USEC' of component 'clkdivce' + +FF/Latch has a constant value of 0 +Node of sequential type is unconnected + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] Index: tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp =================================================================== --- tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp (nonexistent) +++ tst_snhumanio/s3board/sys_tst_snhumanio_s3.ucf_cpp (revision 24) @@ -0,0 +1,15 @@ +## $Id: sys_tst_snhumanio_s3.ucf_cpp 410 2011-09-18 11:23:09Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-09-18 410 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" Index: tst_snhumanio/s3board/.cvsignore =================================================================== --- tst_snhumanio/s3board/.cvsignore (nonexistent) +++ tst_snhumanio/s3board/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_snhumanio_s3.ucf +*.dep_ucf_cpp +*.svf Index: tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd =================================================================== --- tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd (nonexistent) +++ tst_snhumanio/s3board/sys_tst_snhumanio_s3.vhd (revision 24) @@ -0,0 +1,148 @@ +-- $Id: sys_tst_snhumanio_s3.vhd 419 2011-11-01 19:42:30Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_snhumanio_s3 - syn +-- Description: snhumanio tester design for s3board +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/sn_humanio +-- tst_snhumanio +-- s3board/s3_sram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-09-18 410 13.1 O40d xc3s1000-4 149 211 - 143 t 11.4 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-25 419 1.0.2 get entity name right... +-- 2011-10-15 416 1.0.1 remove O_CLKSYS top level port +-- 2011-09-18 410 1.0 Initial version +------------------------------------------------------------------------------ +-- Usage of S3BOARD Switches, Buttons, LEDs: +-- + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.s3boardlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_snhumanio_s3 is -- top level + -- implements s3board_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end sys_tst_snhumanio_s3; + +architecture syn of sys_tst_snhumanio_s3 is + + signal CLK : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal RESET : slbit := '0'; + signal CE_MSEC : slbit := '0'; + +begin + + RESET <= '0'; -- so far not used + + CLK <= I_CLK50; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => 50, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 4, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + HIOTEST : entity work.tst_snhumanio + generic map ( + BWIDTH => 4) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + O_TXD <= I_RXD; + + SRAM_PROT : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; Index: tst_snhumanio/s3board =================================================================== --- tst_snhumanio/s3board (nonexistent) +++ tst_snhumanio/s3board (revision 24)
tst_snhumanio/s3board Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_snhumanio_s3.ucf +*.dep_ucf_cpp +*.svf Index: tst_snhumanio/tst_snhumanio.vhd =================================================================== --- tst_snhumanio/tst_snhumanio.vhd (nonexistent) +++ tst_snhumanio/tst_snhumanio.vhd (revision 24) @@ -0,0 +1,234 @@ +-- $Id: tst_snhumanio.vhd 416 2011-10-15 13:32:57Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_snhumanio - syn +-- Description: simple stand-alone tester for sn_humanio +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-10-15 416 1.0.2 fix sensitivity list of proc_next +-- 2011-10-08 412 1.0.1 use better rndm init (so that swi=0 is non-const) +-- 2011-09-17 410 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.comlib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_snhumanio is -- tester for rlink + generic ( + BWIDTH : positive := 4); -- BTN port width + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + SWI : in slv8; -- switch settings + BTN : in slv(BWIDTH-1 downto 0); -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end tst_snhumanio; + +architecture syn of tst_snhumanio is + + constant c_mode_rndm : slv2 := "00"; + constant c_mode_cnt : slv2 := "01"; + constant c_mode_swi : slv2 := "10"; + constant c_mode_btst : slv2 := "11"; + + type regs_type is record + mode : slv2; -- current mode + allon : slbit; -- all LEDs on if set + cnt : slv16; -- counter + tcnt : slv16; -- swi/btn toggle counter + rndm : slv8; -- random number + swi_1 : slv8; -- last SWI state + btn_1 : slv(BWIDTH-1 downto 0); -- last BTN state + led : slv8; -- LED output state + dsp : slv16; -- display data + dp : slv4; -- display decimal points + end record regs_type; + + -- the rndm start value is /= 0 because a seed of 0 with a SWI setting of 0 + -- will result in a 0-0-0 sequence. The 01010101 start will get trapped in a + -- constant sequence with a 01100011 switch setting, which is rather unlikely. + constant rndminit : slv8 := "01010101"; + + constant btnzero : slv(BWIDTH-1 downto 0) := (others=>'0'); + + constant regs_init : regs_type := ( + c_mode_rndm, -- mode + '0', -- allon + (others=>'0'), -- cnt + (others=>'0'), -- tcnt + rndminit, -- rndm + (others=>'0'), -- swi_1 + btnzero, -- btn_1 + (others=>'0'), -- led + (others=>'0'), -- dsp + (others=>'0') -- dp + + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal BTN4 : slbit := '0'; + +begin + + assert BWIDTH>=4 + report "assert(BWIDTH>=4): at least 4 BTNs available" + severity failure; + + B4YES: if BWIDTH > 4 generate + BTN4 <= BTN(4); + end generate B4YES; + B4NO: if BWIDTH = 4 generate + BTN4 <= '0'; + end generate B4NO; + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, SWI, BTN, BTN4) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable btn03 : slv4 := (others=>'0'); + + begin + r := R_REGS; + n := R_REGS; + + n.swi_1 := SWI; + n.btn_1 := BTN; + + if SWI/=r.swi_1 or BTN/=r.btn_1 then + n.tcnt := slv(unsigned(r.tcnt) + 1); + end if; + + btn03 := BTN(3 downto 0); + n.allon := BTN4; + + if unsigned(BTN) /= 0 then -- is a button being pressed ? + if r.mode /= c_mode_btst then -- not in btst mode + case btn03 is + when "0001" => -- 0001 single button -> rndm mode + n.mode := c_mode_rndm; + n.rndm := rndminit; + + when "0010" => -- 0010 single button -> cnt mode + n.mode := c_mode_cnt; + + when "0100" => -- 0100 single button -> swi mode + n.mode := c_mode_swi; + + when "1000" => -- 1001 single button -> btst mode + n.mode := c_mode_btst; + n.tcnt := (others=>'0'); + + when others => -- any 2+ button combo -> led test + n.allon := '1'; + end case; + + else -- button press in btst mode + + case btn03 is + when "1001" => -- 1001 double btn -> rndm mode + n.mode := c_mode_rndm; + when "1010" => -- 1010 double btn -> rndm cnt + n.mode := c_mode_cnt; + when "1100" => -- 1100 double btn -> rndm swi + n.mode := c_mode_swi; + when others => null; + end case; + + end if; + + else -- no button being pressed + + if CE_MSEC = '1' then -- on every usec + n.cnt := slv(unsigned(r.cnt) + 1); -- inc counter + if unsigned(r.cnt(8 downto 0)) = 0 then -- every 1/2 sec (approx.) + n.rndm := crc8_update(r.rndm, SWI); -- update rndm state + end if; + end if; + end if; + + if r.allon = '1' then -- if led test selected + n.led := (others=>'1'); -- all led,dsp,dp on + n.dsp := (others=>'1'); + n.dp := (others=>'1'); + + else -- no led test, normal output + + case r.mode is + when c_mode_rndm => + n.led := r.rndm; + n.dsp(7 downto 0) := r.rndm; + n.dsp(15 downto 8) := not r.rndm; + + when c_mode_cnt => + n.led := r.cnt(14 downto 7); + n.dsp := r.cnt; + + when c_mode_swi => + n.led := SWI; + n.dsp(7 downto 0) := SWI; + n.dsp(15 downto 8) := not SWI; + + when c_mode_btst => + n.led := SWI; + n.dsp := r.tcnt; + + when others => null; + end case; + + n.dp := BTN(3 downto 0); + + end if; + + N_REGS <= n; + + LED <= r.led; + DSP_DAT <= r.dsp; + DSP_DP <= r.dp; + + end process proc_next; + + +end syn; Index: tst_snhumanio/tst_snhumanio.vbom =================================================================== --- tst_snhumanio/tst_snhumanio.vbom (nonexistent) +++ tst_snhumanio/tst_snhumanio.vbom (revision 24) @@ -0,0 +1,6 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/comlib/comlib.vhd +# components +# design +tst_snhumanio.vhd Index: tst_snhumanio =================================================================== --- tst_snhumanio (nonexistent) +++ tst_snhumanio (revision 24)
tst_snhumanio Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_serloop/tst_serloop.vbom =================================================================== --- tst_serloop/tst_serloop.vbom (nonexistent) +++ tst_serloop/tst_serloop.vbom (revision 24) @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/serport/serportlib.vbom +tst_serlooplib.vhd +# components +# design +tst_serloop.vhd Index: tst_serloop/tst_serlooplib.vhd =================================================================== --- tst_serloop/tst_serlooplib.vhd (nonexistent) +++ tst_serloop/tst_serlooplib.vhd (revision 24) @@ -0,0 +1,111 @@ +-- $Id: tst_serlooplib.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: tst_serlooplib +-- Description: Definitions for tst_serloop records and helpers +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-10 438 1.0.2 add rxui(cnt|dat) fields in hio_stat_type +-- 2011-12-09 437 1.0.1 rename serport stat->moni port +-- 2011-10-14 416 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; +use work.serportlib.all; + +package tst_serlooplib is + + constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity) + constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity) + constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx) + constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back) + + type hio_cntl_type is record -- humanio controls + mode : slv2; -- mode (idle,(tx|tx)blast,loop) + enaxon : slbit; -- enable xon/xoff handling + enaesc : slbit; -- enable xon/xoff escaping + enathrottle : slbit; -- enable 1 msec tx throttling + enaftdi : slbit; -- enable ftdi flush handling + end record hio_cntl_type; + + constant hio_cntl_init : hio_cntl_type := ( + c_mode_idle, -- mode + '0','0','0','0' -- enaxon,enaesc,enathrottle,enaftdi + ); + + type hio_stat_type is record -- humanio status + rxfecnt : slv16; -- rx frame error counter + rxoecnt : slv16; -- rx overrun error counter + rxsecnt : slv16; -- rx sequence error counter + rxcnt : slv32; -- rx char counter + txcnt : slv32; -- tx char counter + rxuicnt : slv8; -- rx unsolicited input counter + rxuidat : slv8; -- rx unsolicited input data + rxokcnt : slv16; -- rxok 1->0 transition counter + txokcnt : slv16; -- txok 1->0 transition counter + end record hio_stat_type; + + constant hio_stat_init : hio_stat_type := ( + (others=>'0'), -- rxfecnt + (others=>'0'), -- rxoecnt + (others=>'0'), -- rxsecnt + (others=>'0'), -- rxcnt + (others=>'0'), -- txcnt + (others=>'0'), -- rxuicnt + (others=>'0'), -- rxuidat + (others=>'0'), -- rxokcnt + (others=>'0') -- txokcnt + ); + +-- ------------------------------------- + +component tst_serloop is -- tester for serport components + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + HIO_CNTL : in hio_cntl_type; -- humanio controls + HIO_STAT : out hio_stat_type; -- humanio status + SER_MONI : in serport_moni_type; -- serport monitor + RXDATA : in slv8; -- receiver data out + RXVAL : in slbit; -- receiver data valid + RXHOLD : out slbit; -- receiver data hold + TXDATA : out slv8; -- transmit data in + TXENA : out slbit; -- transmit data enable + TXBUSY : in slbit -- transmit busy + ); +end component; + +component tst_serloop_hiomap is -- default human I/O mapper + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + HIO_CNTL : out hio_cntl_type; -- tester controls from hio + HIO_STAT : in hio_stat_type; -- tester status to display by hio + SER_MONI : in serport_moni_type; -- serport monitor to display by hio + SWI : in slv8; -- switch settings + BTN : in slv4; -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end component; + +end package tst_serlooplib; Index: tst_serloop/tb/tb_tst_serloop.vhd =================================================================== --- tst_serloop/tb/tb_tst_serloop.vhd (nonexistent) +++ tst_serloop/tb/tb_tst_serloop.vhd (revision 24) @@ -0,0 +1,562 @@ +-- $Id: tb_tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop - sim +-- Description: Generic test bench for sys_tst_serloop_xx +-- +-- Dependencies: vlib/simlib/simclkcnt +-- vlib/serport/serport_uart_rxtx +-- vlib/serport/serport_xontx +-- +-- To test: sys_tst_serloop_xx +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 use new simclkcnt +-- 2011-11-13 425 1.0 Initial version +-- 2011-11-06 420 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; +use work.serportlib.all; + +entity tb_tst_serloop is + port ( + CLKS : in slbit; -- clock for serport + CLKH : in slbit; -- clock for humanio + CLK_STOP : out slbit; -- clock stop + P0_RXD : out slbit; -- port 0 receive data (board view) + P0_TXD : in slbit; -- port 0 transmit data (board view) + P0_RTS_N : in slbit; -- port 0 rts_n + P0_CTS_N : out slbit; -- port 0 cts_n + P1_RXD : out slbit; -- port 1 receive data (board view) + P1_TXD : in slbit; -- port 1 transmit data (board view) + P1_RTS_N : in slbit; -- port 1 rts_n + P1_CTS_N : out slbit; -- port 1 cts_n + SWI : out slv8; -- hio switches + BTN : out slv4 -- hio buttons + ); +end tb_tst_serloop; + +architecture sim of tb_tst_serloop is + + signal CLK_STOP_L : slbit := '0'; + signal CLK_CYCLE : integer := 0; + + signal UART_RESET : slbit := '0'; + signal UART_RXD : slbit := '1'; + signal UART_TXD : slbit := '1'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal CLKDIV : slv13 := (others=>'0'); + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXERR : slbit := '0'; + signal RXACT : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal UART_TXDATA : slv8 := (others=>'0'); + signal UART_TXENA : slbit := '0'; + signal UART_TXBUSY : slbit := '0'; + + signal ACTPORT : slbit := '0'; + signal BREAK : slbit := '0'; + + signal CTS_CYCLE : integer := 0; + signal CTS_FRACT : integer := 0; + signal XON_CYCLE : integer := 0; + signal XON_FRACT : integer := 0; + + signal S2M_ACTIVE : slbit := '0'; + signal S2M_SIZE : integer := 0; + signal S2M_ENAESC : slbit := '0'; + signal S2M_ENAXON : slbit := '0'; + + signal M2S_XONSEEN : slbit := '0'; + signal M2S_XOFFSEEN : slbit := '0'; + + signal R_XONRXOK : slbit := '1'; + signal R_XONTXOK : slbit := '1'; + +begin + + CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE); + + UART : serport_uart_rxtx + generic map ( + CDWIDTH => 13) + port map ( + CLK => CLKS, + RESET => UART_RESET, + CLKDIV => CLKDIV, + RXSD => UART_RXD, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXERR => RXERR, + RXACT => RXACT, + TXSD => UART_TXD, + TXDATA => UART_TXDATA, + TXENA => UART_TXENA, + TXBUSY => UART_TXBUSY + ); + + XONTX : serport_xontx + port map ( + CLK => CLKS, + RESET => UART_RESET, + ENAXON => S2M_ENAXON, + ENAESC => S2M_ENAESC, + UART_TXDATA => UART_TXDATA, + UART_TXENA => UART_TXENA, + UART_TXBUSY => UART_TXBUSY, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + RXOK => R_XONRXOK, + TXOK => R_XONTXOK + ); + + proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N, + P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N) + variable eff_txd : slbit := '0'; + begin + + if BREAK = '0' then -- if no break active + eff_txd := UART_TXD; -- send uart + else -- otherwise + eff_txd := '0'; -- force '0' + end if; + + if ACTPORT = '0' then -- use port 0 + P0_RXD <= eff_txd; -- write port 0 inputs + P0_CTS_N <= CTS_N; + UART_RXD <= P0_TXD; -- get port 0 outputs + RTS_N <= P0_RTS_N; + P1_RXD <= '1'; -- port 1 inputs to idle state + P1_CTS_N <= '0'; + else -- use port 1 + P1_RXD <= eff_txd; -- write port 1 inputs + P1_CTS_N <= CTS_N; + UART_RXD <= P1_TXD; -- get port 1 outputs + RTS_N <= P1_RTS_N; + P0_RXD <= '1'; -- port 0 inputs to idle state + P0_CTS_N <= '0'; + end if; + end process proc_port_mux; + + proc_cts: process(CLKS) + variable cts_timer : integer := 0; + begin + + if rising_edge(CLKS) then + if CTS_CYCLE = 0 then -- if cts throttle off + CTS_N <= '0'; -- cts permanently asserted + + else -- otherwise determine throttling + + if cts_timer>0 and cts_timer0 and xon_timer'0'); + variable btn_num : integer := 0; + variable i_cycle : integer := 0; + variable i_fract : integer := 0; + variable nbyte : integer := 0; + variable enaesc : slbit := '0'; + variable enaxon : slbit := '0'; + variable bcnt : integer := 0; + variable itxdata : slv8 := (others=>'0'); + variable ok : boolean; + variable dname : string(1 to 6) := (others=>' '); + + procedure waitclk(ncyc : in integer) is + begin + for i in 1 to ncyc loop + wait until rising_edge(CLKS); + end loop; -- i + end procedure waitclk; + + begin + + -- initialize some top level out signals + SWI <= (others=>'0'); + BTN <= (others=>'0'); + + wait until rising_edge(CLKS); + + file_loop: while not endfile(fstim) loop + + readline (fstim, iline); + + readcomment(iline, ok); + next file_loop when ok; + + readword(iline, dname, ok); + if ok then + case dname is + when "wait " => -- wait + read_ea(iline, idelta); + writetimestamp(oline, CLK_CYCLE, ": wait "); + write(oline, idelta, right, 5); + writeline(output, oline); + waitclk(idelta); + + when "port " => -- switch rs232 port + read_ea(iline, iactport); + ACTPORT <= iactport; + writetimestamp(oline, CLK_CYCLE, ": port "); + write(oline, iactport, right, 5); + writeline(output, oline); + + when "cts " => -- setup cts throttling + read_ea(iline, i_cycle); + read_ea(iline, i_fract); + CTS_CYCLE <= i_cycle; + CTS_FRACT <= i_fract; + writetimestamp(oline, CLK_CYCLE, ": cts "); + write(oline, i_cycle, right, 5); + write(oline, i_fract, right, 5); + writeline(output, oline); + + when "xon " => -- setup xon throttling + read_ea(iline, i_cycle); + read_ea(iline, i_fract); + XON_CYCLE <= i_cycle; + XON_FRACT <= i_fract; + writetimestamp(oline, CLK_CYCLE, ": cts "); + write(oline, i_cycle, right, 5); + write(oline, i_fract, right, 5); + writeline(output, oline); + + when "swi " => -- new SWI settings + read_ea(iline, iswi); + read_ea(iline, idelta); + writetimestamp(oline, CLK_CYCLE, ": swi "); + write(oline, iswi, right, 10); + write(oline, idelta, right, 5); + writeline(output, oline); + wait until rising_edge(CLKH); + SWI <= iswi; + wait until rising_edge(CLKS); + waitclk(idelta); + + when "btn " => -- BTN push (3 cyc down + 3 cyc wait) + read_ea(iline, btn_num); + read_ea(iline, idelta); + if btn_num>=0 and btn_num<=3 then + writetimestamp(oline, CLK_CYCLE, ": btn "); + write(oline, btn_num, right, 5); + write(oline, idelta, right, 5); + writeline(output, oline); + wait until rising_edge(CLKH); + BTN(btn_num) <= '1'; -- 3 cycle BTN pulse + wait until rising_edge(CLKH); + wait until rising_edge(CLKH); + wait until rising_edge(CLKH); + BTN(btn_num) <= '0'; + wait until rising_edge(CLKH); + wait until rising_edge(CLKH); + wait until rising_edge(CLKH); + wait until rising_edge(CLKS); + waitclk(idelta); + else + write(oline, string'("!! btn: btn number out of range")); + writeline(output, oline); + end if; + + when "expect" => -- expect n bytes data + read_ea(iline, nbyte); + read_ea(iline, enaesc); + read_ea(iline, enaxon); + writetimestamp(oline, CLK_CYCLE, ": expect"); + write(oline, nbyte, right, 5); + write(oline, enaesc, right, 3); + write(oline, enaxon, right, 3); + writeline(output, oline); + + if nbyte > 0 then + S2M_ACTIVE <= '1'; + S2M_SIZE <= nbyte; + else + S2M_ACTIVE <= '0'; + end if; + S2M_ENAESC <= enaesc; + S2M_ENAXON <= enaxon; + wait until rising_edge(CLKS); + + when "send " => -- send n bytes data + read_ea(iline, nbyte); + read_ea(iline, enaesc); + read_ea(iline, enaxon); + writetimestamp(oline, CLK_CYCLE, ": send "); + write(oline, nbyte, right, 5); + write(oline, enaesc, right, 3); + write(oline, enaxon, right, 3); + writeline(output, oline); + bcnt := 0; + itxdata := (others=>'0'); + + wait until falling_edge(CLKS); + while bcnt < nbyte loop + while TXBUSY='1' or RTS_N='1' loop + wait until falling_edge(CLKS); + end loop; + + TXDATA <= itxdata; + itxdata := slv(unsigned(itxdata) + 1); + bcnt := bcnt + 1; + + TXENA <= '1'; + wait until falling_edge(CLKS); + TXENA <= '0'; + wait until falling_edge(CLKS); + end loop; + while TXBUSY='1' or RTS_N='1' loop -- wait till last char send... + wait until falling_edge(CLKS); + end loop; + wait until rising_edge(CLKS); + + when "break " => -- send a break for n cycles + read_ea(iline, idelta); + writetimestamp(oline, CLK_CYCLE, ": break "); + write(oline, idelta, right, 5); + writeline(output, oline); + -- send break for n cycles + BREAK <= '1'; + waitclk(idelta); + BREAK <= '0'; + -- wait for 3 bit cell width + waitclk(3*to_integer(unsigned(CLKDIV)+1)); + -- send 'sync' character + wait until falling_edge(CLKS); + TXDATA <= "10000000"; + TXENA <= '1'; + wait until falling_edge(CLKS); + TXENA <= '0'; + wait until rising_edge(CLKS); + + when "clkdiv" => -- set new clock divider + read_ea(iline, idelta); + writetimestamp(oline, CLK_CYCLE, ": clkdiv"); + write(oline, idelta, right, 5); + writeline(output, oline); + CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length)); + UART_RESET <= '1'; + wait until rising_edge(CLKS); + UART_RESET <= '0'; + + when others => -- unknown command + write(oline, string'("?? unknown command: ")); + write(oline, dname); + writeline(output, oline); + report "aborting" severity failure; + end case; + + else + report "failed to find command" severity failure; + + end if; + + testempty_ea(iline); + end loop; -- file_loop + + writetimestamp(oline, CLK_CYCLE, ": DONE "); + writeline(output, oline); + + -- extra wait for at least two character times (20 bit times) + -- to allow tx and rx of the last character + waitclk(20*(to_integer(unsigned(CLKDIV))+1)); + + CLK_STOP_L <= '1'; + + wait for 500 ns; -- allows dcm's to stop + + wait; -- suspend proc_stim forever + -- clock is stopped, sim will end + + end process proc_stim; + + CLK_STOP <= CLK_STOP_L; + + proc_moni: process + variable oline : line; + variable dclk : integer := 0; + variable active_1 : slbit := '0'; + variable irxdata : slv8 := (others=>'0'); + variable irxeff : slv8 := (others=>'0'); + variable irxval : slbit := '0'; + variable doesc : slbit := '0'; + variable bcnt : integer := 0; + variable xseen : slbit := '0'; + begin + + loop + wait until falling_edge(CLKS); + + M2S_XONSEEN <= '0'; + M2S_XOFFSEEN <= '0'; + + if S2M_ACTIVE='1' and active_1='0' then -- start expect message + irxdata := (others=>'0'); + bcnt := 0; + end if; + + if S2M_ACTIVE='0' and active_1='1' then -- end expect message + if bcnt = S2M_SIZE then + writetimestamp(oline, CLK_CYCLE, ": OK: message seen"); + else + writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen="); + write(oline, bcnt, right, 5); + write(oline, string'(" expect=")); + write(oline, S2M_SIZE, right, 5); + end if; + writeline(output, oline); + end if; + + active_1 := S2M_ACTIVE; + + if RXVAL = '1' then + writetimestamp(oline, CLK_CYCLE, ": char: "); + write(oline, RXDATA, right, 10); + write(oline, string'(" (")); + writeoct(oline, RXDATA, right, 3); + write(oline, string'(") dt=")); + write(oline, dclk, right, 4); + + irxeff := RXDATA; + irxval := '1'; + if doesc = '1' then + irxeff := not RXDATA; + irxval := '1'; + doesc := '0'; + write(oline, string'(" eff=")); + write(oline, irxeff, right, 10); + write(oline, string'(" (")); + writeoct(oline, irxeff, right, 3); + write(oline, string'(")")); + elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then + doesc := '1'; + irxval := '0'; + write(oline, string'(" XESC seen")); + end if; + + xseen := '0'; + if S2M_ENAXON = '1' then + if RXDATA = c_serport_xon then + write(oline, string'(" XON seen")); + M2S_XONSEEN <= '1'; + xseen := '1'; + elsif RXDATA = c_serport_xoff then + write(oline, string'(" XOFF seen")); + M2S_XOFFSEEN <= '1'; + xseen := '1'; + end if; + end if; + + if S2M_ACTIVE='1' and irxval='1' and xseen='0' then + if irxeff = irxdata then + write(oline, string'(" OK")); + else + write(oline, string'(" FAIL: expect=")); + write(oline, irxdata, right, 10); + end if; + irxdata := slv(unsigned(irxdata) + 1); + bcnt := bcnt + 1; + end if; + + writeline(output, oline); + dclk := 0; + + end if; + + if RXERR = '1' then + writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'"); + writeline(output, oline); + end if; + + dclk := dclk + 1; + + end loop; + + end process proc_moni; + +end sim; Index: tst_serloop/tb/tb_tst_serloop.vbom =================================================================== --- tst_serloop/tb/tb_tst_serloop.vbom (nonexistent) +++ tst_serloop/tb/tb_tst_serloop.vbom (revision 24) @@ -0,0 +1,10 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/simlib/simlib.vhd +../../../vlib/serport/serportlib.vbom +# components +../../../vlib/simlib/simclkcnt.vbom +../../../vlib/serport/serport_uart_rxtx.vbom +../../../vlib/serport/serport_xontx.vbom +# design +tb_tst_serloop.vhd Index: tst_serloop/tb/tb_tst_serloop_stim.dat =================================================================== --- tst_serloop/tb/tb_tst_serloop_stim.dat (nonexistent) +++ tst_serloop/tb/tb_tst_serloop_stim.dat (revision 24) @@ -0,0 +1,124 @@ +# $Id: tb_tst_serloop_stim.dat 441 2011-12-20 17:01:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-06 420 1.0 Initial version +# +C ------------------------------------------------ +C try SWI settings +# only the 4 LBS (disp and enable control) +# don't touch the 2 mode settings here !! +# +wait 10 +# +swi 10000000 2 +swi 01000000 2 +swi 00100000 2 +swi 00010000 2 +swi 00000000 2 +wait 2 +# +C ------------------------------------------------ +C loop-back message with 16 bytes on port 0 +# +port 0 +swi 00000000 2 +btn 0 10 +# +# mode=11(loop); +swi 00000110 2 +btn 1 10 +# +expect 16 0 0 +send 16 0 0 +wait 100 +expect 0 0 0 +C ------------------------------------------------ +C loop-back message with 16 bytes on port 1 +# +port 1 +swi 00000001 2 +btn 0 10 +# +# mode=11(loop);port=1 +swi 00000111 2 +btn 1 10 +# +expect 16 0 0 +send 16 0 0 +wait 100 +expect 0 0 0 +# +C ------------------------------------------------ +C loop-back message with 32 bytes escaped on port 0 +# +port 0 +swi 00000000 2 +btn 0 10 +# +# enaesc=1; mode=11(loop) +swi 00100110 2 +btn 1 10 +# +expect 32 1 0 +send 32 1 0 +wait 100 +expect 0 0 0 +# +C ------------------------------------------------ +C loop-back message with 256 bytes escaped on port 1; cts throttle +# +port 1 +swi 00000001 2 +btn 0 10 +# +# enaesc=1; mode=11(loop); port=1 +swi 00100111 2 +btn 1 10 +# +cts 200 100 +expect 256 1 0 +send 256 1 0 +wait 1500 +expect 0 0 0 +cts 0 0 +# +C ------------------------------------------------ +C loop-back message with 256 bytes escaped on port 0; xon throttle +# +port 0 +swi 00000000 2 +btn 0 10 +# +# enaesc=1;enaxon=1; mode=11(loop); port=0 +swi 00110110 2 +btn 1 10 +# +xon 200 100 +expect 256 1 1 +send 256 1 1 +wait 1500 +expect 0 0 0 +xon 0 0 +C ------------------------------------------------ +C loop-back message with 256 bytes escaped on port 1; xon throttle +# +port 1 +swi 00000001 2 +btn 0 10 +# +# enaesc=1;enaxon=1; mode=11(loop); port=1 +swi 00110111 2 +btn 1 10 +# +xon 200 100 +expect 256 1 1 +send 256 1 1 +wait 1500 +expect 0 0 0 +xon 0 0 +# +C ------------------------------------------------ +C cool down +wait 200 + Index: tst_serloop/tb =================================================================== --- tst_serloop/tb (nonexistent) +++ tst_serloop/tb (revision 24)
tst_serloop/tb Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: tst_serloop/tst_serlooplib.vbom =================================================================== --- tst_serloop/tst_serlooplib.vbom (nonexistent) +++ tst_serloop/tst_serlooplib.vbom (revision 24) @@ -0,0 +1,3 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/serport/serportlib.vbom Index: tst_serloop/nexys2/tb/Makefile =================================================================== --- tst_serloop/nexys2/tb/Makefile (nonexistent) +++ tst_serloop/nexys2/tb/Makefile (revision 24) @@ -0,0 +1,34 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-13 424 1.0 Initial version +# +EXE_all = tb_tst_serloop1_n2 +EXE_all += tb_tst_serloop2_n2 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd =================================================================== --- tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd (nonexistent) +++ tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd (revision 24) @@ -0,0 +1,139 @@ +-- $Id: tb_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop1_n2 - sim +-- Description: Test bench for sys_tst_serloop1_n2 +-- +-- Dependencies: simlib/simclk +-- sys_tst_serloop2_n2 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop1_n2 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack +-- 2011-12-16 439 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; + +entity tb_tst_serloop1_n2 is +end tb_tst_serloop1_n2; + +architecture sim of tb_tst_serloop1_n2 is + + signal CLK50 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK50, + CLK_STOP => CLK_STOP + ); + + UUT : entity work.sys_tst_serloop1_n2 + port map ( + I_CLK50 => CLK50, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADV_N => open, + O_MEM_CLK => open, + O_MEM_CRE => open, + I_MEM_WAIT => '0', + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_FLA_CE_N => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLK50, + CLKH => CLK50, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd =================================================================== --- tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd (nonexistent) +++ tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vhd (revision 24) @@ -0,0 +1,167 @@ +-- $Id: tb_tst_serloop2_n2.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop2_n2 - sim +-- Description: Test bench for sys_tst_serloop2_n2 +-- +-- Dependencies: simlib/simclk +-- vlib/xlib/dcm_sfs +-- sys_tst_serloop2_n2 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop2_n2 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack +-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-13 424 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; + +entity tb_tst_serloop2_n2 is +end tb_tst_serloop2_n2; + +architecture sim of tb_tst_serloop2_n2 is + + signal CLK50 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CLKH : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK50, + CLK_STOP => CLK_STOP + ); + + DCM_S : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLK50, + CLKFX => CLKS, + LOCKED => open + ); + + DCM_H : dcm_sfs + generic map ( + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 4, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLK50, + CLKFX => CLKH, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop2_n2 + port map ( + I_CLK50 => CLK50, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADV_N => open, + O_MEM_CLK => open, + O_MEM_CRE => open, + I_MEM_WAIT => '0', + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_FLA_CE_N => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLKS, + CLKH => CLKH, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: tst_serloop/nexys2/tb/tbw.dat =================================================================== --- tst_serloop/nexys2/tb/tbw.dat (nonexistent) +++ tst_serloop/nexys2/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $ +# +[tb_tst_serloop1_n2] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat +[tb_tst_serloop2_n2] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat Index: tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom =================================================================== --- tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom (nonexistent) +++ tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vbom (revision 24) @@ -0,0 +1,11 @@ +# conf +sys_conf = sys_conf1_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../sys_tst_serloop1_n2.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n2.vhd Index: tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom =================================================================== --- tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom (nonexistent) +++ tst_serloop/nexys2/tb/tb_tst_serloop2_n2.vbom (revision 24) @@ -0,0 +1,13 @@ +# conf +sys_conf = sys_conf2_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/xlib/xlib.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/dcm_sfs_gsim.vbom +../sys_tst_serloop2_n2.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop2_n2.vhd Index: tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp =================================================================== --- tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp (nonexistent) +++ tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_serloop1_n2.ucf_cpp \ No newline at end of file
tst_serloop/nexys2/tb/sys_tst_serloop1_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp =================================================================== --- tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp (nonexistent) +++ tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_serloop2_n2.ucf_cpp \ No newline at end of file
tst_serloop/nexys2/tb/sys_tst_serloop2_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_serloop/nexys2/tb/sys_conf1_sim.vhd =================================================================== --- tst_serloop/nexys2/tb/sys_conf1_sim.vhd (nonexistent) +++ tst_serloop/nexys2/tb/sys_conf1_sim.vhd (revision 24) @@ -0,0 +1,43 @@ +-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n2 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-16 439 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 10 cycles (0.2 usec) and a msec + -- to 50 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkdiv_usecdiv : integer := 10; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: tst_serloop/nexys2/tb/sys_conf2_sim.vhd =================================================================== --- tst_serloop/nexys2/tb/sys_conf2_sim.vhd (nonexistent) +++ tst_serloop/nexys2/tb/sys_conf2_sim.vhd (revision 24) @@ -0,0 +1,44 @@ +-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop2_n2 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-13 424 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec + -- to 60 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec + constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: tst_serloop/nexys2/tb/.cvsignore =================================================================== --- tst_serloop/nexys2/tb/.cvsignore (nonexistent) +++ tst_serloop/nexys2/tb/.cvsignore (revision 24) @@ -0,0 +1,10 @@ +tb_tst_serloop1_n2 +tb_tst_serloop1_n2_[sft]sim +tb_tst_serloop1_n2_ISim +tb_tst_serloop1_n2_ISim_[sft]sim +tb_tst_serloop2_n2 +tb_tst_serloop2_n2_[sft]sim +tb_tst_serloop2_n2_ISim +tb_tst_serloop2_n2_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: tst_serloop/nexys2/tb =================================================================== --- tst_serloop/nexys2/tb (nonexistent) +++ tst_serloop/nexys2/tb (revision 24)
tst_serloop/nexys2/tb Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_serloop1_n2 +tb_tst_serloop1_n2_[sft]sim +tb_tst_serloop1_n2_ISim +tb_tst_serloop1_n2_ISim_[sft]sim +tb_tst_serloop2_n2 +tb_tst_serloop2_n2_[sft]sim +tb_tst_serloop2_n2_ISim +tb_tst_serloop2_n2_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: tst_serloop/nexys2/sys_tst_serloop1_n2.vhd =================================================================== --- tst_serloop/nexys2/sys_tst_serloop1_n2.vhd (nonexistent) +++ tst_serloop/nexys2/sys_tst_serloop1_n2.vhd (revision 24) @@ -0,0 +1,241 @@ +-- $Id: sys_tst_serloop1_n2.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_n2 - syn +-- Description: Tester serial link for nexys2 +-- +-- Dependencies: genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-16 439 13.1 O40d xc3s1200e-4 433 634 64 490 t 13.1 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 remove clksys output hack +-- 2011-12-16 439 1.0 Initial version +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop1_n2 is -- top level + -- implements nexys2_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop1_n2; + +architecture syn of sys_tst_serloop1_n2 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + CLK <= I_CLK50; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: tst_serloop/nexys2/sys_tst_serloop2_n2.vhd =================================================================== --- tst_serloop/nexys2/sys_tst_serloop2_n2.vhd (nonexistent) +++ tst_serloop/nexys2/sys_tst_serloop2_n2.vhd (revision 24) @@ -0,0 +1,284 @@ +-- $Id: sys_tst_serloop2_n2.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop2_n2 - syn +-- Description: Tester serial link for nexys2 +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_2clock +-- tst_serloop +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-16 439 13.1 O40d xc3s1200e-4 516 696 64 575 t xx.x +-- 2011-11-16 426 13.1 O40d xc3s1200e-4 494 661 64 547 t xx.x +-- 2011-11-13 425 13.1 O40d xc3s1200e-4 487 645 64 532 t xx.x +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 remove clksys output hack +-- 2011-12-09 437 1.0.4 rename serport stat->moni port +-- 2011-11-26 433 1.0.3 use nx_cram_dummy now +-- 2011-11-23 432 1.0.2 update O_FLA_CE_N usage +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-12 423 1.0 Initial version +-- 2011-11-09 422 0.5 First draft +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop2_n2 is -- top level + -- implements nexys2_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop2_n2; + +architecture syn of sys_tst_serloop2_n2 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal CLKS : slbit := '0'; + signal CES_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + DCM_U : dcm_sfs + generic map ( + CLKFX_DIVIDE => 2, + CLKFX_MULTIPLY => 4, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV_U : clkdivce + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 100 sim: 20 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + DCM_S : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLKS, + LOCKED => open + ); + + CLKDIV_S : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLKS, + CE_USEC => open, + CE_MSEC => CES_MSEC + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLKS, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_2clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLKU => CLK, + RESET => RESET, + CLKS => CLKS, + CES_MSEC => CES_MSEC, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_FLA_CE_N <= '1'; -- keep Flash memory disabled + +end syn; Index: tst_serloop/nexys2/Makefile =================================================================== --- tst_serloop/nexys2/Makefile (nonexistent) +++ tst_serloop/nexys2/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-09 422 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys2.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_serloop/nexys2/sys_tst_serloop1_n2.vbom =================================================================== --- tst_serloop/nexys2/sys_tst_serloop1_n2.vbom (nonexistent) +++ tst_serloop/nexys2/sys_tst_serloop1_n2.vbom (revision 24) @@ -0,0 +1,19 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf1.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_serloop1_n2.vhd +@ucf_cpp: sys_tst_serloop1_n2.ucf Index: tst_serloop/nexys2/sys_tst_serloop2_n2.vbom =================================================================== --- tst_serloop/nexys2/sys_tst_serloop2_n2.vbom (nonexistent) +++ tst_serloop/nexys2/sys_tst_serloop2_n2.vbom (revision 24) @@ -0,0 +1,22 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf2.vhd} +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_2clock.vbom +../tst_serloop.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_serloop2_n2.vhd +@ucf_cpp: sys_tst_serloop2_n2.ucf Index: tst_serloop/nexys2/sys_conf1.vhd =================================================================== --- tst_serloop/nexys2/sys_conf1.vhd (nonexistent) +++ tst_serloop/nexys2/sys_conf1.vhd (revision 24) @@ -0,0 +1,37 @@ +-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-16 439 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkdiv_usecdiv : integer := 50; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 434-1; -- 50000000/115200 + +end package sys_conf; Index: tst_serloop/nexys2/sys_conf2.vhd =================================================================== --- tst_serloop/nexys2/sys_conf2.vhd (nonexistent) +++ tst_serloop/nexys2/sys_conf2.vhd (revision 24) @@ -0,0 +1,39 @@ +-- $Id: sys_conf2.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop2_n2 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-13 424 1.0 Initial version +-- 2011-10-25 419 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkudiv_usecdiv : integer := 100; -- default usec + constant sys_conf_clksdiv_usecdiv : integer := 60; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200 + +end package sys_conf; Index: tst_serloop/nexys2/sys_tst_serloop1_n2.ucf_cpp =================================================================== --- tst_serloop/nexys2/sys_tst_serloop1_n2.ucf_cpp (nonexistent) +++ tst_serloop/nexys2/sys_tst_serloop1_n2.ucf_cpp (revision 24) @@ -0,0 +1,19 @@ +## $Id: sys_tst_serloop1_n2.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-16 439 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" Index: tst_serloop/nexys2/sys_tst_serloop2_n2.ucf_cpp =================================================================== --- tst_serloop/nexys2/sys_tst_serloop2_n2.ucf_cpp (nonexistent) +++ tst_serloop/nexys2/sys_tst_serloop2_n2.ucf_cpp (revision 24) @@ -0,0 +1,32 @@ +## $Id: sys_tst_serloop2_n2.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-16 439 1.0.1 set maxdelay clk-clks to 12 ns +## 2011-09-17 410 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## rules to prevent default 'cross clock' constraints for the dcm generated +## clocks CLK(100 MHz) and CLKS(60 MHz). All essential domain crossing done +## via fifo's or dedicated capture/synch flops. + +NET "CLK" TNM_NET = "CLK"; +NET "CLKS" TNM_NET = "CLKS"; +TIMESPEC "TS_CDC_CLK_CLKS" = FROM "CLK" TO "CLKS" 12 ns; +TIMESPEC "TS_CDC_CLKS_CLK" = FROM "CLKS" TO "CLK" 12 ns; + +## rule to allow that two DCMs are driven by one clock pin. +NET "I_CLK50" CLOCK_DEDICATED_ROUTE = FALSE; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" Index: tst_serloop/nexys2/.cvsignore =================================================================== --- tst_serloop/nexys2/.cvsignore (nonexistent) +++ tst_serloop/nexys2/.cvsignore (revision 24) @@ -0,0 +1,5 @@ +_impactbatch.log +sys_tst_serloop1_n2.ucf +sys_tst_serloop2_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_serloop/nexys2 =================================================================== --- tst_serloop/nexys2 (nonexistent) +++ tst_serloop/nexys2 (revision 24)
tst_serloop/nexys2 Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_serloop1_n2.ucf +sys_tst_serloop2_n2.ucf +*.dep_ucf_cpp +*.svf Index: tst_serloop/nexys3/tb/Makefile =================================================================== --- tst_serloop/nexys3/tb/Makefile (nonexistent) +++ tst_serloop/nexys3/tb/Makefile (revision 24) @@ -0,0 +1,34 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-12-11 438 1.0.1 added tb_tst_serloop1_n3 +# 2011-11-27 433 1.0 Initial version +# +EXE_all = tb_tst_serloop1_n3 +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd =================================================================== --- tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd (nonexistent) +++ tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vhd (revision 24) @@ -0,0 +1,139 @@ +-- $Id: tb_tst_serloop1_n3.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop1_n3 - sim +-- Description: Test bench for sys_tst_serloop1_n3 +-- +-- Dependencies: simlib/simclk +-- sys_tst_serloop1_n3 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop1_n3 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 use new simclk +-- 2011-12-11 438 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.simlib.all; + +entity tb_tst_serloop1_n3 is +end tb_tst_serloop1_n3; + +architecture sim of tb_tst_serloop1_n3 is + + signal CLK100 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv5 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 10 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK100, + CLK_STOP => CLK_STOP + ); + + UUT : entity work.sys_tst_serloop1_n3 + port map ( + I_CLK100 => CLK100, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADV_N => open, + O_MEM_CLK => open, + O_MEM_CRE => open, + I_MEM_WAIT => '0', + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_PPCM_CE_N => open, + O_PPCM_RST_N => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLK100, + CLKH => CLK100, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN(3 downto 0) + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: tst_serloop/nexys3/tb/tbw.dat =================================================================== --- tst_serloop/nexys3/tb/tbw.dat (nonexistent) +++ tst_serloop/nexys3/tb/tbw.dat (revision 24) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $ +# +[tb_tst_serloop1_n3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat +[tb_tst_serloop2_n3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat Index: tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom =================================================================== --- tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom (nonexistent) +++ tst_serloop/nexys3/tb/tb_tst_serloop1_n3.vbom (revision 24) @@ -0,0 +1,11 @@ +# conf +sys_conf = sys_conf1_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../sys_tst_serloop1_n3.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop1_n3.vhd Index: tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp =================================================================== --- tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp (nonexistent) +++ tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_serloop1_n3.ucf_cpp \ No newline at end of file
tst_serloop/nexys3/tb/sys_tst_serloop1_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_serloop/nexys3/tb/sys_conf1_sim.vhd =================================================================== --- tst_serloop/nexys3/tb/sys_conf1_sim.vhd (nonexistent) +++ tst_serloop/nexys3/tb/sys_conf1_sim.vhd (revision 24) @@ -0,0 +1,43 @@ +-- $Id: sys_conf1_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n3 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-11 438 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 20 cycles (0.2 usec) and a msec + -- to 100 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkdiv_usecdiv : integer := 20; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: tst_serloop/nexys3/tb/.cvsignore =================================================================== --- tst_serloop/nexys3/tb/.cvsignore (nonexistent) +++ tst_serloop/nexys3/tb/.cvsignore (revision 24) @@ -0,0 +1,10 @@ +tb_tst_serloop1_n3 +tb_tst_serloop1_n3_[sft]sim +tb_tst_serloop1_n3_ISim +tb_tst_serloop1_n3_ISim_[sft]sim +tb_tst_serloop2_n3 +tb_tst_serloop2_n3_[sft]sim +tb_tst_serloop2_n3_ISim +tb_tst_serloop2_n3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: tst_serloop/nexys3/tb =================================================================== --- tst_serloop/nexys3/tb (nonexistent) +++ tst_serloop/nexys3/tb (revision 24)
tst_serloop/nexys3/tb Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_serloop1_n3 +tb_tst_serloop1_n3_[sft]sim +tb_tst_serloop1_n3_ISim +tb_tst_serloop1_n3_ISim_[sft]sim +tb_tst_serloop2_n3 +tb_tst_serloop2_n3_[sft]sim +tb_tst_serloop2_n3_ISim +tb_tst_serloop2_n3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: tst_serloop/nexys3/sys_tst_serloop1_n3.vhd =================================================================== --- tst_serloop/nexys3/sys_tst_serloop1_n3.vhd (nonexistent) +++ tst_serloop/nexys3/sys_tst_serloop1_n3.vhd (revision 24) @@ -0,0 +1,243 @@ +-- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop1_n3 - syn +-- Description: Tester serial link for nexys3 (serport_1clock case) +-- +-- Dependencies: genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- vlib/nxcramlib/nx_cram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3) +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.nxcramlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop1_n3 is -- top level + -- implements nexys3_fusp_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop1_n3; + +architecture syn of sys_tst_serloop1_n3 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + CLK <= I_CLK100; + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 8, + USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => open, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN(3 downto 0), + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + +end syn; Index: tst_serloop/nexys3/Makefile =================================================================== --- tst_serloop/nexys3/Makefile (nonexistent) +++ tst_serloop/nexys3/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-27 433 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_serloop/nexys3/sys_tst_serloop1_n3.vbom =================================================================== --- tst_serloop/nexys3/sys_tst_serloop1_n3.vbom (nonexistent) +++ tst_serloop/nexys3/sys_tst_serloop1_n3.vbom (revision 24) @@ -0,0 +1,20 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +${sys_conf := sys_conf1.vhd} +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +../../../bplib/nxcramlib/nx_cram_dummy.vbom +# design +sys_tst_serloop1_n3.vhd +@ucf_cpp: sys_tst_serloop1_n3.ucf Index: tst_serloop/nexys3/sys_conf1.vhd =================================================================== --- tst_serloop/nexys3/sys_conf1.vhd (nonexistent) +++ tst_serloop/nexys3/sys_conf1.vhd (revision 24) @@ -0,0 +1,37 @@ +-- $Id: sys_conf1.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop1_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 438 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkdiv_usecdiv : integer := 100; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 868-1; -- 100000000/115200 + +end package sys_conf; Index: tst_serloop/nexys3/sys_tst_serloop1_n3.ucf_cpp =================================================================== --- tst_serloop/nexys3/sys_tst_serloop1_n3.ucf_cpp (nonexistent) +++ tst_serloop/nexys3/sys_tst_serloop1_n3.ucf_cpp (revision 24) @@ -0,0 +1,19 @@ +## $Id: sys_tst_serloop1_n3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-12-09 438 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" Index: tst_serloop/nexys3/.cvsignore =================================================================== --- tst_serloop/nexys3/.cvsignore (nonexistent) +++ tst_serloop/nexys3/.cvsignore (revision 24) @@ -0,0 +1,5 @@ +_impactbatch.log +sys_tst_serloop1_n3.ucf +sys_tst_serloop2_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_serloop/nexys3 =================================================================== --- tst_serloop/nexys3 (nonexistent) +++ tst_serloop/nexys3 (revision 24)
tst_serloop/nexys3 Property changes : Added: svn:ignore ## -0,0 +1,37 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_serloop1_n3.ucf +sys_tst_serloop2_n3.ucf +*.dep_ucf_cpp +*.svf Index: tst_serloop/tst_serloop_hiomap.vhd =================================================================== --- tst_serloop/tst_serloop_hiomap.vhd (nonexistent) +++ tst_serloop/tst_serloop_hiomap.vhd (revision 24) @@ -0,0 +1,219 @@ +-- $Id: tst_serloop_hiomap.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_serloop_hiomap - syn +-- Description: default human I/O mapper +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 437 1.0.2 rename serport stat->moni port +-- 2011-11-16 426 1.0.1 setup leds and dps +-- 2011-11-05 420 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- Usage of Switches, Buttons, LEDs: +-- +-- BTN(3): -- unused -- +-- (2): -- unused -- +-- (1): load enables from SWI(7:4) +-- SWI(7) -> ENAFTDI +-- SWI(6) -> ENATHROTTLE +-- SWI(5) -> ENAESC +-- SWI(4) -> ENAXON +-- (0): reset state [!! decoded by top level design !!] +-- +-- SWI(7:4) select display or enable pattern (when BTN(1) pressed) +-- (3) -- unused -- +-- (2:1): mode 00 idle +-- 01 rxblast +-- 10 txblast +-- 11 loop +-- SWI(0) 0 -> main board RS232 port +-- 1 -> Pmod1 RS232 port +-- +-- LED(7) enaesc +-- (6) enaxon +-- (5) rxfecnt > 0 (frame error) +-- (4) rxoecnt > 0 (overrun error) +-- (3) rxsecnt > 0 (sequence error) +-- (2) abact (shows ab activity) +-- (1) (not rxok) or (not txok) (shows back preasure) +-- (0) rxact or txact (shows activity) +-- +-- DSP data as selected by SWI(7:4) +-- 0000 -> rxfecnt +-- 0001 -> rxoecnt +-- 0010 -> rxsecnt +-- 0100 -> rxcnt.l +-- 0101 -> rxcnt.h +-- 0110 -> txcnt.l +-- 0111 -> txcnt.h +-- 1000 -> rxokcnt +-- 1001 -> txokcnt +-- 1010 -> rxuicnt,rxuidat +-- 1111 -> abclkdiv +-- +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- (2): SER_MONI.txact (shows tx activity) +-- (1): not SER_MONI.rxok (shows rx back preasure) +-- (0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.tst_serlooplib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_serloop_hiomap is -- default human I/O mapper + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + HIO_CNTL : out hio_cntl_type; -- tester controls from hio + HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio + SER_MONI : in serport_moni_type; -- serport monitor to display by hio + SWI : in slv8; -- switch settings + BTN : in slv4; -- button settings + LED : out slv8; -- led data + DSP_DAT : out slv16; -- display data + DSP_DP : out slv4 -- display decimal points + ); +end tst_serloop_hiomap; + +architecture syn of tst_serloop_hiomap is + + type regs_type is record + enaxon : slbit; -- enable xon/xoff handling + enaesc : slbit; -- enable xon/xoff escaping + enathrottle : slbit; -- enable 1 msec tx throttling + enaftdi : slbit; -- enable ftdi flush handling + dspdat : slv16; -- display data + end record regs_type; + + constant regs_init : regs_type := ( + '0','0','0','0', -- enaxon,enaesc,enathrottle,enaftdi + (others=>'0') -- dspdat + + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, HIO_STAT, SER_MONI, SWI, BTN) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable icntl : hio_cntl_type := hio_cntl_init; + variable iled : slv8 := (others=>'0'); + variable idat : slv16 := (others=>'0'); + variable idp : slv4 := (others=>'0'); + + begin + + r := R_REGS; + n := R_REGS; + + icntl := hio_cntl_init; + iled := (others=>'0'); + idat := (others=>'0'); + idp := (others=>'0'); + + -- handle BTN(1) "load enables" press + + if BTN(1) = '1' then + n.enaxon := SWI(4); + n.enaesc := SWI(5); + n.enathrottle := SWI(6); + n.enaftdi := SWI(7); + end if; + + -- setup tester controls + + icntl.mode := SWI(2 downto 1); + icntl.enaxon := r.enaxon; + icntl.enaesc := r.enaesc; + icntl.enathrottle := r.enathrottle; + icntl.enaftdi := r.enaftdi; + + -- setup leds + iled(7) := icntl.enaesc; + iled(6) := icntl.enaxon; + if unsigned(HIO_STAT.rxfecnt) > 0 then iled(5) := '1'; end if; + if unsigned(HIO_STAT.rxoecnt) > 0 then iled(4) := '1'; end if; + if unsigned(HIO_STAT.rxsecnt) > 0 then iled(3) := '1'; end if; + iled(2) := SER_MONI.abact; + iled(1) := (not SER_MONI.rxok) or (not SER_MONI.txok); + iled(0) := SER_MONI.rxact or SER_MONI.txact; + + -- setup display data + + case SWI(7 downto 4) is + when "0000" => idat := HIO_STAT.rxfecnt; + when "0001" => idat := HIO_STAT.rxoecnt; + when "0010" => idat := HIO_STAT.rxsecnt; + when "0100" => idat := HIO_STAT.rxcnt(15 downto 0); + when "0101" => idat := HIO_STAT.rxcnt(31 downto 16); + when "0110" => idat := HIO_STAT.txcnt(15 downto 0); + when "0111" => idat := HIO_STAT.txcnt(31 downto 16); + when "1000" => idat := HIO_STAT.rxokcnt; + when "1001" => idat := HIO_STAT.txokcnt; + when "1010" => idat := HIO_STAT.rxuicnt & HIO_STAT.rxuidat; + when "1111" => idat := SER_MONI.abclkdiv; + when others => null; + end case; + n.dspdat := idat; + + -- setup display decimal points + + idp(3) := not SER_MONI.txok; -- tx back preasure + idp(2) := SER_MONI.txact; -- tx activity + idp(1) := not SER_MONI.rxok; -- rx back preasure + idp(0) := SER_MONI.rxact; -- rx activity + + N_REGS <= n; + + HIO_CNTL <= icntl; + LED <= iled; + DSP_DAT <= r.dspdat; + DSP_DP <= idp; + + end process proc_next; + +end syn; Index: tst_serloop/tst_serloop_hiomap.vbom =================================================================== --- tst_serloop/tst_serloop_hiomap.vbom (nonexistent) +++ tst_serloop/tst_serloop_hiomap.vbom (revision 24) @@ -0,0 +1,7 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/serport/serportlib.vbom +tst_serlooplib.vbom +# components +# design +tst_serloop_hiomap.vhd Index: tst_serloop/Makefile =================================================================== --- tst_serloop/Makefile (nonexistent) +++ tst_serloop/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-10-14 416 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean realclean +# +all : tst_serloop +# +clean : ise_clean +# +realclean : + rm -f tst_serloop +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: tst_serloop/s3board/sys_tst_serloop_s3.vhd =================================================================== --- tst_serloop/s3board/sys_tst_serloop_s3.vhd (nonexistent) +++ tst_serloop/s3board/sys_tst_serloop_s3.vhd (revision 24) @@ -0,0 +1,243 @@ +-- $Id: sys_tst_serloop_s3.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_tst_serloop_s3 - syn +-- Description: Tester serial link for s3board +-- +-- Dependencies: vlib/xlib/dcm_sfs +-- genlib/clkdivce +-- bpgen/bp_rs232_2l4l_iob +-- bpgen/sn_humanio +-- tst_serloop_hiomap +-- vlib/serport/serport_1clock +-- tst_serloop +-- s3board/s3_sram_dummy +-- +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2011-11-16 426 13.1 O40d xc3s1000-4 424 602 64 476 t 13.6 +-- 2011-11-13 425 13.1 O40d xc3s1000-4 421 586 64 466 t 13.6 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-09 437 1.0.2 rename serport stat->moni port +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-12 423 1.0 Initial version +-- 2011-10-25 419 0.5 First draft +------------------------------------------------------------------------------ +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.bpgenlib.all; +use work.tst_serlooplib.all; +use work.serportlib.all; +use work.s3boardlib.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_tst_serloop_s3 is -- top level + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_tst_serloop_s3; + +architecture syn of sys_tst_serloop_s3 is + + signal CLK : slbit := '0'; + signal RESET : slbit := '0'; + + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '0'; + signal TXD : slbit := '0'; + signal CTS_N : slbit := '0'; + signal RTS_N : slbit := '0'; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal HIO_CNTL : hio_cntl_type := hio_cntl_init; + signal HIO_STAT : hio_stat_type := hio_stat_init; + + signal RXDATA : slv8 := (others=>'0'); + signal RXVAL : slbit := '0'; + signal RXHOLD : slbit := '0'; + signal TXDATA : slv8 := (others=>'0'); + signal TXENA : slbit := '0'; + signal TXBUSY : slbit := '0'; + + signal SER_MONI : serport_moni_type := serport_moni_init; + +begin + + DCM : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => I_CLK50, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce + generic map ( + CDUWIDTH => 6, + USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 60 sim: 12 + MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + HIO : sn_humanio + generic map ( + DEBOUNCE => sys_conf_hio_debounce) + port map ( + CLK => CLK, + RESET => '0', + CE_MSEC => CE_MSEC, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RESET <= BTN(0); -- BTN(0) will reset tester !! + + HIOMAP : tst_serloop_hiomap + port map ( + CLK => CLK, + RESET => RESET, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP + ); + + IOB_RS232 : bp_rs232_2l4l_iob + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), -- port selection + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + SERPORT : serport_1clock + generic map ( + CDWIDTH => 15, + CDINIT => sys_conf_uart_cdinit, + RXFAWIDTH => 5, + TXFAWIDTH => 5) + port map ( + CLK => CLK, + CE_MSEC => CE_MSEC, + RESET => RESET, + ENAXON => HIO_CNTL.enaxon, + ENAESC => HIO_CNTL.enaesc, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY, + MONI => SER_MONI, + RXSD => RXD, + TXSD => TXD, + RXRTS_N => RTS_N, + TXCTS_N => CTS_N + ); + + TESTER : tst_serloop + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + HIO_CNTL => HIO_CNTL, + HIO_STAT => HIO_STAT, + SER_MONI => SER_MONI, + RXDATA => RXDATA, + RXVAL => RXVAL, + RXHOLD => RXHOLD, + TXDATA => TXDATA, + TXENA => TXENA, + TXBUSY => TXBUSY + ); + + SRAM : s3_sram_dummy -- connect SRAM to protection dummy + port map ( + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + +end syn; + Index: tst_serloop/s3board/sys_tst_serloop_s3.vbom =================================================================== --- tst_serloop/s3board/sys_tst_serloop_s3.vbom (nonexistent) +++ tst_serloop/s3board/sys_tst_serloop_s3.vbom (revision 24) @@ -0,0 +1,22 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../bplib/bpgen/bpgenlib.vbom +../tst_serlooplib.vbom +../../../vlib/serport/serportlib.vbom +../../../bplib/s3board/s3boardlib.vbom +${sys_conf := sys_conf.vhd} +# components +[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/bpgen/sn_humanio.vbom +../tst_serloop_hiomap.vbom +../../../vlib/serport/serport_1clock.vbom +../tst_serloop.vbom +../../../bplib/s3board/s3_sram_dummy.vbom +# design +sys_tst_serloop_s3.vhd +@ucf_cpp: sys_tst_serloop_s3.ucf Index: tst_serloop/s3board/tb/Makefile =================================================================== --- tst_serloop/s3board/tb/Makefile (nonexistent) +++ tst_serloop/s3board/tb/Makefile (revision 24) @@ -0,0 +1,33 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-05 420 1.0 Initial version +# +EXE_all = tb_tst_serloop_s3 +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean isim_clean +# +#----- +# +include $(RETROBASE)/rtl/make/generic_ghdl.mk +include $(RETROBASE)/rtl/make/generic_isim.mk +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(VBOM_all:.vbom=.dep_isim) +include $(wildcard *.o.dep_ghdl) +endif +# Index: tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd =================================================================== --- tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd (nonexistent) +++ tst_serloop/s3board/tb/tb_tst_serloop_s3.vhd (revision 24) @@ -0,0 +1,149 @@ +-- $Id: tb_tst_serloop_s3.vhd 444 2011-12-25 10:04:58Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_tst_serloop_s3 - sim +-- Description: Test bench for sys_tst_serloop_s3 +-- +-- Dependencies: simlib/simclk +-- vlib/xlib/dcm_sfs +-- sys_tst_serloop_s3 [UUT] +-- tb/tb_tst_serloop +-- +-- To test: sys_tst_serloop_s3 +-- +-- Target Devices: generic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-23 444 1.1 use new simclk +-- 2011-11-17 426 1.0.1 use dcm_sfs now +-- 2011-11-06 420 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.simlib.all; + +entity tb_tst_serloop_s3 is +end tb_tst_serloop_s3; + +architecture sim of tb_tst_serloop_s3 is + + signal CLK50 : slbit := '0'; + signal CLK_STOP : slbit := '0'; + + signal CLKS : slbit := '0'; + + signal I_RXD : slbit := '1'; + signal O_TXD : slbit := '1'; + signal I_SWI : slv8 := (others=>'0'); + signal I_BTN : slv4 := (others=>'0'); + + signal O_FUSP_RTS_N : slbit := '0'; + signal I_FUSP_CTS_N : slbit := '0'; + signal I_FUSP_RXD : slbit := '1'; + signal O_FUSP_TXD : slbit := '1'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '1'; + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + + signal FUSP_RTS_N : slbit := '0'; + signal FUSP_CTS_N : slbit := '0'; + signal FUSP_RXD : slbit := '1'; + signal FUSP_TXD : slbit := '1'; + + constant clock_period : time := 20 ns; + constant clock_offset : time := 200 ns; + constant delay_time : time := 2 ns; + +begin + + SYSCLK : simclk + generic map ( + PERIOD => clock_period, + OFFSET => clock_offset) + port map ( + CLK => CLK50, + CLK_STOP => CLK_STOP + ); + + DCM_S : dcm_sfs + generic map ( + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 6, + CLKIN_PERIOD => 20.0) + port map ( + CLKIN => CLK50, + CLKFX => CLKS, + LOCKED => open + ); + + UUT : entity work.sys_tst_serloop_s3 + port map ( + I_CLK50 => CLK50, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => open, + O_ANO_N => open, + O_SEG_N => open, + O_MEM_CE_N => open, + O_MEM_BE_N => open, + O_MEM_WE_N => open, + O_MEM_OE_N => open, + O_MEM_ADDR => open, + IO_MEM_DATA => open, + O_FUSP_RTS_N => O_FUSP_RTS_N, + I_FUSP_CTS_N => I_FUSP_CTS_N, + I_FUSP_RXD => I_FUSP_RXD, + O_FUSP_TXD => O_FUSP_TXD + ); + + GENTB : entity work.tb_tst_serloop + port map ( + CLKS => CLKS, + CLKH => CLKS, + CLK_STOP => CLK_STOP, + P0_RXD => RXD, + P0_TXD => TXD, + P0_RTS_N => '0', + P0_CTS_N => open, + P1_RXD => FUSP_RXD, + P1_TXD => FUSP_TXD, + P1_RTS_N => FUSP_RTS_N, + P1_CTS_N => FUSP_CTS_N, + SWI => SWI, + BTN => BTN + ); + + I_RXD <= RXD after delay_time; + TXD <= O_TXD after delay_time; + FUSP_RTS_N <= O_FUSP_RTS_N after delay_time; + I_FUSP_CTS_N <= FUSP_CTS_N after delay_time; + I_FUSP_RXD <= FUSP_RXD after delay_time; + FUSP_TXD <= O_FUSP_TXD after delay_time; + + I_SWI <= SWI after delay_time; + I_BTN <= BTN after delay_time; + +end sim; Index: tst_serloop/s3board/tb/tbw.dat =================================================================== --- tst_serloop/s3board/tb/tbw.dat (nonexistent) +++ tst_serloop/s3board/tb/tbw.dat (revision 24) @@ -0,0 +1,4 @@ +# $Id: tbw.dat 441 2011-12-20 17:01:16Z mueller $ +# +[tb_tst_serloop_s3] +tb_tst_serloop_stim = ../../tb/tb_tst_serloop_stim.dat Index: tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom =================================================================== --- tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom (nonexistent) +++ tst_serloop/s3board/tb/tb_tst_serloop_s3.vbom (revision 24) @@ -0,0 +1,13 @@ +# conf +sys_conf = sys_conf_sim.vhd +# libs +../../../../vlib/slvtypes.vhd +../../../../vlib/xlib/xlib.vhd +../../../../vlib/simlib/simlib.vhd +# components +../../../../vlib/simlib/simclk.vbom +../../../../vlib/xlib/dcm_sfs_gsim.vbom +../sys_tst_serloop_s3.vbom +../../tb/tb_tst_serloop.vbom +# design +tb_tst_serloop_s3.vhd Index: tst_serloop/s3board/tb/sys_conf_sim.vhd =================================================================== --- tst_serloop/s3board/tb/sys_conf_sim.vhd (nonexistent) +++ tst_serloop/s3board/tb/sys_conf_sim.vhd (revision 24) @@ -0,0 +1,43 @@ +-- $Id: sys_conf_sim.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop_s3 (for test bench) +-- +-- Dependencies: - +-- Tool versions: xst 11.4; ghdl 0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-05 420 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec + -- to 60 cycles (1 usec). This affects the pulse generators (usec) and + -- mainly the autobauder. A break will be detected after 128 msec periods, + -- this in simulation after 128 usec or 6400 cycles. This is compatible with + -- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles) + + constant sys_conf_clkdiv_usecdiv : integer := 12; -- shortened ! + constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened ! + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim + +end package sys_conf; Index: tst_serloop/s3board/tb/.cvsignore =================================================================== --- tst_serloop/s3board/tb/.cvsignore (nonexistent) +++ tst_serloop/s3board/tb/.cvsignore (revision 24) @@ -0,0 +1,6 @@ +tb_tst_serloop_s3 +tb_tst_serloop_s3_[sft]sim +tb_tst_serloop_s3_ISim +tb_tst_serloop_s3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp =================================================================== --- tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp (nonexistent) +++ tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp (revision 24) @@ -0,0 +1 @@ +link ../sys_tst_serloop_s3.ucf_cpp \ No newline at end of file
tst_serloop/s3board/tb/sys_tst_serloop_s3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: tst_serloop/s3board/tb =================================================================== --- tst_serloop/s3board/tb (nonexistent) +++ tst_serloop/s3board/tb (revision 24)
tst_serloop/s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_tst_serloop_s3 +tb_tst_serloop_s3_[sft]sim +tb_tst_serloop_s3_ISim +tb_tst_serloop_s3_ISim_[sft]sim +tb_tst_serloop_stim +*.dep_ucf_cpp Index: tst_serloop/s3board/Makefile =================================================================== --- tst_serloop/s3board/Makefile (nonexistent) +++ tst_serloop/s3board/Makefile (revision 24) @@ -0,0 +1,28 @@ +# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-10-14 416 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +include $(RETROBASE)/rtl/make/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: tst_serloop/s3board/sys_conf.vhd =================================================================== --- tst_serloop/s3board/sys_conf.vhd (nonexistent) +++ tst_serloop/s3board/sys_conf.vhd (revision 24) @@ -0,0 +1,38 @@ +-- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_tst_serloop_s3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1; ghdl 0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-13 424 1.0 Initial version +-- 2011-10-25 419 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + constant sys_conf_clkdiv_usecdiv : integer := 60; -- default usec + constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200 + +end package sys_conf; Index: tst_serloop/s3board/sys_tst_serloop_s3.mfset =================================================================== --- tst_serloop/s3board/sys_tst_serloop_s3.mfset (nonexistent) +++ tst_serloop/s3board/sys_tst_serloop_s3.mfset (revision 24) @@ -0,0 +1,34 @@ +# $Id: sys_tst_serloop_s3.mfset 441 2011-12-20 17:01:16Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'SIZE' of component 'fifo_1c_dram' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' + +Input > is never used +Input > is never used +Input > is never used +Input > is never used + +Signal > is assigned but never used +Signal is assigned but never used + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] Index: tst_serloop/s3board/.cvsignore =================================================================== --- tst_serloop/s3board/.cvsignore (nonexistent) +++ tst_serloop/s3board/.cvsignore (revision 24) @@ -0,0 +1,4 @@ +_impactbatch.log +sys_tst_serloop_s3.ucf +*.dep_ucf_cpp +*.svf Index: tst_serloop/s3board/sys_tst_serloop_s3.ucf_cpp =================================================================== --- tst_serloop/s3board/sys_tst_serloop_s3.ucf_cpp (nonexistent) +++ tst_serloop/s3board/sys_tst_serloop_s3.ucf_cpp (revision 24) @@ -0,0 +1,19 @@ +## $Id: sys_tst_serloop_s3.ucf_cpp 441 2011-12-20 17:01:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-10-25 419 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" +## +## Pmod1-RS232 on A2 connector +## +#include "bplib/s3board/s3board_a2_pm1_rs232.ucf" Index: tst_serloop/s3board =================================================================== --- tst_serloop/s3board (nonexistent) +++ tst_serloop/s3board (revision 24)
tst_serloop/s3board Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +_impactbatch.log +sys_tst_serloop_s3.ucf +*.dep_ucf_cpp +*.svf Index: tst_serloop/tst_serloop.vhd =================================================================== --- tst_serloop/tst_serloop.vhd (nonexistent) +++ tst_serloop/tst_serloop.vhd (revision 24) @@ -0,0 +1,241 @@ +-- $Id: tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $ +-- +-- Copyright 2011- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tst_serloop - syn +-- Description: simple stand-alone tester for serport components +-- +-- Dependencies: - +-- Test bench: - +-- +-- Target Devices: generic +-- Tool versions: xst 13.1; ghdl 0.29 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs +-- 2011-12-09 437 1.0.1 rename serport stat->moni port +-- 2011-11-06 420 1.0 Initial version +-- 2011-10-14 416 0.5 First draft +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.serportlib.all; +use work.tst_serlooplib.all; + +-- ---------------------------------------------------------------------------- + +entity tst_serloop is -- tester for serport components + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + CE_MSEC : in slbit; -- msec pulse + HIO_CNTL : in hio_cntl_type; -- humanio controls + HIO_STAT : out hio_stat_type; -- humanio status + SER_MONI : in serport_moni_type; -- serport monitor + RXDATA : in slv8; -- receiver data out + RXVAL : in slbit; -- receiver data valid + RXHOLD : out slbit; -- receiver data hold + TXDATA : out slv8; -- transmit data in + TXENA : out slbit; -- transmit data enable + TXBUSY : in slbit -- transmit busy + ); +end tst_serloop; + +architecture syn of tst_serloop is + + type regs_type is record + rxdata : slv8; -- next rx char + txdata : slv8; -- next tx char + rxfecnt : slv16; -- rx frame error counter + rxoecnt : slv16; -- rx overrun error counter + rxsecnt : slv16; -- rx sequence error counter + rxcnt : slv32; -- rx char counter + txcnt : slv32; -- tx char counter + rxuicnt : slv8; -- rx unsolicited input counter + rxuidat : slv8; -- rx unsolicited input data + rxokcnt : slv16; -- rxok 1->0 transition counter + txokcnt : slv16; -- txok 1->0 transition counter + rxok_1 : slbit; -- rxok last cycle + txok_1 : slbit; -- txok last cycle + rxthrottle : slbit; -- rx throttle flag + end record regs_type; + + constant regs_init : regs_type := ( + (others=>'0'), -- rxdata + (others=>'0'), -- txdata + (others=>'0'), -- rxfecnt + (others=>'0'), -- rxoecnt + (others=>'0'), -- rxsecnt + (others=>'0'), -- rxcnt + (others=>'0'), -- txcnt + (others=>'0'), -- rxuicnt + (others=>'0'), -- rxuidat + (others=>'0'), -- rxokcnt + (others=>'0'), -- txokcnt + '0','0', -- rxok_1,txok_1 + '0' -- rxthrottle + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + +begin + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI, + RXDATA, RXVAL, TXBUSY) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + + variable irxhold : slbit := '1'; + variable itxena : slbit := '0'; + variable itxdata : slv8 := (others=>'0'); + variable skipxon : slbit := '0'; + + function nextchar(skipxon: in slbit; data: in slv8) return slv8 is + variable inc : slv8 := (others=>'0'); + begin + inc := "00000001"; + if skipxon='1' and (data=c_serport_xon or data=c_serport_xoff) then + inc := "00000010"; + end if; + return slv(unsigned(data)+unsigned(inc)); + end function nextchar; + + begin + r := R_REGS; + n := R_REGS; + + irxhold := '1'; + itxena := '0'; + + itxdata := RXDATA; + if HIO_CNTL.mode = c_mode_txblast then + itxdata := r.txdata; + end if; + + skipxon := '0'; + if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then + skipxon := '1'; + end if; + + if HIO_CNTL.enathrottle = '1' then + if CE_MSEC = '1' then + n.rxthrottle := not r.rxthrottle; + end if; + else + n.rxthrottle := '0'; + end if; + + + case HIO_CNTL.mode is + when c_mode_idle => + null; + + when c_mode_rxblast => + if RXVAL='1' and r.rxthrottle='0' then + irxhold := '0'; + if RXDATA /= r.rxdata then + n.rxsecnt := slv(unsigned(r.rxsecnt) + 1); + end if; + n.rxdata := nextchar(skipxon, RXDATA); + end if; + + when c_mode_txblast => + if TXBUSY = '0' then + itxena := '1'; + n.txdata := nextchar(skipxon, r.txdata); + end if; + irxhold := '0'; + if RXVAL = '1' then + n.rxuicnt := slv(unsigned(r.rxuicnt) + 1); + n.rxuidat := RXDATA; + end if; + + when c_mode_loop => + if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then + irxhold := '0'; + itxena := '1'; + end if; + + when others => null; + end case; + + + if SER_MONI.abact = '1' then -- if auto bauder active + n.rxfecnt := (others=>'0'); -- reset frame error counter + else -- otherwise + if SER_MONI.rxerr = '1' then -- count rx frame errors + n.rxfecnt := slv(unsigned(r.rxfecnt) + 1); + end if; + end if; + + if SER_MONI.rxovr = '1' then + n.rxoecnt := slv(unsigned(r.rxoecnt) + 1); + end if; + + if RXVAL='1' and irxhold='0' then + n.rxcnt := slv(unsigned(r.rxcnt) + 1); + end if; + + if itxena = '1' then + n.txcnt := slv(unsigned(r.txcnt) + 1); + end if; + + n.rxok_1 := SER_MONI.rxok; + n.txok_1 := SER_MONI.txok; + + if SER_MONI.rxok='0' and r.rxok_1='1' then + n.rxokcnt := slv(unsigned(r.rxokcnt) + 1); + end if; + if SER_MONI.txok='0' and r.txok_1='1' then + n.txokcnt := slv(unsigned(r.txokcnt) + 1); + end if; + + N_REGS <= n; + + RXHOLD <= irxhold; + TXENA <= itxena; + TXDATA <= itxdata; + + HIO_STAT.rxfecnt <= r.rxfecnt; + HIO_STAT.rxoecnt <= r.rxoecnt; + HIO_STAT.rxsecnt <= r.rxsecnt; + HIO_STAT.rxcnt <= r.rxcnt; + HIO_STAT.txcnt <= r.txcnt; + HIO_STAT.rxuicnt <= r.rxuicnt; + HIO_STAT.rxuidat <= r.rxuidat; + HIO_STAT.rxokcnt <= r.rxokcnt; + HIO_STAT.txokcnt <= r.txokcnt; + + end process proc_next; + +end syn; Index: tst_serloop/.cvsignore =================================================================== --- tst_serloop/.cvsignore (nonexistent) +++ tst_serloop/.cvsignore (revision 24) @@ -0,0 +1 @@ +tst_serloop Index: tst_serloop =================================================================== --- tst_serloop (nonexistent) +++ tst_serloop (revision 24)
tst_serloop Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tst_serloop Index: . =================================================================== --- . (nonexistent) +++ . (revision 24)
. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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