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    /w11/tags/w11a_V0.6/rtl/vlib/memlib
    from Rev 19 to Rev 24
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Rev 19 → Rev 24

/Makefile
0,0 → 1,28
# $Id: Makefile 477 2013-01-27 14:07:10Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2011-08-13 405 1.1 use includes from rtl/make
# 2007-12-09 100 1.0.1 drop ISE_p definition
# 2007-06-03 45 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
NGC_all = $(VBOM_all:.vbom=.ngc)
#
# reference board for test synthesis is Spartan-6 based Nexys3
include $(RETROBASE)/rtl/make/xflow_default_nexys3.mk
#
.PHONY : all clean
#
all : $(NGC_all)
#
clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
endif
#
/fifo_2c_dram.vbom
0,0 → 1,11
# libs
../slvtypes.vhd
../genlib/genlib.vhd
memlib.vhd
# components
[ghdl,isim]ram_1swar_1ar_gen.vbom
[xst]ram_1swar_1ar_gen_unisim.vbom
../genlib/gray_cnt_gen.vbom
../genlib/gray2bin_gen.vbom
# design
fifo_2c_dram.vhd
/fifo_2c_dram.vhd
0,0 → 1,336
-- $Id: fifo_2c_dram.vhd 424 2011-11-13 16:38:23Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram - syn
-- Description: FIFO, two clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: ram_1swar_1ar_gen
-- genlib/gray_cnt_n
-- genlib/gray2bin_gen
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-12-28 107 1.0.1 VAL=0 in cycle after RESETR=1
-- 2007-12-28 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2011-11-13 Rev 424: ise 13.1 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m LUT.s Flop Slice CLKW CLKR (xst est.)
-- 4 16 41 32 12 38 54 135MHz 115MHz ( 16 words)
-- 5 16 65 64 14 40 80 113MHz 116MHz ( 32 words)
-- - 2007-12-28 Rev 106: ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop CLKW CLKR (xst est.)
-- 4 16 40 32 42 141MHz 165MHz ( 16 words)
-- 5 16 65 64 52 108MHz 108MHz ( 32 words)
-- 6 16 95 128 61 111MHz 113MHz ( 64 words)
-- 7 16 149 256 74 100MHz 96MHz (128 words)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.genlib.all;
use work.memlib.all;
 
entity fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 5; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end fifo_2c_dram;
 
 
architecture syn of fifo_2c_dram is
 
type regw_type is record
raddr_c : slv(AWIDTH-1 downto 0); -- read address (capt from CLKR)
raddr_s : slv(AWIDTH-1 downto 0); -- read address (sync in CLKW)
sizew : slv(AWIDTH-1 downto 0); -- slots to write
busy : slbit; -- busy flag
rstw : slbit; -- resetw active
rstw_sc : slbit; -- resetw (sync-capt from CLKR-CLKW)
rstw_ss : slbit; -- resetw (sync-sync from CLKR-CLKW)
rstr_c : slbit; -- resetr (capt from CLKR)
rstr_s : slbit; -- resetr (sync from CLKR)
end record regw_type;
 
constant regw_init : regw_type := (
slv(to_unsigned(0,AWIDTH)), -- raddr_c
slv(to_unsigned(0,AWIDTH)), -- raddr_s
slv(to_unsigned(0,AWIDTH)), -- sizew
'0', -- busy
'0','0','0', -- rstw,rstw_sc,rstw_ss
'0','0' -- rstr_c,rstr_s
);
 
type regr_type is record
waddr_c : slv(AWIDTH-1 downto 0); -- write address (capt from CLKW)
waddr_s : slv(AWIDTH-1 downto 0); -- write address (sync in CLKR)
sizer : slv(AWIDTH-1 downto 0); -- slots to read
val : slbit; -- valid flag
rstr : slbit; -- resetr active
rstr_sc : slbit; -- resetr (sync-capt from CLKW-CLKR)
rstr_ss : slbit; -- resetr (sync-sync from CLKW-CLKR)
rstw_c : slbit; -- resetw (capt from CLKW)
rstw_s : slbit; -- resetw (sync from CLKW)
end record regr_type;
 
constant regr_init : regr_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr_c
slv(to_unsigned(0,AWIDTH)), -- waddr_s
slv(to_unsigned(0,AWIDTH)), -- sizer
'0', -- val
'0','0','0', -- rstr,rstr_sc,rstr_ss
'0','0' -- rstw_c,rstw_s
);
 
signal R_REGW : regw_type := regw_init; -- write side state registers
signal N_REGW : regw_type := regw_init; -- next values write side
signal R_REGR : regr_type := regr_init; -- read side state registers
signal N_REGR : regr_type := regr_init; -- next values read side
 
signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
 
signal GCW_RST : slbit := '0';
signal GCW_CE : slbit := '0';
signal GCR_RST : slbit := '0';
signal GCR_CE : slbit := '0';
 
begin
 
RAM : ram_1swar_1ar_gen -- dual ported memory
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLKW,
WE => GCW_CE,
ADDRA => WADDR,
ADDRB => RADDR,
DI => DI,
DOA => open,
DOB => DO
);
GCW : gray_cnt_gen -- gray counter for write address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKW,
RESET => GCW_RST,
CE => GCW_CE,
DATA => WADDR
);
GCR : gray_cnt_gen -- gray counter for read address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKR,
RESET => GCR_RST,
CE => GCR_CE,
DATA => RADDR
);
G2B_WW : gray2bin_gen -- gray->bin for waddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => WADDR, DO => WADDR_BIN);
G2B_WR : gray2bin_gen -- gray->bin for waddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGR.waddr_s, DO => WADDR_S_BIN);
G2B_RW : gray2bin_gen -- gray->bin for raddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => RADDR, DO => RADDR_BIN);
G2B_RR : gray2bin_gen -- gray->bin for raddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGW.raddr_s, DO => RADDR_S_BIN);
proc_regw: process (CLKW)
begin
if rising_edge(CLKW) then
R_REGW <= N_REGW;
end if;
end process proc_regw;
 
proc_nextw: process (R_REGW, RESETW, ENA, R_REGR,
RADDR, RADDR_S_BIN, WADDR_BIN)
 
variable r : regw_type := regw_init;
variable n : regw_type := regw_init;
variable ibusy : slbit := '0';
variable igcw_ce : slbit := '0';
variable igcw_rst : slbit := '0';
variable isizew : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
 
r := R_REGW;
n := R_REGW;
 
isizew := slv(unsigned(RADDR_S_BIN) + unsigned(not WADDR_BIN));
ibusy := '0';
igcw_ce := '0';
igcw_rst := '0';
 
if unsigned(isizew) = 0 then -- if no free slots
ibusy := '1'; -- next cycle busy=1
end if;
 
if ENA='1' and r.busy='0' then -- if ena=1 and this cycle busy=0
igcw_ce := '1'; -- write this value
if unsigned(isizew) = 1 then -- if this last free slot
ibusy := '1'; -- next cycle busy=1
end if;
end if;
if RESETW = '1' then -- reset(write side) request
n.rstw := '1'; -- set RSTW flag
elsif r.rstw_ss = '1' then -- request gone and return seen
n.rstw := '0'; -- clear RSTW flag
end if;
 
if r.rstw='1' and r.rstw_ss='1' then -- RSTW seen on write and read side
igcw_rst := '1'; -- clear write address counter
end if;
if r.rstr_s = '1' then -- RSTR active
igcw_rst := '1'; -- clear write address counter
end if;
 
if RESETW='1' or r.rstw='1' or r.rstw_ss='1' or r.rstr_s='1'
then -- RESETW or RESETR active
ibusy := '1'; -- signal write side busy
isizew := (others=>'1');
end if;
 
n.busy := ibusy;
n.sizew := isizew;
n.raddr_c := RADDR; -- data captuture from CLKR
n.raddr_s := r.raddr_c;
n.rstw_sc := R_REGR.rstw_s;
n.rstw_ss := r.rstw_sc;
n.rstr_c := R_REGR.rstr;
n.rstr_s := r.rstr_c;
 
N_REGW <= n;
 
GCW_CE <= igcw_ce;
GCW_RST <= igcw_rst;
BUSY <= r.busy;
SIZEW <= r.sizew;
 
end process proc_nextw;
 
proc_regr: process (CLKR)
begin
if rising_edge(CLKR) then
R_REGR <= N_REGR;
end if;
end process proc_regr;
 
proc_nextr: process (R_REGR, RESETR, HOLD, R_REGW,
WADDR, WADDR_S_BIN, RADDR_BIN)
 
variable r : regr_type := regr_init;
variable n : regr_type := regr_init;
variable ival : slbit := '0';
variable igcr_ce : slbit := '0';
variable igcr_rst : slbit := '0';
variable isizer : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
 
r := R_REGR;
n := R_REGR;
 
isizer := slv(unsigned(WADDR_S_BIN) - unsigned(RADDR_BIN));
ival := '1';
igcr_ce := '0';
igcr_rst := '0';
 
if unsigned(isizer) = 0 then -- if nothing to read
ival := '0'; -- next cycle val=0
end if;
 
if r.val='1' and HOLD='0' then -- this cycle val=1 and no hold
igcr_ce := '1'; -- retire this value
if unsigned(isizer) = 1 then -- if this is last one
ival := '0'; -- next cycle val=0
end if;
end if;
 
if RESETR = '1' then -- reset(read side) request
n.rstr := '1'; -- set RSTR flag
elsif r.rstr_ss = '1' then -- request gone and return seen
n.rstr := '0'; -- clear RSTR flag
end if;
 
if r.rstr='1' and r.rstr_ss='1' then -- RSTR seen on read and write side
igcr_rst := '1'; -- clear read address counter
end if;
if r.rstw_s = '1' then -- RSTW active
igcr_rst := '1'; -- clear read address counter
end if;
 
if RESETR='1' or r.rstr='1' or r.rstr_ss='1' or r.rstw_s='1'
then -- RESETR or RESETW active
ival := '0'; -- signal read side empty
isizer := (others=>'0');
end if;
n.val := ival;
n.sizer := isizer;
 
n.waddr_c := WADDR; -- data captuture from CLKW
n.waddr_s := r.waddr_c;
n.rstr_sc := R_REGW.rstr_s;
n.rstr_ss := r.rstr_sc;
n.rstw_c := R_REGW.rstw;
n.rstw_s := r.rstw_c;
 
N_REGR <= n;
 
GCR_CE <= igcr_ce;
GCR_RST <= igcr_rst;
VAL <= r.val;
SIZER <= r.sizer;
 
end process proc_nextr;
 
end syn;
/ram_2swsr_rfirst_gen.vhd
0,0 → 1,104
-- $Id: ram_2swsr_rfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_rfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-before-write' semantics (as block RAM).
-- The code is inspired by Xilinx example rams_16.vhd. The
-- 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- now initialize DO to all '0' at start
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_rfirst_gen;
 
 
architecture syn of ram_2swsr_rfirst_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
 
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
 
signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
 
begin
 
proc_clka: process (CLKA)
begin
if rising_edge(CLKA) then
if ENA = '1' then
R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
if WEA = '1' then
sv_ram(to_integer(unsigned(ADDRA))) := DIA;
end if;
end if;
end if;
end process proc_clka;
 
proc_clkb: process (CLKB)
begin
if rising_edge(CLKB) then
if ENB = '1' then
R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
if WEB = '1' then
sv_ram(to_integer(unsigned(ADDRB))) := DIB;
end if;
end if;
end if;
end process proc_clkb;
 
DOA <= R_DOA;
DOB <= R_DOB;
end syn;
/memlib.vhd
0,0 → 1,238
-- $Id: memlib.vhd 424 2011-11-13 16:38:23Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: memlib
-- Description: Basic memory components: single/dual port synchronous and
-- asynchronus rams; Fifo's.
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0.2 change generic default for BRAM models
-- 2007-12-27 106 1.0.1 add fifo_2c_dram
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
package memlib is
 
component ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
component ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
 
component ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
generic (
AWIDTH : positive := 10; -- address port width
DWIDTH : positive := 16); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
 
component ram_1swsr_rfirst_gen is -- RAM, 1 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end component;
 
component ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
 
component ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
 
component ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w port
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end component;
 
component ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end component;
 
component fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
WE : in slbit; -- write enable
RE : in slbit; -- read enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
EMPTY : out slbit; -- empty flag
FULL : out slbit -- full flag
);
end component;
 
component fifo_1c_dram is -- fifo, 1 clock, dram based
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZE : out slv(AWIDTH downto 0) -- number of used slots
);
end component;
 
component fifo_1c_bubble is -- fifo, 1 clock, bubble regs
generic (
NSTAGE : positive := 4; -- number of stages
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit -- read hold
);
end component;
 
component fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end component;
 
end package memlib;
/ram_1swsr_wfirst_gen.vhd
0,0 → 1,90
-- $Id: ram_1swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_rfirst_gen - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- and 'read-through' semantics (as block RAM).
-- The 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Notes: For xst 8.1.03i: can be written with a signal or a shared
-- variable declared at the architecture level. Use variable
-- because this seemed better for simulation. Using a simple
-- variable declared at process level leads to an array of
-- registers and a big mux.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swsr_wfirst_gen;
 
 
architecture syn of ram_1swsr_wfirst_gen is
 
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
 
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
 
signal R_DO : slv(DWIDTH-1 downto 0) := datzero;
 
begin
 
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if EN = '1' then
if WE = '1' then
sv_ram(to_integer(unsigned(ADDR))) := DI;
end if;
R_DO <= sv_ram(to_integer(unsigned(ADDR)));
end if;
end if;
end process proc_clk;
 
DO <= R_DO;
end syn;
 
/ram_2swsr_wfirst_gen.vhd
0,0 → 1,102
-- $Id: ram_2swsr_wfirst_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_wfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-through' semantics (as block RAM).
-- The code is inspired by Xilinx example rams_16.vhd. The
-- 'ram_style' attribute is set to 'block', this will
-- force in XST a synthesis as block RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.4 now numeric_std clean
-- 2010-06-03 299 1.0.3 use sv_ prefix for shared variables
-- 2008-03-08 123 1.0.2 use std_..._arith, not _unsigned; use unsigned();
-- 2008-03-02 122 1.0.1 change generic default for BRAM models
-- 2007-06-03 45 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_wfirst_gen;
 
 
architecture syn of ram_2swsr_wfirst_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (0 to memsize-1) of slv(DWIDTH-1 downto 0);
shared variable sv_ram : ram_type := (others=>datzero);
 
attribute ram_style : string;
attribute ram_style of sv_ram : variable is "block";
signal R_DOA : slv(DWIDTH-1 downto 0) := datzero;
signal R_DOB : slv(DWIDTH-1 downto 0) := datzero;
begin
 
proc_clka: process (CLKA)
begin
if rising_edge(CLKA) then
if ENA = '1' then
if WEA = '1' then
sv_ram(to_integer(unsigned(ADDRA))) := DIA;
end if;
R_DOA <= sv_ram(to_integer(unsigned(ADDRA)));
end if;
end if;
end process proc_clka;
 
proc_clkb: process (CLKB)
begin
if rising_edge(CLKB) then
if ENB = '1' then
if WEB = '1' then
sv_ram(to_integer(unsigned(ADDRB))) := DIB;
end if;
R_DOB <= sv_ram(to_integer(unsigned(ADDRB)));
end if;
end if;
end process proc_clkb;
 
DOA <= R_DOA;
DOB <= R_DOB;
end syn;
/fifo_1c_dram.vhd
0,0 → 1,94
-- $Id: fifo_1c_dram.vhd 421 2011-11-07 21:23:50Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_1c_dram - syn
-- Description: FIFO, single clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: fifo_1c_dram_raw
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-06-06 49 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop clock(xst est.)
-- 4 16 31 32 22 153MHz ( 16 words)
-- 5 16 49 64 23 120MHz ( 32 words)
-- 6 16 70 128 23 120MHz ( 64 words)
-- 7 16 111 256 30 120MHz (128 words)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.memlib.all;
 
entity fifo_1c_dram is -- fifo, 1 clock, dram based
generic (
AWIDTH : positive := 7; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
DI : in slv(DWIDTH-1 downto 0); -- input data
ENA : in slbit; -- write enable
BUSY : out slbit; -- write port hold
DO : out slv(DWIDTH-1 downto 0); -- output data
VAL : out slbit; -- read valid
HOLD : in slbit; -- read hold
SIZE : out slv(AWIDTH downto 0) -- number of used slots
);
end fifo_1c_dram;
 
 
architecture syn of fifo_1c_dram is
 
signal WE : slbit := '0';
signal RE : slbit := '0';
signal SIZE_L : slv(AWIDTH-1 downto 0) := (others=>'0');
signal EMPTY : slbit := '0';
signal FULL : slbit := '0';
begin
 
FIFO : fifo_1c_dram_raw
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
RESET => RESET,
WE => WE,
RE => RE,
DI => DI,
DO => DO,
SIZE => SIZE_L,
EMPTY => EMPTY,
FULL => FULL
);
 
WE <= ENA and (not FULL);
RE <= (not EMPTY) and (not HOLD);
 
BUSY <= FULL;
VAL <= not EMPTY;
SIZE <= FULL & SIZE_L;
 
end syn;
/fifo_1c_dram_raw.vhd
0,0 → 1,161
-- $Id: fifo_1c_dram_raw.vhd 421 2011-11-07 21:23:50Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: fifo_1c_dram_raw - syn
-- Description: FIFO, single clock domain, distributed RAM based, 'raw'
-- interface exposing dram signals.
--
-- Dependencies: ram_1swar_1ar_gen
--
-- Test bench: tb/tb_fifo_1c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-03 47 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.memlib.all;
 
entity fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
generic (
AWIDTH : positive := 4; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
WE : in slbit; -- write enable
RE : in slbit; -- read enable
DI : in slv(DWIDTH-1 downto 0); -- input data
DO : out slv(DWIDTH-1 downto 0); -- output data
SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
EMPTY : out slbit; -- empty flag
FULL : out slbit -- full flag
);
end fifo_1c_dram_raw;
 
 
architecture syn of fifo_1c_dram_raw is
 
type regs_type is record
waddr : slv(AWIDTH-1 downto 0); -- write address
raddr : slv(AWIDTH-1 downto 0); -- read address
empty : slbit; -- empty flag
full : slbit; -- full flag
end record regs_type;
 
constant memsize : positive := 2**AWIDTH;
constant regs_init : regs_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr
slv(to_unsigned(0,AWIDTH)), -- raddr
'1','0' -- empty,full
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
 
signal RAM_WE : slbit := '0';
begin
 
RAM : ram_1swar_1ar_gen
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLK,
WE => RAM_WE,
ADDRA => R_REGS.waddr,
ADDRB => R_REGS.raddr,
DI => DI,
DOA => open,
DOB => DO
);
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
 
end process proc_regs;
 
proc_next: process (R_REGS, RESET, WE, RE)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable isize : slv(AWIDTH-1 downto 0) := (others=>'0');
 
variable we_val : slbit := '0';
variable re_val : slbit := '0';
variable iram_we : slbit := '0';
 
begin
 
r := R_REGS;
n := R_REGS;
 
re_val := RE and not r.empty;
we_val := WE and ((not r.full) or RE);
isize := slv(unsigned(r.waddr) - unsigned(r.raddr));
iram_we := '0';
if RESET = '1' then
n := regs_init;
 
else
 
if we_val = '1' then
n.waddr := slv(unsigned(r.waddr) + 1);
iram_we := '1';
if re_val = '0' then
n.empty := '0';
if unsigned(isize) = memsize-1 then
n.full := '1';
end if;
end if;
end if;
 
if re_val = '1' then
n.raddr := slv(unsigned(r.raddr) + 1);
if we_val = '0' then
n.full := '0';
if unsigned(isize) = 1 then
n.empty := '1';
end if;
end if;
end if;
 
end if;
 
N_REGS <= n;
 
RAM_WE <= iram_we;
 
SIZE <= isize;
EMPTY <= r.empty;
FULL <= r.full;
end process proc_next;
end syn;
/ram_1swar_gen.vhd
0,0 → 1,82
-- $Id: ram_1swar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_gen - syn
-- Description: Single-Port RAM with with one synchronous write and one
-- asynchronius read port (as distributed RAM).
-- The code is inspired by Xilinx example rams_04.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm Comments
-- 4 16 - 16 16*RAM16X1S
-- 5 16 - 32 16*RAM32X1S
-- 6 16 18 64 32*RAM32X1S Note: A(4) via F5MUX, A(5) via LUT
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swar_gen;
 
 
architecture syn of ram_1swar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
 
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
 
begin
 
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDR))) <= DI;
end if;
end if;
end process proc_clk;
 
DO <= RAM(to_integer(unsigned(ADDR)));
 
end syn;
/ram_1swar_1ar_gen.vhd
0,0 → 1,89
-- $Id: ram_1swar_1ar_gen.vhd 422 2011-11-10 18:44:06Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_1ar_gen - syn
-- Description: Dual-Port RAM with with one synchronous write and two
-- asynchronius read ports (as distributed RAM).
-- The code is inspired by Xilinx example rams_09.vhd. The
-- 'ram_style' attribute is set to 'distributed', this will
-- force in XST a synthesis as distributed RAM.
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-08 422 1.0.2 now numeric_std clean
-- 2008-03-08 123 1.0.1 use std_..._arith, not _unsigned; use unsigned()
-- 2007-06-03 45 1.0 Initial version
--
-- Some synthesis results:
-- - 2010-06-03 ise 11.4 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUTl LUTm Comments
-- 4 16 - 32 16*RAM16X1D
-- 5 16 34 64 32*RAM16X1D
-- 6 16 68 128 64*RAM16X1D, 32*MUXF5
-- 7 16 136 256 128*RAM16X1D, 64*MUXF5, 32*MUXF6
-- 8 16 292 512 256*RAM16X1D,144*MUXF5, 64*MUXF6, 32*MUXF7
-- - 2007-12-31 ise 8.2.03 for xc3s1000-ft256-4:
-- {same results as above for AW=4 and 6}
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
 
entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_1swar_1ar_gen;
 
 
architecture syn of ram_1swar_1ar_gen is
constant memsize : positive := 2**AWIDTH;
constant datzero : slv(DWIDTH-1 downto 0) := (others=>'0');
type ram_type is array (memsize-1 downto 0) of slv (DWIDTH-1 downto 0);
signal RAM : ram_type := (others=>datzero);
 
attribute ram_style : string;
attribute ram_style of RAM : signal is "distributed";
 
begin
 
proc_clk: process (CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
RAM(to_integer(unsigned(ADDRA))) <= DI;
end if;
end if;
end process proc_clk;
 
DOA <= RAM(to_integer(unsigned(ADDRA)));
DOB <= RAM(to_integer(unsigned(ADDRB)));
 
end syn;
/ram_1swsr_xfirst_gen_unisim.vhd
0,0 → 1,323
-- $Id: ram_1swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_xfirst_gen_unisim - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end ram_1swsr_xfirst_gen_unisim;
 
 
architecture syn of ram_1swsr_xfirst_gen_unisim is
 
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
 
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
 
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => O"000000000000",
SRVAL => O"000000000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(36*i+31 downto 36*i),
DOP => L_DO(36*i+35 downto 36*i+32),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(36*i+31 downto 36*i),
DIP => L_DI(36*i+35 downto 36*i+32),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
 
DO <= L_DO(DO'range);
end generate AW_09_S36;
 
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36
generic map (
INIT => X"00000000",
SRVAL => X"00000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(32*i+31 downto 32*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(32*i+31 downto 32*i),
DIP => "0000",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_09_S32;
 
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
 
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => O"000000",
SRVAL => O"000000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(18*i+15 downto 18*i),
DOP => L_DO(18*i+17 downto 18*i+16),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(18*i+15 downto 18*i),
DIP => L_DI(18*i+17 downto 18*i+16),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
 
DO <= L_DO(DO'range);
end generate AW_10_S18;
 
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18
generic map (
INIT => X"0000",
SRVAL => X"0000",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(16*i+15 downto 16*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(16*i+15 downto 16*i),
DIP => "00",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_10_S16;
 
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => O"000",
SRVAL => O"000",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(9*i+7 downto 9*i),
DOP => L_DO(9*i+8 downto 9*i+8),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(9*i+7 downto 9*i),
DIP => L_DI(9*i+8 downto 9*i+8),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
 
DO <= L_DO(DO'range);
end generate AW_11_S9;
 
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9
generic map (
INIT => X"00",
SRVAL => X"00",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(8*i+7 downto 8*i),
DOP => open,
ADDR => ADDR,
CLK => CLK,
DI => DI(8*i+7 downto 8*i),
DIP => "0",
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_11_S8;
 
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4
generic map (
INIT => X"0",
SRVAL => X"0",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(4*i+3 downto 4*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(4*i+3 downto 4*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
 
DO <= L_DO(DO'range);
end generate AW_12_S4;
 
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DO : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DI : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DI(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DI(DI'range) <= DI;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2
generic map (
INIT => "00",
SRVAL => "00",
WRITE_MODE => WRITE_MODE)
port map (
DO => L_DO(2*i+1 downto 2*i),
ADDR => ADDR,
CLK => CLK,
DI => L_DI(2*i+1 downto 2*i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
 
DO <= L_DO(DO'range);
end generate AW_13_S2;
 
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1
generic map (
INIT => "0",
SRVAL => "0",
WRITE_MODE => WRITE_MODE)
port map (
DO => DO(i downto i),
ADDR => ADDR,
CLK => CLK,
DI => DI(i downto i),
EN => EN,
SSR => '0',
WE => WE
);
end generate GL;
end generate AW_14_S1;
 
end syn;
 
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
/ram_2swsr_xfirst_gen_unisim.vhd
0,0 → 1,456
-- $Id: ram_2swsr_xfirst_gen_unisim.vhd 406 2011-08-14 21:06:44Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_xfirst_gen_unisim - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2,.., 13.1; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2011-08-14 406 1.0.2 cleaner code for L_DI(A|B) initialization
-- 2008-04-13 135 1.0.1 fix range error for AW_14_S1
-- 2008-03-08 123 1.0 Initial version (merged from _rfirst/_wfirst)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9; -- data port width
WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_xfirst_gen_unisim;
 
 
architecture syn of ram_2swsr_xfirst_gen_unisim is
 
constant ok_mod32 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+35)/36)=((DWIDTH+31)/32);
constant ok_mod16 : boolean := (DWIDTH mod 16)=0 and
((DWIDTH+17)/18)=((DWIDTH+16)/16);
constant ok_mod08 : boolean := (DWIDTH mod 32)=0 and
((DWIDTH+8)/9)=((DWIDTH+7)/8);
 
begin
assert AWIDTH>=9 and AWIDTH<=14
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported BRAM from factor"
severity failure;
 
AW_09_S36: if AWIDTH=9 and not ok_mod32 generate
constant dw_mem : positive := ((DWIDTH+35)/36)*36;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/36-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => O"000000000000",
INIT_B => O"000000000000",
SRVAL_A => O"000000000000",
SRVAL_B => O"000000000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(36*i+31 downto 36*i),
DOB => L_DOB(36*i+31 downto 36*i),
DOPA => L_DOA(36*i+35 downto 36*i+32),
DOPB => L_DOB(36*i+35 downto 36*i+32),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(36*i+31 downto 36*i),
DIB => L_DIB(36*i+31 downto 36*i),
DIPA => L_DIA(36*i+35 downto 36*i+32),
DIPB => L_DIB(36*i+35 downto 36*i+32),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
 
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_09_S36;
 
AW_09_S32: if AWIDTH=9 and ok_mod32 generate
GL: for i in DWIDTH/32-1 downto 0 generate
MEM : RAMB16_S36_S36
generic map (
INIT_A => X"00000000",
INIT_B => X"00000000",
SRVAL_A => X"00000000",
SRVAL_B => X"00000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(32*i+31 downto 32*i),
DOB => DOB(32*i+31 downto 32*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(32*i+31 downto 32*i),
DIB => DIB(32*i+31 downto 32*i),
DIPA => "0000",
DIPB => "0000",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_09_S32;
 
AW_10_S18: if AWIDTH=10 and not ok_mod16 generate
constant dw_mem : positive := ((DWIDTH+17)/18)*18;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/18-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => O"000000",
INIT_B => O"000000",
SRVAL_A => O"000000",
SRVAL_B => O"000000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(18*i+15 downto 18*i),
DOB => L_DOB(18*i+15 downto 18*i),
DOPA => L_DOA(18*i+17 downto 18*i+16),
DOPB => L_DOB(18*i+17 downto 18*i+16),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(18*i+15 downto 18*i),
DIB => L_DIB(18*i+15 downto 18*i),
DIPA => L_DIA(18*i+17 downto 18*i+16),
DIPB => L_DIB(18*i+17 downto 18*i+16),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
 
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_10_S18;
 
AW_10_S16: if AWIDTH=10 and ok_mod16 generate
GL: for i in DWIDTH/16-1 downto 0 generate
MEM : RAMB16_S18_S18
generic map (
INIT_A => X"0000",
INIT_B => X"0000",
SRVAL_A => X"0000",
SRVAL_B => X"0000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(16*i+15 downto 16*i),
DOB => DOB(16*i+15 downto 16*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(16*i+15 downto 16*i),
DIB => DIB(16*i+15 downto 16*i),
DIPA => "00",
DIPB => "00",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_10_S16;
 
AW_11_S9: if AWIDTH=11 and not ok_mod08 generate
constant dw_mem : positive := ((DWIDTH+8)/9)*9;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/9-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => O"000",
INIT_B => O"000",
SRVAL_A => O"000",
SRVAL_B => O"000",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(9*i+7 downto 9*i),
DOB => L_DOB(9*i+7 downto 9*i),
DOPA => L_DOA(9*i+8 downto 9*i+8),
DOPB => L_DOB(9*i+8 downto 9*i+8),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(9*i+7 downto 9*i),
DIB => L_DIB(9*i+7 downto 9*i),
DIPA => L_DIA(9*i+8 downto 9*i+8),
DIPB => L_DIB(9*i+8 downto 9*i+8),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
 
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_11_S9;
 
AW_11_S8: if AWIDTH=11 and ok_mod08 generate
GL: for i in DWIDTH/8-1 downto 0 generate
MEM : RAMB16_S9_S9
generic map (
INIT_A => X"00",
INIT_B => X"00",
SRVAL_A => X"00",
SRVAL_B => X"00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(8*i+7 downto 8*i),
DOB => DOB(8*i+7 downto 8*i),
DOPA => open,
DOPB => open,
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(8*i+7 downto 8*i),
DIB => DIB(8*i+7 downto 8*i),
DIPA => "0",
DIPB => "0",
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_11_S8;
 
AW_12_S4: if AWIDTH = 12 generate
constant dw_mem : positive := ((DWIDTH+3)/4)*4;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/4-1 downto 0 generate
MEM : RAMB16_S4_S4
generic map (
INIT_A => X"0",
INIT_B => X"0",
SRVAL_A => X"0",
SRVAL_B => X"0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(4*i+3 downto 4*i),
DOB => L_DOB(4*i+3 downto 4*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(4*i+3 downto 4*i),
DIB => L_DIB(4*i+3 downto 4*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
 
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_12_S4;
 
AW_13_S2: if AWIDTH = 13 generate
constant dw_mem : positive := ((DWIDTH+1)/2)*2;
signal L_DOA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DOB : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIA : slv(dw_mem-1 downto 0) := (others=> '0');
signal L_DIB : slv(dw_mem-1 downto 0) := (others=> '0');
begin
DI_PAD: if dw_mem>DWIDTH generate
L_DIA(dw_mem-1 downto DWIDTH) <= (others=>'0');
L_DIB(dw_mem-1 downto DWIDTH) <= (others=>'0');
end generate DI_PAD;
L_DIA(DIA'range) <= DIA;
L_DIB(DIB'range) <= DIB;
GL: for i in dw_mem/2-1 downto 0 generate
MEM : RAMB16_S2_S2
generic map (
INIT_A => "00",
INIT_B => "00",
SRVAL_A => "00",
SRVAL_B => "00",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => L_DOA(2*i+1 downto 2*i),
DOB => L_DOB(2*i+1 downto 2*i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => L_DIA(2*i+1 downto 2*i),
DIB => L_DIB(2*i+1 downto 2*i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
 
DOA <= L_DOA(DOA'range);
DOB <= L_DOB(DOB'range);
end generate AW_13_S2;
 
AW_14_S1: if AWIDTH = 14 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAMB16_S1_S1
generic map (
INIT_A => "0",
INIT_B => "0",
SRVAL_A => "0",
SRVAL_B => "0",
WRITE_MODE_A => WRITE_MODE,
WRITE_MODE_B => WRITE_MODE)
port map (
DOA => DOA(i downto i),
DOB => DOB(i downto i),
ADDRA => ADDRA,
ADDRB => ADDRB,
CLKA => CLKA,
CLKB => CLKB,
DIA => DIA(i downto i),
DIB => DIB(i downto i),
ENA => ENA,
ENB => ENB,
SSRA => '0',
SSRB => '0',
WEA => WEA,
WEB => WEB
);
end generate GL;
end generate AW_14_S1;
 
end syn;
 
-- Note: in XST 8.2 the defaults for INIT_(A|B) and SRVAL_(A|B) are
-- nonsense: INIT_A : bit_vector := X"000";
-- This is a 12 bit value, while a 9 bit one is needed. Thus the
-- explicit definition above.
/ram_1swsr_wfirst_gen_unisim.vbom
0,0 → 1,7
# libs
../slvtypes.vhd
memlib.vhd
# components
ram_1swsr_xfirst_gen_unisim.vbom
# design
ram_1swsr_wfirst_gen_unisim.vhd
/ram_1swsr_xfirst_gen_unisim.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
@lib:unisim
# design
ram_1swsr_xfirst_gen_unisim.vhd
/ram_2swsr_wfirst_gen_unisim.vbom
0,0 → 1,7
# libs
../slvtypes.vhd
memlib.vhd
# components
ram_2swsr_xfirst_gen_unisim.vbom
# design
ram_2swsr_wfirst_gen_unisim.vhd
/ram_1swsr_wfirst_gen.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
ram_1swsr_wfirst_gen.vhd
/ram_2swsr_wfirst_gen.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
ram_2swsr_wfirst_gen.vhd
/ram_1swsr_wfirst_gen_unisim.vhd
0,0 → 1,70
-- $Id: ram_1swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swsr_wfirst_gen - syn
-- Description: Single-Port RAM with with one synchronous read/write port
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
use work.memlib.all;
 
entity ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w port, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLK : in slbit; -- clock
EN : in slbit; -- enable
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address
DI : in slv(DWIDTH-1 downto 0); -- data in
DO : out slv(DWIDTH-1 downto 0) -- data out
);
end ram_1swsr_wfirst_gen;
 
 
architecture syn of ram_1swsr_wfirst_gen is
begin
UMEM: ram_1swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLK => CLK,
EN => EN,
WE => WE,
ADDR => ADDR,
DI => DI,
DO => DO
);
end syn;
/ram_2swsr_wfirst_gen_unisim.vhd
0,0 → 1,83
-- $Id: ram_2swsr_wfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_wfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-through' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
use work.memlib.all;
 
entity ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
generic (
AWIDTH : positive := 11; -- address port width
DWIDTH : positive := 9); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_wfirst_gen;
 
 
architecture syn of ram_2swsr_wfirst_gen is
begin
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "WRITE_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
end syn;
/fifo_1c_dram_raw.vbom
0,0 → 1,8
# libs
../slvtypes.vhd
memlib.vhd
# components
[ghdl,isim]ram_1swar_1ar_gen.vbom
[xst]ram_1swar_1ar_gen_unisim.vbom
# design
fifo_1c_dram_raw.vhd
/ram_1swar_gen.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
ram_1swar_gen.vhd
/ram_2swsr_rfirst_gen_unisim.vbom
0,0 → 1,7
# libs
../slvtypes.vhd
memlib.vhd
# components
ram_2swsr_xfirst_gen_unisim.vbom
# design
ram_2swsr_rfirst_gen_unisim.vhd
/ram_1swar_gen_unisim.vhd
0,0 → 1,118
-- $Id: ram_1swar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_gen_unisim - syn
-- Description: Single-Port RAM with with one synchronous write and one
-- asynchronius read port (as distributed RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.0.1 use shorter label names
-- 2008-03-02 122 1.0 Initial version
--
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_1swar_gen is -- RAM, 1 sync w asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable
ADDR : in slv(AWIDTH-1 downto 0); -- address port
DI : in slv(DWIDTH-1 downto 0); -- data in port
DO : out slv(DWIDTH-1 downto 0) -- data out port
);
end ram_1swar_gen;
 
 
architecture syn of ram_1swar_gen is
 
begin
 
assert AWIDTH>=4 and AWIDTH<=6
report "assert(AWIDTH>=4 and AWIDTH<=6): only 4..6 bit AWIDTH supported"
severity failure;
 
AW_4: if AWIDTH = 4 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM16X1S
generic map (
INIT => X"0000")
port map (
O => DO(i),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
D => DI(i),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_4;
 
AW_5: if AWIDTH = 5 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM32X1S
generic map (
INIT => X"00000000")
port map (
O => DO(i),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
A4 => ADDR(4),
D => DI(i),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_5;
 
AW_6: if AWIDTH = 6 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM64X1S
generic map (
INIT => X"0000000000000000")
port map (
O => DO(i),
A0 => ADDR(0),
A1 => ADDR(1),
A2 => ADDR(2),
A3 => ADDR(3),
A4 => ADDR(4),
A5 => ADDR(5),
D => DI(i),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_6;
 
end syn;
/ram_1swar_1ar_gen.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
ram_1swar_1ar_gen.vhd
/ram_1swar_1ar_gen_unisim.vhd
0,0 → 1,170
-- $Id: ram_1swar_1ar_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_1swar_1ar_gen - syn
-- Description: Dual-Port RAM with with one synchronous write and two
-- asynchronius read ports (as distributed RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-06-03 300 1.1 add hack for AW=5 for Spartan's
-- 2008-03-08 123 1.0.1 use shorter label names
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
generic (
AWIDTH : positive := 4; -- address port width
DWIDTH : positive := 16); -- data port width
port (
CLK : in slbit; -- clock
WE : in slbit; -- write enable (port A)
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_1swar_1ar_gen;
 
 
architecture syn of ram_1swar_1ar_gen is
 
begin
 
assert AWIDTH>=4 and AWIDTH<=5
report "assert(AWIDTH>=4 and AWIDTH<=5): only 4..5 bit AWIDTH supported"
severity failure;
 
AW_4: if AWIDTH = 4 generate
GL: for i in DWIDTH-1 downto 0 generate
MEM : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB(i),
SPO => DOA(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE
);
end generate GL;
end generate AW_4;
 
-- Note: Spartan-3 doesn't support RAM32X1D, therefore this kludge..
AW_5: if AWIDTH = 5 generate
signal WE0 : slbit := '0';
signal WE1 : slbit := '0';
signal DOA0 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOA1 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOB0 : slv(DWIDTH-1 downto 0) := (others=>'0');
signal DOB1 : slv(DWIDTH-1 downto 0) := (others=>'0');
begin
WE0 <= WE and not ADDRA(4);
WE1 <= WE and ADDRA(4);
GL: for i in DWIDTH-1 downto 0 generate
MEM0 : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB0(i),
SPO => DOA0(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE0
);
MEM1 : RAM16X1D
generic map (
INIT => X"0000")
port map (
DPO => DOB1(i),
SPO => DOA1(i),
A0 => ADDRA(0),
A1 => ADDRA(1),
A2 => ADDRA(2),
A3 => ADDRA(3),
D => DI(i),
DPRA0 => ADDRB(0),
DPRA1 => ADDRB(1),
DPRA2 => ADDRB(2),
DPRA3 => ADDRB(3),
WCLK => CLK,
WE => WE1
);
DOA <= DOA0 when ADDRA(4)='0' else DOA1;
DOB <= DOB0 when ADDRB(4)='0' else DOB1;
end generate GL;
end generate AW_5;
 
-- AW_6: if AWIDTH = 6 generate
-- GL: for i in DWIDTH-1 downto 0 generate
-- MEM : RAM64X1D
-- generic map (
-- INIT => X"0000000000000000")
-- port map (
-- DPO => DOB(i),
-- SPO => DOA(i),
-- A0 => ADDRA(0),
-- A1 => ADDRA(1),
-- A2 => ADDRA(2),
-- A3 => ADDRA(3),
-- A4 => ADDRA(4),
-- A5 => ADDRA(5),
-- D => DI(i),
-- DPRA0 => ADDRB(0),
-- DPRA1 => ADDRB(1),
-- DPRA2 => ADDRB(2),
-- DPRA3 => ADDRB(3),
-- DPRA4 => ADDRB(4),
-- DPRA5 => ADDRB(5),
-- WCLK => CLK,
-- WE => WE
-- );
-- end generate GL;
-- end generate AW_6;
 
end syn;
 
-- Note: The VHDL instantiation example in the 8.1i Librariers Guide is wrong.
-- The annotation states that DPO is the port A output and SPO is port B
-- output. The text before is correct, DPO is port B and SPO is port A.
/ram_2swsr_xfirst_gen_unisim.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
@lib:unisim
# design
ram_2swsr_xfirst_gen_unisim.vhd
/ram_2swsr_rfirst_gen.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
ram_2swsr_rfirst_gen.vhd
/ram_2swsr_rfirst_gen_unisim.vhd
0,0 → 1,83
-- $Id: ram_2swsr_rfirst_gen_unisim.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ram_2swsr_rfirst_gen - syn
-- Description: Dual-Port RAM with with two synchronous read/write ports
-- and 'read-before-write' semantics (as block RAM).
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: Spartan-3, Virtex-2,-4
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-08 123 1.1 use now ram_2swsr_xfirst_gen_unisim
-- 2008-03-02 122 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
use work.memlib.all;
 
entity ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
generic (
AWIDTH : positive := 13; -- address port width 11/9 or 13/8
DWIDTH : positive := 8); -- data port width
port(
CLKA : in slbit; -- clock port A
CLKB : in slbit; -- clock port B
ENA : in slbit; -- enable port A
ENB : in slbit; -- enable port B
WEA : in slbit; -- write enable port A
WEB : in slbit; -- write enable port B
ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
DIA : in slv(DWIDTH-1 downto 0); -- data in port A
DIB : in slv(DWIDTH-1 downto 0); -- data in port B
DOA : out slv(DWIDTH-1 downto 0); -- data out port A
DOB : out slv(DWIDTH-1 downto 0) -- data out port B
);
end ram_2swsr_rfirst_gen;
 
 
architecture syn of ram_2swsr_rfirst_gen is
begin
 
UMEM: ram_2swsr_xfirst_gen_unisim
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH,
WRITE_MODE => "READ_FIRST")
port map (
CLKA => CLKA,
CLKB => CLKB,
ENA => ENA,
ENB => ENB,
WEA => WEA,
WEB => WEB,
ADDRA => ADDRA,
ADDRB => ADDRB,
DIA => DIA,
DIB => DIB,
DOA => DOA,
DOB => DOB
);
 
end syn;
/fifo_1c_dram.vbom
0,0 → 1,7
# libs
../slvtypes.vhd
memlib.vhd
# components
fifo_1c_dram_raw.vbom
# design
fifo_1c_dram.vhd
/ram_1swar_gen_unisim.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
@lib:unisim
# design
ram_1swar_gen_unisim.vhd
/ram_1swar_1ar_gen_unisim.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
@lib:unisim
# design
ram_1swar_1ar_gen_unisim.vhd
/.
. Property changes : Added: svn:ignore ## -0,0 +1,32 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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