Subversion Repositories w11

/tb/Makefile

/tb/tb_s3board_fusp.vhd

/tb/tb_s3board_fusp.vbom

/tb/tb_s3board_core.vhd

/tb/tb_s3board_core.vbom

/tb/tb_s3_sram_memctl.vbom

/tb/tb_s3_sram_memctl.vhd

/tb/tb_s3_sram_memctl_stim.dat

/tb/s3board_fusp_dummy.vhd

/tb/s3board_fusp_dummy.vbom

/tb/tb_s3_sram_memctl_ssim.vbom

/tb/tbw.dat

/tb/.cvsignore

/tb

tb Property changes : Added: svn:ignore ## -0,0 +1,46 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_s3board_dummy +tb_s3board_dummy_[sft]sim +tb_s3board_dummy_ISim +tb_s3board_dummy_ISim_[sft]sim +tb_s3board_fusp_dummy +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tb_s3_sram_memctl +tb_s3_sram_memctl_[sft]sim +tb_s3_sram_memctl_stim +tb_s3_sram_memctl_ISim +tb_s3_sram_memctl_ISim_[sft]sim Index: Makefile =================================================================== --- Makefile (nonexistent) +++ Makefile (revision 26) @@ -0,0 +1,31 @@ +# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD +# 2011-08-13 405 1.1 use includes from rtl/make +# 2007-12-09 100 1.0.1 drop ISE_p definition +# 2007-09-16 83 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +ifndef XTW_BOARD + XTW_BOARD=s3board +endif +include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: s3_sram_dummy.vhd =================================================================== --- s3_sram_dummy.vhd (nonexistent) +++ s3_sram_dummy.vhd (revision 26) @@ -0,0 +1,56 @@ +-- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s3_sram_dummy - syn +-- Description: s3board: SRAM protection dummy +-- +-- Dependencies: - +-- Test bench: - +-- Target Devices: generic +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26 +-- Revision History: +-- Date Rev Version Comment +-- 2010-04-17 278 1.0.2 renamed from sram_dummy +-- 2007-12-09 101 1.0.1 use _N for active low +-- 2007-12-08 100 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +entity s3_sram_dummy is -- SRAM protection dummy + port ( + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end s3_sram_dummy; + + +architecture syn of s3_sram_dummy is +begin + + O_MEM_CE_N <= "11"; -- disable sram chips + O_MEM_BE_N <= "1111"; + O_MEM_WE_N <= '1'; + O_MEM_OE_N <= '1'; + O_MEM_ADDR <= (others=>'0'); + IO_MEM_DATA <= (others=>'0'); + +end syn; Index: s3boardlib.vhd =================================================================== --- s3boardlib.vhd (nonexistent) +++ s3boardlib.vhd (revision 26) @@ -0,0 +1,126 @@ +-- $Id: s3boardlib.vhd 426 2011-11-18 18:14:08Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: s3boardlib +-- Description: S3BOARD components +-- +-- Dependencies: - +-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29 +-- Revision History: +-- Date Rev Version Comment +-- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib +-- 2011-07-08 390 1.3.4 move s3_(dispdrv|humanio*) to bpgenlib +-- 2011-07-03 387 1.3.3 move s3_rs232_iob_(int|ext) to bpgenlib +-- 2010-12-30 351 1.3.2 use rblib; rename human s3_humanio_rri -> _rbus +-- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50 +-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib) +-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_ +-- 2010-05-16 291 1.2.1 rename memctl_s3sram -> s3_sram_memctl; _usp->_fusp +-- 2010-05-01 286 1.2 added s3board_usp_aif (base+pm1_rs232) +-- 2010-04-17 278 1.1.6 rename, prefix dispdrv,sram_summy with s3_; +-- add s3_rs232_iob_(int|ext|int_ext) +-- 2010-04-11 276 1.1.5 add DEBOUNCE for s3_humanio +-- 2010-04-10 275 1.1.4 add s3_humanio +-- 2008-02-17 117 1.1.3 memctl_s3sram: use req,we interface +-- 2008-01-20 113 1.1.2 rename memdrv -> memctl_s3sram +-- 2007-12-16 101 1.1.1 use _N for active low +-- 2007-12-09 100 1.1 add sram memory signals; sram_dummy; memdrv +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package s3boardlib is + +component s3board_aif is -- S3BOARD, abstract iface, base + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end component; + +component s3board_fusp_aif is -- S3BOARD, abstract iface, base+fusp + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end component; + +component s3_sram_dummy is -- SRAM protection dummy + port ( + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end component; + +component s3_sram_memctl is -- SRAM driver + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv18; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end component; + +end package s3boardlib; Index: s3_sram_memctl.vhd =================================================================== --- s3_sram_memctl.vhd (nonexistent) +++ s3_sram_memctl.vhd (revision 26) @@ -0,0 +1,366 @@ +-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $ +-- +-- Copyright 2007-2011 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: s3_sram_memctl - syn +-- Description: s3board: SRAM driver +-- +-- Dependencies: vlib/xlib/iob_reg_o +-- vlib/xlib/iob_reg_o_gen +-- vlib/xlib/iob_reg_io_gen +-- Test bench: tb/tb_s3_sram_memctl +-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3 +-- Target Devices: generic +-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2010-05-23 293 11.4 L68 xc3s1000-4 7 22 0 14 s 8.5 +-- 2008-02-16 116 8.2.03 I34 xc3s1000-4 5 30 0 17 s 7.0 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2011-11-19 427 1.0.6 now numeric_std clean +-- 2010-06-03 299 1.0.5 add "KEEP" for data iob; +-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl +-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface +-- 2008-01-20 113 1.0.2 rename memdrv -> memctl_s3sram +-- 2007-12-15 101 1.0.1 use _N for active low; get ce/we clocking right +-- 2007-12-08 100 1.0 Initial version +-- +-- Timing of some signals: +-- +-- single read request: +-- +-- state |_idle |_read |_idle | +-- +-- CLK __|^^^|___|^^^|___|^^^|___|^ +-- +-- REQ _______|^^^^^|______________ +-- WE ____________________________ +-- +-- IOB_CE __________|^^^^^^^|_________ +-- IOB_OE __________|^^^^^^^|_________ +-- +-- DO oooooooooooooooooo|ddddddd|d +-- BUSY ____________________________ +-- ACK_R __________________|^^^^^^^|_ +-- +-- single write request: +-- +-- state |_idle |_write1|_write2|_idle | +-- +-- CLK __|^^^|___|^^^|___|^^^|___|^^^|___|^ +-- +-- REQ _______|^^^^^|______________ +-- WE _______|^^^^^|______________ +-- +-- IOB_CE __________|^^^^^^^^^^^^^^^|_________ +-- IOB_BE __________|^^^^^^^^^^^^^^^|_________ +-- IOB_OE ____________________________________ +-- IOB_WE ______________|^^^^^^^|_____________ +-- +-- BUSY __________|^^^^^^^|_________________ +-- ACK_W __________________|^^^^^^^|_________ +-- +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; + +entity s3_sram_memctl is -- SRAM driver for S3BOARD + port ( + CLK : in slbit; -- clock + RESET : in slbit; -- reset + REQ : in slbit; -- request + WE : in slbit; -- write enable + BUSY : out slbit; -- controller busy + ACK_R : out slbit; -- acknowledge read + ACK_W : out slbit; -- acknowledge write + ACT_R : out slbit; -- signal active read + ACT_W : out slbit; -- signal active write + ADDR : in slv18; -- address + BE : in slv4; -- byte enable + DI : in slv32; -- data in (memory view) + DO : out slv32; -- data out (memory view) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32 -- sram: data lines + ); +end s3_sram_memctl; + + +architecture syn of s3_sram_memctl is + + type state_type is ( + s_idle, -- s_idle: wait for req + s_read, -- s_read: read cycle + s_write1, -- s_write1: write cycle, 1st half + s_write2, -- s_write2: write cycle, 2nd half + s_bta_r2w, -- s_bta_r2w: bus turn around: r->w + s_bta_w2r -- s_bta_w2r: bus turn around: w->r + ); + + type regs_type is record + state : state_type; -- state + ackr : slbit; -- signal ack_r + end record regs_type; + + constant regs_init : regs_type := ( + s_idle, + '0' -- ackr + ); + + signal R_REGS : regs_type := regs_init; -- state registers + signal N_REGS : regs_type := regs_init; -- next value state regs + + signal CLK_180 : slbit := '0'; + signal MEM_CE_N : slv2 := "00"; + signal MEM_BE_N : slv4 := "0000"; + signal MEM_WE_N : slbit := '0'; + signal MEM_OE_N : slbit := '0'; + signal ADDR_CE : slbit := '0'; + signal DATA_CEI : slbit := '0'; + signal DATA_CEO : slbit := '0'; + signal DATA_OE : slbit := '0'; + +begin + + CLK_180 <= not CLK; + + IOB_MEM_CE : iob_reg_o_gen + generic map ( + DWIDTH => 2, + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_CE_N, + PAD => O_MEM_CE_N + ); + + IOB_MEM_BE : iob_reg_o_gen + generic map ( + DWIDTH => 4, + INIT => '1') + port map ( + CLK => CLK, + CE => ADDR_CE, + DO => MEM_BE_N, + PAD => O_MEM_BE_N + ); + + IOB_MEM_WE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK_180, + CE => '1', + DO => MEM_WE_N, + PAD => O_MEM_WE_N + ); + + IOB_MEM_OE : iob_reg_o + generic map ( + INIT => '1') + port map ( + CLK => CLK, + CE => '1', + DO => MEM_OE_N, + PAD => O_MEM_OE_N + ); + + IOB_MEM_ADDR : iob_reg_o_gen + generic map ( + DWIDTH => 18) + port map ( + CLK => CLK, + CE => ADDR_CE, + DO => ADDR, + PAD => O_MEM_ADDR + ); + + IOB_MEM_DATA : iob_reg_io_gen + generic map ( + DWIDTH => 32, + PULL => "KEEP") + port map ( + CLK => CLK, + CEI => DATA_CEI, + CEO => DATA_CEO, + OE => DATA_OE, + DI => DO, + DO => DI, + PAD => IO_MEM_DATA + ); + + proc_regs: process (CLK) + begin + + if rising_edge(CLK) then + if RESET = '1' then + R_REGS <= regs_init; + else + R_REGS <= N_REGS; + end if; + end if; + + end process proc_regs; + + proc_next: process (R_REGS, REQ, WE, BE) + + variable r : regs_type := regs_init; + variable n : regs_type := regs_init; + variable ibusy : slbit := '0'; + variable iackw : slbit := '0'; + variable iactr : slbit := '0'; + variable iactw : slbit := '0'; + variable imem_ce : slv2 := "00"; + variable imem_be : slv4 := "0000"; + variable imem_we : slbit := '0'; + variable imem_oe : slbit := '0'; + variable iaddr_ce : slbit := '0'; + variable idata_cei : slbit := '0'; + variable idata_ceo : slbit := '0'; + variable idata_oe : slbit := '0'; + + begin + + r := R_REGS; + n := R_REGS; + n.ackr := '0'; + + ibusy := '0'; + iackw := '0'; + iactr := '0'; + iactw := '0'; + + imem_ce := "00"; + imem_be := "1111"; + imem_we := '0'; + imem_oe := '0'; + iaddr_ce := '0'; + idata_cei := '0'; + idata_ceo := '0'; + idata_oe := '0'; + + case r.state is + when s_idle => -- s_idle: wait for req + if REQ = '1' then -- if IO requested + if WE = '0' then -- if READ requested + iaddr_ce := '1'; -- latch address and be's + imem_ce := "11"; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + n.state := s_read; -- next: read + else -- if WRITE requested + iaddr_ce := '1'; -- latch address and be's + idata_ceo := '1'; -- latch output data + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := "11"; -- ce SRAM next cycle + imem_be := BE; -- use request BE's + n.state := s_write1; -- next: write 1st part + end if; + end if; + + when s_read => -- s_read: read cycle + idata_cei := '1'; -- latch input data + iactr := '1'; -- signal mem read + n.ackr := '1'; -- ACK_R next cycle + if REQ = '1' then -- if IO requested + if WE = '0' then -- if READ requested + iaddr_ce := '1'; -- latch address and be's + imem_ce := "11"; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + n.state := s_read; -- next: continue read + else -- if WRITE requested + iaddr_ce := '1'; -- latch address and be's + idata_ceo := '1'; -- latch output data + imem_be := BE; -- use request BE's + n.state := s_bta_r2w; -- next: bus turn around cycle + end if; + else + n.state := s_idle; -- next: idle if nothing to do + end if; + + when s_write1 => -- s_write1: write cycle, 1st half + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := "11"; -- ce SRAM next cycle + imem_we := '1'; -- we SRAM next shifted cycle + n.state := s_write2; -- next: write cycle, 2nd half + + when s_write2 => -- s_write2: write cycle, 2nd half + iactw := '1'; -- signal mem write + iackw := '1'; -- signal write acknowledge + idata_cei := '1'; -- latch input data (from SRAM) + if REQ = '1' then -- if IO requested + if WE = '1' then -- if WRITE requested + iaddr_ce := '1'; -- latch address and be's + idata_ceo := '1'; -- latch output data + idata_oe := '1'; -- oe FPGA next cycle + imem_ce := "11"; -- ce SRAM next cycle + imem_be := BE; -- use request BE's + n.state := s_write1; -- next: continue read + else -- if READ requested + iaddr_ce := '1'; -- latch address and be's + n.state := s_bta_w2r; -- next: bus turn around cycle + end if; + else + n.state := s_idle; -- next: idle if nothing to do + end if; + + when s_bta_r2w => -- s_bta_r2w: bus turn around: r->w + ibusy := '1'; -- signal busy, unable to handle req + iactw := '1'; -- signal mem write + imem_ce := "11"; -- ce SRAM next cycle + idata_oe := '1'; -- oe FPGA next cycle + n.state := s_write1; -- next: start write + + when s_bta_w2r => -- s_bta_w2r: bus turn around: w->r + ibusy := '1'; -- signal busy, unable to handle req + iactr := '1'; -- signal mem read + imem_ce := "11"; -- ce SRAM next cycle + imem_oe := '1'; -- oe SRAM next cycle + n.state := s_read; -- next: start read + + when others => null; + end case; + + N_REGS <= n; + + MEM_CE_N <= not imem_ce; + MEM_WE_N <= not imem_we; + MEM_BE_N <= not imem_be; + MEM_OE_N <= not imem_oe; + ADDR_CE <= iaddr_ce; + DATA_CEI <= idata_cei; + DATA_CEO <= idata_ceo; + DATA_OE <= idata_oe; + + BUSY <= ibusy; + ACK_R <= r.ackr; + ACK_W <= iackw; + ACT_R <= iactr; + ACT_W <= iactw; + + end process proc_next; + +end syn; Index: s3board_pins.ucf =================================================================== --- s3board_pins.ucf (nonexistent) +++ s3board_pins.ucf (revision 26) @@ -0,0 +1,133 @@ +## $Id: s3board_pins.ucf 402 2011-08-05 18:56:44Z mueller $ +## +## Pin locks for S3BOARD core functionality: +## - internal RS232 +## - human I/O (switches, buttons, leds, display) +## - sram +## +## Revision History: +## Date Rev Version Comment +## 2010-11-06 336 1.1.1 Rename CLK -> I_CLK50 +## 2008-05-25 150 1.1 Use DRIVE=6|SLEW=SLOW|KEEPER for memory data lines +## 2008-02-17 101 1.0 Initial version +## +## Note: default is DRIVE=12 | SLEW=SLOW +## +## clocks -------------------------------------------------------------------- +NET "I_CLK50" LOC = "t9" | IOSTANDARD=LVCMOS33; +## +## RS232 interface ----------------------------------------------------------- +NET "I_RXD" LOC = "t13" | IOSTANDARD=LVCMOS33; +NET "O_TXD" LOC = "r13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## switches and buttons ------------------------------------------------------ +NET "I_SWI<0>" LOC = "f12" | IOSTANDARD=LVCMOS33; +NET "I_SWI<1>" LOC = "g12" | IOSTANDARD=LVCMOS33; +NET "I_SWI<2>" LOC = "h14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<3>" LOC = "h13" | IOSTANDARD=LVCMOS33; +NET "I_SWI<4>" LOC = "j14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<5>" LOC = "j13" | IOSTANDARD=LVCMOS33; +NET "I_SWI<6>" LOC = "k14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<7>" LOC = "k13" | IOSTANDARD=LVCMOS33; +## +NET "I_BTN<0>" LOC = "m13" | IOSTANDARD=LVCMOS33; +NET "I_BTN<1>" LOC = "m14" | IOSTANDARD=LVCMOS33; +NET "I_BTN<2>" LOC = "l13" | IOSTANDARD=LVCMOS33; +NET "I_BTN<3>" LOC = "l14" | IOSTANDARD=LVCMOS33; +## +## LEDs ---------------------------------------------------------------------- +NET "O_LED<0>" LOC = "k12" | IOSTANDARD=LVCMOS33; +NET "O_LED<1>" LOC = "p14" | IOSTANDARD=LVCMOS33; +NET "O_LED<2>" LOC = "l12" | IOSTANDARD=LVCMOS33; +NET "O_LED<3>" LOC = "n14" | IOSTANDARD=LVCMOS33; +NET "O_LED<4>" LOC = "p13" | IOSTANDARD=LVCMOS33; +NET "O_LED<5>" LOC = "n12" | IOSTANDARD=LVCMOS33; +NET "O_LED<6>" LOC = "p12" | IOSTANDARD=LVCMOS33; +NET "O_LED<7>" LOC = "p11" | IOSTANDARD=LVCMOS33; +NET "O_LED<*>" DRIVE=12 | SLEW=SLOW; +## +## 7 segment display --------------------------------------------------------- +NET "O_ANO_N<0>" LOC = "d14" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<1>" LOC = "g14" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<2>" LOC = "f14" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<3>" LOC = "e13" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW; +## +NET "O_SEG_N<0>" LOC = "e14" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<1>" LOC = "g13" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<2>" LOC = "n15" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<3>" LOC = "p15" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<4>" LOC = "r16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<5>" LOC = "f13" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<6>" LOC = "n16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<7>" LOC = "p16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW; +## +## SRAM ---------------------------------------------------------------------- +NET "O_MEM_CE_N<0>" LOC = "p7" | IOSTANDARD=LVCMOS33; +NET "O_MEM_CE_N<1>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_CE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_BE_N<0>" LOC = "p6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<1>" LOC = "t4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<2>" LOC = "p5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<3>" LOC = "r4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_WE_N" LOC = "g3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_OE_N" LOC = "k4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_ADDR<0>" LOC = "l5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<1>" LOC = "n3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<2>" LOC = "m4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<3>" LOC = "m3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<4>" LOC = "l4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<5>" LOC = "g4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<6>" LOC = "f3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<7>" LOC = "f4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<8>" LOC = "e3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<9>" LOC = "e4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<10>" LOC = "g5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<11>" LOC = "h3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<12>" LOC = "h4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<13>" LOC = "j4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<14>" LOC = "j3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<15>" LOC = "k3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<16>" LOC = "k5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<17>" LOC = "l3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST; +## +NET "IO_MEM_DATA<0>" LOC = "n7" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<1>" LOC = "t8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<2>" LOC = "r6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<3>" LOC = "t5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<4>" LOC = "r5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<5>" LOC = "c2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<6>" LOC = "c1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<7>" LOC = "b1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<8>" LOC = "d3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<9>" LOC = "p8" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<10>" LOC = "f2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<11>" LOC = "h1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<12>" LOC = "j2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<13>" LOC = "l2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<14>" LOC = "p1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<15>" LOC = "r1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<16>" LOC = "p2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<17>" LOC = "n2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<18>" LOC = "m2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<19>" LOC = "k1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<20>" LOC = "j1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<21>" LOC = "g2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<22>" LOC = "e1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<23>" LOC = "d1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<24>" LOC = "d2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<25>" LOC = "e2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<26>" LOC = "g1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<27>" LOC = "f5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<28>" LOC = "c3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<29>" LOC = "k2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<30>" LOC = "m1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<31>" LOC = "n1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## Index: s3boardlib.vbom =================================================================== --- s3boardlib.vbom (nonexistent) +++ s3boardlib.vbom (revision 26) @@ -0,0 +1,3 @@ +# libs +../../vlib/slvtypes.vhd +s3boardlib.vhd Index: s3board_a2_pm1_rs232.ucf =================================================================== --- s3board_a2_pm1_rs232.ucf (nonexistent) +++ s3board_a2_pm1_rs232.ucf (revision 26) @@ -0,0 +1,15 @@ +## $Id: s3board_a2_pm1_rs232.ucf 295 2010-05-29 16:58:01Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-05-22 293 1.1 Rename PM1 -> FUSP +## 2010-04-24 281 1.0 Initial version +## +## expansion connector A2 / slot PMod 1 / usage RS232 for FTDI USB serport --- +## +## PmodRS232: pins: 1 RTS; 2 CTS; 3 RXD; 4 TXD; 5 GND; 6 VCC +## +NET "O_FUSP_RTS_N" LOC = "c6" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "e7" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "c7" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "d7" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; Index: s3_sram_dummy.vbom =================================================================== --- s3_sram_dummy.vbom (nonexistent) +++ s3_sram_dummy.vbom (revision 26) @@ -0,0 +1,5 @@ +# libs +../../vlib/slvtypes.vhd +# components +# design +s3_sram_dummy.vhd Index: s3_sram_memctl.vbom =================================================================== --- s3_sram_memctl.vbom (nonexistent) +++ s3_sram_memctl.vbom (revision 26) @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/xlib/xlib.vhd +# components +../../vlib/xlib/iob_reg_o.vbom +../../vlib/xlib/iob_reg_o_gen.vbom +../../vlib/xlib/iob_reg_io_gen.vbom +# design +s3_sram_memctl.vhd Index: . =================================================================== --- . (nonexistent) +++ . (revision 26)

. Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log