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/pdp11_dpath.vhd
0,0 → 1,344
-- $Id: pdp11_dpath.vhd 569 2014-07-13 14:36:32Z mueller $ |
-- |
-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: pdp11_dpath - syn |
-- Description: pdp11: CPU datapath |
-- |
-- Dependencies: pdp11_gpr |
-- pdp11_psr |
-- pdp11_ounit |
-- pdp11_aunit |
-- pdp11_lunit |
-- pdp11_munit |
-- |
-- Test bench: tb/tb_pdp11_core (implicit) |
-- Target Devices: generic |
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-07-12 569 1.2.3 use DIV_QUIT and S_DIV_SR for pdp11_munit |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2010-09-18 300 1.2.1 rename (adlm)box->(oalm)unit |
-- 2010-06-13 305 1.2 rename CPDIN -> CP_DIN; add CP_DOUT out port; |
-- remove CPADDR out port; drop R_CPADDR, proc_cpaddr; |
-- added R_CPDOUT, proc_cpdout |
-- 2009-05-30 220 1.1.6 final removal of snoopers (were already commented) |
-- 2008-12-14 177 1.1.5 fill gpr_* fields in DM_STAT_DP |
-- 2008-08-22 161 1.1.4 rename ubf_ -> ibf_; use iblib |
-- 2008-04-19 137 1.1.3 add DM_STAT_DP port |
-- 2008-03-02 121 1.1.2 remove snoopers |
-- 2008-02-24 119 1.1.1 add CPADDR register, remove R_MDIN (not needed) |
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now (for psr access) |
-- 2007-06-14 56 1.0.1 Use slvtypes.all |
-- 2007-05-12 26 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.iblib.all; |
use work.pdp11.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity pdp11_dpath is -- CPU datapath |
port ( |
CLK : in slbit; -- clock |
CRESET : in slbit; -- console reset |
CNTL : in dpath_cntl_type; -- control interface |
STAT : out dpath_stat_type; -- status interface |
CP_DIN : in slv16; -- console port data in |
CP_DOUT : out slv16; -- console port data out |
PSWOUT : out psw_type; -- current psw |
PCOUT : out slv16; -- current pc |
IREG : out slv16; -- ireg out |
VM_ADDR : out slv16; -- virt. memory address |
VM_DOUT : in slv16; -- virt. memory data out |
VM_DIN : out slv16; -- virt. memory data in |
IB_MREQ : in ib_mreq_type; -- ibus request |
IB_SRES : out ib_sres_type; -- ibus response |
DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status |
); |
end pdp11_dpath; |
|
architecture syn of pdp11_dpath is |
|
signal R_DSRC : slv16 := (others=>'0'); -- SRC register |
signal R_DDST : slv16 := (others=>'0'); -- DST register |
signal R_DTMP : slv16 := (others=>'0'); -- TMP register |
|
signal R_IREG : slv16 := (others=>'0'); -- IREG register |
|
signal R_CPDOUT : slv16 := (others=>'0'); -- cp dout buffer |
|
signal GPR_DSRC : slv16 := (others=>'0'); -- |
signal GPR_DDST : slv16 := (others=>'0'); -- |
signal GPR_PC : slv16 := (others=>'0'); -- |
|
signal PSW : psw_type := psw_init; -- |
signal CCIN : slv4 := (others=>'0'); -- cc input to xbox's |
signal CCOUT : slv4 := (others=>'0'); -- cc output from xbox's |
|
signal DRES : slv16 := (others=>'0'); -- result bus |
signal DRESE : slv16 := (others=>'0'); -- result bus extra |
|
signal OUNIT_DOUT : slv16 := (others=>'0'); -- result ounit |
signal AUNIT_DOUT : slv16 := (others=>'0'); -- result aunit |
signal LUNIT_DOUT : slv16 := (others=>'0'); -- result lunit |
signal MUNIT_DOUT : slv16 := (others=>'0'); -- result munit |
|
signal OUNIT_NZOUT : slv2 := (others=>'0'); -- nz flags ounit |
signal OUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags ounit |
signal AUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags aunit |
signal LUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags lunit |
signal MUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags munit |
|
subtype lal_ibf_addr is integer range 15 downto 1; |
subtype lah_ibf_addr is integer range 5 downto 0; |
constant lah_ibf_ena_22bit: integer := 6; |
constant lah_ibf_ena_ubmap: integer := 7; |
|
begin |
|
GPR : pdp11_gpr port map ( |
CLK => CLK, |
DIN => DRES, |
ASRC => CNTL.gpr_asrc, |
ADST => CNTL.gpr_adst, |
MODE => CNTL.gpr_mode, |
RSET => CNTL.gpr_rset, |
WE => CNTL.gpr_we, |
BYTOP => CNTL.gpr_bytop, |
PCINC => CNTL.gpr_pcinc, |
DSRC => GPR_DSRC, |
DDST => GPR_DDST, |
PC => GPR_PC |
); |
|
PSR : pdp11_psr port map( |
CLK => CLK, |
CRESET => CRESET, |
DIN => DRES, |
CCIN => CCOUT, |
CCWE => CNTL.psr_ccwe, |
WE => CNTL.psr_we, |
FUNC => CNTL.psr_func, |
PSW => PSW, |
IB_MREQ => IB_MREQ, |
IB_SRES => IB_SRES |
); |
|
OUNIT : pdp11_ounit port map ( |
DSRC => R_DSRC, |
DDST => R_DDST, |
DTMP => R_DTMP, |
PC => GPR_PC, |
ASEL => CNTL.ounit_asel, |
AZERO => CNTL.ounit_azero, |
IREG8 => R_IREG(7 downto 0), |
VMDOUT => VM_DOUT, |
CONST => CNTL.ounit_const, |
BSEL => CNTL.ounit_bsel, |
OPSUB => CNTL.ounit_opsub, |
DOUT => OUNIT_DOUT, |
NZOUT => OUNIT_NZOUT |
); |
|
AUNIT : pdp11_aunit port map ( |
DSRC => R_DSRC, |
DDST => R_DDST, |
CI => CCIN(0), |
SRCMOD => CNTL.aunit_srcmod, |
DSTMOD => CNTL.aunit_dstmod, |
CIMOD => CNTL.aunit_cimod, |
CC1OP => CNTL.aunit_cc1op, |
CCMODE => CNTL.aunit_ccmode, |
BYTOP => CNTL.aunit_bytop, |
DOUT => AUNIT_DOUT, |
CCOUT => AUNIT_CCOUT |
); |
|
LUNIT : pdp11_lunit port map ( |
DSRC => R_DSRC, |
DDST => R_DDST, |
CCIN => CCIN, |
FUNC => CNTL.lunit_func, |
BYTOP => CNTL.lunit_bytop, |
DOUT => LUNIT_DOUT, |
CCOUT => LUNIT_CCOUT |
); |
|
MUNIT : pdp11_munit port map ( |
CLK => CLK, |
DSRC => R_DSRC, |
DDST => R_DDST, |
DTMP => R_DTMP, |
GPR_DSRC => GPR_DSRC, |
FUNC => CNTL.munit_func, |
S_DIV => CNTL.munit_s_div, |
S_DIV_CN => CNTL.munit_s_div_cn, |
S_DIV_CR => CNTL.munit_s_div_cr, |
S_DIV_SR => CNTL.munit_s_div_sr, |
S_ASH => CNTL.munit_s_ash, |
S_ASH_CN => CNTL.munit_s_ash_cn, |
S_ASHC => CNTL.munit_s_ashc, |
S_ASHC_CN => CNTL.munit_s_ashc_cn, |
SHC_TC => STAT.shc_tc, |
DIV_CR => STAT.div_cr, |
DIV_CQ => STAT.div_cq, |
DIV_QUIT => STAT.div_quit, |
DOUT => MUNIT_DOUT, |
DOUTE => DRESE, |
CCOUT => MUNIT_CCOUT |
); |
|
CCIN <= PSW.cc; |
|
OUNIT_CCOUT <= OUNIT_NZOUT & "0" & CCIN(0); -- clear v, keep c |
|
proc_dres_sel: process (OUNIT_DOUT, AUNIT_DOUT, LUNIT_DOUT, MUNIT_DOUT, |
VM_DOUT, R_IREG, CP_DIN, CNTL) |
begin |
case CNTL.dres_sel is |
when c_dpath_res_ounit => DRES <= OUNIT_DOUT; |
when c_dpath_res_aunit => DRES <= AUNIT_DOUT; |
when c_dpath_res_lunit => DRES <= LUNIT_DOUT; |
when c_dpath_res_munit => DRES <= MUNIT_DOUT; |
when c_dpath_res_vmdout => DRES <= VM_DOUT; |
when c_dpath_res_fpdout => DRES <= (others=>'0'); |
when c_dpath_res_ireg => DRES <= R_IREG; |
when c_dpath_res_cpdin => DRES <= CP_DIN; |
when others => null; |
end case; |
end process proc_dres_sel; |
|
proc_cres_sel: process (OUNIT_CCOUT, AUNIT_CCOUT, LUNIT_CCOUT, MUNIT_CCOUT, |
CCIN, CNTL) |
begin |
case CNTL.cres_sel is |
when c_dpath_res_ounit => CCOUT <= OUNIT_CCOUT; |
when c_dpath_res_aunit => CCOUT <= AUNIT_CCOUT; |
when c_dpath_res_lunit => CCOUT <= LUNIT_CCOUT; |
when c_dpath_res_munit => CCOUT <= MUNIT_CCOUT; |
when c_dpath_res_vmdout => CCOUT <= CCIN; |
when c_dpath_res_fpdout => CCOUT <= "0000"; |
when c_dpath_res_ireg => CCOUT <= CCIN; |
when c_dpath_res_cpdin => CCOUT <= CCIN; |
when others => null; |
end case; |
end process proc_cres_sel; |
|
proc_dregs: process (CLK) |
begin |
|
if rising_edge(CLK) then |
|
if CNTL.dsrc_we = '1' then |
if CNTL.dsrc_sel = '0' then |
R_DSRC <= GPR_DSRC; |
else |
R_DSRC <= DRES; |
end if; |
end if; |
|
if CNTL.ddst_we = '1' then |
if CNTL.ddst_sel = '0' then |
R_DDST <= GPR_DDST; |
else |
R_DDST <= DRES; |
end if; |
end if; |
|
if CNTL.dtmp_we = '1' then |
case CNTL.dtmp_sel is |
when c_dpath_dtmp_dsrc => R_DTMP <= GPR_DSRC; |
when c_dpath_dtmp_psw => |
R_DTMP <= (others=>'0'); |
R_DTMP(psw_ibf_cmode) <= PSW.cmode; |
R_DTMP(psw_ibf_pmode) <= PSW.pmode; |
R_DTMP(psw_ibf_rset) <= PSW.rset; |
R_DTMP(psw_ibf_pri) <= PSW.pri; |
R_DTMP(psw_ibf_tflag) <= PSW.tflag; |
R_DTMP(psw_ibf_cc) <= PSW.cc; |
when c_dpath_dtmp_dres => R_DTMP <= DRES; |
when c_dpath_dtmp_drese => R_DTMP <= DRESE; |
when others => null; |
end case; |
end if; |
|
end if; |
|
end process proc_dregs; |
|
proc_mregs: process (CLK) |
begin |
|
if rising_edge(CLK) then |
|
if CNTL.ireg_we = '1' then |
R_IREG <= VM_DOUT; |
end if; |
|
end if; |
end process proc_mregs; |
|
proc_cpdout: process (CLK) |
begin |
if rising_edge(CLK) then |
if CRESET = '1' then |
R_CPDOUT <= (others=>'0'); |
else |
if CNTL.cpdout_we = '1' then |
R_CPDOUT <= DRES; |
end if; |
end if; |
end if; |
end process proc_cpdout; |
|
proc_vmaddr_sel: process (R_DSRC, R_DDST, R_DTMP, GPR_PC, CNTL) |
begin |
case CNTL.vmaddr_sel is |
when c_dpath_vmaddr_dsrc => VM_ADDR <= R_DSRC; |
when c_dpath_vmaddr_ddst => VM_ADDR <= R_DDST; |
when c_dpath_vmaddr_dtmp => VM_ADDR <= R_DTMP; |
when c_dpath_vmaddr_pc => VM_ADDR <= GPR_PC; |
when others => null; |
end case; |
end process proc_vmaddr_sel; |
|
STAT.ccout_z <= CCOUT(2); -- current Z cc flag |
|
PSWOUT <= PSW; |
PCOUT <= GPR_PC; |
IREG <= R_IREG; |
VM_DIN <= DRES; |
CP_DOUT <= R_CPDOUT; |
|
DM_STAT_DP.pc <= GPR_PC; |
DM_STAT_DP.psw <= PSW; |
DM_STAT_DP.ireg <= R_IREG; |
DM_STAT_DP.ireg_we <= CNTL.ireg_we; |
DM_STAT_DP.dsrc <= R_DSRC; |
DM_STAT_DP.ddst <= R_DDST; |
DM_STAT_DP.dtmp <= R_DTMP; |
DM_STAT_DP.dres <= DRES; |
DM_STAT_DP.gpr_adst <= CNTL.gpr_adst; |
DM_STAT_DP.gpr_mode <= CNTL.gpr_mode; |
DM_STAT_DP.gpr_bytop <= CNTL.gpr_bytop; |
DM_STAT_DP.gpr_we <= CNTL.gpr_we; |
|
end syn; |
/tb/tb_pdp11core_stim.dat
0,0 → 1,8571
# $Id: tb_pdp11core_stim.dat 569 2014-07-13 14:36:32Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2014-07-13 569 2.3 after ECO-026: correct test 31.1 wrong V=1 cases |
# correct test 37.2: 2 V=1 cases have regs now updated |
# 2010-06-20 308 2.2.1 add wibrb, ribr, wibr based tests |
# 2010-06-13 305 2.2 adopt to new rri address and function semantics |
# 2009-11-22 252 2.1.14 change SSR0 expects, adapt to ECO-021. |
# 2009-05-02 211 2.1.13 add nop after spl in pirq test, 11/70 spl now !! |
# 2008-08-29 163 2.1.12 add wtlam to harvest attn after sto in test 13 |
# 2008-04-27 139 2.1.11 adapt expected ssr1 after mtpi/d after ECO-009 fix |
# 2008-03-15 125 2.1.10 exclude some tests from simh ([[off/on]] |
# 2008-03-09 124 2.1.9 fixed addr-mode in code 34, shifted 47+50 |
# 2008-03-02 121 2.1.8 add meory access error tests |
# add Code 13, testing WAIT and bwm/brm while CPU runs |
# 2008-02-24 119 2.1.7 add tests for lah,rps,wps; use rps,wps |
# use 22bit mode for nxm test (now needed!) |
# 2008-02-23 118 2.1.6 for nxm tests use mmu and page below i/o-page |
# in code 35 use access to 160000 to test trap |
# 2007-09-23 84 2.1.5 use .reset to make it re-executable |
# 2007-09-16 83 2.1.4 clear CPUERR in beginning of test 20 {runs in FPGA} |
# 2007-09-02 79 2.1.3 add .mode command (for pi_rri use) |
# 2007-08-25 75 2.1.2 add .cpmon/.rpmon (for use with rri) |
# 2007-08-16 74 2.1.1 adapt to changed LAM handling |
# 2007-08-12 73 2.1 use wtgo (revised conv_stim) |
# 2007-08-03 71 2.0 convert to command mode with conv_stim |
# 2007-07-08 65 1.2 removed 1st 'delay' parameter; use .to_(cmd|stp|go) |
# 2007-06-10 51 1.1 consolidate w11a test bench |
# 2007-05-13 29 1.0 initial version (imported) |
# |
.mode pdpcp |
.tocmd 50 |
.tostp 100 |
.togo 5000 |
.rlmon 0 |
.rbmon 0 |
.scntl 13 0 |
# |
.reset |
.wait 10 |
.anena 1 |
# |
C "Code 0" Some elementary initial tests |
C write registers |
# |
wr0 000001 -- set r0,..,r7 |
wr1 000101 -- |
wr2 000201 -- |
wr3 000301 -- |
wr4 000401 -- |
wr5 000501 -- |
wsp 000601 -- |
wpc 000701 -- |
# |
C read registers |
# |
rr0 d=000001 -- ! r0 |
rr1 d=000101 -- ! r1 |
rr2 d=000201 -- ! r2 |
rr3 d=000301 -- ! r3 |
rr4 d=000401 -- ! r4 |
rr5 d=000501 -- ! r5 |
rsp d=000601 -- ! sp |
rpc d=000701 -- ! pc |
# |
C write memory |
# |
wal 002000 -- write mem(2000,...,2006) |
bwm 4 |
007700 -- |
007710 -- |
007720 -- |
007730 -- |
# |
C read memory |
# |
wal 002000 |
brm 4 |
d=007700 -- ! mem(2000) |
d=007710 -- ! mem(2002) |
d=007720 -- ! mem(2004) |
d=007730 -- ! mem(2006) |
# |
C write/read PSW via various mechanisms |
C via wps/rps |
# |
wps 000017 |
rps d=000017 |
wps 000000 |
rps d=000000 |
# |
C via 16bit cp addressing (wal 177776) |
# |
wal 177776 |
wm 000017 -- set all cc flags in psw |
rm d=000017 -- ! psw |
rps d=000017 |
wm 000000 -- clear psw |
rm d=000000 -- ! psw |
rps d=000000 |
# |
C via 22bit cp addressing (wal 177776; wah 177) |
# |
wal 177776 |
wah 000177 |
wm 000017 -- set all cc flags in psw |
rm d=000017 -- ! psw |
rps d=000017 |
wm 000000 -- clear psw |
rm d=000000 -- ! psw |
rps d=000000 |
# |
C via ibr (ibrb 177700) |
# |
wibrb 177700 |
wibr 76 000017 -- set all cc flags in psw |
ribr 76 d=000017 -- ! psw |
rps d=000017 |
wibr 76 000000 -- set all cc flags in psw |
ribr 76 d=000000 -- ! psw |
rps d=000000 |
# |
C write register set 1, sm,um stack |
# |
wps 004000 -- psw: cm=kernel, set=1 |
wr0 010001 -- set r0,..,r5 [[r10]] |
wr1 010101 -- [[r11]] |
wr2 010201 -- [[r12]] |
wr3 010301 -- [[r13]] |
wr4 010401 -- [[r14]] |
wr5 010501 -- [[r15]] |
wps 044000 -- psw: cm=super(01),set=1 |
wsp 010601 -- set ssp [[ssp]] |
wps 144000 -- psw: cm=user(11),set=1 |
wsp 110601 -- set usp [[usp]] |
# |
C read all registers set 0/1, km,sm,um stack |
# |
wps 000000 -- psw: cm=kernel(00),set=0 |
rr0 d=000001 -- ! r0 |
rr1 d=000101 -- ! r1 |
rr2 d=000201 -- ! r2 |
rr3 d=000301 -- ! r3 |
rr4 d=000401 -- ! r4 |
rr5 d=000501 -- ! r5 |
rsp d=000601 -- ! ksp |
rpc d=000701 -- ! pc |
wps 040000 -- psw: cm=super(01),set=0 |
rsp d=010601 -- ! ssp [[ssp]] |
wps 140000 -- psw: cm=user(11),set=0 |
rsp d=110601 -- ! usp [[usp]] |
wps 144000 -- psw: cm=user(11),set=1 |
rr0 d=010001 -- ! r0 [[r10]] |
rr1 d=010101 -- ! r1 [[r11]] |
rr2 d=010201 -- ! r2 [[r12]] |
rr3 d=010301 -- ! r3 [[r13]] |
rr4 d=010401 -- ! r4 [[r14]] |
rr5 d=010501 -- ! r5 [[r15]] |
# |
C write IB space: MMU SAR supervisor mode (16 bit regs) |
# |
wal 172240 -- set first three SM I space address regs |
bwm 3 |
012340 |
012342 |
012344 |
# |
C read IB space: MMU SAR supervisor mode (16 bit regs) |
# |
wal 172240 -- ! verify first three SM I space address regs |
brm 3 |
d=012340 |
d=012342 |
d=012344 |
# |
C read IB space via ibr: MMU SAR supervisor mode (16 bit regs) |
# |
wibrb 172200 |
ribr 40 d=012340 |
ribr 42 d=012342 |
ribr 44 d=012344 |
# |
C byte write IB space via ibr: MMU SAR supervisor mode (16 bit regs) |
# |
wibrb 172201 -- write low byte |
wibr 40 177000 |
wibr 42 177002 |
wibr 44 177004 |
wal 172240 -- ! verify |
brm 3 |
d=012000 |
d=012002 |
d=012004 |
# |
wibrb 172202 -- write high byte |
wibr 40 000377 |
wibr 42 022377 |
wibr 44 044377 |
wal 172240 -- ! verify |
brm 3 |
d=000000 |
d=022002 |
d=044004 |
# |
wibrb 172203 -- write high and low byte (both be set) |
wibr 40 012340 |
wibr 42 012342 |
wibr 44 012344 |
wal 172240 -- ! verify |
brm 3 |
d=012340 |
d=012342 |
d=012344 |
# |
#[[off]] - this tests cp not the cpu - meaningless in simh |
# |
C test access error handling to memory (use 17740000) |
C with wm/rm |
# |
wal 140000 |
wah 000177 |
.merr 1 |
.sdef s=10000001 |
wm 000000 |
rm d=- |
.merr 0 |
.sdef s=00000000,01110000 |
# |
C with bwm/brm |
# |
wal 140000 |
wah 000177 |
.merr 1 |
.sdef s=10000001 |
bwm 2 |
000000 |
000000 |
.merr 0 |
.sdef s=00000000,01110000 |
# |
wal 140000 |
wah 000177 |
.merr 1 |
.sdef s=10000001 |
brm 2 |
d=- |
d=- |
.merr 0 |
.sdef s=00000000,01110000 |
# |
C test access error handling to IB space (use 00160000) |
C with wm/rm |
wal 160000 |
.merr 1 |
.sdef s=10000001 |
wm 000000 |
rm d=- |
.merr 0 |
.sdef s=00000000,01110000 |
C with bwm/brm |
# |
wal 160000 |
.merr 1 |
.sdef s=10000001 |
bwm 2 |
000000 |
000000 |
.merr 0 |
.sdef s=00000000,01110000 |
# |
wal 160000 |
.merr 1 |
.sdef s=10000001 |
brm 2 |
d=- |
d=- |
.merr 0 |
.sdef s=00000000,01110000 |
#[[on]] |
#----------------------------------------------------------------------------- |
C Setup trap catchers |
# |
wal 000004 -- vectors: 4...34 (trap catcher) |
bwm 14 |
000006 -- PC:06 ; vector 4 |
000000 -- PS:0 |
000012 -- PC:12 ; vector 10 |
000000 -- PS:0 |
000016 -- PC:16 ; vector 14 (T bit; BPT) |
000000 -- PS:0 |
000022 -- PC:22 ; vector 20 (IOT) |
000000 -- PS:0 |
000026 -- PC:26 ; vector 24 (Power fail, not used) |
000000 -- PS:0 |
000032 -- PC:32 ; vector 30 (EMT) |
000000 -- PS:0 |
000036 -- PC:36 ; vector 34 (TRAP) |
000000 -- PS:0 |
wal 000240 -- vectors: 240,244,250 (trap catcher) |
bwm 6 |
000242 -- PC:242 ; vector 240 (PIRQ) |
000000 -- PS:0 |
000246 -- PC:246 ; vector 244 (FPU) |
000000 -- PS:0 |
000252 -- PC:252 ; vector 250 (MMU) |
000000 -- PS:0 |
# |
C Setup MMU |
# |
wal 172300 -- kernel I space DR |
bwm 8 |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
wal 172340 -- kernel I space AR |
bwm 8 |
000000 -- 0 |
000200 -- 200 020000 base |
000400 -- 400 040000 base |
000600 -- 600 060000 base |
001000 -- 1000 100000 base |
001200 -- 1200 120000 base |
001400 -- 1400 140000 base |
177600 -- 176000 (map to I/O page) |
#----------------------------------------------------------------------------- |
C Setup code 1 [base 2100] (very basics: cont,start; 'simple' instructions) |
# |
wal 002100 -- code test 1: (sec+clc+halt) |
bwm 3 |
000261 -- sec |
000250 -- cln |
000000 -- halt |
#----- |
wal 002120 -- code test 2: (4 *inc R2, starting from -2) |
bwm 5 |
005202 -- inc r2 |
005202 -- inc r2 |
005202 -- inc r2 |
005202 -- inc r2 |
#2130 |
000000 -- halt |
#----- |
wal 002140 -- code test 3: (dec r3; bne -2; halt) |
bwm 3 |
005303 -- dec r3 |
001376 -- bne -2 |
000000 -- halt |
#----- |
wal 002160 -- code test 4: (inc r1; sob r0,-2; halt) |
bwm 3 |
005201 -- inc r1 |
077002 -- sob r0,-2 |
000000 -- halt |
# |
C Exec code 1 (very basics: cont,start; 'simple' instructions) |
C Exec test 1.1 (sec+clc+halt) |
# |
wpc 002100 -- pc=2100 |
wps 000010 -- psw: set N flag |
cont -- cont @ 2100 |
wtgo |
rpc d=002106 -- ! pc |
rps d=000001 -- ! N cleared, C set now |
# |
C Exec test 1.2 (4 *inc R2, starting from -2) |
# |
wr2 177776 -- r2=-2 |
stapc 002120 -- start @ 2120 |
wtgo |
rr2 d=000002 -- ! r2=2 |
rpc d=002132 -- ! pc |
# |
C Exec test 1.3 (dec r3; bne -2; halt) |
# |
wr3 000002 -- r3=2 |
stapc 002140 -- start @ 2140 |
wtgo |
rr3 d=000000 -- ! r3=0 |
rpc d=002146 -- ! pc |
# |
C Exec test 1.4 (inc r1; sob r0,-2; halt) |
# |
wr0 000002 -- r0=2 |
wr1 000000 -- r1=0 |
stapc 002160 -- start @ 2160 |
wtgo |
rr0 d=000000 -- ! r0=0 |
rr1 d=000002 -- ! r1=2 |
rpc d=002166 -- ! pc |
#----------------------------------------------------------------------------- |
C Setup code 2 [base 2200] (bpt against trap catcher @14) |
# |
wal 002200 -- code: |
bwm 4 |
000257 -- cl(nzvc) |
000261 -- sec |
000003 -- bpt |
000000 -- halt |
# |
C Exec code 2 (bpt against trap catcher @14) |
# |
wsp 001400 -- sp=1400 |
stapc 002200 -- start @ 2200 |
wtgo |
rsp d=001374 -- ! sp |
rpc d=000020 -- ! pc |
wal 001374 |
brm 2 |
d=002206 -- ! (sp) old pc |
d=000341 -- ! 2(sp) old ps |
#----------------------------------------------------------------------------- |
C Setup code 3 [base 2300] (bpt against trap handler doing inc r0; rtt) |
# |
wal 002300 -- code: |
bwm 4 |
000257 -- cl(nzvc) |
000003 -- bpt |
005201 -- inc r1 |
000000 -- halt |
wal 000014 -- vector: 14 |
bwm 2 |
002320 -- PC:2320 |
000002 -- PS:2 |
wal 002320 -- code (trap 14): |
bwm 3 |
005200 -- inc r0 |
000006 -- rtt |
000000 -- halt |
# |
C Exec code 3 (bpt against trap handler doing inc r0; rtt) |
# |
wr0 000000 -- r0=0 |
wr1 000000 -- r1=0 |
wsp 001400 -- sp=1400 |
stapc 002300 -- start @ 2300 |
wtgo |
rr0 d=000001 -- ! r0 |
rr1 d=000001 -- ! r1 |
rsp d=001400 -- ! sp |
rpc d=002310 -- ! pc |
#----------------------------------------------------------------------------- |
C Setup code 4 [base 2400] (enable T-trap on handler of code 3; run 2* inc r1) |
# |
wal 002400 |
bwm 4 |
000006 -- rtt |
005201 -- inc r1 |
005201 -- inc r1 |
000000 -- halt |
# |
C Exec code 4 (enable T-trap on handler of code 3; run 2* inc r1) |
# |
wr0 000000 -- r0=0 |
wr1 000000 -- r1=0 |
wsp 001374 -- sp=1374 |
wal 001374 -- setup stack with rtt return frame setting T flag |
bwm 2 |
002402 -- start address |
000020 -- set T flag in PSW |
stapc 002400 -- start @ 2400 -> rtt -> 2402 from stack |
wtgo |
rr0 d=000002 -- ! r0 |
rr1 d=000002 -- ! r1 |
rsp d=001400 -- ! sp |
rpc d=002410 -- ! pc |
# |
rst -- console reset (to clear T flag) |
wal 000014 -- vector: 14 -> trap catcher again |
bwm 2 |
000016 -- PC:16 |
000000 -- PS:0 |
#----------------------------------------------------------------------------- |
C Setup code 5 [base 2500] (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0)) |
# |
wal 002500 -- code: |
bwm 6 |
011001 -- mov (r0),r1 |
012002 -- mov (r0)+,r2 |
012003 -- mov (r0)+,r3 |
014004 -- mov -(r0),r4 |
013005 -- mov @(r0)+,r5 |
000000 -- halt |
# |
wal 002540 -- data: |
bwm 2 |
000070 -- |
002550 -- |
wal 002550 -- data: |
bwm 2 |
000072 -- |
000074 -- |
# |
C Exec code 5 (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0)) |
# |
wr0 002540 -- r0=2540 |
wr1 000000 -- r1=0 |
wr2 000000 -- r2=0 |
wr3 000000 -- r3=0 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 002500 -- start @ 2500 |
wtgo |
rr0 d=002544 -- ! r0 |
rr1 d=000070 -- ! r1 |
rr2 d=000070 -- ! r2 |
rr3 d=002550 -- ! r3 |
rr4 d=002550 -- ! r4 |
rr5 d=000072 -- ! r5 |
rsp d=001400 -- ! sp |
rpc d=002514 -- ! pc |
#----------------------------------------------------------------------------- |
C Setup code 6 [base 2600] (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes) |
# |
wal 002600 -- code: |
bwm 11 |
016001 -- mov 2(r0),r1 |
000002 |
017002 -- mov @2(r0),r2 |
000002 |
012703 -- mov (pc)+,r3 ; #377 |
000377 |
013704 -- mov @(pc)+,r4 ; @#2552 (in previous code !) |
002552 |
#2620 |
112705 -- movb (pc)+,r5 ; #377 |
000377 |
000000 -- halt |
# |
C Exec code 6 (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes) |
# |
wr0 002540 -- r0=2540 (in previous code !) |
wr1 000000 -- r1=0 |
wr2 000000 -- r2=0 |
wr3 000000 -- r3=0 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 002600 -- start @ 2600 |
wtgo |
rr0 d=002540 -- ! r0 |
rr1 d=002550 -- ! r1 |
rr2 d=000072 -- ! r2 |
rr3 d=000377 -- ! r3 |
rr4 d=000074 -- ! r4 |
rr5 d=177777 -- ! r5 |
rsp d=001400 -- ! sp |
rpc d=002626 -- ! pc |
#----------------------------------------------------------------------------- |
C Setup code 7 [base 2700] (dstw modes: mov rn,xxx: all non-r modes) |
# |
wal 002700 -- code: |
bwm 18 |
012710 -- mov #110,(r0) (to 2750) |
000110 |
012721 -- mov #120,(r1)+ (to 2752) |
000120 |
012732 -- mov #130,@(r2)+ (to 2754) |
000130 |
012743 -- mov #140,-(r3) (to 2756) |
000140 |
#2720 |
012754 -- mov #150,@-(r4) (to 2760) |
000150 |
012760 -- mov #160,12(r0) (to 2762) |
000160 |
000012 |
012770 -- mov #170,@24(r0) (to 2764) |
000170 |
000024 |
#2740 |
010546 -- mov r5,-(r6) |
000000 -- halt |
# |
wal 002770 -- data: |
bwm 3 |
002754 -- mem(2770)=2754 |
002760 -- mem(2772)=2760 |
002764 -- mem(2774)=2764 |
# |
C Exec code 7 (dstw modes: mov rn,xxx: all non-r modes) |
# |
wr0 002750 -- r0=2750 |
wr1 002752 -- r1=2752 |
wr2 002770 -- r2=2770 |
wr3 002760 -- r3=2760 |
wr4 002774 -- r4=2774 |
wr5 000666 -- r5=666 |
wsp 001400 -- sp=1400 |
stapc 002700 -- start @ 2700 |
wtgo |
rr0 d=002750 -- ! r0 |
rr1 d=002754 -- ! r1 |
rr2 d=002772 -- ! r2 |
rr3 d=002756 -- ! r3 |
rr4 d=002772 -- ! r4 |
rr5 d=000666 -- ! r5 |
rsp d=001376 -- ! sp |
rpc d=002744 -- ! pc |
wal 002750 |
brm 7 |
d=000110 -- ! mem(2750)=110 |
d=000120 -- ! mem(2752)=120 |
d=000130 -- ! mem(2754)=130 |
d=000140 -- ! mem(2756)=140 |
d=000150 -- ! mem(2760)=150 |
d=000160 -- ! mem(2762)=160 |
d=000170 -- ! mem(2764)=170 |
wal 001376 |
rmi d=000666 -- ! mem(sp)=666 |
#----------------------------------------------------------------------------- |
C Setup code 10 [base 3000] (dstm modes: inc xxx: all non-r modes) |
# |
wal 003000 -- code: |
bwm 10 |
005210 -- inc (r0) (to 3050) |
005221 -- inc (r1)+ (to 3052) |
005232 -- inc @(r2)+ (to 3054) |
005243 -- inc -(r3) (to 3056) |
005254 -- inc @-(r4) (to 3060) |
005260 -- inc 12(r0) (to 3062) |
000012 |
005270 -- inc @24(r0) (to 3064) |
#3020 |
000024 |
000000 -- halt |
# |
wal 003050 -- data: |
bwm 7 |
000110 -- mem(3050)=110 |
000120 -- mem(3052)=120 |
000130 -- mem(3054)=130 |
000140 -- mem(3056)=140 |
000150 -- mem(3060)=150 |
000160 -- mem(3062)=160 |
000170 -- mem(3064)=170 |
wal 003070 -- data: |
bwm 3 |
003054 -- mem(3070)=3054 |
003060 -- mem(3072)=3060 |
003064 -- mem(3074)=3064 |
# |
C Exec code 10 (dstm modes: inc xxx: all non-r modes) |
# |
wr0 003050 -- r0=3050 |
wr1 003052 -- r1=3052 |
wr2 003070 -- r2=3070 |
wr3 003060 -- r3=3060 |
wr4 003074 -- r4=3074 |
wsp 001400 -- sp=1400 |
stapc 003000 -- start @ 3000 |
wtgo |
rr0 d=003050 -- ! r0 |
rr1 d=003054 -- ! r1 |
rr2 d=003072 -- ! r2 |
rr3 d=003056 -- ! r3 |
rr4 d=003072 -- ! r4 |
rpc d=003024 -- ! pc |
wal 003050 |
brm 7 |
d=000111 -- ! mem(3050)=111 |
d=000121 -- ! mem(3052)=121 |
d=000131 -- ! mem(3054)=131 |
d=000141 -- ! mem(3056)=141 |
d=000151 -- ! mem(3060)=151 |
d=000161 -- ! mem(3062)=161 |
d=000171 -- ! mem(3064)=171 |
#----------------------------------------------------------------------------- |
C Setup code 11 [base 3100; use 31-32] (dsta modes: jsr pc,xxx: all non-r modes) |
# |
wal 003100 -- code: |
bwm 10 |
004710 -- jsr pc,(r0) (to 3210) r0->3210 |
004721 -- jsr pc,(r1)+ (to 3220) r1->3220 |
004732 -- jsr pc,@(r2)+ (to 3230) r2->3140->3230 |
004743 -- jsr pc,-(r3) (to 3240) r3->3242 |
004754 -- jsr pc,@-(r4) (to 3250) r4->3142->3250 |
004760 -- jsr pc,50(r0) (to 3260) r0->3210+50->3260 |
000050 |
004770 -- jsr pc,@-44(r0) (to 3270) r0->3210-44->3144->3270 |
#3120 |
177734 |
000000 -- halt |
# |
wal 003140 -- data: |
bwm 3 |
003230 -- mem(3140)=3230 |
003250 -- mem(3142)=3250 |
003270 -- mem(3144)=3270 |
# |
wal 003210 -- code: |
bwm 28 |
012725 -- mov #110,(r5)+ |
000110 |
000207 -- rts pc |
000000 -- halt |
#3220 |
012725 -- mov #120,(r5)+ |
000120 |
000207 -- rts pc |
000000 -- halt |
012725 -- mov #130,(r5)+ |
000130 |
000207 -- rts pc |
000000 -- halt |
#3240 |
012725 -- mov #140,(r5)+ |
000140 |
000207 -- rts pc |
000000 -- halt |
012725 -- mov #150,(r5)+ |
000150 |
000207 -- rts pc |
000000 -- halt |
#3260 |
012725 -- mov #160,(r5)+ |
000160 |
000207 -- rts pc |
000000 -- halt |
012725 -- mov #170,(r5)+ |
000170 |
000207 -- rts pc |
000000 -- halt |
# |
C Exec code 11 (dsta modes: jsr pc,xxx: all non-r modes) |
# |
wr0 003210 -- r0=3210 |
wr1 003220 -- r1=3220 |
wr2 003140 -- r2=3140 |
wr3 003242 -- r3=3242 |
wr4 003144 -- r4=3144 |
wr5 003160 -- r5=3160 |
wsp 001400 -- sp=1400 |
stapc 003100 -- start @ 3100 |
wtgo |
rr0 d=003210 -- ! r0=3210 |
rr1 d=003222 -- ! r1=3222 |
rr2 d=003142 -- ! r2=3142 |
rr3 d=003240 -- ! r3=3240 |
rr4 d=003142 -- ! r4=3142 |
rr5 d=003176 -- ! r5=3176 |
rsp d=001400 -- ! sp |
rpc d=003124 -- ! pc |
wal 003160 |
brm 7 |
d=000110 -- ! mem(3160)=110 |
d=000120 -- ! mem(3162)=120 |
d=000130 -- ! mem(3164)=130 |
d=000140 -- ! mem(3166)=140 |
d=000150 -- ! mem(3170)=150 |
d=000160 -- ! mem(3172)=160 |
d=000170 -- ! mem(3174)=170 |
#----------------------------------------------------------------------------- |
C Setup code 12 [base 3300; use 33-34] (PSW access via sex,clx,spl,mov, and clr) |
# |
wal 003300 -- code: |
bwm 23 |
011025 -- mov (r0),(r5)+ |
012710 -- mov #030000,(r0) ; write full PSW: pmode=um |
030000 |
011025 -- mov (r0),(r5)+ |
000263 -- se(v,c) |
011025 -- mov (r0),(r5)+ |
000237 -- spl 7 |
011025 -- mov (r0),(r5)+ |
#3320 |
000274 -- se(n,z) |
011025 -- mov (r0),(r5)+ |
000233 -- spl 3 |
011025 -- mov (r0),(r5)+ |
000241 -- clc |
011025 -- mov (r0),(r5)+ |
112710 -- movb #40,(r0) ; write PSW_low (set pri=1) |
000040 |
#3340 |
011025 -- mov (r0),(r5)+ |
112711 -- movb #20,(r1) ; write PSW_high: pmode=sm |
000020 |
011025 -- mov (r0),(r5)+ |
005010 -- clr (r0) |
011025 -- mov (r0),(r5)+ |
000000 -- halt |
# |
C Exec code 12 (PSW access via sex,clx,spl,mov, and clr) |
# |
wps 000017 -- psw: set all condition codes (to check psw clear @ start) |
# |
wr0 177776 -- r0=177776 |
wr1 177777 -- r1=177777 |
wr5 003400 -- r5=3400 |
wsp 001400 -- sp=1400 |
stapc 003300 -- start @ 3300 |
wtgo |
rr5 d=003424 -- ! r5=3424 |
rpc d=003356 -- ! pc |
wal 003400 |
brm 10 |
d=000340 -- ! mem(3400) after start |
d=030000 -- ! mem(3402) after mov #030000,(r0) |
d=030003 -- ! mem(3404) after se(v,c) (VC) |
d=030341 -- ! mem(3406) after spl 7 (pri=7,C) |
d=030355 -- ! mem(3410) after se(n,z) (pri=7,NZC) |
d=030141 -- ! mem(3412) after spl 3 (pri=3,C) |
d=030140 -- ! mem(3414) after clc (pri=3) |
d=030040 -- ! mem(3416) after movb #40,(r0) (pri=1) |
d=010040 -- ! mem(3420) after movb #20,(r1) pmode=sm |
d=000000 -- ! mem(3422) after clr (r0) |
#----------------------------------------------------------------------------- |
C Setup code 13 [base 3500] (test WAIT and rdma (bwm/rwm while CPU running) |
# |
#[[off]] - can't emulate 'sto' command in simh, rdma meaningless in simh |
# |
wal 003500 -- code 13.1 (to be stepped) |
bwm 4 |
000001 -- wait |
000001 -- wait |
000001 -- wait |
000000 -- halt |
# |
wal 003520 -- code 13.2 (busy loop) |
bwm 3 |
005700 -- tst r0 |
001776 -- beq .-1 |
000000 -- halt |
# |
wal 003540 -- code 13.3 (just a WAIT) |
bwm 2 |
000001 -- wait |
000000 -- halt |
# |
C Exec code 13.1a (run WAIT) |
# |
stapc 003500 -- start @ 3500 |
.wait 20 -- let it go |
rpc d=003502 -- ! should hang here ... |
.wait 20 -- let it go |
rpc d=003502 -- ! should hang here ... |
sto |
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command |
rpc d=003502 -- ! should stay there ... |
# |
C Exec code 13.1b (step WAIT) |
wpc 003500 -- pc=3500 |
step -- step over 1st WAIT |
rpc d=003502 -- ! |
step -- step over 2nd WAIT |
rpc d=003504 -- ! |
step -- step over 3rd WAIT |
rpc d=003506 -- ! |
step -- step over HALT |
rpc d=003510 -- ! |
# |
C Exec code 13.2 (test bwm/brm while CPU busy looping) |
wr0 000000 -- r0=0 |
stapc 003520 -- start @ 3520 |
# |
wal 003560 -- write data while CPU active |
bwm 8 |
003560 |
003562 |
003564 |
003566 |
003570 |
003572 |
003574 |
003576 |
wal 003560 -- read data while CPU active |
brm 8 |
d=003560 |
d=003562 |
d=003564 |
d=003566 |
d=003570 |
d=003572 |
d=003574 |
d=003576 |
# |
wr0 000001 -- r0=1 --> should end loop |
wtgo |
rpc d=003526 -- ! |
# |
C Exec code 13.3 (test bwm/brm while CPU on WAIT) |
# |
stapc 003540 -- start @ 3540 |
# |
wal 003560 -- write data while CPU active |
bwm 8 |
073560 |
073562 |
073564 |
073566 |
073570 |
073572 |
073574 |
073576 |
wal 003560 -- read data while CPU active |
brm 8 |
d=073560 |
d=073562 |
d=073564 |
d=073566 |
d=073570 |
d=073572 |
d=073574 |
d=073576 |
# |
sto |
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command |
rpc d=003542 -- ! |
#[[on]] |
#----------------------------------------------------------------------------- |
# Setup code 14 --- code 14 doesn't exist anymore... |
#----------------------------------------------------------------------------- |
C Setup code 15 [base 3600; use 36-37] (test 4 traps) |
# |
wal 003600 -- code: |
bwm 5 |
000003 -- bpt (to 14) |
000004 -- iot (to 20) |
104077 -- emt 77 (to 30) |
104477 -- trap 77 (to 34) |
000000 -- halt |
# |
wal 003620 -- code: trap handlers |
bwm 11 |
010025 -- mov r0,(r5)+ (@ 3620) |
000405 -- br .+10 |
010125 -- mov r1,(r5)+ (@ 3624) |
000403 -- br .+6 |
010225 -- mov r2,(r5)+ (@ 3630) |
000401 -- br .+2 |
010325 -- mov r3,(r5)+ (@ 3634) |
#3640 |
011604 -- mov (sp),r4 ; r4 points after instruction |
016425 -- mov -2(r4),(r5)+ ; load instruction |
177776 |
000002 -- rti |
# |
wal 000014 -- vector: 14+20 |
bwm 4 |
003620 -- PC:3620 |
000000 -- PS:0 |
003624 -- PC:3624 |
000000 -- PS:0 |
wal 000030 -- vector: 30+34 |
bwm 4 |
003630 -- PC:3630 |
000000 -- PS:0 |
003634 -- PC:3634 |
000000 -- PS:0 |
# |
C Exec code 15 (test 4 traps) |
# |
wr0 000011 -- r0=11 |
wr1 000022 -- r1=22 |
wr2 000033 -- r2=33 |
wr3 000044 -- r3=44 |
wr5 003700 -- r5=3700 |
wsp 001400 -- sp=140 |
stapc 003600 -- start @ 3600 |
wtgo |
rr5 d=003720 -- ! r5=3720 |
rsp d=001400 -- ! sp |
rpc d=003612 -- ! pc |
wal 003700 |
brm 8 |
d=000011 -- ! mem(3700)=11 |
d=000003 -- ! mem(3702)=3 |
d=000022 -- ! mem(3704)=22 |
d=000004 -- ! mem(3706)=4 |
d=000033 -- ! mem(3710)=33 |
d=104077 -- ! mem(3712)=104077 |
d=000044 -- ! mem(3714)=44 |
d=104477 -- ! mem(3716)=104477 |
wal 000014 -- vector: 14+20 -> trap catcher again |
bwm 4 |
000016 -- PC:16 |
000000 -- PS:0 |
000022 -- PC:22 |
000000 -- PS:0 |
wal 000030 -- vector: 30+34 -> trap catcher again |
bwm 4 |
000032 -- PC:32 |
000000 -- PS:0 |
000036 -- PC:36 |
000000 -- PS:0 |
#----------------------------------------------------------------------------- |
C Setup code 16 [base 4000] (enable MMU, check ssr1, ssr2 response) |
# |
wal 172516 -- SSR3 |
wmi 000002 -- I/D enabled for sm only (to check CRESET) |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
# |
wal 004000 -- code (to be single stepped...) |
bwm 7 |
011105 -- mov (r1),r5 |
012105 -- mov (r1)+,r5 |
014105 -- mov -(r1),r5 |
012122 -- mov (r1)+,(r2)+ |
112105 -- movb (r1)+,r5 |
112721 -- movb #200,(r1)+ |
000200 |
# |
wal 004030 -- code test 1: |
wmi 000000 -- halt |
# |
wal 004040 -- data: |
bwm 2 |
000001 |
000300 |
# |
C Exec code 16 (enable MMU, check ssr1, ssr2 response) |
# |
wr1 004040 -- r1=4040 |
wr2 004060 -- r2=4060 |
wsp 001400 -- sp=1400 |
wpc 004000 -- pc=4000 |
step -- step (mov (r1),r5) |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=000000 -- ! SSR1: |
d=004000 -- ! SSR2: 4000 (eff. PC) |
rr1 d=004040 -- ! r1 |
rr5 d=000001 -- ! r5 |
step -- step (mov (r1)+,r5) |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=000021 -- ! SSR1: rb none; ra=1,+2 |
d=004002 -- ! SSR2: 4002 (eff. PC) |
rr1 d=004042 -- ! r1 |
rr5 d=000001 -- ! r5 |
step -- step (mov -(r1),r5) |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=000361 -- ! SSR1: rb none; ra=1,-2 |
d=004004 -- ! SSR2: 4004 (eff. PC) |
rr1 d=004040 -- ! r1 |
rr5 d=000001 -- ! r5 |
step -- step (mov (r1)+,(r2)+) |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=011021 -- ! SSR1: rb=2,2; ra=1,2 |
d=004006 -- ! SSR2: 4006 (eff. PC) |
rr1 d=004042 -- ! r1 |
rr2 d=004062 -- ! r2 |
step -- step (movb (r1)+,r5) |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=000011 -- ! SSR1: rb=none; ra=1,1 |
d=004010 -- ! SSR2: 4010 (eff. PC) |
rr1 d=004043 -- ! r1 |
rr5 d=177700 -- ! r5 |
step -- step (movb #200,(r1)+) |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=004427 -- ! SSR1: rb=1,1; ra=7,2 |
d=004012 -- ! SSR2: 4012 (eff. PC) |
rr1 d=004044 -- ! r1 |
# |
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start) |
# |
wps 000000 -- psw: set pri=0 |
stapc 004030 -- start @ 4030 (just HALT, testing console reset) |
wtgo |
rpc d=004032 -- ! pc=4032 |
rps d=000340 -- ! psw: reset by CRESET |
wal 172516 -- SSR3 |
rmi d=000000 -- ! cleared by CRESET |
wal 177572 -- SSR0 |
rmi d=000000 -- ! cleared by CRESET |
#----------------------------------------------------------------------------- |
C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test) |
# |
wal 004100 -- code: (length 70) |
bwm 32 |
010124 -- mov r1,(r4)+ (#4711, #123456) |
020124 -- cmp r1,(r4)+ (#4711, #123456) |
020224 -- cmp r2,(r4)+ (#123456,#4711) |
020124 -- cmp r1,(r4)+ (#4711, #4711) |
005024 -- clr (r4)+ (#123456) |
030124 -- bit r1,(r4)+ (#4711, #11) |
030124 -- bit r1,(r4)+ (#4711, #66) |
040124 -- bic r1,(r4)+ (#4711, #123456) |
#4120 |
050124 -- bis r1,(r4)+ (#4711, #123456) |
060124 -- add r1,(r4)+ (#4711, #123456) |
160124 -- sub r1,(r4)+ (#4711, #123456) |
005124 -- com (r4)+ (#123456) |
005224 -- inc (r4)+ (#123456) |
005324 -- dec (r4)+ (#123456) |
005424 -- neg (r4)+ (#123456) |
005724 -- tst (r4)+ (#123456) |
#4140 |
006024 -- ror (r4)+ (#100201) Cin=0; Cout=1 |
006024 -- ror (r4)+ (#002201) Cin=1; Cout=1 |
006124 -- rol (r4)+ (#100200) Cin=1; Cout=1 |
006224 -- asr (r4)+ (#200) |
006224 -- asr (r4)+ (#100200) |
006324 -- asl (r4)+ (#200) |
006324 -- asl (r4)+ (#100200) |
060124 -- add r1,(r4)+ (#4711, #077777) |
#4160 |
005524 -- adc (r4)+ (#200) |
160124 -- sub r1,(r4)+ (#4711, #4700) |
005624 -- sbc (r4)+ (#200) |
000324 -- swap (r4)+ (#111000) |
006724 -- sxt (r4)+ (#111111 with N=1) |
074124 -- xor r1,(r4)+ (#070707,#4711) |
006724 -- sxt (r4)+ (#111111 with N=0) |
000000 -- halt |
# |
wal 000014 -- vector: 14 |
bwm 2 |
004270 -- PC:4270 |
000000 -- PS:0 |
#----- |
wal 004270 -- code: (trap 14): |
bwm 3 |
016625 -- mov 2(sp),(r5)+ |
000002 |
000006 -- rtt |
#----- |
wal 004300 -- data 1: (length 66) |
bwm 31 |
123456 -- |
123456 -- |
004711 -- |
004711 -- |
123456 -- |
000011 -- |
000066 -- |
123456 -- |
#4320 |
123456 -- |
123456 -- |
123456 -- |
123456 -- |
123456 -- |
123456 -- |
123456 -- |
123456 -- |
#4340 |
100201 -- |
002201 -- |
100200 -- |
000200 -- |
100200 -- |
000200 -- |
100200 -- |
177000 -- |
#4360 |
000200 -- |
004701 -- |
000200 -- |
111000 -- |
111111 -- |
070707 -- |
111111 -- |
# |
C Exec code 17 (basic instruction and cc test) |
# |
wr1 004711 -- r1=4711 |
wr2 123456 -- r2=123456 |
wr4 004300 -- r4=4300 |
wr5 004500 -- r5=4500 |
wsp 001374 -- sp=1374 |
wal 001374 -- setup stack with rtt return frame setting T flag |
bwm 2 |
004100 -- start address (code 17 @ 4100) |
000020 -- set T flag in PSW |
stapc 004274 -- start @ 4274 -> rtt -> 4100 from stack |
wtgo |
rr1 d=004711 -- ! r1=4711 |
rr2 d=123456 -- ! r2=123456 |
rr4 d=004376 -- ! r4=4376 |
rr5 d=004576 -- ! r5=4576 |
rsp d=001400 -- ! sp=1400 |
rpc d=004200 -- ! pc=4200 |
wal 004300 |
brm 31 |
d=004711 -- ! mem(4300)=004711; mov r1,(r4)+ (#4711, #123456) |
d=123456 -- ! mem(4302)=123456; cmp r1,(r4)+ (#4711, #123456) |
d=004711 -- ! mem(4304)=004711; cmp r1,(r4)+ (#123456,#4711) |
d=004711 -- ! mem(4306)=004711; cmp r1,(r4)+ (#4711, #4711) |
d=000000 -- ! mem(4310)=000000; clr (r4)+ (#123456) |
d=000011 -- ! mem(4312)=000011; bit r1,(r4)+ (#4711, #11) |
d=000066 -- ! mem(4314)=000066; bit r1,(r4)+ (#4711, #66) |
d=123046 -- ! mem(4316)=123046; bic r1,(r4)+ (#4711, #123456) |
d=127757 -- ! mem(4320)=127757; bis r1,(r4)+ (#4711, #123456) |
d=130367 -- ! mem(4322)=130367; add r1,(r4)+ (#4711, #123456) |
d=116545 -- ! mem(4324)=116545; sub r1,(r4)+ (#4711, #123456) |
d=054321 -- ! mem(4326)=054321; com (r4)+ (#123456) |
d=123457 -- ! mem(4330)=123457; inc (r4)+ (#123456) |
d=123455 -- ! mem(4332)=123455; dec (r4)+ (#123456) |
d=054322 -- ! mem(4334)=054322; neg (r4)+ (#123456) |
d=123456 -- ! mem(4336)=123456; tst (r4)+ (#123456) |
d=040100 -- ! mem(4340)=040100; ror (r4)+ (#100201) |
d=101100 -- ! mem(4342)=101100; ror (r4)+ (#002201) |
d=000401 -- ! mem(4344)=000401; rol (r4)+ (#100200) |
d=000100 -- ! mem(4346)=000100; asr (r4)+ (#200) |
d=140100 -- ! mem(4350)=140100; asr (r4)+ (#100200) |
d=000400 -- ! mem(4352)=000400; asl (r4)+ (#200) |
d=000400 -- ! mem(4354)=000400; asl (r4)+ (#100200) |
d=003711 -- ! mem(4356)=003711; add r1,(r4)+ (#4711, ,#177000) |
d=000201 -- ! mem(4360)=000201; adc (r4)+ (#200) |
d=177770 -- ! mem(4362)=177770; sub r1,(r4)+ (#4711, #4701) |
d=000177 -- ! mem(4364)=000177; sbc (r4)+ (#200) |
d=000222 -- ! mem(4366)=000222; swap (r4)+ (#111000) |
d=177777 -- ! mem(4370)=177777; sxt (r4)+ (#111111) |
d=074016 -- ! mem(4372)=074016; xor r1,(r4)+ (#070707) |
d=000000 -- ! mem(4374)=000000; sxt (r4)+ (#111111) |
# |
wal 004500 -- NZVC |
brm 31 |
d=000020 -- ! mem(4500)=0000; mov r1,(r4)+ (#4711, #123456) |
d=000021 -- ! mem(4502)=000C; cmp r1,(r4)+ (#4711, #123456) |
d=000030 -- ! mem(4504)=N000; cmp r1,(r4)+ (#123456,#4711) |
d=000024 -- ! mem(4506)=0Z00; cmp r1,(r4)+ (#4711, #4711) |
d=000024 -- ! mem(4510)=0Z00; clr (r4)+ (#123456) |
d=000020 -- ! mem(4512)=0000; bit r1,(r4)+ (#4711, #11) |
d=000024 -- ! mem(4514)=0Z00; bit r1,(r4)+ (#4711, #66) |
d=000030 -- ! mem(4516)=N000; bic r1,(r4)+ (#4711, #123456) |
d=000030 -- ! mem(4520)=N000; bis r1,(r4)+ (#4711, #123456) |
d=000030 -- ! mem(4522)=N000; add r1,(r4)+ (#4711, #123456) |
d=000030 -- ! mem(4524)=N000; sub r1,(r4)+ (#4711, #123456) |
d=000021 -- ! mem(4526)=000C; com (r4)+ (#123456) |
d=000031 -- ! mem(4530)=N00C; inc (r4)+ (#123456) keep C! |
d=000031 -- ! mem(4532)=N00C; dec (r4)+ (#123456) keep C! |
d=000021 -- ! mem(4534)=000C; neg (r4)+ (#123456) |
d=000030 -- ! mem(4536)=N000; tst (r4)+ (#123456) |
d=000023 -- ! mem(4540)=00VC; ror (r4)+ (#100201) |
d=000031 -- ! mem(4542)=N00C; ror (r4)+ (#002201) |
d=000023 -- ! mem(4544)=00VC; rol (r4)+ (#100200) |
d=000020 -- ! mem(4546)=0000; asr (r4)+ (#200) |
d=000032 -- ! mem(4550)=N0V0; asr (r4)+ (#100200) |
d=000020 -- ! mem(4552)=0000; asl (r4)+ (#200) |
d=000023 -- ! mem(4554)=00VC; asl (r4)+ (#100200) |
d=000021 -- ! mem(4556)=000C; add r1,(r4)+ (#4711, ,#177000) |
d=000020 -- ! mem(4560)=0000; adc (r4)+ (#200) |
d=000031 -- ! mem(4562)=N00C; sub r1,(r4)+ (#4711, #4701) |
d=000020 -- ! mem(4564)=0000; sbc (r4)+ (#200) |
d=000030 -- ! mem(4566)=N000; swap (r4)+ (#111000) |
d=000030 -- ! mem(4570)=N000; sxt (r4)+ (#111111 with N=1) |
d=000020 -- ! mem(4572)=0000; xor r1,(r4)+ (#4711, #070707) |
d=000024 -- ! mem(4574)=0Z00; sxt (r4)+ (#111111 with N=0) |
# |
rst -- console reset (to clear T flag) |
wal 000014 -- vector: 14 -> trap catcher again |
bwm 2 |
000016 -- PC:16 |
000000 -- PS:0 |
#----------------------------------------------------------------------------- |
C Setup code 20 [base 4700] (check CPUERR and error handling) |
#[[off]] |
wal 004700 -- code (to be single stepped...) |
bwm 11 |
010025 -- mov r0,(r5)+ (@ 4777) |
010025 -- mov r0,(r5)+ (@ 150000) |
010025 -- mov r0,(r5)+ (@ 160000) |
000101 -- jmp r1 |
004701 -- jsr pc,r1 |
000000 -- halt |
014321 -- mov -(r3),(r1)+ (@ 20000) |
024321 -- cmp -(r3),(r1)+ (@ 20400) |
#4720 |
064321 -- add -(r3),(r1)+ (@ 20000) |
010046 -- mov r0,-(sp) (@ 340) |
000004 -- iot (with sp=342,...) |
# |
wal 000004 -- vector: 4+10 (trap catch) |
bwm 4 |
000006 -- PC:6 |
000000 -- PS:0 |
000012 -- PC:12 |
000000 -- PS:0 |
#---------- |
C Exec code 20 (check CPUERR and error handling) |
C Exec test 20.1 (odd address abort) |
rst -- console reset |
wps 000000 -- psw: clear |
wal 001374 -- clean stack |
bwm 2 |
000000 -- |
000000 -- |
wal 177766 -- check initial CPUERR (=0!) |
rm d=000000 -- ! |
wr0 000011 -- r0=11 |
wr5 004775 -- r5=4775 |
wsp 001400 -- sp=1400 |
wpc 004700 -- pc=4700 |
step -- step (mov r0,(r5)+): trap 4 + CPUERR.adderr set [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=001374 -- ! sp=1374 |
wal 001374 -- check stack |
brm 2 |
d=004702 -- ! pc=4702 |
d=000000 -- ! ps=0 |
wal 177766 -- check CPUERR |
rm d=000100 -- ! CPUERR: (adderr=1) |
wm 000000 -- any write access will clear CPUERR |
rm d=000000 -- ! CPUERR: 0 |
#---------- |
C Exec test 20.2 (non-existent memory abort) |
wal 172354 -- kernel I space AR(6) |
wm 177400 -- (map to 8 k below I/O page, never available in w11a) |
wal 177572 -- SSR0 |
wmi 000001 -- enable |
wal 172516 -- SSR3 |
wmi 000020 -- ena_22bit=1 |
# |
wr5 140000 -- r5=140000 |
wsp 001400 -- sp=1400 |
wpc 004702 -- pc=4702 |
step -- step (mov r0,(r5)+): trap 4 + CPUERR.nxm set [[s:2]] |
rpc d=000006 -- ! pc= 6 (trap 4 catch) |
rsp d=001374 -- ! sp=1374 |
wal 177766 -- check CPUERR |
rm d=000040 -- ! CPUERR: (nxm=1) |
wm 000000 -- any write access will clear CPUERR |
rm d=000000 -- ! CPUERR: 0 |
# |
wal 177572 -- SSR0 |
wmi 000000 -- disable |
wal 172354 -- kernel I space AR(6) |
wm 001400 -- 1400 140000 base (default 1-to-1 map) |
#---------- |
C Exec test 20.3 (I/O bus timeout abort) |
wr5 160000 -- r5=160000 |
wsp 001400 -- sp=1400 |
wpc 004704 -- pc=4704 |
step -- step (mov r0,(r5)+): trap 4 + CPUERR.iobto set [[s:2]] |
rpc d=000006 -- ! pc= 6 (trap 4 catch) |
rsp d=001374 -- ! sp=1374 |
wal 177766 -- check CPUERR |
rm d=000020 -- ! CPUERR: (iobto=1) |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.4 (address error abort after jmp r1) |
wsp 001400 -- sp=1400 |
wpc 004706 -- pc=4706 |
step -- step (jmp r1): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 10 catch) |
rsp d=001374 -- ! sp=1374 |
wal 177766 -- check CPUERR |
rm d=000000 -- ! CPUERR: none |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.5 (address error abort after jsr pc,r1) |
wsp 001400 -- sp=1400 |
wpc 004710 -- pc=4710 |
step -- step (jsr pc,r1): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 10 catch) |
rsp d=001374 -- ! sp=1374 |
wal 177766 -- check CPUERR |
rm d=000000 -- ! CPUERR: none |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.6 (halt in user mode) |
wsp 001400 -- sp=1400 (kernel) |
wpc 004712 -- pc=4712 |
wps 170000 -- psw: cmode=pmode=11 (user) |
step -- step (halt): trap 4 + CPUERR.illhlt set [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=001374 -- ! sp=1374 (now kernel again...) |
wal 001374 -- check stack |
brm 2 |
d=004714 -- ! |
d=170000 -- ! |
wal 177766 -- check CPUERR |
rm d=000200 -- ! CPUERR: (illhlt=1) |
wm 000000 -- clear CPUERR |
# |
wps 000000 -- psw: cmode=pmode=0 (kernel) |
#---------- |
# |
# test mmu aborts |
# |
wal 000250 -- vector: 250 -> trap catcher |
bwm 2 |
000252 -- PC:252 |
000000 -- PS:0 |
# |
wal 177572 -- SSR0 |
wmi 000001 -- enable |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident) |
#---------- |
C Exec test 20.7 (non resident abort) |
wr1 020000 -- r1=20000 |
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16 |
wsp 001400 -- sp=1400 |
wpc 004714 -- pc=4714 |
step -- step (mov -(r3),(r1)+): abort to 250 [[s:2]] |
rr1 d=020002 -- ! r1=20002 (inc done before trap (here dstw)) |
rr3 d=000014 -- ! r3=16 (dec done before trap) |
rpc d=000252 -- ! pc=252 (trap 250 catch) |
rsp d=001374 -- ! sp=1374 |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=100003 -- ! SSR0: (abo_nonres=1,seg=1,ena=1) |
d=010763 -- ! SSR1: rb=1,2; ra=3,-2 |
d=004714 -- ! SSR2: 4714 (eff. PC) |
# |
wal 177572 -- SSR0 |
wmi 000001 -- enable and clear error bits |
#---------- |
C Exec test 20.8 (segment length violation abort) |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 001406 -- slf=3; ed=0(up); acf=6 (w/r) |
# |
wr1 020400 -- r1=20400 |
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16 |
wsp 001400 -- sp=1400 |
wpc 004716 -- pc=4716 |
step -- step (cmp -(r3),(r1)+): abort to 250 [[s:2]] |
rr1 d=020402 -- ! r1=20402 (inc done before trap (here dstr)) |
rr3 d=000014 -- ! r3=16 (dec done before trap) |
rpc d=000252 -- ! pc=252 (trap 250 catch) |
rsp d=001374 -- ! sp=1374 |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=040003 -- ! SSR0: (abo_length=1,seg=1,ena=1) |
d=010763 -- ! SSR1: rb=1,2; ra=3,-2 |
d=004716 -- ! SSR2: 4716 (eff. PC) |
# |
wal 177572 -- SSR0 |
wmi 000001 -- enable and clear error bits |
#---------- |
C Exec test 20.9 (read-only abort) |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 077402 -- slf=127; ed=0(up); acf=2 (read-only) |
# |
wr1 020000 -- r1=20000 |
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16 |
wsp 001400 -- sp=1400 |
wpc 004720 -- pc=4720 |
step -- step (add -(r3),(r1)+): abort to 250 [[s:2]] |
rr1 d=020002 -- ! r1=20000 (inc done before trap (here dstm)) |
rr3 d=000014 -- ! r3=16 (dec done before trap) |
rpc d=000252 -- ! pc=252 (trap 250 catch) |
rsp d=001374 -- ! sp=1374 |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=020003 -- ! SSR0: (abo_rdonly=1,seg=1,ena=1) |
d=010763 -- ! SSR1: rb=1,2; ra=3,-2 |
d=004720 -- ! SSR2: 4720 (eff. PC) |
# |
# mmu back to default setup, disable |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w) |
wal 177572 -- SSR0 |
wmi 000000 -- disable |
#---------- |
# |
# test mmu trap |
# |
wal 177572 -- SSR0 |
wmi 001001 -- enable, trap enable |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 077404 -- slf=127; ed=0(up); acf=4 (r/w, trap on r/w) |
#---------- |
C Exec test 20.10 (trap on write) |
wr1 020000 -- r1=20000 |
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16 |
wsp 001400 -- sp=1400 |
wpc 004714 -- pc=4714 |
step -- step (mov -(r3),(r1)+): trap to 250 [[s:2]] |
rr1 d=020002 -- ! r1=20002 (inc done before trap) |
rr3 d=000014 -- ! r3=16 (dec done before trap) |
rpc d=000252 -- ! pc=252 (trap 250 catch) |
rsp d=001374 -- ! sp=1374 |
wal 020000 -- check target area |
rm d=000016 -- ! mem(20000)=16 |
wm 000000 -- clean tainted memory |
wal 177572 -- check SSR0 |
brm 3 |
d=011001 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=0,ena=1) |
d=010763 -- ! SSR1: rb=1,2; ra=3,-2 |
d=004714 -- ! SSR2: 4714 (eff. PC) |
#---------- |
C Exec test 20.11 (2nd write, should not trap again) |
wr1 020002 -- r1=20002 |
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16 |
wsp 001400 -- sp=1400 |
wpc 004714 -- pc=4714 |
step -- step (mov -(r3),(r1)+): no trap [[s:2]] |
rr1 d=020004 -- ! r1=20004 (inc done before trap) |
rr3 d=000014 -- ! r3=16 (dec done before trap) |
rpc d=004716 -- ! pc=252 (trap 250 catch) |
rsp d=001400 -- ! sp=1374 |
wal 020002 -- check target area |
rm d=000016 -- ! mem(20002)=16 |
wm 000000 -- clean tainted memory |
wal 177572 -- check SSR0 |
brm 3 |
d=011003 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=1,ena=1) |
d=010763 -- ! SSR1: rb=1,2; ra=3,-2 |
d=004714 -- ! SSR2: 4714 (eff. PC) |
# |
# mmu back to default setup, disable |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w) |
wal 177572 -- SSR0 |
wmi 000000 -- disable |
#---------- |
# |
# now test stack limit logic |
# |
C Exec test 20.12 (red stack abort when pushing data to stack) |
wr0 123456 -- r0=123456 |
wsp 000340 -- sp=340 |
wpc 004722 -- pc=4722 |
step -- step (mov r0,-(sp)): abort to 4 [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000000 -- ! sp=0 |
wal 000336 -- check that stack wasn't written |
rm d=000000 -- ! mem(336) untainted |
wal 000000 -- check emergency stack at 0,2 |
brm 2 |
d=004724 -- ! mem(0): PC |
d=000010 -- ! mem(2): PS |
wal 177766 -- check CPUERR |
rm d=000004 -- ! CPUERR: (rsv=1) |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.13 (red stack abort on 2nd word of interrupt/trap push) |
wps 000017 -- psw: set all cc flags |
wsp 000342 -- sp=342 |
wpc 004724 -- pc=4724 |
step -- step (iot): abort to 4 [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000000 -- ! sp=0 |
wal 000336 -- check stack |
brm 2 |
d=000000 -- ! mem(336) untainted |
d=000017 -- ! mem(340) PS of 1st attempt |
wal 000000 -- check emergency stack at 0,2 |
brm 2 |
d=004726 -- ! mem(0): PC |
d=000000 -- ! mem(2): PS (will be 0, orgininal PS lost !!) |
wal 177766 -- check CPUERR |
rm d=000004 -- ! CPUERR: (rsv=1) |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.14 (yellow stack trap when pushing data to stack; sp=400) |
wps 000017 -- psw: set all cc flags |
wr0 123456 -- r0=123456 |
wsp 000400 -- sp=400 |
wpc 004722 -- pc=4722 |
step -- step (mov r0,-(sp)): trap to 4 |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000372 -- ! sp=372 |
wal 000372 -- check stack |
brm 3 |
d=004724 -- ! mem(372) PC of trapped instruction |
d=000011 -- ! mem(374) PS of trapped instruction |
d=123456 -- ! mem(376) pushed word |
wal 177766 -- check CPUERR |
rm d=000010 -- ! CPUERR: (ysv=1) |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.15 (yellow stack trap on 2nd word of interrupt/trap push; sp=402) |
wps 000017 -- psw: set all cc flags |
wsp 000402 -- sp=402 |
wpc 004724 -- pc=4724 |
step -- step (iot): abort to 4 [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000372 -- ! sp=372 |
wal 000372 -- check stack |
brm 4 |
d=000022 -- ! mem(372) PC of IOT handler |
d=000000 -- ! mem(374) PS of IOT handler |
d=004726 -- ! mem(376) PC of IOT trap |
d=000017 -- ! mem(400) PS of IOT trap |
wal 177766 -- check CPUERR |
rm d=000010 -- ! CPUERR: (ysv=1) |
wm 000000 -- clear CPUERR |
#---------- |
# now test red stack escalation |
# |
C Exec test 20.16 (red stack escalation: abort kernel stack odd; sp=1001) |
wr0 123456 -- r0=123456 |
wsp 001001 -- sp=1001 |
wpc 004722 -- pc=4722 |
step -- step (mov r0,-(sp)): abort to 4 [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000000 -- ! sp=0 |
wal 000000 -- check emergency stack at 0,2 |
brm 2 |
d=004724 -- ! mem(0): PC |
d=000010 -- ! mem(2): PS |
wal 177766 -- check CPUERR |
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1) |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.17 (red stack escalation: abort kernel stack in non-mem) |
wal 172354 -- kernel I space AR(6) |
wm 177400 -- (map to 8 k below I/O page, never available in w11a) |
wal 177572 -- SSR0 |
wmi 000001 -- enable |
wal 172516 -- SSR3 |
wmi 000020 -- ena_22bit=1 |
# |
wr0 123456 -- r0=123456 |
wsp 140004 -- sp=140004 |
wpc 004722 -- pc=4722 |
step -- step (mov r0,-(sp)): abort to 4 [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000000 -- ! sp=0 |
wal 000000 -- check emergency stack at 0,2 |
brm 2 |
d=004724 -- ! mem(0): PC |
d=000010 -- ! mem(2): PS |
wal 177766 -- check CPUERR |
rm d=000044 -- ! CPUERR: (rsv=1,nxm=1) |
wm 000000 -- clear CPUERR |
# |
wal 177572 -- SSR0 |
wmi 000000 -- disable |
wal 172354 -- kernel I space AR(6) |
wm 001400 -- 1400 140000 base (default 1-to-1 map) |
#---------- |
C Exec test 20.18 (red stack escalation: abort kernel stack iob-to;sp=160004) |
wr0 123456 -- r0=123456 |
wsp 160004 -- sp=160004 |
wpc 004722 -- pc=4722 |
step -- step (mov r0,-(sp)): abort to 4 [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000000 -- ! sp=0 |
wal 000000 -- check emergency stack at 0,2 |
brm 2 |
d=004724 -- ! mem(0): PC |
d=000010 -- ! mem(2): PS |
wal 177766 -- check CPUERR |
rm d=000024 -- ! CPUERR: (rsv=1,iobto=1) |
wm 000000 -- clear CPUERR |
#---------- |
C Exec test 20.19 (red stack escalation: abort kernel stack mmu abort;sp=020004) |
# |
wal 177572 -- SSR0 |
wmi 000001 -- enable |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident) |
# |
wr0 123456 -- r0=123456 |
wsp 020004 -- sp=020004 |
wpc 004722 -- pc=4722 |
step -- step (mov r0,-(sp)): abort to 4 [[s:2]] |
rpc d=000006 -- ! pc=6 (trap 4 catch) |
rsp d=000000 -- ! sp=0 |
wal 020002 -- check that stack wasn't written |
rm d=000000 -- ! mem(20002) untainted |
wal 000000 -- check emergency stack at 0,2 |
brm 2 |
d=004724 -- ! mem(0): PC |
d=000010 -- ! mem(2): PS |
wal 177766 -- check CPUERR |
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1) |
wm 000000 -- clear CPUERR |
# mmu back to default setup |
wal 172302 -- kernel I space DR segment 1 (base 20000) |
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w) |
wal 177572 -- SSR0 |
wmi 000000 -- disable |
wal 172516 -- SSR3 |
wmi 000000 -- disable |
# |
#[[on]] |
#----------------------------------------------------------------------------- |
C Setup code 21 [base 4740] (MTPx/MFPx; MMU for user mode with I/D) |
# |
#use setting as for test 22 |
wal 177600 -- user I space DR |
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r) |
wal 177620 -- user D space DR |
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r) |
wal 177640 -- user I space AR |
wmi 000053 -- 53 -> maps 0 -> 5300 |
wal 177660 -- user D space AR |
wmi 000055 -- 55 -> maps 0 -> 5500 |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wal 172516 -- SSR3 |
wmi 000001 -- enable D space for user mode |
# |
wal 004740 -- code (to be single stepped...) |
bwm 6 |
006610 -- mtpi (r0) |
106610 -- mtpd (r0) |
006606 -- mtpi r6 |
006510 -- mfpi (r0) |
106510 -- mfpd (r0) |
006506 -- mfpi r6 |
# |
C Exec code 21 (MTPx/MFPx; MMU for user mode with I/D) |
# |
wps 030000 -- psw: cmode=0, pmode=11 |
wal 001372 -- setup kernel stack |
bwm 3 |
012300 -- |
001230 -- |
000666 -- |
wr0 000002 -- r0=2 |
wsp 001372 -- sp=1372 |
# |
wpc 004740 -- pc=4740 |
step -- step (mtpi (r0)) |
rpc d=004742 -- ! pc=next |
rsp d=001374 -- ! sp=1374 (one popped) |
wal 005302 -- user I base |
rm d=012300 -- ! mem_ui(2) = 012300 |
# |
step -- step (mtpd (r0)) |
rpc d=004744 -- ! pc=next |
rsp d=001376 -- ! sp=1376 (one popped) |
wal 005502 -- user D base |
rm d=001230 -- ! mem_ud(2) = 001230 |
# |
step -- step (mtpi r6) |
rpc d=004746 -- ! pc=next |
rsp d=001400 -- ! sp=1400 (one popped) |
wps 170000 -- psw: cmode=11, pmode=11 |
rsp d=000666 -- ! sp_um=666 [[usp]] |
wps 030000 -- psw: cmode=0, pmode=11 |
# |
wal 001374 -- clear stack |
bwm 3 |
000000 -- |
000000 -- |
000000 -- |
# |
step -- step (mfpi (r0)) |
rpc d=004750 -- ! pc=next |
rsp d=001376 -- ! sp=1376 (one pushed) |
wal 001376 -- top of stack |
rm d=012300 -- ! |
# |
step -- step (mfpd (r0)) |
rpc d=004752 -- ! pc=next |
rsp d=001374 -- ! sp=1374 (one pushed) |
wal 001374 -- top of stack |
rm d=001230 -- ! |
# |
step -- step (mtpi r6) |
rpc d=004754 -- ! pc=next |
rsp d=001372 -- ! sp=1372 (one pushed) |
wal 001372 -- top of stack |
rm d=000666 -- ! |
# |
wal 005302 -- clean tainted memory |
wm 000000 -- |
wal 005502 -- |
wm 000000 -- |
# |
wps 000000 -- psw: cmode=pmode=0 (kernel) |
#----------------------------------------------------------------------------- |
C Setup code 22 [base 5000, use 50-57] (MMU ; run user mode code with I/D) |
# |
wal 177600 -- user I space DR |
wmi 000002 -- slf=0; ed=0(up); acf=2(read-only) |
wal 177620 -- user D space DR |
wmi 000006 -- slf=0; ed=0(up); acf=6(w/r) |
wal 177640 -- user I space AR |
wmi 000053 -- 53 -> maps 0 -> 5300 |
wal 177660 -- user D space AR |
wmi 000055 -- 55 -> maps 0 -> 5500 |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wal 172516 -- SSR3 |
wmi 000001 -- enable D space for user mode |
# |
wal 005000 -- code (kernel): |
bwm 5 |
012746 -- mov #144000,-(sp) ;PS for RTI |
174000 -- cmode=11,pmode=11,rset=1 |
012746 -- mov #0,-(sp) ;PC for RTI |
000000 -- |
000002 -- rti |
#----- |
wal 000034 -- vector: 34 (TRAP) |
bwm 2 |
005020 -- PC:5020 |
000340 -- PS: pri=7 |
#----- |
wal 005020 -- code (kernel, trap 34): |
bwm 4 |
011600 -- mov (sp),r0 |
006560 -- mfpi -2(r0) |
177776 |
000000 -- halt |
#----- |
wal 000250 -- vector: 250 (MMU) |
bwm 2 |
005040 -- PC:5040 |
000340 -- PS: pri=7 |
#----- |
wal 005040 -- code (kernel, trap 4): |
bwm 68 |
005337 -- dec @#5256 |
005256 |
001001 -- bne .+2 |
000000 -- halt |
013700 -- mov ssr0,r0 |
177572 |
042700 -- bic #177741,r0 ; clear all but id+asn fields |
177741 |
#5060 |
062700 -- add #177600,r0 ; user DR address base |
177600 |
# 5 23 062710 0 -- add #400,(r0) |
# 5 23 000400 0 |
105260 -- incb 1(r0) ; odd address IB access fails !! |
000001 |
010025 -- mov r0,(r5)+ |
012025 -- mov (r0),(r5)+ |
013700 -- mov ssr1,r0 |
177574 |
#5100 |
010025 -- mov r0,(r5)+ |
012701 -- mov #2,r1 |
000002 |
052737 -- bis #004000,psw |
004000 |
177776 |
005046 -- clr -(sp) |
106506 -- mfpd sp |
#5120 |
010546 -- mov r5,-(sp) |
010446 -- mov r4,-(sp) |
010346 -- mov r3,-(sp) |
010246 -- mov r2,-(sp) |
010146 -- mov r1,-(sp) |
010046 -- mov r0,-(sp) |
042737 -- bic #004000,psw |
004000 |
#5140 |
177776 |
010002 -- L1: mov r0,r2 |
110003 -- movb r0,r3 |
042702 -- bic #177770,r2 ; mask regnum field |
177770 |
006302 -- asl r2 |
060602 -- add sp,r2 ; address of reg on stack |
006203 -- asr r3 ; shift delta field down 3 bit |
#5160 |
006203 -- asr r3 |
006203 -- asr r3 |
160312 -- sub r3,(r2) ; correct register contents |
000300 -- swap r0 |
077114 -- sob r1,L1 (.-12) |
052737 -- bis #004000,psw |
004000 |
177776 |
#5200 |
012600 -- mov (sp)+,r0 |
012601 -- mov (sp)+,r1 |
012602 -- mov (sp)+,r2 |
012603 -- mov (sp)+,r3 |
012604 -- mov (sp)+,r4 |
012605 -- mov (sp)+,r5 |
106606 -- mtpd sp |
005726 -- tst (sp)+ |
#5220 |
042737 -- bic #004000,psw |
004000 |
177776 |
013700 -- mov ssr2,r0 |
177576 |
010025 -- mov r0,(r5)+ |
010016 -- mov r0,(sp) |
042737 -- bic #160000,ssr0 ; clear abort bits |
#5240 |
160000 |
177572 |
000002 -- rti |
000000 -- halt |
#----- |
wal 005256 -- data (kernel): |
wmi 000003 -- stop at 3rd call of MMU handler |
#----- |
wal 005300 -- code (user): |
bwm 8 |
012706 -- mov #100,sp |
000100 |
005000 -- clr r0 |
012701 -- mov #074,r1 |
000074 |
062021 -- add (r0)+,(r1)+ ; r1 = 74 |
000137 -- jmp @#74 |
000074 |
# |
wal 005374 -- .=5374 |
bwm 4 |
062021 -- add (r0)+,(r1)+ ; r1 = 76 |
062021 -- add (r0)+,(r1)+ ; r1 = 100 |
#5400 |
062021 -- add (r0)+,(r1)+ ; r1 = 102 |
104417 -- trap 17 |
# |
wal 005500 -- data (user): |
bwm 4 |
002001 -- mem_ud(0)=02001 |
002002 -- mem_ud(2)=02002 |
002003 -- mem_ud(4)=02003 |
002004 -- mem_ud(6)=02004 |
wal 005574 -- data (user): |
bwm 4 |
000300 -- mem_ud(074)=0300 |
000300 -- mem_ud(076)=0300 |
000300 -- mem_ud(100)=0300 |
000300 -- mem_ud(102)=0300 |
# |
C Exec code 22 (MMU ; run user mode code with I/D) |
wr5 005260 -- r5=5260 |
wsp 001400 -- sp=1400 |
wpc 005000 -- pc=5000 |
cont -- cont @ 5000 |
wtgo |
rsp d=001372 -- ! sp |
rpc d=005030 -- ! pc (halt in TRAP handler) |
wal 001372 -- check stack (1372) |
brm 3 |
d=104417 -- ! TRAP instruction |
d=000104 -- ! PC trap |
d=174000 -- ! PS trap |
# |
wal 005256 -- |
brm 9 |
d=000001 -- ! mem(5256) (mmu 3 - trap count) |
d=177620 -- ! mem(5260) (1st trap: address fixed DR) |
d=000406 -- ! mem(5262) (1st trap: new content of DR) |
d=010420 -- ! mem(5264) (1st trap: ssr1: ra=0,2;rb=1,2) |
d=000076 -- ! mem(5266) (1st trap: ssr2: pc) |
d=177600 -- ! mem(5270) (2nd trap: address fixed DR) |
d=000402 -- ! mem(5272) (2nd trap: new content of DR) |
d=000000 -- ! mem(5274) (2nd trap: ssr1: none) |
d=000100 -- ! mem(5276) (2nd trap: ssr2: pc) |
# |
wal 005574 |
brm 4 |
d=002301 -- ! mem(5574)=02301 was mem_ud(074) |
d=002302 -- ! mem(5576)=02302 was mem_ud(076) |
d=002303 -- ! mem(5600)=02303 was mem_ud(100) |
d=002304 -- ! mem(5602)=02304 was mem_ud(102) |
# |
wal 000034 -- vector: 34 -> trap catcher again |
bwm 2 |
000036 -- PC:36 |
000000 -- PS:0 |
wal 000250 -- vector: 250 -> trap catcher again |
bwm 2 |
000252 -- PC:252 |
000000 -- PS:0 |
# |
wps 000000 -- psw: cmode=pmode=0 (kernel) |
#----------------------------------------------------------------------------- |
C Setup code 23 [base 5700; use 57-63] (test cmp and conditional branch) |
# |
wal 005700 -- code test 1: |
bwm 5 |
012012 -- mov (r0)+,(r2) ; load PSW from table |
004737 -- jsr pc,@#6000 |
006000 |
077104 -- sob r1,-4 |
000000 -- halt |
# |
wal 005720 -- code test 2: |
bwm 6 |
000230 -- spl 0 |
005720 -- tst (r0)+ ; verify tst response |
004737 -- jsr pc,@#6000 |
006000 |
077104 -- sob r1,-4 |
000000 -- halt |
# |
wal 005740 -- code test 3: |
bwm 6 |
000230 -- spl 0 |
022020 -- cmp (r0+),(r0)+ ; verify cmp response |
004737 -- jsr pc,@#6000 |
006000 |
077104 -- sob r1,-4 |
000000 -- halt |
# |
# test 1 test 2 test 3 |
# - C V Z N < = > < = > |
# code branch condition mask 1 2 3 4 5 1 2 3 1 2 3 4 5 6 7 |
# BNE if Z = 0 000004 y y y y y y y y y y y y |
# BEQ if Z = 1 000010 y y y |
# BGE if (N xor V) = 0 000020 y y y y y y y y y |
# BLT if (N xor V) = 1 000040 y y y y y y |
# BGT if (Z or (N xor V)) = 0 000100 y y y y y y |
# BLE if (Z or (N xor V)) = 1 000200 y y y y y y y y y |
# BPL if N = 0 000400 y y y y y y y y y y |
# BMI if N = 1 001000 y y y y y |
# BHI if (C or Z) = 0 002000 y y y y y y y y |
# BLOS if (C or Z) = 1 004000 y y y y y y y |
# BVC if V = 0 010000 y y y y y y y y y y y y |
# BVS if V = 1 020000 y y y |
# BCC if C = 0 (aka BHIS) 040000 y y y y y y y y y y y |
# BCS if C = 1 (aka BLO) 100000 y y y y |
# |
wal 006000 -- code check: |
bwm 63 |
011203 -- mov (r2),r3 ; save PSW |
012704 -- mov #177774,r4 ; set pattern store |
177774 -- |
010312 -- mov r3,(r2) ; restore PSW |
001003 -- bne .+3 |
042704 -- bic #000004,r4 |
000004 -- |
010312 -- mov r3,(r2) |
#6020 |
001403 -- beq .+3 |
042704 -- bic #000010,r4 |
000010 -- |
010312 -- mov r3,(r2) |
002003 -- bge .+3 |
042704 -- bic #000020,r4 |
000020 -- |
010312 -- mov r3,(r2) |
#6040 |
002403 -- blt .+3 |
042704 -- bic #000040,r4 |
000040 -- |
010312 -- mov r3,(r2) |
003003 -- bgt .+3 |
042704 -- bic #000100,r4 |
000100 -- |
010312 -- mov r3,(r2) |
#6060 |
003403 -- ble .+3 |
042704 -- bic #000200,r4 |
000200 -- |
010312 -- mov r3,(r2) |
100003 -- bpl .+3 |
042704 -- bic #000400,r4 |
000400 -- |
010312 -- mov r3,(r2) |
#6100 |
100403 -- bmi .+3 |
042704 -- bic #001000,r4 |
001000 -- |
010312 -- mov r3,(r2) |
101003 -- bhi .+3 |
042704 -- bic #002000,r4 |
002000 -- |
010312 -- mov r3,(r2) |
#6120 |
101403 -- blos .+3 |
042704 -- bic #004000,r4 |
004000 -- |
010312 -- mov r3,(r2) |
102003 -- bvc .+3 |
042704 -- bic #010000,r4 |
010000 -- |
010312 -- mov r3,(r2) |
#6140 |
102403 -- bvs .+3 |
042704 -- bic #020000,r4 |
020000 -- |
010312 -- mov r3,(r2) |
103003 -- bcc .+3 |
042704 -- bic #040000,r4 |
040000 -- |
010312 -- mov r3,(r2) |
#6160 |
103403 -- bcs .+3 |
042704 -- bic #100000,r4 |
100000 -- |
010312 -- mov r3,(r2) |
010325 -- mov r3,(r5)+ |
010425 -- mov r4,(r5)+ |
000207 -- rts pc |
# |
wal 006200 -- data test 1: |
bwm 5 |
000000 -- PSW - no cc |
000001 -- PSW - C=1 |
000002 -- PSW - V=1 |
000004 -- PSW - Z=1 |
000010 -- PSW - N=1 |
# |
wal 006220 -- data test 2: |
bwm 3 |
177777 -- tst -1 |
000000 -- tst 0 |
000001 -- tst 1 |
# |
wal 006230 -- data test 3: |
bwm 14 |
000001 -- cmp 1,2 |
000002 |
000001 -- cmp 1,1 |
000001 |
#6240 |
000002 -- cmp 2,1 |
000001 |
177777 -- cmp -1,2 |
000002 |
000002 -- cmp 2,-1 |
177777 |
100000 -- cmp 100000,077777 |
077777 |
#6260 |
077777 -- cmp 077777,100000 |
100000 |
# |
C Exec code 23 (test cmp and conditional branch) |
C Exec test 23.1 (explict cc setting) |
# |
wr0 006200 -- r0=6200 (input data) |
wr1 000005 -- r1=5 |
wr2 177776 -- r2=177776 (PS address) |
wr5 006300 -- r5=6300 (output data) |
wsp 001400 -- sp=1400 |
stapc 005700 -- start @ 5700 |
wtgo |
rr0 d=006212 -- ! r0 |
rr1 d=000000 -- ! r1 |
rr5 d=006324 -- ! r5 |
rsp d=001400 -- ! sp |
rpc d=005712 -- ! pc |
wal 006300 -- use BCC/BCS naming below |
brm 10 |
d=000000 -- ! mem(6300) 1 PS: none |
d=052524 -- ! mem(6302) 1 BNE,BGE,BGT,BPL,BHI,BVC,BCC |
d=000001 -- ! mem(6304) 2 PS: C=1 |
d=114524 -- ! mem(6306) 2 BNE,BGE,BGT,BPL,BLOS,BVC,BCS |
d=000002 -- ! mem(6310) 3 PS: V=1 |
d=062644 -- ! mem(6312) 3 BNE,BLT,BLE,BPL,BHI,BVS,BCC |
d=000004 -- ! mem(6314) 4 PS: Z=1 |
d=054630 -- ! mem(6316) 4 BEQ,BGE,BLE,BPL,BLOS,BVC,BCC |
d=000010 -- ! mem(6320) 5 PS: N=1 |
d=053244 -- ! mem(6322) 5 BNE,BLT,BLE,BMI,BHI,BVC,BCC |
# |
C Exec test 23.2 (tst testing) |
# |
wr0 006220 -- r0=6220 (input data) |
wr1 000003 -- r1=3 |
wr2 177776 -- r2=177776 (PS address) |
wr5 006330 -- sp=6330 (output data) |
wsp 001400 -- sp=1400 |
stapc 005720 -- start @ 5720 |
wtgo |
rr0 d=006226 -- ! r0 |
rr1 d=000000 -- ! r1 |
rr5 d=006344 -- ! r5 |
rsp d=001400 -- ! sp |
rpc d=005734 -- ! pc |
wal 006330 -- use BHIS(BCC)/BLO(BLO) naming below |
brm 6 |
d=000010 -- ! mem(6330) 1 PS: tst -1: N=1 |
d=053244 -- ! mem(6332) 1 BNE,BLT,BLE,BMI,BHI,BVC,BHIS |
d=000004 -- ! mem(6334) 2 PS: tst 0: Z=1 |
d=054630 -- ! mem(6336) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS |
d=000000 -- ! mem(6340) 3 PS: tst 1: all 0 |
d=052524 -- ! mem(6342) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS |
# |
C Exec test 23.3 (cmp testing) |
# |
wr0 006230 -- r0=6230 (input data) |
wr1 000007 -- r1=7 |
wr2 177776 -- r2=177776 (PS address) |
wr5 006344 -- sp=6344 (output data) |
wsp 001400 -- sp=1400 |
stapc 005740 -- start @ 5740 |
wtgo |
rr0 d=006264 -- ! r0 |
rr1 d=000000 -- ! r1 |
rr5 d=006400 -- ! r5 |
rsp d=001400 -- ! sp |
rpc d=005754 -- ! pc |
wal 006344 -- cmp= S-D ! |
brm 14 |
d=000011 -- ! mem(6344) 1 PS: cmp 1,2: N=1,C=1 ok |
d=115244 -- ! mem(6346) 1 BNE,BLT,BLE,BMI,BLOS,BVC,BLO |
d=000004 -- ! mem(6350) 2 PS: cmp 1,1: Z=1 ok |
d=054630 -- ! mem(6352) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS |
d=000000 -- ! mem(6354) 3 PS: cmp 2,1: none ok |
d=052524 -- ! mem(6356) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS |
d=000010 -- ! mem(6360) 4 PS: cmp -1,2: N=1 |
d=053244 -- ! mem(6362) 4 BNE,BLT,BLE,BMI,BHI,BVC,BHIS ok |
d=000001 -- ! mem(6364) 5 PS: cmp 2,-1: C=1 |
d=114524 -- ! mem(6366) 5 BNE,BGE,BGT,BPL,BLOS,BVC,BLO ok |
d=000002 -- ! mem(6370) 6 PS: cmp 10..,07..: V=1 |
d=062644 -- ! mem(6372) 6 BNE,BLT,BLE,BPL,BHI,BVS,BHIS ok |
d=000013 -- ! mem(6374) 7 PS: cmp 07..,10..: N=1,V=1,C=1 |
d=125124 -- ! mem(6376) 7 BNE,BGE,BGT,BMI,BLOS,BVS,BLO ok |
# |
#----------------------------------------------------------------------------- |
C Setup code 24 [base 6400] (test MARK instruction) |
# |
wal 006400 -- code (main): |
bwm 13 |
010546 -- mov r5,-(sp) ; push old r5 on stack |
012746 -- mov #101,-(sp) ; push 1st parameter |
000101 |
012746 -- mov #102,-(sp) ; push 2nd parameter |
000102 |
012746 -- mov #103,-(sp) ; push 3rd parameter |
000103 |
012746 -- mov #mark3,-(sp) ; push MARK 3 |
#6420 |
006403 |
010605 -- mov sp,r5 ; address of MARK N |
004737 -- jsr pc,@#6440 ; call procedure |
006440 |
000000 -- halt |
# |
# stack of procedure when called: |
# addr content |
# 576 12(sp) 10(r5) old r5 |
# 574 10(sp) 6(r5) param1 |
# 572 6(sp) 4(r5) param2 |
# 570 4(sp) 2(r5) param3 |
# 566 2(sp) (r5) mark 3 |
# 564 (sp) return pc |
# |
wal 006440 -- code (procedure): |
bwm 7 |
016520 -- mov 6(r5),(r0)+ ; get 1st param |
000006 |
016520 -- mov 4(r5),(r0)+ ; get 2nd param |
000004 |
016520 -- mov 2(r5),(r0)+ ; get 3rd param |
000002 |
000205 -- rts r5 |
# |
C Exec code 24 (test MARK instruction) |
# |
wr0 006470 -- r0=6470 |
wr5 123456 -- r5=123456 |
wsp 001400 -- sp=1400 |
stapc 006400 -- start @ 6400 |
wtgo |
rr0 d=006476 -- ! r0=6476 (3 words written) |
rr5 d=123456 -- ! r5 (restored) |
rsp d=001400 -- ! sp |
rpc d=006432 -- ! pc |
wal 001364 -- check stack |
brm 6 |
d=006430 -- ! mem(1364) |
d=006403 -- ! mem(1366) |
d=000103 -- ! mem(1370) |
d=000102 -- ! mem(1372) |
d=000101 -- ! mem(1374) |
d=123456 -- ! mem(1376) |
wal 006470 -- check stored values |
brm 3 |
d=000101 -- ! mem(6470) (1st param) |
d=000102 -- ! mem(6472) (2nd param) |
d=000103 -- ! mem(6474) (3rd param) |
# |
# probably first and last time MARK is used. It's a bastard anyway. |
# |
#----------------------------------------------------------------------------- |
C Setup code 25 [base 6500; use 65-66] (basic byte instruction and cc test) |
# |
wal 006500 -- code: |
bwm 22 |
110124 -- movb r1,(r4)+ (#123, #333) |
120124 -- cmpb r1,(r4)+ (#123, #333) |
120224 -- cmpb r2,(r4)+ (#321, #111) |
120124 -- cmpb r1,(r4)+ (#123, #123) |
105024 -- clrb (r4)+ (#333) |
130124 -- bitb r1,(r4)+ (#123, #11) |
130124 -- bitb r1,(r4)+ (#123, #44) |
140124 -- bicb r1,(r4)+ (#123, #333) |
#6520 |
150124 -- bisb r1,(r4)+ (#123, #111) |
105124 -- comb (r4)+ (#321) |
105224 -- incb (r4)+ (#321) |
105324 -- decb (r4)+ (#321) |
105424 -- negb (r4)+ (#321) |
105724 -- tstb (r4)+ (#321) |
106024 -- rorb (r4)+ (#201) Cin=0; Cout=1 |
106024 -- rorb (r4)+ (#021) Cin=1; Cout=1 |
#6540 |
106124 -- rolb (r4)+ (#210) Cin=1; Cout=1 |
106224 -- asrb (r4)+ (#020) |
106224 -- asrb (r4)+ (#220) |
106324 -- aslb (r4)+ (#020) |
106324 -- aslb (r4)+ (#220) |
000000 -- halt |
# |
wal 000014 -- vector: 14 |
bwm 2 |
006560 -- PC:6560 |
000000 -- PS:0 |
# |
wal 006560 -- code: (trap 14): |
bwm 3 |
016625 -- mov 2(sp),(r5)+ |
000002 |
000006 -- rtt |
# |
wal 006600 -- data 1: |
bwm 11 |
155733 -- (#333,#333) |
051511 -- (#123,#111) |
044333 -- (#11 ,#333) |
155444 -- (#333,#44) |
150511 -- (#321,#111) |
150721 -- (#321,#321) |
150721 -- (#321,#321) |
010601 -- (#021,#201) |
#6620 |
010210 -- (#020,#210) |
010220 -- (#020,#220) |
000220 -- (....,#220) |
# |
C Exec code 25 (basic byte instruction and cc test) |
# |
wr1 000123 -- r1=123 |
wr2 000321 -- r2=321 |
wr4 006600 -- r4=6600 |
wr5 006626 -- r5=6626 |
wsp 001374 -- sp=1374 |
wal 001374 -- setup stack with rtt return frame setting T flag |
bwm 2 |
006500 -- start address (code 25 @ 6500) |
000020 -- set T flag in PSW |
stapc 006564 -- start @ 6564 -> rtt -> 6500 from stack |
wtgo |
rr1 d=000123 -- ! r1=123 |
rr2 d=000321 -- ! r2=321 |
rr4 d=006625 -- ! r4=6625 |
rr5 d=006700 -- ! r5=6700 |
rsp d=001400 -- ! sp=1400 |
rpc d=006554 -- ! pc=6554 |
wal 006600 |
brm 11 |
d=155523 -- ! mem(6600)=123; movb r1,(r4)+ (#123, #333) |
# ! mem(6601)=333; cmpb r1,(r4)+ (#123, #333) |
d=051511 -- ! mem(6602)=111; cmpb r1,(r4)+ (#321, #111) |
# ! mem(6603)=123; cmpb r1,(r4)+ (#123, #123) |
d=044000 -- ! mem(6604)=000; clrb (r4)+ (#333) |
# ! mem(6605)=011; bitb r1,(r4)+ (#123, #11) |
d=104044 -- ! mem(6606)=044; bitb r1,(r4)+ (#123, #44) |
# ! mem(6607)=210; bicb r1,(r4)+ (#123, #333) |
d=027133 -- ! mem(6610)=133; bisb r1,(r4)+ (#123, #111) |
# ! mem(6611)=056; comb (r4)+ (#321) |
d=150322 -- ! mem(6612)=322; incb (r4)+ (#321) |
# ! mem(6613)=320; decb (r4)+ (#321) |
d=150457 -- ! mem(6614)=057; negb (r4)+ (#321) |
# ! mem(6615)=321; tstb (r4)+ (#321) |
d=104100 -- ! mem(6616)=100; rorb (r4)+ (#201) Cout=1 |
# ! mem(6617)=210; rorb (r4)+ (#021) Cout=1 |
d=004021 -- ! mem(6620)=021; rolb (r4)+ (#210) Cout=1 |
# ! mem(6621)=010; asrb (r4)+ (#020) |
d=020310 -- ! mem(6622)=310; asrb (r4)+ (#220) |
# ! mem(6623)=040; aslb (r4)+ (#020) |
d=000040 -- ! mem(6624)=040; aslb (r4)+ (#220) |
# |
wal 006626 -- NZVC |
brm 21 |
d=000020 -- ! mem(6626)=0000; movb r1,(r4)+ (#123, #333) |
d=000021 -- ! mem(6630)=000C; cmpb r1,(r4)+ (#123, #333) |
d=000030 -- ! mem(6632)=N000; cmpb r1,(r4)+ (#321, #111) |
d=000024 -- ! mem(6634)=0Z00; cmpb r1,(r4)+ (#123, #123) |
d=000024 -- ! mem(6636)=0Z00; clrb (r4)+ (#333) |
d=000020 -- ! mem(6640)=0000; bitb r1,(r4)+ (#123, #11) |
d=000024 -- ! mem(6642)=0Z00; bitb r1,(r4)+ (#123, #44) |
d=000030 -- ! mem(6644)=N000; bicb r1,(r4)+ (#123, #333) |
d=000020 -- ! mem(6646)=0000; bisb r1,(r4)+ (#123, #111) |
d=000021 -- ! mem(6650)=000C; comb (r4)+ (#321) |
d=000031 -- ! mem(6652)=N00C; incb (r4)+ (#321) keep C! |
d=000031 -- ! mem(6654)=N00C; decb (r4)+ (#321) keep C! |
d=000021 -- ! mem(6656)=000C; negb (r4)+ (#321) |
d=000030 -- ! mem(6660)=N000; tstb (r4)+ (#321) |
d=000023 -- ! mem(6662)=00VC; rorb (r4)+ (#201) |
d=000031 -- ! mem(6664)=N00C; rorb (r4)+ (#021) |
d=000023 -- ! mem(6666)=00VC; rolb (r4)+ (#210) |
d=000020 -- ! mem(6670)=0000; asrb (r4)+ (#020) |
d=000032 -- ! mem(6672)=N0V0; asrb (r4)+ (#220) |
d=000020 -- ! mem(6674)=0000; aslb (r4)+ (#020) |
d=000023 -- ! mem(6676)=00VC; aslb (r4)+ (#220) |
# |
rst -- console reset (to clear T flag) |
wal 000014 -- vector: 14 -> trap catcher again |
bwm 2 |
000016 -- PC:16 |
000000 -- PS:0 |
#----------------------------------------------------------------------------- |
C Setup code 26 [base 6700; use 67-70] (address modes torture tests) |
# |
wal 006700 -- code test 1: |
bwm 5 |
012020 -- mov (r0)+,(r0)+ |
062020 -- add (r0)+,(r0)+ |
014141 -- mov -(r1),-(r1) |
064141 -- add -(r1),-(r1) |
#6710 |
000000 -- halt |
#----- |
wal 006720 -- code test 2: |
bwm 8 |
016767 -- mov a(pc),b(pc) |
000014 -- here pc=6724, target@6740 --> index=14 |
000014 -- here pc=6726, target@6742 --> index=14 |
066767 -- add c(pc),d(pc) |
#6730 |
000012 -- here pc=6732, target@6744 --> index=12 |
000012 -- here pc=6734, target@6746 --> index=12 |
000000 -- halt |
000000 -- halt |
# |
wal 006740 -- data (pc relative) for test 2: |
bwm 4 |
006740 -- target for mov a(pc) |
006742 -- target for ,b(pc) |
000011 -- target for add c(pc) |
006746 -- target for ,d(pc) |
#----- |
wal 006750 -- code test 3: |
bwm 12 |
012727 -- mov #1,#0 |
000001 |
000000 |
062727 -- add #1,#2 |
#6760 |
000001 |
000002 |
016767 -- mov -14(pc),2(pc) |
177764 -- pc here: 6770: read dst of mov #1,#0 (@6754) |
000002 -- pc here: 6772: write src of add #0,r0 (@6774) |
062700 -- add #0,r0 |
000000 |
000000 -- halt |
#----- |
wal 007000 -- code test 4: |
bwm 8 |
005200 -- inc r0 |
010001 -- mov r0,r1 |
010702 -- mov pc,r2 |
005007 -- clr pc |
000000 -- halt |
000000 -- halt |
005203 -- L1: inc r3 |
000000 -- halt |
#----- |
wal 000000 -- code test 4 (handler at address=0): |
bwm 2 |
000137 -- jmp @#L1 |
007014 |
#----- |
wal 007020 -- code test 5: |
bwm 11 |
012707 -- mov #L2,pc |
007032 |
000000 -- halt |
000000 -- halt |
000000 -- halt |
062707 -- L2: add #2,pc |
000002 |
005201 -- inc r1 |
#7040 |
005201 -- inc r1 |
005201 -- inc r1 |
000000 -- halt |
#----- |
wal 007060 -- data for test 1 (r0)+ part: |
bwm 4 |
000111 |
000222 |
000333 |
000444 |
wal 007070 -- data for test 1 -(r1) part: |
bwm 4 |
000111 |
000222 |
000333 |
000444 |
C Exec code 26 (address modes torture tests) |
C Exec test 26.1 (test src-dst update hazards with (r0)+,(r0)+ ect): |
# |
wr0 007060 -- r0=7060 (input data for (r0)+...) |
wr1 007100 -- r1=7100 (input data for -(r1)...) |
wsp 001400 -- sp=1400 |
stapc 006700 -- start @ 6700 |
wtgo |
rr0 d=007070 -- ! r0 |
rr1 d=007070 -- ! r1 |
rpc d=006712 -- ! pc |
wal 007060 -- |
brm 4 |
d=000111 -- ! mem(7060) |
d=000111 -- ! mem(7062) |
d=000333 -- ! mem(7064) |
d=000777 -- ! mem(7066) |
wal 007070 -- |
brm 4 |
d=000333 -- ! mem(7070) |
d=000222 -- ! mem(7072) |
d=000444 -- ! mem(7074) |
d=000444 -- ! mem(7076) |
C Exec test 26.2 (test indexed mode with pc (mode 67)): |
# |
wsp 001400 -- sp=1400 |
stapc 006720 -- start @ 6720 |
wtgo |
rpc d=006736 -- ! pc |
wal 006740 -- |
brm 4 |
d=006740 -- ! mem(6740) |
d=006740 -- ! mem(6742) |
d=000011 -- ! mem(6744) |
d=006757 -- ! mem(6746) |
C Exec test 26.3 (test (pc)+ as dst): |
# |
wr0 000111 -- r0=0111 |
wsp 001400 -- sp=1400 |
stapc 006750 -- start @ 6750 |
wtgo |
rr0 d=000112 -- ! r0 |
rpc d=007000 -- ! pc |
wal 006752 -- |
brm 2 |
d=000001 -- ! mem(6752) src mov #1,#0 |
d=000001 -- ! mem(6754) dst mov #1,#0 |
wal 006760 -- |
brm 2 |
d=000001 -- ! mem(6760) src add #1,#2 |
d=000003 -- ! mem(6762) dst add #1,#2 |
wal 006774 -- ! |
rmi d=000001 -- ! mem(6774) dst mov -12(pc),2(pc) |
C Exec test 26.4 (test pc as dst in clr): |
# |
wr0 000100 -- r0=0100 |
wr1 000110 -- r1=0110 |
wr2 000120 -- r2=0120 |
wr3 000130 -- r3=0130 |
wsp 001400 -- sp=1400 |
stapc 007000 -- start @ 7000 |
wtgo |
rr0 d=000101 -- ! r0 |
rr1 d=000101 -- ! r1 |
rr2 d=007006 -- ! r2 (pc after mov pc,r2) |
rr3 d=000131 -- ! r3 |
rpc d=007020 -- ! pc |
# cleanup 'vector 0': |
wal 000000 |
bwm 2 |
000000 |
000000 |
C Exec test 26.5 (test pc as dst in mov and add): |
# |
wr1 000000 -- r1=0 |
wsp 001400 -- sp=1400 |
stapc 007020 -- start @ 7020 |
wtgo |
rr1 d=000002 -- ! r1 |
rpc d=007046 -- ! pc |
#----------------------------------------------------------------------------- |
C Setup code 27 [base 7100; use 71-101] (test ASH/ASHC instruction) |
# |
wal 007100 -- code test 1 (ash) |
bwm 7 |
000230 -- spl 0 |
012004 -- L1: mov (r0)+,r4 -- load low |
072420 -- ash (r0)+,r4 -- shift |
011321 -- mov (r3),(r1)+ -- store psw |
010421 -- mov r4,(r1)+ -- store low |
077205 -- sob r2,L1 (.-5) |
000000 -- halt |
#----- |
wal 007120 -- code test 2 (ashc even) |
bwm 9 |
000230 -- spl 0 |
012004 -- L1: mov (r0)+,r4 -- load high |
012005 -- mov (r0)+,r5 -- load low |
073420 -- ashc (r0)+,r4 -- shift |
011321 -- mov (r3),(r1)+ -- store psw |
010421 -- mov r4,(r1)+ -- store high |
010521 -- mov r5,(r1)+ -- store low |
077207 -- sob r2,L1 (.-7) |
#7140 |
000000 -- halt |
#----- |
wal 007150 -- code test 3 (ashc odd) |
bwm 7 |
000230 -- spl 0 |
012005 -- L1: mov (r0)+,r5 -- load low |
073520 -- ashc (r0)+,r5 -- shift |
011321 -- mov (r3),(r1)+ -- store psw |
#7160 |
010521 -- mov r5,(r1)+ -- store low |
077205 -- sob r2,L1 (.-5) |
000000 -- halt |
#----- |
wal 007200 -- data 1: |
bwm 24 |
000200 -- (000200, +1) |
000001 -- |
000200 -- (000200, -1) |
177777 -- |
000200 -- (000200, +7) |
000007 -- |
000200 -- (000200, +8) |
000010 -- |
#7220 |
000200 -- (000200, +9) |
000011 -- |
000200 -- (000200, -7) |
177771 -- |
100000 -- (100000, 0) |
000000 -- |
000000 -- (000000, 0) |
000000 -- |
#7240 |
000200 -- (000200, -8) |
177770 -- |
000200 -- (000200, 0) |
000000 -- |
100000 -- (100000, -6) |
177772 -- |
040000 -- (040000, +1) |
000001 -- |
#----- |
wal 007300 -- data 2: |
bwm 30 |
000020 -- (000020,000200, +1) |
000200 -- |
000001 -- |
000020 -- (000020,000200, -1) |
000200 -- |
177777 -- |
000020 -- (000020,000200, +7) |
000200 -- |
#7320 |
000007 -- |
000020 -- (000020,000200, +8) |
000200 -- |
000010 -- |
000020 -- (000020,000200, +9) |
000200 -- |
000011 -- |
000000 -- (000000,000200, +23) |
#7340 |
000200 -- |
000027 -- |
000000 -- (000000,000200, +24) |
000200 -- |
000030 -- |
000000 -- (000000,000200, +25) |
000200 -- |
000031 -- |
#7360 |
000020 -- (000020,000200, -5) |
000200 -- |
177773 -- |
000020 -- (000020,000200, -8) |
000200 -- |
177770 -- |
#----- |
wal 007440 -- data 3: |
bwm 6 |
000200 -- (000200, +1) |
000001 -- |
000200 -- (000200, -1) |
177777 -- |
000201 -- (000201, -1) |
177777 -- |
# |
C Exec code 27 (test ASH/ASHC instruction) |
C Exec test 27.1 (test ash) |
# |
wr0 007200 -- r0=7200 (input data) |
wr1 007500 -- r1=7500 (output data) |
wr2 000014 -- r2=14 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
stapc 007100 -- start @ 7100 |
wtgo |
rr0 d=007260 -- ! r0 |
rr1 d=007560 -- ! r1 |
rpc d=007116 -- ! pc |
wal 007500 -- |
brm 24 |
d=000000 -- ! mem(7500) ash +1, 000200 -> nzvc=0 |
d=000400 -- ! mem(7502) |
d=000000 -- ! mem(7504) ash -1, 000200 -> nzvc=0 |
d=000100 -- ! mem(7506) |
d=000000 -- ! mem(7510) ash +7, 000200 -> nzvc=0 |
d=040000 -- ! mem(7512) |
d=000012 -- ! mem(7514) ash +8, 000200 -> n1,z0,v1,c0 |
d=100000 -- ! mem(7516) |
d=000007 -- ! mem(7520) ash +9, 000200 -> n0,z1,v1,c1 |
d=000000 -- ! mem(7522) |
d=000000 -- ! mem(7524) ash -7, 000200 -> nzvc=0 |
d=000001 -- ! mem(7526) |
d=000010 -- ! mem(7530) ash 0, 100000 -> n1,z0,v0,c0 |
d=100000 -- ! mem(7532) |
d=000004 -- ! mem(7534) ash 0, 000000 -> n0,z1,v0,c0 |
d=000000 -- ! mem(7536) |
d=000005 -- ! mem(7540) ash -8, 000200 -> n1,z1,v0,c1 |
d=000000 -- ! mem(7542) |
d=000000 -- ! mem(7544) ash 0, 000200 -> n0,z0,v0,c0 |
d=000200 -- ! mem(7546) |
d=000010 -- ! mem(7550) ash -6, 100000 -> n1,z0,v0,c0 |
d=177000 -- ! mem(7552) |
d=000012 -- ! mem(7554) ash +1, 040000 -> n1,z0,v1,c0 |
d=100000 -- ! mem(7556) |
#---- |
C Exec test 27.2 (test ashc even) |
# |
wr0 007300 -- r0=7300 (input data) |
wr1 007600 -- r1=7600 (output data) |
wr2 000012 -- r2=12 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
stapc 007120 -- start @ 7120 |
wtgo |
rr0 d=007374 -- ! r0 |
rr1 d=007674 -- ! r1 |
rpc d=007142 -- ! pc |
wal 007600 -- |
brm 30 |
d=000000 -- ! mem(7600) ashc +1, 000020,000200 -> nzvc=0 |
d=000040 -- ! mem(7602) |
d=000400 -- ! mem(7604) |
d=000000 -- ! mem(7606) ashc -1, 000020,000200 -> nzvc=0 |
d=000010 -- ! mem(7610) |
d=000100 -- ! mem(7612) |
d=000000 -- ! mem(7614) ashc +7, 000020,000200 -> nzvc=0 |
d=004000 -- ! mem(7616) |
d=040000 -- ! mem(7620) |
d=000000 -- ! mem(7622) ashc +8, 000020,000200 -> nzvc=0 |
d=010000 -- ! mem(7624) |
d=100000 -- ! mem(7626) |
d=000000 -- ! mem(7630) ashc +9, 000020,000200 -> nzvc=0 |
d=020001 -- ! mem(7632) |
d=000000 -- ! mem(7634) |
d=000000 -- ! mem(7636) ashc +23, 000000,000200 -> nzvc=0 |
d=040000 -- ! mem(7640) |
d=000000 -- ! mem(7642) |
d=000012 -- ! mem(7644) ashc +24, 000000,000200 -> n1z0v1c0 |
d=100000 -- ! mem(7646) |
d=000000 -- ! mem(7650) |
d=000007 -- ! mem(7652) ashc +25, 000000,000200 -> n0z1v1c1 |
d=000000 -- ! mem(7654) |
d=000000 -- ! mem(7656) |
d=000000 -- ! mem(7660) ashc -5, 000020,000200 -> nzvc=0 |
d=000000 -- ! mem(7662) |
d=100004 -- ! mem(7664) |
d=000001 -- ! mem(7666) ashc -8, 000020,000200 -> n0z0v0c1 |
d=000000 -- ! mem(7670) |
d=010000 -- ! mem(7672) |
#---- |
C Exec test 27.3 (test ashc odd) |
# |
wr0 007440 -- r0=7440 (input data) |
wr1 007740 -- r1=7740 (output data) |
wr2 000003 -- r2=3 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
stapc 007150 -- start @ 7150 |
wtgo |
rr0 d=007454 -- ! r0 |
rr1 d=007754 -- ! r1 |
rpc d=007166 -- ! pc |
wal 007740 -- |
brm 6 |
d=000000 -- ! mem(7740) ashc +1, 000200 -> nzvc=0 |
d=000400 -- ! mem(7742) |
d=000000 -- ! mem(7744) ashc -1, 000200 -> nzvc=0 |
d=000100 -- ! mem(7746) |
d=000001 -- ! mem(7750) ashc -1, 000201 -> n0z0v0c1 |
d=100100 -- ! mem(7752) |
#----------------------------------------------------------------------------- |
C Setup code 30 [base 10200; use 102-103] (test MUL instruction) |
# |
wal 010200 -- code test 1 (mul even) |
bwm 8 |
000230 -- spl 0 |
012004 -- L1: mov (r0)+,r4 -- load p1 |
070420 -- mul (r0)+,r4 -- mul |
011321 -- mov (r3),(r1)+ -- store psw |
010421 -- mov r4,(r1)+ -- store p_high |
010521 -- mov r5,(r1)+ -- store p_low |
077206 -- sob r2,L1 (.-6) |
000000 -- halt |
#----- |
wal 010220 -- code test 2 (mul odd) |
bwm 7 |
000230 -- spl 0 |
012005 -- L1: mov (r0)+,r5 -- load p1 |
070520 -- mul (r0)+,r5 -- mul |
010521 -- mov r5,(r1)+ -- store p_low |
060403 -- add r4,r3 -- check r4 |
077205 -- sob r2,L1 (.-5) |
000000 -- halt |
# |
# 31022 074456 * 9562 022532 -> 296632364 010656,040054 |
# 18494 044076 * -24041 121027 -> -444614254 162577,134622 |
# -12549 147373 * 2397 004535 -> -30079953 177065,002057 |
# -20493 127763 * -23858 121316 -> 488921994 016444,055612 |
# |
# 105 000151 * 198 000306 -> 20790 000000,050466 |
# 233 000351 * -94 177642 -> -21902 177777,125162 |
# 186 000272 * -205 177463 -> -38130 177777,065416 |
# |
wal 010240 -- data 1: |
bwm 16 |
074456 -- |
022532 -- |
044076 -- |
121027 -- |
147373 -- |
004535 -- |
127763 -- |
121316 -- |
#10260 |
000151 -- |
000306 -- |
000351 -- |
177642 -- |
000272 -- |
177463 -- |
000000 -- |
000272 -- |
# |
C Exec code 30 (test MUL instruction) |
C Exec test 30.1 (test mul even) |
# |
wr0 010240 -- r0=10240 (input data) |
wr1 010300 -- r1=10300 (output data) |
wr2 000010 -- r2=10 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
stapc 010200 -- start @ 10200 |
wtgo |
rr0 d=010300 -- ! r0 |
rr1 d=010360 -- ! r1 |
rpc d=010220 -- ! pc |
wal 010300 -- |
brm 24 |
d=000001 -- ! mem(10300) mul 074456,022532 -> n0z0v0c1 |
d=010656 -- ! mem(10302) |
d=040054 -- ! mem(10304) |
d=000011 -- ! mem(10306) mul 044076,121027 -> n1z0v0c1 |
d=162577 -- ! mem(10310) |
d=134622 -- ! mem(10312) |
d=000011 -- ! mem(10314) mul 147373,004535 -> n1z0v0c1 |
d=177065 -- ! mem(10316) |
d=002057 -- ! mem(10320) |
d=000001 -- ! mem(10322) mul 127763,121316 -> n0z0v0c1 |
d=016444 -- ! mem(10324) |
d=055612 -- ! mem(10326) |
d=000000 -- ! mem(10330) mul 000151,000306 -> n0z0v0c0 |
d=000000 -- ! mem(10332) |
d=050466 -- ! mem(10334) |
d=000010 -- ! mem(10336) mul 000351,177642 -> n1z0v0c0 |
d=177777 -- ! mem(10340) |
d=125162 -- ! mem(10342) |
d=000011 -- ! mem(10344) mul 000272,177463 -> n1z0v0c1 |
d=177777 -- ! mem(10346) |
d=065416 -- ! mem(10350) |
d=000004 -- ! mem(10352) mul 000000,000272 -> n0z1v0c0 |
d=000000 -- ! mem(10354) |
d=000000 -- ! mem(10356) |
#---- |
C Exec test 30.2 (test mul odd) |
# |
wr0 010240 -- r0=10240 (input data) |
wr1 010360 -- r1=10300 (output data) |
wr2 000010 -- r2=10 (test count) |
wr3 000000 -- r3=0 |
wr4 000000 -- r4=0 |
wsp 001400 -- sp=1400 |
stapc 010220 -- start @ 10220 |
wtgo |
rr0 d=010300 -- ! r0 |
rr1 d=010400 -- ! r1 |
rr3 d=000000 -- ! r3 |
rpc d=010236 -- ! pc |
wal 010360 -- |
brm 8 |
d=040054 -- ! mem(10360) |
d=134622 -- ! mem(10362) |
d=002057 -- ! mem(10364) |
d=055612 -- ! mem(10366) |
d=050466 -- ! mem(10370) |
d=125162 -- ! mem(10372) |
d=065416 -- ! mem(10374) |
d=000000 -- ! mem(10376) |
# |
#----------------------------------------------------------------------------- |
C Setup code 31 [base 10400; use 104-110] (test DIV instruction, also ADC,SXT) |
# Note: test 2 uses sbc too, but if div/div work correctly we have always |
# C=0 for sbc, so sbc isn't tested. adc has C=0 or C=1 though. |
# |
wal 010400 -- code test 1 |
bwm 8 |
012004 -- L1: mov (r0)+,r4 -- load dd high |
012005 -- mov (r0)+,r5 -- load dd low |
071420 -- div (r0)+,r4 -- div |
011321 -- mov (r3),(r1)+ -- store psw |
010421 -- mov r4,(r1)+ -- store q |
010521 -- mov r5,(r1)+ -- store r |
077207 -- sob r2,L1 (.-7) |
000000 -- halt |
#----- |
wal 010420 -- code test 2 |
bwm 24 |
012146 -- L1: mov (r1)+,-(sp) -- save psw on stack |
016002 -- mov 4(r0),r2 -- load divisor |
000004 |
070221 -- mul (r1)+,r2 -- multiply with quotient |
061103 -- add (r1),r3 -- add reminder |
005502 -- adc r2 |
005721 -- tst (r1)+ |
006704 -- sxt r4 |
#10440 |
060402 -- add r4,r2 |
166003 -- sub 2(r0),r3 -- subtract divident |
000002 |
005602 -- sbc r2 |
161002 -- sub (r0),r2 |
001002 -- bne L2 (.+2) -- error if !=0 |
005703 -- tst r3 |
001404 -- beq L3 (.+4) -- error if !=0 |
#10460 |
032726 -- L2: bit #3,(sp)+ -- check V,C bits |
000003 |
001001 -- bne L3 (.+1) -- if V or C =1, ignore |
000000 -- halt |
062700 -- L3: add #6,r0 -- |
000006 -- |
077527 -- sob r5,L1 (.-23) |
000000 -- halt |
# r q |
# 6249 014151 * 9158 021706 + 4989 011575 -> 57233331 001551,047663 y n |
# 5194 012112 * -23807 121401 + -3990 170152 -> -123657548 174241,021264 n y |
# -19943 131031 * 27112 064750 + -16037 140533 -> -540710653 157705,064403 y n |
# -20493 127763 * -23858 121316 + 10744 024770 -> 488932738 016444,102602 y y |
# |
# -12549 147373 * 2397 004535 + -11187 152115 -> -30091140 177064,154174 n n |
# 22620 054134 * -9272 155710 + -19907 131075 -> -209752547 171577,067035 y y |
# 10723 024743 * 7931 017373 + 9824 023140 -> 85053937 002421,150761 n n |
# -3548 171044 * -15677 141303 + 3019 005713 -> 55625015 001520,142467 n y |
# |
## 1 000001 * -32767 100001 + 0 000000 -> -32767 177777,100001 V=0 |
## -1 177777 * 32767 077777 + 0 000000 -> -32767 177777,100001 V=0 |
# 1 000001 * -32768 100000 + 0 000000 -> -32768 177777,100000 V=1 |
# -1 177777 * ...... ...... + 0 000000 -> -32768 177777,100000 V=1 |
# |
# 32767 077777 * 32767 077777 + 32766 077776 -> 1073709055 037777,077777 V=0 |
# 32767 077777 * ............ + ............ -> 1073709056 037777,100000 V=1 |
# 32767 077777 * -32767 100001 + -32766 100002 ->-1073709055 140000,100001 V=0 |
# 32767 077777 * ............ + ............ ->-1073709056 140000,100000 V=1 |
# |
# 32767 077777 * ............ + ............ -> 1073741824 040000,000000 V=1 |
##32767 077777 * ............ + ............ ->-2147483648 100000,000000 V=1 |
# |
# |
wal 010500 -- data 1: |
bwm 63 |
000000 -- (000000,000042, 000005) 34/ 5 -> q: 6 r: 4 |
000042 -- |
000005 -- |
000000 -- (000000,000042, 177773) 34/-5 -> q:-6 r: 4 |
000042 -- |
177773 -- |
177777 -- (177777,177736, 000005) -34/ 5 -> q:-6 r:-4 |
177736 -- |
#010520 |
000005 -- |
177777 -- (177777,177736, 177773) -34/-5 -> q: 6 r:-4 |
177736 -- |
177773 -- |
001551 -- (001551,047663, 014151) 57233331 / 6249 |
047663 -- -> q: 9158 r: 4989 |
014151 -- |
174241 -- (174241,021264, 012112) -123657548 / 5194 |
#010540 |
021264 -- -> q: -23807 r: -3990 |
012112 -- |
157705 -- (157705,064403, 131031) -540710653 / -19943 |
064403 -- -> q: 27112 r: -16037 |
131031 -- |
016444 -- (016444,102602, 127763) 488932738 / -20493 |
102602 -- -> q: -23858 r: 10744 |
127763 -- |
#010560 |
177064 -- (177064,154174, 147373) -30091140 / -12549 |
154174 -- -> q: 2397 r: -11187 |
147373 -- |
171577 -- (171577,067035, 054134) -209752547 / 22620 |
067035 -- -> q: -9272 r: -19907 |
054134 -- |
002421 -- (002421,150761, 024743) 85053937 / 10723 |
150761 -- -> q: 7931 r: 9824 |
#010600 |
024743 -- |
001520 -- (001520,142467, 171044) 55625015 / -3548 |
142467 -- -> q: -15677 r: 3019 |
171044 -- |
001520 -- (001520,142467,000000) 55625015 / 0 |
142467 -- |
000000 -- |
000000 -- (000000,000000,021706) 0 / 9158 |
#010620 |
000000 -- |
021706 -- |
177777 -- (177777,100000,000001) -32768 / 1 |
100000 -- |
000001 -- |
177777 -- (177777,100000,177777) -32768 / -1 |
100000 -- |
177777 -- |
#010640 |
037777 -- (037777,077777,077777) 1073709055 / 32767 |
077777 -- |
077777 -- |
037777 -- (037777,100000,077777) 1073709056 / 32767 |
100000 -- |
077777 -- |
140000 -- (140000,100001,077777) -1073709055 / 32767 |
100001 -- |
#010660 |
077777 -- |
140000 -- (140000,100000,077777) -1073709056 / 32767 |
100000 -- |
077777 -- |
040000 -- (040000,000000,077777) 1073741824 / 32767 |
000000 -- |
077777 -- |
# |
C Exec code 31 (test DIV instruction, also ADC,SXT) |
C Exec test 31.1 (test div) |
# |
wr0 010500 -- r0=10500 (input data) |
wr1 010700 -- r1=10700 (output data) |
wr2 000025 -- r2=25 (test count) |
wr3 177776 -- r3=177776 (#PSW) |
wsp 001400 -- sp=1400 |
rst -- console reset ; do reset; cont to start with |
wps 000000 -- clear psw ; psw cc code dump below |
wpc 010400 -- pc=10400 |
cont -- cont @ 10400 |
wtgo |
rr0 d=010676 -- ! r0 |
rr1 d=011076 -- ! r1 |
rpc d=010420 -- ! pc |
wal 010700 -- |
brm 63 |
d=000000 -- ! mem(10700) div 000000, 000042,000005 -> n0z0v0c0 |
d=000006 -- ! mem(10702) 34/ 5 -> 6,4 |
d=000004 -- ! mem(10704) |
d=000010 -- ! mem(10706) div 000000,000042, 177773 -> n1z0v0c0 |
d=177772 -- ! mem(10710) 34/-5 -> -6,4 |
d=000004 -- ! mem(10712) |
d=000010 -- ! mem(10714) div 177777,177736, 000005 -> n1z0v0c0 |
d=177772 -- ! mem(10716) -34/ 5 -> -6,-4 |
d=177774 -- ! mem(10720) |
d=000000 -- ! mem(10722) div 177777,177736, 177773 -> n0z0v0c0 |
d=000006 -- ! mem(10724) -34/-5 -> 6,-4 |
d=177774 -- ! mem(10726) |
d=000000 -- ! mem(10730) div 001551,047663, 014151 -> n0z0v0c0 |
d=021706 -- ! mem(10732) 57233331/6249 -> 9158,4989 |
d=011575 -- ! mem(10734) |
d=000010 -- ! mem(10736) div 174241,021264, 012112 -> n1z0v0c0 |
d=121401 -- ! mem(10740) -123657548/5194 -> -23807,-3990 |
d=170152 -- ! mem(10742) |
d=000000 -- ! mem(10744) div 157705,064403, 131031 -> n0z0v0c0 |
d=064750 -- ! mem(10746) -540710653/-19943 -> 27112,-16037 |
d=140533 -- ! mem(10750) |
d=000010 -- ! mem(10752) div 016444,102602, 127763 -> n1z0v0c0 |
d=121316 -- ! mem(10754) 488932738/-20493 -> -23858, 10744 |
d=024770 -- ! mem(10756) |
d=000000 -- ! mem(10760) div 177064,154174, 147373 -> n0z0v0c0 |
d=004535 -- ! mem(10762) -30091140/-12549 -> 2397,-11187 |
d=152115 -- ! mem(10764) |
d=000010 -- ! mem(10766) div 171577,067035, 054134 -> n1z0v0c0 |
d=155710 -- ! mem(10770) -209752547/22620 -> -9272,-19907 |
d=131075 -- ! mem(10772) |
d=000000 -- ! mem(10774) div 002421,150761, 024743 -> n0z0v0c0 |
d=017373 -- ! mem(10776) 85053937/10723 -> 7931,9824 |
d=023140 -- ! mem(11000) |
d=000010 -- ! mem(11002) div 001520,142467, 171044 -> n1z0v0c0 |
d=141303 -- ! mem(11004) 55625015/-3548 -> -15677,3019 |
d=005713 -- ! mem(11006) |
d=000007 -- ! mem(11010) div 001520,142467,000000 -> n0z1v1c1 |
d=001520 -- ! mem(11012) 55625015/0 -> V=1, keep regs |
d=142467 -- ! mem(11014) |
d=000004 -- ! mem(11016) div 000000,000000,021706 -> n0z1v1c0 |
d=000000 -- ! mem(11020) 0/9158 -> 0,0 |
d=000000 -- ! mem(11022) |
d=000010 -- ! mem(11024) div 177777,100000,000001->n1z0v1c0 |
d=100000 -- ! mem(11026) -32768/1 -> -32768,0 |
d=000000 -- ! mem(11030) |
d=000002 -- ! mem(11032) div 177777,100000,177777 -> n0z0v1c0 ?? 2 |
d=177777 -- ! mem(11034) -32768/-1 -> overflow |
d=100000 -- ! mem(11036) |
d=000000 -- ! mem(11040) div 037777,077777,077777 -> n0z0v0c0 |
d=077777 -- ! mem(11042) 1073709055/32767 -> 32767,32766 |
d=077776 -- ! mem(11044) |
d=000002 -- ! mem(11046) div 037777,100000,077777 -> n0z0v1c0 |
d=037777 -- ! mem(11050) 1073709056/32767 -> overflow |
d=100000 -- ! mem(11052) |
d=000010 -- ! mem(11054) div 140000,100001,077777 -> n1z0v0c0 |
d=100001 -- ! mem(11056) -1073709055/32767 -> -32767,-32766 |
d=100002 -- ! mem(11060) |
d=000010 -- ! mem(11062) div 140000,100000,077777->n1z0v1c0 |
d=100000 -- ! mem(11064) -1073709056/32767 -> -32768,0 |
d=000000 -- ! mem(11066) |
d=000002 -- ! mem(11070) div 040000,000000,077777 -> n0z0v1c0 |
d=040000 -- ! mem(11072) 1073741824/32767 -> overflow |
d=000000 -- ! mem(11074) |
# |
# simh notes: |
# 1. a quotient of 100000 leads to an overflow (V=1) on the W11 |
# simh will not indicate overflow and returns q=100000 |
# |
#---- |
C Exec test 31.2 (test mul after div) |
# |
wr0 010500 -- r0=10500 (input data from DIV) |
wr1 010700 -- r1=10700 (output data from DIV) |
wr5 000016 -- r5=16 (test count) |
wsp 001400 -- sp=1400 |
stapc 010420 -- start @ 10420 |
wtgo |
rr0 d=010624 -- ! r0 |
rr1 d=011024 -- ! r1 |
rr2 d=000000 -- ! r2 |
rr3 d=000000 -- ! r3 |
rr5 d=000000 -- ! r5 |
rpc d=010500 -- ! pc |
#----------------------------------------------------------------------------- |
C Setup code 32 [base 11100; use 111-112] (PIRQ test) |
# The code will exercise all 7 pirq interrupt levels: |
# set 1+3 -> handle 3, set 7 -> handle 7, set 6+4 -> handle 6 |
# -> handle 4, set 5+2 -> handle 5 -> handle 2 > handle 1 |
# |
wal 011100 -- code: |
bwm 14 |
000237 -- spl 7 |
011425 -- mov (r4),(r5)+ ; save PSW |
012713 -- mov #1000,(r3) ; set PIRQ 1 |
001000 |
011325 -- mov (r3),(r5)+ ; save PIRQ |
112763 -- movb #12,1(r3) ; set PIRQ 1+3 |
000012 |
000001 |
#11120 |
011325 -- mov (r3),(r5)+ ; save PIRQ |
000232 -- spl 2 ; now pri=2 |
000240 -- nop ; allow interrupt to happen |
000230 -- spl 0 ; now pri=0 |
#11130 |
000240 -- nop ; allow interrupt to happen |
000000 -- halt |
#----- |
wal 000240 -- vector: 240 |
bwm 2 |
011134 -- PC:11134 |
000340 -- PS:pri=7 |
#----- |
wal 011134 -- code: (vector 240) |
bwm 18 |
011300 -- mov (r3),r0 ; get pirq |
010625 -- mov sp,(r5)+ ; save sp |
#11140 |
010025 -- mov r0,(r5)+ ; save pirq |
110014 -- movb r0,(r4) ; PSW=PIRQ (sets priority) |
042700 -- bic #177761,r0 ; mask out index bits |
177761 |
010001 -- mov r0,r1 ; r0 is word index (pri*2) |
006201 -- asr r1 ; r1 is byte index (pri*1) |
012702 -- mov #400,r2 |
000400 |
#11160 |
072201 -- ash r1,r2 ; r2 = 1<<(pri) |
040213 -- bic r2,(r3) ; clear current level in pirq |
010246 -- mov r2,-(sp) ; save pirq level mask |
056013 -- bis 11200(r0),(r3) ; trigger new pirq's |
011200 |
000240 -- noop |
012625 -- mov (sp)+,(r5)+ ; save pirq level mask |
000002 -- rti |
#11200 |
#----- |
wal 011200 -- data: |
bwm 8 |
000000 -- mem(11200)=0 ; new pirq @ level 0 |
000000 -- mem(11202)=0 ; new pirq @ level 1 |
000000 -- mem(11204)=0 ; new pirq @ level 2 |
100000 -- mem(11206)=100000 ; new pirq @ level 3 -> 7 |
022000 -- mem(11210)=022000 ; new pirq @ level 4 -> 5+2 |
000000 -- mem(11212)=0 ; new pirq @ level 5 |
000000 -- mem(11214)=0 ; new pirq @ level 6 |
050000 -- mem(11216)=050000 ; new pirq @ level 7 -> 6+4 |
# |
C Exec code 32 (PIRQ test) |
# |
wr3 177772 -- r3=177772 (#PIRQ) |
wr4 177776 -- r4=177776 (#PSW) |
wr5 011220 -- r1=11220 (output data) |
wsp 001400 -- sp=1400 |
stapc 011100 -- start @ 11100 |
wtgo |
rr5 d=011300 -- ! r5 |
rsp d=001400 -- ! sp |
rpc d=011134 -- ! pc |
rps d=000000 -- ! PSW |
wal 177772 -- |
rmi d=000000 -- ! PIRQ |
wal 011220 -- |
brm 24 |
d=000340 -- ! mem(11220) PSW after SPL 7 |
d=001042 -- ! mem(11222) PIRQ when 1 set |
d=005146 -- ! mem(11224) PIRQ when 1+3 set |
d=001374 -- ! mem(11226) -> PI:3 SP |
d=005146 -- ! mem(11230) PIRQ (3+1 pending) |
d=001366 -- ! mem(11232) -> PI:7 SP |
d=101356 -- ! mem(11234) PIRQ (7+1 pending) |
d=100000 -- ! mem(11236) <- PI:7 mask |
d=001366 -- ! mem(11240) -> PI:6 SP |
d=051314 -- ! mem(11242) PIRQ (6+4+1 pending) |
d=040000 -- ! mem(11244) <- PI:6 mask |
d=001366 -- ! mem(11246) -> PI:4 SP |
d=011210 -- ! mem(11250) PIRQ (4+1 pending) |
d=001360 -- ! mem(11252) -> PI:5 SP |
d=023252 -- ! mem(11254) PIRQ (5+2+1 pending) |
d=020000 -- ! mem(11256) <- PI:5 mask |
d=010000 -- ! mem(11260) <- PI:4 mask |
d=004000 -- ! mem(11262) <- PI:3 mask |
d=001374 -- ! mem(11264) -> PI:2 SP |
d=003104 -- ! mem(11266) PIRQ |
d=002000 -- ! mem(11270) <- PI:2 mask |
d=001374 -- ! mem(11272) -> PI:1 SP |
d=001042 -- ! mem(11274) PIRQ |
d=001000 -- ! mem(11276) <- PI:1 mask |
# |
wal 000240 -- vector: 240 -> trap catcher again |
bwm 2 |
000242 -- PC:242 |
000000 -- PS:0 |
#----------------------------------------------------------------------------- |
C Setup code 33 [base 11200; use 112-113] (adc(b) and sbc(b) test) |
# |
wal 011200 -- code test 1: (adc) |
bwm 5 |
006020 -- L1: ror (r0)+ |
005520 -- adc (r0)+ |
006120 -- rol (r0)+ |
077104 -- sob r1,L1 (.-4) |
000000 -- halt |
#----- |
wal 011220 -- code test 2: (sbc) |
bwm 5 |
006020 -- L1: ror (r0)+ |
005620 -- sbc (r0)+ |
006120 -- rol (r0)+ |
077104 -- sob r1,L1 (.-4) |
000000 -- halt |
#----- |
wal 011240 -- code test 3: (adcb) |
bwm 5 |
006020 -- L1: ror (r0)+ |
105520 -- adcb (r0)+ |
106120 -- rolb (r0)+ |
077104 -- sob r1,L1 (.-4) |
000000 -- halt |
#----- |
wal 011260 -- code test 4: (sbcb) |
bwm 5 |
006020 -- L1: ror (r0)+ |
105620 -- sbcb (r0)+ |
106120 -- rolb (r0)+ |
077104 -- sob r1,L1 (.-4) |
000000 -- halt |
#----- |
wal 011300 -- data test 1: (adc) |
bwm 9 |
000000 -- 177776 + 0 -> 177776 + 0 |
177776 |
000000 |
000001 -- 177776 + 1 -> 177777 + 0 |
177776 |
000000 |
000001 -- 177777 + 1 -> 000000 + 1 |
177777 |
000000 |
#----- |
wal 011324 -- data test 2: (sbc) |
bwm 9 |
000000 -- 000002 - 0 -> 000002 - 0 |
000002 |
000000 |
000001 -- 000002 - 1 -> 000001 - 0 |
000002 |
000000 |
000001 -- 000000 - 1 -> 177777 - 1 |
000000 |
000000 |
#----- |
wal 011350 -- data test 3: (adcb) |
bwm 6 |
000000 -- 376 + 0 -> 376 + 0 |
000376 |
000001 -- 376 + 1 -> 377 + 0 |
000376 |
000001 -- 377 + 1 -> 000 + 1 |
000377 |
#----- |
wal 011364 -- data test 4: (sbcb) |
bwm 6 |
000000 -- 002 - 0 -> 002 - 0 |
000002 |
000001 -- 002 - 1 -> 001 - 0 |
000002 |
000001 -- 000 - 1 -> 337 - 1 |
000000 |
# |
C Exec code 33 (adc and sbc test) |
C Exec test 33.1 (adc) |
# |
wr0 011300 -- r0=11300 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
stapc 011200 -- start @ 11200 |
wtgo |
rr0 d=011322 -- ! r0=11322 |
rpc d=011212 -- ! pc |
wal 011300 |
brm 9 |
d=000000 -- ! mem(11300)=000000 -- 177776 + 0 -> 177776 + 0 |
d=177776 -- ! mem(11302)=000000 |
d=000000 -- ! mem(11304)=000000 |
d=000000 -- ! mem(11306)=000000 -- 177776 + 1 -> 177777 + 0 |
d=177777 -- ! mem(11310)=000000 |
d=000000 -- ! mem(11312)=000000 |
d=000000 -- ! mem(11314)=000000 -- 177777 + 1 -> 000000 + 1 |
d=000000 -- ! mem(11316)=000000 |
d=000001 -- ! mem(11320)=000000 |
#---- |
C Exec test 33.2 (sbc) |
# |
wr0 011324 -- r0=11324 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
stapc 011220 -- start @ 11220 |
wtgo |
rr0 d=011346 -- ! r0=11346 |
rpc d=011232 -- ! pc |
wal 011324 |
brm 9 |
d=000000 -- ! mem(11324)=000000 -- 000002 - 0 -> 000002 - 0 |
d=000002 -- ! mem(11326)=000000 |
d=000000 -- ! mem(11330)=000000 |
d=000000 -- ! mem(11332)=000000 -- 000002 - 1 -> 000001 - 0 |
d=000001 -- ! mem(11334)=000000 |
d=000000 -- ! mem(11336)=000000 |
d=000000 -- ! mem(11340)=000000 -- 000000 - 1 -> 177777 - 1 |
d=177777 -- ! mem(11342)=000000 |
d=000001 -- ! mem(11344)=000000 |
#---- |
C Exec test 33.3 (adcb) |
# |
wr0 011350 -- r0=11350 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
stapc 011240 -- start @ 11240 |
wtgo |
rr0 d=011364 -- ! r0=11364 |
rpc d=011252 -- ! pc |
wal 011350 |
brm 6 |
d=000000 -- ! mem(11350)=000000 -- 376 + 0 -> 376 + 0 |
d=000376 -- ! mem(11352)=000000 |
d=000000 -- ! mem(11354)=000000 -- 376 + 1 -> 377 + 0 |
d=000377 -- ! mem(11356)=000000 |
d=000000 -- ! mem(11360)=000000 -- 377 + 1 -> 000 + 1 |
d=000400 -- ! mem(11362)=000000 |
#---- |
C Exec test 33.4 (sbcb) |
# |
wr0 011364 -- r0=11364 |
wr1 000003 -- r1=3 |
wsp 001400 -- sp=1400 |
stapc 011260 -- start @ 11260 |
wtgo |
rr0 d=011400 -- ! r0=11400 |
rpc d=011272 -- ! pc |
wal 011364 |
brm 6 |
d=000000 -- ! mem(11364)=000000 -- 002 - 0 -> 002 - 0 |
d=000002 -- ! mem(11366)=000000 |
d=000000 -- ! mem(11370)=000000 -- 002 - 1 -> 001 - 0 |
d=000001 -- ! mem(11372)=000000 |
d=000000 -- ! mem(11374)=000000 -- 000 - 1 -> 337 - 1 |
d=000777 -- ! mem(11377)=000000 |
#----------------------------------------------------------------------------- |
C Setup code 34 [base 11400; use 114-115] (11/34 self test code) |
# code adapted from M9312 23-248F1 console PROM, the 11/04-34 Diagnostic PROM |
# |
wal 011400 -- code: |
bwm 51 |
005000 -- clr r0 ; r0=000000 c=0 |
005200 -- inc r0 ; r0=000001 c=0 |
005100 -- com r0 ; r0=177776 c=1 |
006200 -- asr r0 ; r0=177777 c=0 |
006300 -- asl r0 ; r0=177776 c=1 |
006000 -- ror r0 ; r0=177777 c=0 |
005700 -- tst r0 ; r0=177777 c=0 ?impact unclear? |
005400 -- neg r0 ; r0=000001 c=1 |
#11420 |
005300 -- dec r0 ; r0=000000 c=1 |
005600 -- sbc r0 ; r0=177777 c=1 |
006100 -- rol r0 ; r0=177777 c=1 |
005500 -- adc r0 ; r0=000000 c=1 |
000300 -- swab r0 ; r0=000000 c=0 |
001401 -- beq .+1 ; |
000000 -- halt ; |
012702 -- mov #data0,r2 ; r2=011560 |
#11440 |
011560 |
011203 -- mov (r2),r3 ; r2=011560 r3=011560 |
022203 -- cmp (r2)+,r3 ; r2=011562 r3=011560 |
001401 -- beq .+1 ; |
000000 -- halt ; |
063203 -- add @(r2)+,r3 ; r2=011564 r3=<2*11560> |
165203 -- sub @-(r2),r3 ; r2=011562 r3=011560 |
044203 -- bic -(r2),r3 ; r2=011560 r3=000000 |
#11460 |
056203 -- bis 12(r2),r3 ; r2=011560 r3=011566 |
000012 |
037203 -- bis @12(r2),r3 ; r2=011560 r3=011566 |
000012 |
001001 -- bne .+1 ; |
000000 -- halt ; |
010701 -- mov pc,r1 ; r1=011476 |
000121 -- jmp (r1)+ ; jump 1.self 2. next; r1=011500 |
#11500 |
012701 -- mov #L2,r1 ; r1=011510 |
011510 |
000131 -- jmp @(r1)+ ; r1=011512 pc=011506 |
000111 -- L1:jmp (r1) ; r1=011512 pc=011512 |
011506 -- L2:.word L1 |
105737 -- tstb data1 ; |
011564 |
001401 -- beq .+1 ; |
#11520 |
000000 -- halt ; |
010204 -- mov r2,r4 ; keep r2 for later check |
022424 -- cmp (r4)+,(r4)+ ; r4=011564 |
105724 -- tstb (r4)+ ; r4=011565 (r4)+=000 |
001401 -- beq .+1 ; |
000000 -- halt ; |
105714 -- tstb (r4) ; r4=011565 (r4)=200 |
100402 -- bmi .+2 ; |
#11540 |
000000 -- halt ; |
000000 -- halt ; |
000000 -- halt ; |
#----- |
wal 011560 -- data: |
bwm 8 |
011560 -- data0: .word data0 |
011560 -- .word data0 |
100000 -- data1: .byte 000,200 |
177777 -- data2: .word 177777 |
011566 -- .word data2 |
011566 -- .word data2 |
000700 -- .word mem+0 |
000701 -- .word mem+1 |
# |
C Exec code 34 (11/34 self test code) |
# D RE RQ FU DAT |
stapc 011400 -- start @ 11400 |
wtgo |
rr0 d=000000 -- ! r0 |
rr1 d=011512 -- ! r1 |
rr2 d=011560 -- ! r2 |
rr3 d=011566 -- ! r3 |
rr4 d=011565 -- ! r4 |
rpc d=011546 -- ! pc |
#----------------------------------------------------------------------------- |
C Setup code 35 [base 11600; use 116-121] (11/70 self test code) |
# code adapted from M9312 23-616F1 console PROM, the 11/60-70 Diagnostic PROM |
# |
wal 011600 -- code: |
bwm 117 |
005006 -- clr sp ; sp=000000 |
100404 -- bmi L3 ; |
102403 -- bvs L3 ; |
101002 -- bhi L3 ; |
002401 -- blt L3 ; |
101401 -- blos L4 ; |
000000 -- L3: halt ; |
005306 -- L3: dec sp ; sp=177777 |
#11620 |
100003 -- bpl L5 ; |
001402 -- beq L5 ; |
002001 -- bge L5 ; |
003401 -- ble L6 ; |
000000 -- L5: halt ; |
006006 -- L6: ror sp ; sp=077777 |
102002 -- bvc L7 ; |
103001 -- bcc L7 ; |
#11640 |
001001 -- bne L8 ; |
000000 -- L7: halt ; |
012706 -- L8: mov #125252,sp ; sp=125252 |
125252 |
010600 -- mov sp,r0 ; |
010001 -- mov r0,r1 ; |
010102 -- mov r1,r2 ; |
010203 -- mov r2,r3 ; |
#11660 |
010304 -- mov r3,r4 ; |
010405 -- mov r4,r5 ; |
160501 -- sub r5,r1 ; r1=00000 |
002401 -- blt L9a ; |
001401 -- beq L9 ; |
000000 -- L9a: halt ; |
006102 -- L9: rol r2 ; r2=052524 c=1 |
103001 -- bcc L10 ; |
#11700 |
002401 -- blt L11 ; |
000000 -- L10: halt ; |
060203 -- L11: add r2,r3 ; r3=177776 (125252+052524) |
005203 -- inc r3 ; r3=177777 |
005103 -- com r3 ; r3=000000 |
060301 -- add r3,r1 ; r1=000000 c=0 |
103401 -- bcs L12 ; |
003401 -- ble L13 ; |
#11720 |
000000 -- L12: halt ; |
006004 -- L13: ror r4 ; r4=052525 |
050403 -- bis r4,r3 ; r3=052525 (r3 was 0) |
060503 -- add r5,r3 ; r3=177777 c=0 (125252+052525) |
005203 -- inc r3 ; r3=000000 c=0 (kept) |
103402 -- bcs L14 ; |
005301 -- dec r1 ; r1=177777 |
002401 -- blt L15 ; |
#11740 |
000000 -- L14: halt ; |
005100 -- L15: com r0 ; r0=052525 |
101401 -- blos L16 ; |
000000 -- halt ; |
040001 -- L16: bic r0,r1 ; r1=125252 |
060101 -- L16: add r1,r1 ; r1=052524 c=1 |
003001 -- bgt L17 ; |
003401 -- ble L18 ; |
#11760 |
000000 -- L17: halt ; |
000301 -- L18: swab r1 ; r1=052125 |
020127 -- cmp r1,#052125 ; |
052125 |
001004 -- bne L19 ; |
030405 -- bit r4,r5 ; |
003002 -- bgt L19 ; |
005105 -- com r5 ; r5=052525 |
#12000 |
001001 -- bne L20 ; |
000000 -- L19: halt ; |
112700 -- L20: movb #177401,r0 ; |
177401 |
100001 -- bpl L21 ; |
000000 -- L22: halt ; |
077002 -- L21: sob r0,L22 ; |
000261 -- sec ; c=1 |
#12020 |
006100 -- rol r0 ; r0=000001 |
006100 -- rol r0 ; r0=000002 |
006100 -- rol r0 ; r0=000004 |
010001 -- mov r0,r1 ; r1=000004 |
005401 -- neg r1 ; r1=177774 |
005201 -- L23: inc r1 ; |
077002 -- sob r0,L23 ; |
005700 -- tst r0 ; here r0=r1=0 |
#12040 |
001002 -- bne L24 ; |
005701 -- tst r1 ; |
001401 -- beq L25 ; |
000000 -- L24: halt ; |
012706 -- L25: mov #776,sp ; |
000776 -- |
004767 -- jsr pc,L26 ; |
000002 |
#12060 |
000000 -- N2: halt ; |
022716 -- L26: cmp #N2,(sp) ; |
012060 |
001401 -- beq L27 ; |
000000 -- halt ; |
012716 -- L27: mov #N3,(sp) ; |
012102 |
000207 -- rts pc ; |
#12100 |
000000 -- halt ; |
005046 -- N3: clr -(sp) ; |
012746 -- mov #N4,-(sp) ; |
012114 |
000002 -- rti ; |
000000 -- halt ; |
000137 -- N4: jmp @#N5 ; |
012122 |
#12120 |
000000 -- halt ; |
012705 -- N5: mov #160000,r5 ; r5=160000 |
160000 |
005037 -- clr @#6 ; |
000006 |
012737 -- mov #N6,@#4 ; |
012150 |
000004 |
#12140 |
012706 -- mov #776,sp ; sp=776 |
000776 |
005715 -- tst (r5) ; will fail, first word of I/O page |
000000 -- halt ; |
000000 -- N6: halt ; |
# |
C Exec code 35 (11/70 self test code) |
# D RE RQ FU DAT |
stapc 011600 -- start @ 11600 |
wtgo |
rpc d=012152 -- ! pc |
wal 000004 -- vector: 4 -> trap catcher again |
bwm 2 |
000006 -- PC:6 |
000000 -- PS:0 |
#----------------------------------------------------------------------------- |
# Up to here code and data (both input and result) occupied 'fresh' memory. |
# Easy to debug, but inconvenient when test should be extended later. |
# From here on, only code will always occupy fresh memory. |
# Data will be put into the upper part of the 16 kbyte memory: |
# test vector: 036000 (512 byte area) |
# result data: 037000 (512 byte area) |
#----------------------------------------------------------------------------- |
C Setup code 36 [base 12200] (systematic CMP test) |
# |
wal 012200 -- code: |
bwm 7 |
000230 -- spl 0 |
012400 -- L1: mov (r4)+,r0 |
012401 -- mov (r4)+,r1 |
020001 -- cmp r0,r1 |
011225 -- mov (r2),(r5)+ |
077305 -- sob r3,L1 |
000000 -- halt |
# |
C Exec code 36 (systematic CMP test) |
C Exec test 36.1: data adapted from cmp.s11 code of Begemot p11-2.10c |
# |
wal 036000 -- setup test vector: |
bwm 22 |
000000 -- 000000, 000000 --> nzvc=0100 |
000000 -- |
000001 -- 000001, 000001 --> nzvc=0100 |
000001 -- |
177777 -- 177777, 177777 --> nzvc=0100 |
177777 -- |
000000 -- 000000, 000001 --> nzvc=1001 |
000001 -- |
000000 -- 000000, 177777 --> nzvc=0001 |
177777 -- |
000001 -- 000001, 000000 --> nzvc=0000 |
000000 -- |
177777 -- 177777, 000000 --> nzvc=1000 |
000000 -- |
000001 -- 000001, 177777 --> nzvc=0001 |
177777 -- |
177777 -- 177777, 000001 --> nzvc=1000 |
000001 -- |
077777 -- 077777, 100000 --> nzvc=1011 |
100000 -- |
100000 -- 100000, 077777 --> nzvc=0010 |
077777 -- |
#---- |
wr2 177776 -- r2=177776 -> psw |
wr3 000013 -- r3=13 -> test count |
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
stapc 012200 -- start @ 12200 |
wtgo |
rpc d=012216 -- ! pc |
rr3 d=000000 -- ! r3=0 |
rr4 d=036054 -- ! r4=12354 |
rr5 d=037026 -- ! r5=12426 |
wal 037000 -- |
brm 11 |
d=000004 -- 000000, 000000 --> nzvc=0100 |
d=000004 -- 000001, 000001 --> nzvc=0100 |
d=000004 -- 177777, 177777 --> nzvc=0100 |
d=000011 -- 000000, 000001 --> nzvc=1001 |
d=000001 -- 000000, 177777 --> nzvc=0001 |
d=000000 -- 000001, 000000 --> nzvc=0000 |
d=000010 -- 177777, 000000 --> nzvc=1000 |
d=000001 -- 000001, 177777 --> nzvc=0001 |
d=000010 -- 177777, 000001 --> nzvc=1000 |
d=000013 -- 077777, 100000 --> nzvc=1011 |
d=000002 -- 100000, 077777 --> nzvc=0010 |
#----------------------------------------------------------------------------- |
C Setup code 37 [base 12300] (systematic DIV test) |
# |
wal 012300 -- code: |
bwm 9 |
000230 -- spl 0 |
012400 -- L1: mov (r4)+,r0 |
012401 -- mov (r4)+,r1 |
071024 -- div (r4)+,r0 |
011225 -- mov (r2),(r5)+ |
010025 -- mov r0,(r5)+ |
010125 -- mov r1,(r5)+ |
077307 -- sob r3,L1 |
#12520 |
000000 -- halt |
# |
C Exec code 37 (systematic DIV test) |
C Exec test 37.1: data adapted from div.s11 code of Begemot p11-2.10c |
# |
wal 036000 -- setup test vector: |
bwm 57 |
000000 -- 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4 |
000004 -- |
000000 -- |
000000 -- 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0 |
000004 -- |
000002 -- |
000000 -- 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0 |
000006 -- |
000002 -- |
000000 -- 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0 |
000004 -- |
177776 -- |
#36030 |
000002 -- 2, 0, 1, 2, 2, 0# 0x20000 / 1 |
000000 -- |
000001 -- |
000002 -- 2, 0, -2, 12, 2, 0# 0x20000 / -2 |
000000 -- |
177776 -- |
100000 -- 100000, 0, 1, 12,100000, 0# 0x80000000 / 1 |
000000 -- |
000001 -- |
177776 -- 177776,177777, -1, 2,177776,177777# -0x10001 / -1 |
177777 -- |
177777 -- |
#36060 |
177777 -- 177777,177773, 2, 10, -2, -1# -5 / 2 |
177773 -- |
000002 -- |
177777 -- 177777,177773, -2, 0, 2, -1# -5 / -2 |
177773 -- |
177776 -- |
177776 -- 177776, 0, 40000, 10, -10, 0# -0x20000/0x4000 |
000000 -- |
040000 -- |
000100 -- 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f |
000200 -- |
177601 -- |
#36110 |
000000 -- 0, 1, 0, 7, 0, 1 # zero divide |
000001 -- |
000000 -- |
177777 -- -1, -1, 0, 7, -1, -1 # zero divide |
177777 -- |
000000 -- |
000000 -- 0, 0, 0, 7, 0, 0 # zero divide |
000000 -- |
000000 -- |
000001 -- 1, 1, 1, 2, 1, 1 # overflow |
000001 -- |
000001 -- |
#36140 |
000001 -- 1, 1, -1, 012, 1, 1 # overflow |
000001 -- |
177777 -- |
177777 -- -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow |
177777 -- |
000001 -- |
177777 -- -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow |
177777 -- |
177777 -- |
#---- |
wr2 177776 -- r2=177776 -> psw |
wr3 000023 -- r3=23 -> test count |
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
stapc 012300 -- start @ 12300 |
wtgo |
rpc d=012322 -- ! pc |
rr3 d=000000 -- ! r3=0 |
rr4 d=036162 -- ! r4=36162 |
rr5 d=037162 -- ! r5=37162 |
wal 037000 -- |
brm 57 |
d=000007 --! 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4 |
d=000000 --! |
d=000004 --! |
d=000000 --! 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0 |
d=000002 --! |
d=000000 --! |
d=000000 --! 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0 |
d=000003 --! |
d=000000 --! |
d=000010 --! 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0 |
d=177776 --! |
d=000000 --! |
#37030 |
d=000002 --! 2, 0, 1, 2, 2, 0# 0x20000 / 1 |
d=000002 --! |
d=000000 --! |
d=000012 --! 2, 0, -2, 12, 2, 0# 0x20000 / -2 |
d=000002 --! |
d=000000 --! |
d=000012 --!100000, 0, 1, 12,100000, 0# 0x80000000 / 1 |
d=100000 --! |
d=000000 --! |
d=000002 --!177776,177777, -1, 2,177776,177777# -0x10001 / -1 |
d=177776 --! |
d=177777 --! |
#37060 |
d=000010 --!177777,177773, 2, 10, -2, -1# -5 / 2 |
d=177776 --! |
d=177777 --! |
d=000000 --!177777,177773, -2, 0, 2, -1# -5 / -2 |
d=000002 --! |
d=177777 --! |
d=000010 --!177776, 0, 40000, 10, -10, 0# -0x20000/0x4000 |
d=177770 --! |
d=000000 --! |
d=000012 --! 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f |
d=000100 --! |
d=000200 --! |
#37110 |
d=000007 --! 0, 1, 0, 7, 0, 1 # zero divide |
d=000000 --! |
d=000001 --! |
d=000007 --! -1, -1, 0, 7, -1, -1 # zero divide |
d=177777 --! |
d=177777 --! |
d=000007 --! 0, 0, 0, 7, 0, 0 # zero divide |
d=000000 --! |
d=000000 --! |
d=000002 --! 1, 1, 1, 2, 1, 1 # overflow |
d=000001 --! |
d=000001 --! |
#13740 |
d=000012 --! 1, 1, -1, 012, 1, 1 # overflow |
d=000001 --! |
d=000001 --! |
d=000010 --! -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow |
d=177777 --! |
d=000000 --! |
d=000000 --! -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow |
d=000001 --! |
d=000000 --! |
#-------- |
C Exec test 37.2: data adapted from KDJ11.MAC, test 213, p. 139-141 |
# D RE RQ FU DAT |
wal 036000 -- setup test vector: |
bwm 51 |
177777 -- 177777,177777,177777, 0, 1, 0# |
177777 -- |
177777 -- |
000000 -- 0,177777,177777,12, 0,177777# w11a:12,000001,000000 |
177777 -- |
177777 -- |
177777 -- 177777, 0,177777, 2,177777, 0# |
000000 -- |
177777 -- |
000000 -- 0, 7642, 7643, 4, 0, 7642# |
007642 -- |
007643 -- |
000000 -- 0, 137,177543, 4, 0, 137# |
000137 -- |
177543 -- |
000000 -- 0, 7643, 7643, 0, 1, 0# |
007643 -- |
007643 -- |
100000 -- 100000, 4376, 10021,12,100000, 4376# |
004376 -- |
010021 -- |
177700 -- 177700,170033, 10021,10,176024,171307# |
170033 -- |
010021 -- |
177700 -- 177700,170033,167757, 0, 1754,171307# |
170033 -- |
167757 -- |
000000 -- 0,177777, 1, 2, 0,177777# |
177777 -- |
000001 -- |
177777 -- 177777, 45716, 1,12,177777, 45716# w11a:12,045716,000000 |
045716 -- |
000001 -- |
000000 -- 0, 2,177770, 4, 0, 2# |
000002 -- |
177770 -- |
177777 -- 177777,177776, 10, 4, 0,177776# |
177776 -- |
000010 -- |
000001 -- 1,177777, 1, 2, 1,177777# |
177777 -- |
000001 -- |
000001 -- 1, 0, 2, 2, 1, 0# |
000000 -- |
000002 -- |
000001 -- 1, 0, 3, 0, 52525, 1# |
000000 -- |
000003 -- |
000023 -- 23, 16054, 16537, 0, 246, 10222# |
016054 -- |
016537 -- |
#---- |
wr2 177776 -- r2=177776 -> psw |
wr3 000021 -- r3=21 (17.) -> test count |
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
stapc 012300 -- start @ 12300 |
wtgo |
rpc d=012322 -- ! pc |
rr3 d=000000 -- ! r3=0 |
rr4 d=036146 -- ! r4=36146 |
rr5 d=037146 -- ! r5=37146 |
wal 037000 -- |
brm 51 |
d=000000 --!177777,177777,177777, 0, 1, 0# |
d=000001 --! |
d=000000 --! |
d=000012 --! 0,177777,177777,12, 0,177777# w11a:12,000001,000000 |
d=000001 --! |
d=000000 --! |
d=000002 --!177777, 0,177777, 2,177777, 0# |
d=177777 --! |
d=000000 --! |
d=000004 --! 0, 7642, 7643, 4, 0, 7642# |
d=000000 --! |
d=007642 --! |
d=000004 --! 0, 137,177543, 4, 0, 137# |
d=000000 --! |
d=000137 --! |
d=000000 --! 0, 7643, 7643, 0, 1, 0# |
d=000001 --! |
d=000000 --! |
d=000012 --!100000, 4376, 10021,12,100000, 4376# |
d=100000 --! |
d=004376 --! |
d=000010 --!177700,170033, 10021,10,176024,171307# |
d=176024 --! |
d=171307 --! |
d=000000 --!177700,170033,167757, 0, 1754,171307# |
d=001754 --! |
d=171307 --! |
d=000002 --! 0,177777, 1, 2, 0,177777# |
d=000000 --! |
d=177777 --! |
d=000012 --!177777, 45716, 1,12,177777, 45716# w11a:12,045716,000000 |
d=045716 --! |
d=000000 --! |
d=000004 --! 0, 2,177770, 4, 0, 2# |
d=000000 --! |
d=000002 --! |
d=000004 --!177777,177776, 10, 4, 0,177776# |
d=000000 --! |
d=177776 --! |
d=000002 --! 1,177777, 1, 2, 1,177777# |
d=000001 --! |
d=177777 --! |
d=000002 --! 1, 0, 2, 2, 1, 0# |
d=000001 --! |
d=000000 --! |
d=000000 --! 1, 0, 3, 0, 52525, 1# |
d=052525 --! |
d=000001 --! |
d=000000 --! 23, 16054, 16537, 0, 246, 10222# |
d=000246 --! |
d=010222 --! |
#----------------------------------------------------------------------------- |
C Setup code 40 [base 12400] (systematic ASH test) |
# |
wal 012400 -- code: |
bwm 15 |
000230 -- spl 0 |
016400 -- L1: mov 2(r4),r0 |
000002 |
011412 -- mov (r4),(r2) |
072064 -- ash 4(r4),r0 |
000004 |
011265 -- mov (r2),2(r5) |
000002 |
#12420 |
010015 -- mov r0,(r5) |
062704 -- add #6,r4 |
000006 |
062705 -- add #4,r5 |
000004 |
077315 -- sob r3,L1 |
000000 -- halt |
# |
C Exec code 40 (systematic ASH test) |
C Exec test 40.1: data adapted from ash.s11 code of Begemot p11-2.10c |
# |
# The {} comments are original comments from Harti Brandt |
# Annotations starting with !! indicated mods for W11 |
# Note, that the W11 does not have the microcode bugs of the J11 ! |
# |
wal 036000 -- setup test vector: |
# test shift amount 0 |
bwm 150 |
000000 -- 00, 000000, 000000, 000000, 04 |
000000 -- |
000000 -- |
000017 -- 17, 000000, 000000, 000000, 04 |
000000 -- |
000000 -- |
000017 -- 17, 100001, 000000, 100001, 10 |
100001 -- |
000000 -- |
000017 -- 17, 040001, 000000, 040001, 00 |
040001 -- |
000000 -- |
000017 -- 17, 040001, 177700, 040001, 00 |
040001 -- |
177700 -- |
# right shift positive values |
000000 -- 00, 000000, 000077, 000000, 04 |
000000 -- |
000077 -- |
000017 -- 17, 000000, 000077, 000000, 04 |
000000 -- |
000077 -- |
000000 -- 00, 000002, 000077, 000001, 00 |
000002 -- |
000077 -- |
000000 -- 00, 000001, 000077, 000000, 05 |
000001 -- |
000077 -- |
000000 -- 00, 000003, 000076, 000000, 05 |
000003 -- |
000076 -- |
000000 -- 00, 000001, 000076, 000000, 04 |
000001 -- |
000076 -- |
000000 -- 00, 040000, 000062, 000001, 00 |
040000 -- |
000062 -- |
000000 -- 00, 040000, 000061, 000000, 05 |
040000 -- |
000061 -- |
000000 -- 00, 040000, 000060, 000000, 04 |
040000 -- |
000060 -- |
000000 -- 00, 040000, 000042, 000000, 04 |
040000 -- |
000042 -- |
000000 -- 00, 040000, 000041, 000000, 04 |
040000 -- |
000041 -- |
000000 -- 00, 040000, 000040, 000000, 04 |
040000 -- |
000040 -- |
000000 -- 00, 040000, 100037, 000000, 04 |
040000 -- |
100037 -- |
# right shift negative numbers |
000000 -- 00, 100002, 000077, 140001, 10 |
100002 -- |
000077 -- |
000000 -- 00, 100002, 000076, 160000, 11 |
100002 -- |
000076 -- |
000000 -- 00, 100002, 000075, 170000, 10 |
100002 -- |
000075 -- |
000000 -- 00, 100002, 000062, 177776, 10 |
100002 -- |
000062 -- |
000000 -- 00, 100002, 000061, 177777, 10 |
100002 -- |
000061 -- |
000000 -- 00, 100002, 000060, 177777, 11 |
100002 -- |
000060 -- |
000000 -- 00, 100002, 000057, 177777, 11 |
100002 -- |
000057 -- |
000000 -- 00, 100002, 000056, 177777, 11 |
100002 -- |
000056 -- |
000000 -- 00, 100002, 000041, 177777, 11 |
100002 -- |
000041 -- |
000000 -- 00, 100002, 000040, 177777, 11 |
100002 -- |
000040 -- |
000000 -- 00, 100002, 040037, 177777, 11 |
100002 -- |
040037 -- |
# left shift positive numbers |
000000 -- 00, 000000, 000001, 000000, 04 |
000000 -- |
000001 -- |
000017 -- 17, 000000, 000001, 000000, 04 |
000000 -- |
000001 -- |
000000 -- 00, 000001, 000007, 000200, 00 |
000001 -- |
000007 -- |
000000 -- 00, 000001, 000016, 040000, 00 |
000001 -- |
000016 -- |
000000 -- 00, 000001, 000017, 100000, 12 |
000001 -- |
000017 -- |
000000 -- 00, 000001, 000020, 000000, 07 |
000001 -- |
000020 -- |
000000 -- 00, 000001, 000021, 000000, 06 |
000001 -- |
000021 -- |
000000 -- 00, 000001, 000036, 000000, 06 |
000001 -- |
000036 -- |
000000 -- 00, 000001, 000037, 000000, 04 {????} |
000001 -- |
000037 -- |
000000 -- 00, 000001, 000040, 000000, 04 {right shift!} |
000001 -- |
000040 -- |
000000 -- 00, 000001, 010037, 000000, 04 {right shift!} |
000001 -- |
010037 -- |
# left shift negative numbers |
000000 -- 00, 100001, 000001, 000002, 03 |
100001 -- |
000001 -- |
000000 -- 00, 140001, 000001, 100002, 11 |
140001 -- |
000001 -- |
000000 -- 00, 140001, 000002, 000004, 03 |
140001 -- |
000002 -- |
000000 -- 00, 140001, 000016, 040000, 02 |
140001 -- |
000016 -- |
000000 -- 00, 140001, 000017, 100000, 12 |
140001 -- |
000017 -- |
000000 -- 00, 140001, 000020, 000000, 07 |
140001 -- |
000020 -- |
000000 -- 00, 140001, 000021, 000000, 06 |
140001 -- |
000021 -- |
000000 -- 00, 140002, 000035, 000000, 06 |
140002 -- |
000035 -- |
000000 -- 00, 140002, 000036, 000000, 06 |
140002 -- |
000036 -- |
000000 -- 00, 140002, 000037, 177777, 11 {????} |
140002 -- |
000037 -- |
#---- |
wr2 177776 -- r2=177776 -> psw |
wr3 000062 -- r3=62 -> test count |
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
stapc 012400 -- start @ 12400 |
wtgo |
rpc d=012436 -- ! pc |
rr3 d=000000 -- ! r3=0 |
rr4 d=036454 -- ! r4=36454 |
rr5 d=037310 -- ! r5=37310 |
wal 037000 -- |
# test shift amount 0 |
brm 100 |
d=000000 -- 00, 000000, 000000, 000000, 04 |
d=000004 -- |
d=000000 -- 17, 000000, 000000, 000000, 04 |
d=000004 -- |
d=100001 -- 17, 100001, 000000, 100001, 10 |
d=000010 -- |
d=040001 -- 17, 040001, 000000, 040001, 00 |
d=000000 -- |
d=040001 -- 17, 040001, 177700, 040001, 00 |
d=000000 -- |
#37024 # right shift positive values |
d=000000 -- 00, 000000, 000077, 000000, 04 |
d=000004 -- |
d=000000 -- 17, 000000, 000077, 000000, 04 |
d=000004 -- |
d=000001 -- 00, 000002, 000077, 000001, 00 |
d=000000 -- |
#37040 |
d=000000 -- 00, 000001, 000077, 000000, 05 |
d=000005 -- |
d=000000 -- 00, 000003, 000076, 000000, 05 |
d=000005 -- |
d=000000 -- 00, 000001, 000076, 000000, 04 |
d=000004 -- |
d=000001 -- 00, 040000, 000062, 000001, 00 |
d=000000 -- |
#37060 |
d=000000 -- 00, 040000, 000061, 000000, 05 |
d=000005 -- |
d=000000 -- 00, 040000, 000060, 000000, 04 |
d=000004 -- |
d=000000 -- 00, 040000, 000042, 000000, 04 |
d=000004 -- |
d=000000 -- 00, 040000, 000041, 000000, 04 |
d=000004 -- |
#37100 |
d=000000 -- 00, 040000, 000040, 000000, 04 |
d=000004 -- |
d=000000 -- 00, 040000, 100037, 000000, 04 |
d=000006 -- !!04->06 |
#37110 # right shift negative numbers |
d=140001 -- 00, 100002, 000077, 140001, 10 |
d=000010 -- |
d=160000 -- 00, 100002, 000076, 160000, 11 |
d=000011 -- |
#37120 |
d=170000 -- 00, 100002, 000075, 170000, 10 |
d=000010 -- |
d=177776 -- 00, 100002, 000062, 177776, 10 |
d=000010 -- |
d=177777 -- 00, 100002, 000061, 177777, 10 |
d=000010 -- |
d=177777 -- 00, 100002, 000060, 177777, 11 |
d=000011 -- |
#37140 |
d=177777 -- 00, 100002, 000057, 177777, 11 |
d=000011 -- |
d=177777 -- 00, 100002, 000056, 177777, 11 |
d=000011 -- |
d=177777 -- 00, 100002, 000041, 177777, 11 |
d=000011 -- |
d=177777 -- 00, 100002, 000040, 177777, 11 |
d=000011 -- see Note below [[s:10]] |
d=000000 -- 00, 100002, 040037, 177777, 11 !!-1->0 |
d=000006 -- !!11->06 |
#37164 # left shift positive numbers |
d=000000 -- 00, 000000, 000001, 000000, 04 |
d=000004 -- |
d=000000 -- 17, 000000, 000001, 000000, 04 |
d=000004 -- |
d=000200 -- 00, 000001, 000007, 000200, 00 |
d=000000 -- |
#37200 |
d=040000 -- 00, 000001, 000016, 040000, 00 |
d=000000 -- |
d=100000 -- 00, 000001, 000017, 100000, 12 |
d=000012 -- |
d=000000 -- 00, 000001, 000020, 000000, 07 |
d=000007 -- |
d=000000 -- 00, 000001, 000021, 000000, 06 |
d=000006 -- |
#37220 |
d=000000 -- 00, 000001, 000036, 000000, 06 |
d=000006 -- |
d=000000 -- 00, 000001, 000037, 000000, 04 {????} |
d=000006 -- !!04->06 |
d=000000 -- 00, 000001, 000040, 000000, 04 {right shift!} |
d=000004 -- |
d=000000 -- 00, 000001, 010037, 000000, 04 {right shift!} |
d=000006 -- !!04->06 |
#37240 # left shift negative numbers |
d=000002 -- 00, 100001, 000001, 000002, 03 |
d=000003 -- |
d=100002 -- 00, 140001, 000001, 100002, 11 |
d=000011 -- |
d=000004 -- 00, 140001, 000002, 000004, 03 |
d=000003 -- |
d=040000 -- 00, 140001, 000016, 040000, 02 |
d=000002 -- |
#37260 |
d=100000 -- 00, 140001, 000017, 100000, 12 |
d=000012 -- |
d=000000 -- 00, 140001, 000020, 000000, 07 |
d=000007 -- |
d=000000 -- 00, 140001, 000021, 000000, 06 |
d=000006 -- |
d=000000 -- 00, 140002, 000035, 000000, 06 |
d=000006 -- |
#37300 |
d=000000 -- 00, 140002, 000036, 000000, 06 |
d=000006 -- |
d=000000 -- 00, 140002, 000037, 177777, 11 {????} !!-1->0 |
d=000006 -- !!11->06 |
# |
# simh notes: |
# 1. ash dst=100002,src=040 sets C=0 in simh. PSW is: s:10 b:11 W11:11 |
# |
#----------------------------------------------------------------------------- |
C Setup code 41 [base 12500] (systematic ASHC even test) |
# |
wal 012500 -- code: |
bwm 19 |
000230 -- spl 0 |
016400 -- L1: mov 2(r4),r0 |
000002 |
016401 -- mov 4(r4),r1 |
000004 |
011412 -- mov (r4),(r2) |
073064 -- ashc 6(r4),r0 |
000006 |
#12520 |
011265 -- mov (r2),4(r5) |
000004 |
010015 -- mov r0,(r5) |
010165 -- mov r1,2(r5) |
000002 |
062704 -- add #10,r4 |
000010 |
062705 -- add #6,r5 |
#12540 |
000006 |
077321 -- sob r3,L1 |
000000 -- halt |
# |
C Exec code 41 (systematic ASHC even test) |
C Exec test 41.1: data adapted from ashc.s11 code of Begemot p11-2.10c |
# |
# The {} comments are original comments from Harti Brandt |
# Annotations starting with !! indicated mods for W11 |
# Note, that the W11 does not have the microcode bugs of the J11 ! |
# |
wal 036000 -- setup test vector: |
# test when no shift at all, cc must be correctly set |
bwm 188 |
000000 -- 00, 000000, 000000, 000000, 000000, 000000, 04 |
000000 -- |
000000 -- |
000000 -- |
000017 -- 17, 000000, 000000, 000000, 000000, 000000, 04 |
000000 -- |
000000 -- |
000000 -- |
000017 -- 17, 040000, 000001, 000000, 040000, 000001, 00 |
040000 -- |
000001 -- |
000000 -- |
000017 -- 17, 100000, 000001, 000000, 100000, 000001, 10 |
100000 -- |
000001 -- |
000000 -- |
000017 -- 17, 100000, 000001, 177700, 100000, 000001, 10 |
100000 -- |
000001 -- |
177700 -- |
# right shifts of positive numbers |
000000 -- 00, 000000, 000000, 000077, 000000, 000000, 04 |
000000 -- |
000000 -- |
000077 -- |
000017 -- 17, 000000, 000000, 000077, 000000, 000000, 04 |
000000 -- |
000000 -- |
000077 -- |
000000 -- 00, 040000, 000000, 000077, 020000, 000000, 00 |
040000 -- |
000000 -- |
000077 -- |
000000 -- 00, 040000, 000000, 177777, 020000, 000000, 00 |
040000 -- |
000000 -- |
000077 -- |
000000 -- 00, 040000, 000000, 000060, 000000, 040000, 00 |
040000 -- |
000000 -- |
000060 -- |
000000 -- 00, 040000, 000000, 000042, 000000, 000001, 00 |
040000 -- |
000000 -- |
000042 -- |
000000 -- 00, 040000, 000000, 000041, 000000, 000000, 05 |
040000 -- |
000000 -- |
000041 -- |
000000 -- 00, 040000, 000000, 000040, 000000, 000000, 04 |
040000 -- |
000000 -- |
000040 -- |
000000 -- 00, 040000, 000000, 177737, 000000, 000000, 04 |
040000 -- |
000000 -- |
177737 -- |
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04 |
000000 -- |
000001 -- |
177737 -- |
# right shifts of negative numbers |
000000 -- 00, 100000, 000002, 000077, 140000, 000001, 10 |
100000 -- |
000002 -- |
000077 -- |
000000 -- 00, 100020, 000001, 000077, 140010, 000000, 11 |
100020 -- |
000001 -- |
000077 -- |
000000 -- 00, 177777, 177776, 000077, 177777, 177777, 10 |
177777 -- |
177776 -- |
000077 -- |
000000 -- 00, 177777, 177777, 000077, 177777, 177777, 11 |
177777 -- |
177777 -- |
000077 -- |
000000 -- 00, 100000, 100000, 000060, 177777, 100000, 11 |
100000 -- |
100000 -- |
000060 -- |
000000 -- 00, 100000, 000000, 000060, 177777, 100000, 10 |
100000 -- |
000000 -- |
000060 -- |
000000 -- 00, 100000, 000001, 000042, 177777, 177776, 10 |
100000 -- |
000001 -- |
000042 -- |
000000 -- 00, 100000, 000001, 000041, 177777, 177777, 10 |
100000 -- |
000001 -- |
000041 -- |
000000 -- 00, 100000, 000001, 000040, 177777, 177777, 11 |
100000 -- |
000001 -- |
000040 -- |
000000 -- 00, 100000, 000001, 177737, 177777, 177777, 11 |
100000 -- |
000001 -- |
177737 -- |
# left shifts of positive numbers |
000000 -- 00, 000000, 000000, 000001, 000000, 000000, 04 |
000000 -- |
000000 -- |
000001 -- |
000017 -- 17, 000000, 000000, 000001, 000000, 000000, 04 |
000000 -- |
000000 -- |
000001 -- |
000000 -- 00, 000002, 000001, 000001, 000004, 000002, 00 |
000002 -- |
000001 -- |
000001 -- |
000000 -- 00, 000002, 100000, 000001, 000005, 000000, 00 |
000002 -- |
100000 -- |
000001 -- |
000000 -- 00, 040000, 000000, 000001, 100000, 000000, 12 |
040000 -- |
000000 -- |
000001 -- |
000000 -- 00, 040000, 000000, 000002, 000000, 000000, 07 |
040000 -- |
000000 -- |
000002 -- |
000000 -- 00, 040000, 000000, 000003, 000000, 000000, 06 |
040000 -- |
000000 -- |
000003 -- |
000000 -- 00, 000000, 000001, 177701, 000000, 000002, 00 |
000000 -- |
000001 -- |
177701 -- |
000000 -- 00, 000000, 000001, 177735, 020000, 000000, 00 |
000000 -- |
000001 -- |
177735 -- |
000000 -- 00, 000000, 000001, 177736, 040000, 000000, 00 |
000000 -- |
000001 -- |
177736 -- |
000000 -- 00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!} |
000000 -- |
000001 -- |
000037 -- |
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!} |
000000 -- |
000001 -- |
177737 -- |
000000 -- 00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!} |
000000 -- |
000001 -- |
020037 -- |
# left shifts of negative numbers |
000000 -- 00, 177777, 177777, 000001, 177777, 177776, 11 |
177777 -- |
177777 -- |
000001 -- |
000000 -- 00, 177777, 177777, 000002, 177777, 177774, 11 |
177777 -- |
177777 -- |
000002 -- |
000000 -- 00, 177777, 177777, 000036, 140000, 000000, 11 |
177777 -- |
177777 -- |
000036 -- |
000000 -- 00, 177777, 177777, 000037, 100000, 000000, 11 |
177777 -- |
177777 -- |
000037 -- |
000000 -- 00, 177777, 177776, 000037, 000000, 000000, 07 |
177777 -- |
177776 -- |
000037 -- |
000000 -- 00, 177777, 177774, 000037, 000000, 000000, 06 |
177777 -- |
177774 -- |
000037 -- |
000000 -- 00, 177777, 177777, 177701, 177777, 177776, 11 |
177777 -- |
177777 -- |
177701 -- |
000000 -- 00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!} |
177777 -- |
177777 -- |
001037 -- |
000000 -- 00, 177777, 177777, 001036, 140000, 000000, 11 |
177777 -- |
177777 -- |
001036 -- |
#---- |
wr2 177776 -- r2=177776 |
wr3 000057 -- r3=57 (47.) |
wr4 036000 -- r4=36000 |
wr5 037000 -- r5=37000 |
wsp 001400 -- sp=1400 |
stapc 012500 -- start @ 12500 |
wtgo |
rpc d=012546 -- ! pc |
rr3 d=000000 -- ! r3=0 |
rr4 d=036570 -- ! r4=36570 |
rr5 d=037432 -- ! r5=37432 |
wal 037000 -- |
# test when no shift at all, cc must be correctly set |
brm 141 |
d=000000 --!00, 000000, 000000, 000000, 000000, 000000, 04 |
d=000000 --! |
d=000004 --! |
d=000000 --!17, 000000, 000000, 000000, 000000, 000000, 04 |
d=000000 --! |
d=000004 --! |
d=040000 --!17, 040000, 000001, 000000, 040000, 000001, 00 |
d=000001 --! |
d=000000 --! |
d=100000 --!17, 100000, 000001, 000000, 100000, 000001, 10 |
d=000001 --! |
d=000010 --! |
#37030 |
d=100000 --!17, 100000, 000001, 177700, 100000, 000001, 10 |
d=000001 --! |
d=000010 --! |
# right shifts of positive numbers |
d=000000 --!00, 000000, 000000, 000077, 000000, 000000, 04 |
d=000000 --! |
d=000004 --! |
d=000000 --!17, 000000, 000000, 000077, 000000, 000000, 04 |
d=000000 --! |
d=000004 --! |
d=020000 --!00, 040000, 000000, 000077, 020000, 000000, 00 |
d=000000 --! |
d=000000 --! |
#37060 |
d=020000 --!00, 040000, 000000, 177777, 020000, 000000, 00 |
d=000000 --! |
d=000000 --! |
d=000000 --!00, 040000, 000000, 000060, 000000, 040000, 00 |
d=040000 --! |
d=000000 --! |
d=000000 --!00, 040000, 000000, 000042, 000000, 000001, 00 |
d=000001 --! |
d=000000 --! |
d=000000 --!00, 040000, 000000, 000041, 000000, 000000, 05 |
d=000000 --! |
d=000005 --! |
#37110 |
d=000000 --!00, 040000, 000000, 000040, 000000, 000000, 04 |
d=000000 --! |
d=000004 --! |
d=000000 --!00, 040000, 000000, 177737, 000000, 000000, 04 |
d=000000 --! |
d=000006 --! !!04->06 |
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04!!->100000 |
d=000000 --! |
d=000012 --! !!04->12 |
# right shifts of negative numbers |
d=140000 --!00, 100000, 000002, 000077, 140000, 000001, 10 |
d=000001 --! |
d=000010 --! |
#37140 |
d=140010 --!00, 100020, 000001, 000077, 140010, 000000, 11 |
d=000000 --! |
d=000011 --! |
d=177777 --!00, 177777, 177776, 000077, 177777, 177777, 10 |
d=177777 --! |
d=000010 --! |
d=177777 --!00, 177777, 177777, 000077, 177777, 177777, 11 |
d=177777 --! |
d=000011 --! |
d=177777 --!00, 100000, 100000, 000060, 177777, 100000, 11 |
d=100000 --! |
d=000011 --! |
#37170 |
d=177777 --!00, 100000, 000000, 000060, 177777, 100000, 10 |
d=100000 --! |
d=000010 --! |
d=177777 --!00, 100000, 000001, 000042, 177777, 177776, 10 |
d=177776 --! |
d=000010 --! |
d=177777 --!00, 100000, 000001, 000041, 177777, 177777, 10 |
d=177777 --! |
d=000010 --! |
d=177777 --!00, 100000, 000001, 000040, 177777, 177777, 11 |
d=177777 --! |
d=000011 --! |
#37220 |
d=100000 --!00, 100000, 000001, 177737, 177777, 177777, 11!!->100000 |
d=000000 --! !!->000000 |
d=000012 --! !!11->12 |
# left shifts of positive numbers |
d=000000 --!00, 000000, 000000, 000001, 000000, 000000, 04 |
d=000000 --! |
d=000004 --! |
d=000000 --!17, 000000, 000000, 000001, 000000, 000000, 04 |
d=000000 --! |
d=000004 --! |
d=000004 --!00, 000002, 000001, 000001, 000004, 000002, 00 |
d=000002 --! |
d=000000 --! |
#37250 |
d=000005 --!00, 000002, 100000, 000001, 000005, 000000, 00 |
d=000000 --! |
d=000000 --! |
d=100000 --!00, 040000, 000000, 000001, 100000, 000000, 12 |
d=000000 --! |
d=000012 --! |
d=000000 --!00, 040000, 000000, 000002, 000000, 000000, 07 |
d=000000 --! |
d=000007 --! |
d=000000 --!00, 040000, 000000, 000003, 000000, 000000, 06 |
d=000000 --! |
d=000006 --! |
#37300 |
d=000000 --!00, 000000, 000001, 177701, 000000, 000002, 00 |
d=000002 --! |
d=000000 --! |
d=020000 --!00, 000000, 000001, 177735, 020000, 000000, 00 |
d=000000 --! |
d=000000 --! |
d=040000 --!00, 000000, 000001, 177736, 040000, 000000, 00 |
d=000000 --! |
d=000000 --! |
d=100000 --!00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!} |
d=000000 --! |
d=000012 --! |
#37330 |
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!} !!->100000 |
d=000000 --! |
d=000012 --! !!04->12 |
d=100000 --!00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!} !!->100000 |
d=000000 --! |
d=000012 --! !!04->12 |
# left shifts of negative numbers |
d=177777 --!00, 177777, 177777, 000001, 177777, 177776, 11 |
d=177776 --! |
d=000011 --! |
d=177777 --!00, 177777, 177777, 000002, 177777, 177774, 11 |
d=177774 --! |
d=000011 --! |
#37360 |
d=140000 --!00, 177777, 177777, 000036, 140000, 000000, 11 |
d=000000 --! |
d=000011 --! |
d=100000 --!00, 177777, 177777, 000037, 100000, 000000, 11 |
d=000000 --! |
d=000011 --! |
d=000000 --!00, 177777, 177776, 000037, 000000, 000000, 07 |
d=000000 --! |
d=000007 --! |
d=000000 --!00, 177777, 177774, 000037, 000000, 000000, 06 |
d=000000 --! |
d=000006 --! |
#37410 |
d=177777 --!00, 177777, 177777, 177701, 177777, 177776, 11 |
d=177776 --! |
d=000011 --! |
d=100000 --!00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!} !!->100000 |
d=000000 --! !!->00000 |
d=000011 --! |
d=140000 --!00, 177777, 177777, 001036, 140000, 000000, 11 |
d=000000 --! |
d=000011 --! |
#----------------------------------------------------------------------------- |
C Setup code 42 [base 12600] (systematic ASHC odd test) |
# |
wal 012600 -- code: |
bwm 15 |
000230 -- spl 0 |
016401 -- L1: mov 2(r4),r1 |
000002 |
011412 -- mov (r4),(r2) |
073164 -- ashc 4(r4),r1 |
000004 |
011265 -- mov (r2),2(r5) |
000002 |
#12620 |
010115 -- mov r1,(r5) |
062704 -- add #6,r4 |
000006 |
062705 -- add #4,r5 |
000004 |
077315 -- sob r3,L1 |
000000 -- halt |
# |
C Exec code 42 (systematic ASHC odd test) |
C Exec test 42.1: data adapted from ashc.s11 code of Begemot p11-2.10c |
# |
# The {} comments are original comments from Harti Brandt |
# Annotations starting with !! indicated mods for W11 |
# Note, that the W11 does not have the microcode bugs of the J11 ! |
# |
wal 036000 -- setup test vector: |
# test shift amount 0 |
bwm 165 |
000000 -- 00, 000000, 000000, 000000, 04 |
000000 -- |
000000 -- |
000017 -- 17, 000000, 000000, 000000, 04 |
000000 -- |
000000 -- |
000017 -- 17, 100001, 000000, 100001, 10 |
100001 -- |
000000 -- |
000017 -- 17, 040001, 000000, 040001, 00 |
040001 -- |
000000 -- |
000017 -- 17, 040001, 177700, 040001, 00 |
040001 -- |
177700 -- |
# right rotate positive values |
000000 -- 00, 000000, 000077, 000000, 04 |
000000 -- |
000077 -- |
000017 -- 17, 000000, 000077, 000000, 04 |
000000 -- |
000077 -- |
000000 -- 00, 000002, 000077, 000001, 00 |
000002 -- |
000077 -- |
000000 -- 00, 000001, 000077, 100000, 01 {cc is funny!} |
000001 -- |
000077 -- |
000000 -- 00, 000003, 000076, 140000, 01 |
000003 -- |
000076 -- |
000000 -- 00, 000001, 000076, 040000, 00 |
000001 -- |
000076 -- |
000000 -- 00, 040000, 000060, 040000, 00 |
040000 -- |
000060 -- |
000000 -- 00, 040000, 000043, 000002, 00 |
040000 -- |
000043 -- |
000000 -- 00, 040000, 000042, 000001, 00 |
040000 -- |
000042 -- |
000000 -- 00, 040000, 000041, 000000, 05 |
040000 -- |
000041 -- |
000000 -- 00, 040000, 000040, 000000, 04 |
040000 -- |
000040 -- |
000000 -- 00, 040000, 100037, 000000, 04 |
040000 -- |
100037 -- |
000000 -- 00, 020000, 000043, 000001, 00 |
020000 -- |
000043 -- |
000000 -- 00, 020000, 000042, 000000, 05 |
020000 -- |
000042 -- |
000000 -- 00, 020000, 000041, 000000, 04 |
020000 -- |
000041 -- |
# right rotate negative numbers |
000000 -- 00, 100002, 000077, 040001, 10 |
100002 -- |
000077 -- |
000000 -- 00, 100002, 000076, 120000, 11 |
100002 -- |
000076 -- |
000000 -- 00, 100002, 000075, 050000, 10 |
100002 -- |
000075 -- |
000000 -- 00, 100002, 000061, 000005, 10 |
100002 -- |
000061 -- |
000000 -- 00, 100002, 000060, 100002, 11 |
100002 -- |
000060 -- |
000000 -- 00, 100002, 000057, 140001, 10 |
100002 -- |
000057 -- |
000000 -- 00, 100002, 000056, 160000, 11 |
100002 -- |
000056 -- |
000000 -- 00, 100002, 000055, 170000, 10 |
100002 -- |
000055 -- |
000000 -- 00, 100002, 000042, 177776, 10 |
100002 -- |
000042 -- |
000000 -- 00, 100002, 000041, 177777, 10 |
100002 -- |
000041 -- |
000000 -- 00, 100002, 000040, 177777, 11 |
100002 -- |
000040 -- |
000000 -- 00, 100002, 040037, 177777, 11 |
100002 -- |
040037 -- |
# left rotate positive numbers |
000000 -- 00, 000000, 000001, 000000, 04 |
000000 -- |
000001 -- |
000000 -- 17, 000000, 000001, 000000, 04 |
000000 -- |
000001 -- |
000000 -- 00, 000001, 000007, 000200, 00 |
000001 -- |
000007 -- |
000000 -- 00, 000001, 000016, 040000, 00 |
000001 -- |
000016 -- |
000000 -- 00, 000001, 000017, 100000, 12 |
000001 -- |
000017 -- |
000000 -- 00, 000001, 000020, 000000, 03 |
000001 -- |
000020 -- |
000000 -- 00, 000001, 000021, 000000, 02 |
000001 -- |
000021 -- |
000000 -- 00, 000001, 000036, 000000, 02 |
000001 -- |
000036 -- |
000000 -- 00, 000001, 000037, 000000, 12 |
000001 -- |
000037 -- |
000000 -- 00, 000001, 000040, 000000, 04 {right shift!} |
000001 -- |
000040 -- |
000000 -- 00, 000001, 010037, 000000, 04 {right shift!} |
000001 -- |
010037 -- |
# left rotate negative numbers |
000000 -- 00, 100001, 000001, 000002, 03 |
100001 -- |
000001 -- |
000000 -- 00, 140001, 000001, 100002, 11 |
140001 -- |
000001 -- |
000000 -- 00, 140001, 000002, 000004, 03 |
140001 -- |
000002 -- |
000000 -- 00, 140001, 000016, 040000, 02 |
140001 -- |
000016 -- |
000000 -- 00, 140001, 000017, 100000, 12 |
140001 -- |
000017 -- |
000000 -- 00, 140001, 000020, 000000, 13 |
140001 -- |
000020 -- |
000000 -- 00, 140001, 000021, 000000, 13 |
140001 -- |
000021 -- |
000000 -- 00, 140001, 000022, 000000, 03 |
140001 -- |
000022 -- |
000000 -- 00, 140001, 000023, 000000, 02 |
140001 -- |
000023 -- |
000000 -- 00, 140002, 000035, 000000, 02 |
140002 -- |
000035 -- |
000000 -- 00, 140002, 000036, 000000, 12 |
140002 -- |
000036 -- |
000000 -- 00, 140002, 000037, 000000, 07 |
140002 -- |
000037 -- |
#---- |
wr2 177776 -- r2=177776 -> psw |
wr3 000067 -- r3=67 (55.) -> test count |
wr4 036000 -- r4=36000 -> input area |
wr5 037000 -- r5=37000 -> output area |
wsp 001400 -- sp=1400 |
stapc 012600 -- start @ 12600 |
wtgo |
rpc d=012636 -- ! pc |
rr3 d=000000 -- ! r3=0 |
rr4 d=036512 -- ! r4=36512 |
rr5 d=037334 -- ! r5=37334 |
wal 037000 -- |
# test shift amount 0 |
brm 110 |
d=000000 --!00, 000000, 000000, 000000, 04 |
d=000004 --! |
d=000000 --!17, 000000, 000000, 000000, 04 |
d=000004 --! |
d=100001 --!17, 100001, 000000, 100001, 10 |
d=000010 --! |
d=040001 --!17, 040001, 000000, 040001, 00 |
d=000000 --! |
#37020 |
d=040001 --!17, 040001, 177700, 040001, 00 |
d=000000 --! |
# right rotate positive values |
d=000000 --!00, 000000, 000077, 000000, 04 |
d=000004 --! |
d=000000 --!17, 000000, 000077, 000000, 04 |
d=000004 --! |
d=000001 --!00, 000002, 000077, 000001, 00 |
d=000000 --! |
#37040 |
d=100000 --!00, 000001, 000077, 100000, 01 {cc is funny!} |
d=000001 --! |
d=140000 --!00, 000003, 000076, 140000, 01 |
d=000001 --! |
d=040000 --!00, 000001, 000076, 040000, 00 |
d=000000 --! |
d=040000 --!00, 040000, 000060, 040000, 00 |
d=000000 --! |
#37060 |
d=000002 --!00, 040000, 000043, 000002, 00 |
d=000000 --! |
d=000001 --!00, 040000, 000042, 000001, 00 |
d=000000 --! |
d=000000 --!00, 040000, 000041, 000000, 05 |
d=000005 --! |
d=000000 --!00, 040000, 000040, 000000, 04 |
d=000004 --! |
#37100 |
d=000000 --!00, 040000, 100037, 000000, 04 |
d=000006 --! !!04->06 |
d=000001 --!00, 020000, 000043, 000001, 00 |
d=000000 --! |
d=000000 --!00, 020000, 000042, 000000, 05 |
d=000005 --! |
d=000000 --!00, 020000, 000041, 000000, 04 |
d=000004 --! |
#37120 # right rotate negative numbers |
d=040001 --!00, 100002, 000077, 040001, 10 |
d=000010 --! |
d=120000 --!00, 100002, 000076, 120000, 11 |
d=000011 --! |
d=050000 --!00, 100002, 000075, 050000, 10 |
d=000010 --! |
d=000005 --!00, 100002, 000061, 000005, 10 |
d=000010 --! |
#37140 |
d=100002 --!00, 100002, 000060, 100002, 11 |
d=000011 --! |
d=140001 --!00, 100002, 000057, 140001, 10 |
d=000010 --! |
d=160000 --!00, 100002, 000056, 160000, 11 |
d=000011 --! |
d=170000 --!00, 100002, 000055, 170000, 10 |
d=000010 --! |
#37160 |
d=177776 --!00, 100002, 000042, 177776, 10 |
d=000010 --! |
d=177777 --!00, 100002, 000041, 177777, 10 |
d=000010 --! |
d=177777 --!00, 100002, 000040, 177777, 11 |
d=000011 --! |
d=000000 --!00, 100002, 040037, 177777, 11 !!->000000 |
d=000007 --! !!11->07 |
#37200 # left rotate positive numbers |
d=000000 --!00, 000000, 000001, 000000, 04 |
d=000004 --! |
d=000000 --!17, 000000, 000001, 000000, 04 |
d=000004 --! |
d=000200 --!00, 000001, 000007, 000200, 00 |
d=000000 --! |
d=040000 --!00, 000001, 000016, 040000, 00 |
d=000000 --! |
#37220 |
d=100000 --!00, 000001, 000017, 100000, 12 |
d=000012 --! |
d=000000 --!00, 000001, 000020, 000000, 03 |
d=000003 --! |
d=000000 --!00, 000001, 000021, 000000, 02 |
d=000002 --! |
d=000000 --!00, 000001, 000036, 000000, 02 |
d=000002 --! |
#37240 |
d=000000 --!00, 000001, 000037, 000000, 12 |
d=000012 --! |
d=000000 --!00, 000001, 000040, 000000, 04 {right shift!} |
d=000004 --! |
d=000000 --!00, 000001, 010037, 000000, 04 {right shift!} |
d=000012 --! !!04->12 |
# left rotate negative numbers |
d=000002 --!00, 100001, 000001, 000002, 03 |
d=000003 --! |
#37260 |
d=100002 --!00, 140001, 000001, 100002, 11 |
d=000011 --! |
d=000004 --!00, 140001, 000002, 000004, 03 |
d=000003 --! |
d=040000 --!00, 140001, 000016, 040000, 02 |
d=000002 --! |
d=100000 --!00, 140001, 000017, 100000, 12 |
d=000012 --! |
#37300 |
d=000000 --!00, 140001, 000020, 000000, 13 |
d=000013 --! |
d=000000 --!00, 140001, 000021, 000000, 13 |
d=000013 --! |
d=000000 --!00, 140001, 000022, 000000, 03 |
d=000003 --! |
d=000000 --!00, 140001, 000023, 000000, 02 |
d=000002 --! |
#37320 |
d=000000 --!00, 140002, 000035, 000000, 02 |
d=000002 --! |
d=000000 --!00, 140002, 000036, 000000, 12 |
d=000012 --! |
d=000000 --!00, 140002, 000037, 000000, 07 |
d=000007 --! |
#----------------------------------------------------------------------------- |
C Setup code 43 [base 12700] (Begemot MARK instruction test) |
# test data and code adapted from Mark.s11 code of Begemot p11-2.10c |
# |
wal 012700 -- code test 1: (basics) |
bwm 14 |
012705 -- mov #77077,r5 ; cookie |
077077 |
010546 -- mov r5,-(sp) ; push r5 |
012746 -- mov #12,-(sp) ; parameter 1 |
000012 |
012746 -- mov #23,-(sp) ; parameter 2 |
000023 |
012746 -- mov #mark+2,-(sp) ; now the mark instruction |
#12720 |
006402 |
010605 -- mov sp,r5 ; let r5 point to mark instruction |
004737 -- jsr pc,subr ; call subroutine |
012770 |
000240 -- noop |
000000 -- halt |
#----- |
wal 012740 -- code test 2: (MARK with max. # of args) |
bwm 10 |
010546 -- mov r5, -(sp) ; push r5 |
162706 -- sub #2*77, sp ; max number |
000176 |
012746 -- mov #mark+77, -(sp) ; the mark instruction |
006477 |
010605 -- mov sp, r5 ; let r5 point to mark instruction |
004737 -- jsr pc, subr ; call subroutine |
012770 |
#12760 |
000240 -- noop |
000000 -- halt |
#----- |
wal 012770 -- code (procedure): |
wmi 000205 -- subr: rts r5 |
#----- |
C Exec code 43 (Begemot MARK test) |
C Exec test 43.1 (basics) |
# D RE RQ FU DAT |
wsp 001400 -- sp=1400 |
stapc 012700 -- start @ 12700 |
wtgo |
rpc d=012734 -- ! pc |
rr5 d=077077 -- ! r5 |
rsp d=001400 -- ! sp |
wal 001366 -- |
brm 5 |
d=012730 -- ! mem(1366) |
d=006402 -- ! mem(1370) |
d=000023 -- ! mem(1372) |
d=000012 -- ! mem(1374) |
d=077077 -- ! mem(1376) |
#---- |
C Exec test 43.2 (MARK with max. # of args) |
# D RE RQ FU DAT |
wsp 001400 -- sp=1400 |
stapc 012740 -- start @ 12740 |
wtgo |
rpc d=012764 -- ! pc |
rr5 d=077077 -- ! r5 |
rsp d=001400 -- ! sp |
#----------------------------------------------------------------------------- |
C Setup code 44 [base 13000] (Implementation variations) |
# test various PDP11 implementation variations (DCJ11 user guide, table C-1) |
# |
wal 013000 -- code: (to be single stepped mostly) |
bwm 22 |
010424 -- mov r4,(r4)+ ; case 1 and 2 |
010444 -- mov r4,-(r4) |
010764 -- mov pc,2(r4) |
000002 |
000124 -- jmp (r4)+ |
000104 -- jmp r4 |
000304 -- swab r4 |
005214 -- inc (r4) |
#13020 |
000006 -- rtt |
000000 -- halt |
000002 -- rti |
000000 -- halt |
010011 -- mov r0,(r1) |
010046 -- mov r0,-(sp) |
000114 -- jmp (r4) |
010021 -- mov r0,(r1)+ |
#13040 |
012100 -- mov (r1)+,r0 |
005221 -- inc (r1)+ |
106621 -- mtpd (r1)+ |
106506 -- mfpd sp |
106606 -- mtpd sp |
000003 -- bpt |
#----- |
wal 013070 -- code: (target for rtt,rti tests) |
bwm 2 |
000240 -- noop |
000000 -- halt |
#----- |
C Exec code 44 (Implementation variations) |
C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source |
# |
rst -- console reset |
wps 000000 -- clear psw |
wr4 001600 -- r4=1600 |
wsp 001400 -- sp=1400 |
wpc 013000 -- pc=13000 |
step -- step (mov r4,(r4)+) |
rpc d=013002 -- ! pc=13002 |
rr4 d=001602 -- ! r4=1602 |
wal 001600 -- check target location |
rmi d=001600 -- ! ; initial content of R expected for 11/70 |
# |
C test 44.2: OPR R,-(R) : decremented before {J11} or after {70} use as source |
# |
wr4 001600 -- r4=1600 |
wsp 001400 -- sp=1400 |
wpc 013002 -- pc=13002 |
step -- step (mov r4,-(r4)) |
rpc d=013004 -- ! pc=13004 |
rr4 d=001576 -- ! r4=1576 |
wal 001600 -- check target location |
rmi d=001600 -- ! ; initial content of R expected for 11/70 |
# |
C test 44.3: OPR PC,A(R) : store PC+2 {70} or PC+4 {J11} |
# |
wr4 001600 -- r4=1600 |
wsp 001400 -- sp=1400 |
wpc 013004 -- pc=13004 |
step -- step (mov pc,2(r4)) |
rpc d=013010 -- ! pc=13010 |
wal 001602 -- check target location |
rmi d=013006 -- ! ; PC+2 expected for 11/70 |
# |
C test 44.4: JMP (R)+ : R used {70;J11} or R+2 used {05,10,15,20} |
# |
wr4 013074 -- r4=13074 |
wsp 001400 -- sp=1400 |
wpc 013010 -- pc=13010 |
step -- step (jmp (r4)+) |
rpc d=013074 -- ! pc=13074 ; R expected for 11/70 |
rr4 d=013076 -- ! r4=13076 |
# |
C test 44.5: JMP R : traps to 10 {44,45,70;J11} or 4 {all others} |
C Note: J11 doc is wrong, 11/70 traps 10, not 4, as stated |
# |
wal 177766 -- clear CPUERR |
wm 000000 -- |
wr4 000000 -- r4=0 |
wsp 001400 -- sp=1400 |
wpc 013012 -- pc=13012 |
step -- step (jmp r4) [[s:2]] |
rpc d=000012 -- ! pc=12 ; trap 10 expected for 11/70 [[s:10]] |
rsp d=001374 -- ! sp=1374 |
wal 177766 -- check CPUERR |
rm d=000000 -- ! CPUERR: no bit set |
wm 000000 -- clear CPUERR |
# |
C test 44.6: SWAB does not change V {15,20} or clears V {all others} |
# |
wr4 000300 -- r4=3000 |
wsp 001400 -- sp=1400 |
wpc 013014 -- pc=13014 |
wps 000017 -- psw: set all cc flags in psw |
step -- step (swab r4) |
rpc d=013016 -- ! pc=13074 |
rr4 d=140000 -- ! r4=140000 |
rps d=000004 -- ! psw: Z=1 ; clear V expected for 11/70 |
# |
C test 44.7: CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10} |
# |
wr4 177700 -- r4=177700 |
wsp 001400 -- sp=1400 |
wpc 013016 -- pc=13016 |
step -- step (inc (r4)) [[s:2]] |
rpc d=000006 -- ! pc=6 ; trap 4 expected for 11/70 [[s:10]] |
rsp d=001374 -- ! sp=1374 |
wal 177766 -- check CPUERR |
rm d=000020 -- ! CPUERR: (iobto=1) |
wm 000000 -- clear CPUERR |
# |
C test 44.10: If RTT sets T bit, trap occurs after instr. following RTT {70,J11} |
# |
wal 001374 -- setup stack with rtt return frame setting T flag |
bwm 2 |
013070 -- start address (points to: noop, halt) |
000020 -- set T flag in PSW |
wsp 001374 -- sp=1374 |
wpc 013020 -- pc=13020 |
cont -- cont (rtt) |
wtgo |
rpc d=000020 -- ! pc=20 ; T-trap executed |
rsp d=001374 -- ! sp=1374 |
wal 001374 -- check stack |
brm 2 |
d=013072 -- trap address: address after noop expected for 11/70 |
d=000020 -- PSW |
rst -- console reset (to clear T flag) |
# |
C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11} |
# |
wal 001374 -- setup stack with rtt return frame setting T flag |
bwm 2 |
013070 -- start address (points to: noop, halt) |
000020 -- set T flag in PSW |
wsp 001374 -- sp=1374 |
wpc 013024 -- pc=13024 |
cont -- cont (rti) |
wtgo |
rpc d=000020 -- ! pc=20 ; T-trap executed |
rsp d=001374 -- ! sp=1374 |
wal 001374 -- check stack |
brm 2 |
d=013070 -- trap address: address of noop expected for 11/70 |
d=000020 -- PSW |
rst -- console reset (to clear T flag) |
# |
C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit |
# |
wr0 000030 -- r0=30 (set T bit, N also) |
wr1 177776 -- r1=177776 (PSW address) |
wsp 001400 -- sp=1400 |
wpc 013030 -- pc=13030 |
step -- step (mov r0,(r1)) |
rpc d=013032 -- ! pc=13032 |
rps d=000010 -- ! psw: T bit not set expected for 11/70 |
# |
C test 44.15: odd address using SP causes HALT {<=20} or emmergency stack {>35} |
# |
wsp 001401 -- sp=1401 |
wpc 013032 -- pc=13032 |
step -- step (mov r0,-(sp)) [[s:2]] |
rpc d=000006 -- ! pc=6 ; trap 4 [[s:13034]] |
rsp d=000000 -- ! sp=0 ; emergency stack expected for 11/70 [[s:4]] |
wal 000000 -- check emergency stack |
brm 2 |
d=013034 -- ! PC of abort [[s:0]] |
d=000000 -- ! PS of abort (currently gets lost...) |
rst -- console reset (to clear CPUERR reg) |
wal 000000 -- clean tainted memory |
bwm 2 |
000000 -- |
000000 -- |
# |
# simh notes: |
# 1. apparently not consistently implemented in simh. SP is set to 4, but |
# interrupt/trap sequence isn't executed. Effectively, simh halt's. |
# |
# for the test 28/29/30x enable MMU and make address 100000 unavailable |
# |
wal 172310 -- kernel I space DR segment 4 (base 100000) |
wmi 077400 -- slf=127; ed=0(up); acf=0 (non resident) |
# |
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40} |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr4 100000 -- r4=100000 |
wsp 001400 -- sp=1400 |
wpc 013034 -- pc=13034 |
cont -- cont (jmp (r4)) |
wtgo |
rpc d=000254 -- ! pc=254 ; trap 240 ; Note: halt is executed, was cont ! |
rsp d=001374 -- ! sp=1374 |
wal 001374 -- check stack |
brm 2 |
d=100002 -- trap address: PC inc'ed expected for 11/70 [[s:100000]] |
d=000340 -- PSW |
rst -- console reset (to clear CPUERR reg) |
# |
# simh notes: |
# 1. simh reads instruction, later increments PC. Thus PC not inc'ed in simh. |
# |
C test 44.29/30a: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} |
C test for dstw chain (mov r0,(r1)+) |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr1 100000 -- r1=100000 |
wsp 001400 -- sp=1400 |
wpc 013036 -- pc=13036 |
step -- step (mov r0,(r1)+) [[s:2]] |
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]] |
rsp d=001374 -- ! sp=1374 |
rr1 d=100002 -- ! r1=100002 |
wal 177572 -- check SSR0/1 |
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=000021 -- ! SSR1: ra=1,2 |
rst -- console reset (to clear CPUERR reg) |
# |
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} |
C test for srcr chain (mov (r1)+,r0) |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr1 100000 -- r1=100000 |
wsp 001400 -- sp=1400 |
wpc 013040 -- pc=13040 |
step -- step ((mov (r1)+,r0) [[s:2]] |
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]] |
rsp d=001374 -- ! sp=1374 |
rr1 d=100002 -- ! r1=100002 |
wal 177572 -- check SSR0/1 |
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=000021 -- ! SSR1: ra=1,2 |
rst -- console reset (to clear CPUERR reg) |
# |
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} |
C test for dstr chain (inc (r1)+) |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr1 100000 -- r1=100000 |
wsp 001400 -- sp=1400 |
wpc 013042 -- pc=13042 |
step -- step (inc (r1)+) [[s:2]] |
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]] |
rsp d=001374 -- ! sp=1374 |
rr1 d=100002 -- ! r1=100002 |
wal 177572 -- check SSR0/1 |
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=000021 -- ! SSR1: ra=1,2 |
rst -- console reset (to clear CPUERR reg) |
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44} |
C test for dsta chain (mtpd (r1)+) |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr1 100000 -- r1=100000 |
wsp 001376 -- sp=1376 |
wpc 013044 -- pc=13044 |
wal 001376 -- push a word on stack for mtpd |
wmi 123456 -- |
step -- step (mtpd (r1)+) [[s:2]] |
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]] |
rsp d=001374 -- ! sp=1374 |
rr1 d=100002 -- ! r1=100002 |
wal 177572 -- check SSR0/1 |
brm 2 |
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]] |
d=010426 -- ! SSR1: rb=1,2; ra=6,2 |
rst -- console reset (to clear CPUERR reg) |
# |
# simh notes: |
# 1. simh first pops, than writes to destination, reversing ra,rb in SSR1 |
# |
# now reset MMU to default |
# |
wal 172310 -- kernel I space DR segment 4 (base 100000) |
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w) |
# |
C test 44.39: cmode=10 will cause abort {70,J11}, treated as kmode {23,24} |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr1 001400 -- r1=1400 |
wsp 001400 -- sp=1400 |
wps 100000 -- psw: set cm=10, pm=00 |
wpc 013042 -- pc=13042 |
step -- step (inc (r1)+) [[s:2]] |
rpc d=000252 -- ! pc=252 ; trap 250; as expected for 11/70 [[s:254]] |
rsp d=001374 -- ! sp=1374 |
rr1 d=001400 -- ! r1=1400 |
wal 177572 -- check SSR0/1 |
brm 3 |
d=140101 -- ! SSR0: (abo_nr=1,abo_l=1,m=10,seg=0,ena=1) [[s:140301]] |
d=000000 -- ! SSR1: ra=none |
d=013042 -- ! SSR2: PC of failed instruction |
wal 001374 -- check stack |
brm 2 |
d=013044 -- ! PC after failed instruction [[s:013042]] |
d=100000 -- ! PS |
rst -- console reset (to clear CPUERR reg, PSW) |
# |
# simh notes: |
# 1. simh saves PC of failed instruction on stack, not PC after instruction |
# |
C test 44.43: user mode HALT: trap 4 {70} or 10 {others} |
# |
wal 177766 -- check CPUERR ;??? remove if console reset fixed |
wm 000000 -- clear |
wsp 001400 -- sp=1400 |
wps 170000 -- psw: set cm=11, pm=11 |
wpc 013022 -- pc=13022 |
step -- step (halt in user mode) [[s:2]] |
rpc d=000006 -- ! pc=6 ; trap 4; as expected for 11/70 [[s:10]] |
rsp d=001374 -- ! sp=1374 |
wal 001374 -- check stack |
brm 2 |
d=013024 -- ! PC after failed instruction |
d=170000 -- ! PS |
wal 177766 -- check CPUERR |
rm d=000200 -- ! CPUERR: (illhalt=1) |
rst -- console reset (to clear CPUERR reg, PSW) |
# |
C test 44.44: PDR bit<0> implemented {70} or not {others} |
# |
wal 172310 -- kernel I space DR, segment 4 |
wm 077401 -- set acf bit 0: slf=127; ed=0(up); acf=1 (r+trap) |
rm d=077401 -- ! check; works as expected for 11/70 |
wm 077406 -- restore: slf=127; ed=0(up); acf=6(w/r) |
# |
C test 44.45: PDR bit<7>(AIB any access) implemented {70} or not {others} |
# |
wal 172300 -- kernel I space DR, reset segment 0 and 1 |
bwm 2 |
077404 -- slf=127; ed=0(up); acf=4(w/r and trap) |
077404 -- slf=127; ed=0(up); acf=4(w/r and trap) |
wal 172300 -- check kernel I space DR, segment 0 and 1 |
brm 2 |
d=077404 -- ! |
d=077404 -- ! |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr0 123456 -- r0=123456 |
wr1 030000 -- r1=30000 |
wsp 001400 -- sp=1400 |
wpc 013030 -- pc=13030 |
step -- step (mov r0,(r1)) |
rpc d=013032 -- ! pc=next |
rsp d=001400 -- ! sp=1400 |
wal 030000 -- check target memory, untaint |
rm d=123456 -- ! |
wm 000000 -- |
wal 172300 -- check kernel I space DR, segment 0 and 1 |
brm 2 |
d=077604 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=10 (A=1,W=0) |
d=077704 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=11 (A=1,W=1) |
wal 172300 -- kernel I space DR, reset segment 0 and 1 |
bwm 2 |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
077406 -- slf=127; ed=0(up); acf=6(w/r) |
rst -- console reset (to clear CPUERR reg) |
# |
C test 44.46: Full PAR implemented {44,70,J11} or not {others} |
# |
wal 172350 -- kernel I space AR, segment 4 |
wm 177777 -- set all bits |
rm d=177777 -- ! check; works as expected for 11/70 |
wm 001000 -- restore: 1000 100000 base |
# |
C test 44.47: MMR0<9>(mmu trap) implemented {70} or not {others} |
# |
wal 177572 -- SSR0 |
wm 001000 -- set trap enable |
rm d=001000 -- ! check; works as expected for 11/70 |
wm 000000 -- restore |
# |
C test 44.48: MMR3<2:0>(D space) implemented {44,70,J11} or not {others} |
# |
wal 172516 -- SSR3 |
wm 000007 -- set D space bis |
rm d=000007 -- ! check; works as expected for 11/70 |
wm 000000 -- restore |
# |
C test 44.49: MMR3<5:4>(UMAP, 22 bit) implemented {44,70,J11} or not {others} |
# |
wal 172516 -- SSR3 |
wm 000060 -- set D space bits |
rm d=000060 -- ! check; available, as expected for 11/70 |
wm 000000 -- restore |
# |
C test 44.50: MMR3<3>(CSM enable) implemented {44,J11} or not {others} |
# |
wal 172516 -- SSR3 |
wm 000010 -- set D space bit |
rm d=000000 -- ! check; not available, as expected for 11/70 |
wm 000000 -- restore |
# |
C test 44.51: MMR2 tracks fetches {70} or instructions only {others} |
C here W11 behaves like {others}, fetches are not tracked in SSR2 |
C Also: instruction complete flag set in SSR0 after bpt. |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wsp 001400 -- sp=1400 |
wpc 013052 -- pc=13052 |
step -- step (bpt) |
rpc d=000016 -- ! pc=16; trap 14 see note [[s:13054]] |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=000000 -- ! SSR1: ra=none |
d=013052 -- ! SSR2: PC of bpt |
step -- step (halt) |
rpc d=000020 -- ! pc=20 (after halt) |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (ena=1) |
d=000000 -- ! SSR1: ra=none |
d=000016 -- ! SSR2: PC of halt |
rst -- console reset (to clear CPUERR reg, PSW) |
# |
# simh notes: |
# 1. when simh steps over a BPT,IOT,..., the PC is pointing after the |
# instruction. The trap sequence together with first instruction is |
# executed in next step. |
# |
C test 44.52: MT/FPx SP for pmode=10 unpredictable {others} / user SP {J11} |
# write registers |
# |
wr0 000001 -- set r0,..,r7 |
wr1 000101 -- |
wr2 000201 -- |
wr3 000301 -- |
wr4 000401 -- |
wr5 000501 -- |
wsp 001400 -- |
wpc 000701 -- |
# write register set 1, sm,um stack |
# |
wps 004000 -- psw: cm=kernel, set=1 |
wr0 010001 -- set r0,..,r5 [[r10]] |
wr1 010101 -- [[r11]] |
wr2 010201 -- [[r12]] |
wr3 010301 -- [[r13]] |
wr4 010401 -- [[r14]] |
wr5 010501 -- [[r15]] |
wps 044000 -- psw: cm=super(01),set=1 |
wsp 010601 -- set ssp [[ssp]] |
wps 144000 -- psw: cm=user(11),set=1 |
wsp 110601 -- set usp [[usp]] |
# |
C 52a: MFPS for pmode=10 |
# |
wps 020000 -- psw: set cm=00, pm=10 |
wpc 013046 -- pc=13046 |
step -- step (mfpd sp) |
rpc d=013050 -- ! pc=next |
rsp d=001376 -- ! sp=1376 |
wal 001376 -- check stack |
rmi d=013046 -- ! it returns PC like 11/70 unpredictable [[s:0]] |
rst -- console reset (to clear CPUERR reg) |
# |
# simh note: |
# 1. simh returns 0 here, just unpredictable in a different way ... |
# |
C 52a: MTPS for pmode=10 |
# |
wal 001376 -- setup stack with value for mtpd |
wmi 123446 -- |
wps 020000 -- psw: set cm=00, pm=10 |
wpc 013050 -- pc=13050 |
step -- step (mtpd sp) |
rpc d=013052 -- ! pc=next |
rsp d=001400 -- ! sp=1400 |
# check registers |
# |
rr0 d=000001 -- ! r0,..,r7 |
rr1 d=000101 -- ! |
rr2 d=000201 -- ! |
rr3 d=000301 -- ! |
rr4 d=000401 -- ! |
rr5 d=000501 -- ! |
# check register set 1, sm,um stack |
# |
wps 004000 -- psw: cm=kernel, set=1 |
rr0 d=010001 -- ! r0,..,r5 [[r10]] |
rr1 d=010101 -- ! [[r11]] |
rr2 d=010201 -- ! [[r12]] |
rr3 d=010301 -- ! [[r13]] |
rr4 d=010401 -- ! [[r14]] |
rr5 d=010501 -- ! [[r15]] |
wps 044000 -- psw: cm=super(01),set=1 |
rsp d=010601 -- ! ssp [[ssp]] |
wps 144000 -- psw: cm=user(11),set=1 |
rsp d=110601 -- ! usp [[usp]] |
# --> all preset values intact; -> mtpd thus noop --> like 11/70 unpredictable |
# |
rst -- console reset (to clear CPUERR reg) |
# |
# simh notes on MMR0: |
# 1. simh doesn't freeze MMR0 bit 7, the instr.compl. bit is set again after |
# executing first instruction of trap handler. |
# |
#----------------------------------------------------------------------------- |
C Setup code 45 [base 13100] (mmr1 and instructions with implicit stack push/pop |
# |
wal 013100 -- code: (to be single stepped mostly) |
bwm 5 |
106621 -- mtpd (r1)+ |
106521 -- mfpd (r1)+ |
004721 -- jsr pc,(r1)+ |
000000 -- halt |
#13110 |
000207 -- rts pc |
#----- |
C Exec code 45 (mmr1 and instructions with implicit stack push/pop) |
C test 45.1: mtpd (r1)+ |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wal 001376 -- setup stack with value for mtpd |
wmi 123456 -- |
wr1 030000 -- r1=30000 |
wsp 001376 -- sp=1376 |
wpc 013100 -- pc=13100 |
step -- step (mtpd (r1)+) |
rpc d=013102 -- ! pc=next |
rsp d=001400 -- ! sp=1400 |
rr1 d=030002 -- ! r1=30002 |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000003 -- ! SSR0: (seg=1,ena=1) |
d=010426 -- ! SSR1: rb=1,2; ra=6,2 |
d=013100 -- ! SSR2: PC of mtpd |
wal 030000 -- check target memory |
rm d=123456 -- ! |
rst -- console reset |
# |
C test 45.2: mfpd (r1)+ |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr1 030000 -- r1=30000 |
wsp 001400 -- sp=1400 |
wpc 013102 -- pc=13102 |
step -- step (mfpd (r1)+) |
rpc d=013104 -- ! pc=next |
rsp d=001376 -- ! sp=1376 |
rr1 d=030002 -- ! r1=30002 |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (seg=0,ena=1) |
d=173021 -- ! SSR1: rb=6,-2; ra=1,2 |
d=013102 -- ! SSR2: PC of mtpd |
wal 001376 -- check stack |
rmi d=123456 -- ! |
wal 030000 -- clear tainted target memory |
wm 000000 -- |
rst -- console reset |
# |
C test 45.3: jsr pc,(r1)+ and rts pc |
# |
wal 177572 -- SSR0 |
wmi 000001 -- set enable bit |
wr1 013110 -- r1=13110 |
wsp 001400 -- sp=1400 |
wpc 013104 -- pc=13104 |
step -- step (jsr pc,(r1)+) |
rpc d=013110 -- ! pc=target |
rsp d=001376 -- ! sp=1376 |
rr1 d=013112 -- ! r1=13112 |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (seg=0,ena=1) |
d=173021 -- ! SSR1: rb=6,-2; ra=1,2 |
d=013104 -- ! SSR2: PC of jsr |
wal 001376 -- check stack |
rmi d=013106 -- ! PC after jsr |
step -- step (rts pc) |
rpc d=013106 -- ! pc=target |
rsp d=001400 -- ! sp=1400 |
wal 177572 -- check SSR0/1/2 |
brm 3 |
d=000001 -- ! SSR0: (seg=0,ena=1) |
d=000026 -- ! SSR1: ra=6,2 [[s:0]] |
d=013110 -- ! SSR2: PC of rts |
rst -- console reset |
# |
# simh notes: |
# 1. simh reads stack and incremets sp later. In case of an MMU abort on |
# stack read, simh SSR1 will be 0, while W11 shows the sp increment |
# |
#----------------------------------------------------------------------------- |
C Setup code 46 [base 13200] (systematic result+cc test of 1+2op instructions) |
# the following codes expect: |
# r0-> psw |
# r1-> loop count |
# r2-> input ptr |
# r3-> output ptr |
# r4-> src reg |
# r5-> dst reg |
# |
wal 013200 -- code 1: test 1op register |
bwm 8 |
000230 -- spl 0 |
012205 -- L1: mov (r2)+,r5 ; load dst |
000000 -- halt ; ccmov set cc's |
000000 -- halt ; iut instr. under test |
011023 -- mov (r0),(r3)+ ; save psw |
010523 -- mov r5,(r3)+ ; save dst |
077106 -- sob r1,L1 (.-6) |
000000 -- halt |
#---- |
wal 013220 -- code 2: test 1op memory |
bwm 8 |
000230 -- spl 0 |
012215 -- L1: mov (r2)+,(r5) ; load dst |
000000 -- halt ; ccmov set cc's |
000000 -- halt ; iut instr. under test |
011023 -- mov (r0),(r3)+ ; save psw |
011523 -- mov (r5),(r3)+ ; save dst |
077106 -- sob r1,L1 (.-6) |
000000 -- halt |
#----- |
wal 013240 -- code 3: test 2op register |
bwm 9 |
000230 -- spl 0 |
012204 -- L1: mov (r2)+,r4 ; load src |
012205 -- mov (r2)+,r5 ; load dst |
000000 -- halt ; ccmov set cc's |
000000 -- halt ; iut instr. under test |
011023 -- mov (r0),(r3)+ ; save psw |
010523 -- mov r5,(r3)+ ; save dst |
077107 -- sob r1,L1 (.-7) |
#13260 |
000000 -- halt |
#----- |
wal 013270 -- code 4: test 2op memory |
bwm 9 |
000230 -- spl 0 |
012214 -- L1: mov (r2)+,(r4) ; load src |
012215 -- mov (r2)+,(r5) ; load dst |
000000 -- halt ; ccmov set cc's |
#13300 |
000000 -- halt ; iut instr. under test |
011023 -- mov (r0),(r3)+ ; save psw |
011523 -- mov (r5),(r3)+ ; save dst |
077107 -- sob r1,L1 (.-7) |
000000 -- halt |
#---- |
C Exec code 46 pass 1 (systematic result+cc test of 1+2op instructions; word) |
C Exec test 46.1wr: COM - reg |
# |
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst |
bwm 5 |
000000 -- com 000000 |
000001 -- com 000001 |
077777 -- com 077777 |
100000 -- com 100000 |
177777 -- com 177777 |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
005105 -- iut= com r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! com 000000 -> n1z0v0c1; 177777 |
d=177777 -- ! |
d=000011 -- ! com 000001 -> n1z0v0c1; 177776 |
d=177776 -- ! |
d=000011 -- ! com 077777 -> n1z0v0c1; 100000 |
d=100000 -- ! |
d=000001 -- ! com 100000 -> n0z0v0c1; 077777 |
d=077777 -- ! |
d=000005 -- ! com 177777 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.1wm: COM - mem |
# |
wal 013224 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
005115 -- iut= com (r5) |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! com 000000 -> n1z0v0c1; 177777 |
d=177777 -- ! |
d=000011 -- ! com 000001 -> n1z0v0c1; 177776 |
d=177776 -- ! |
d=000011 -- ! com 077777 -> n1z0v0c1; 100000 |
d=100000 -- ! |
d=000001 -- ! com 100000 -> n0z0v0c1; 077777 |
d=077777 -- ! |
d=000005 -- ! com 177777 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.2wrc0: INC - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
005205 -- iut= inc r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000000 -- ! inc 000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! inc 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000012 -- ! inc 077777 -> n1z0v1c0; 100000 |
d=100000 -- ! |
d=000010 -- ! inc 100000 -> n1z0v0c0; 100001 |
d=100001 -- ! |
d=000004 -- ! inc 177777 -> n0z1v0c0; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.2wrc1: INC - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
005205 -- iut= inc r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000001 -- ! inc 000000 -> n0z0v0c1; 000001 |
d=000001 -- ! |
d=000001 -- ! inc 000001 -> n0z0v0c1; 000002 |
d=000002 -- ! |
d=000013 -- ! inc 077777 -> n1z0v1c1; 100000 |
d=100000 -- ! |
d=000011 -- ! inc 100000 -> n1z0v0c1; 100001 |
d=100001 -- ! |
d=000005 -- ! inc 177777 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.3wrc0: DEC - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
005305 -- iut= dec r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000010 -- ! dec 000000 -> n1z0v0c0; 177777 |
d=177777 -- ! |
d=000004 -- ! dec 000001 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! dec 077777 -> n0z0v0c0; 077776 |
d=077776 -- ! |
d=000002 -- ! dec 100000 -> n0z0v1c0; 077777 |
d=077777 -- ! |
d=000010 -- ! dec 177777 -> n1z0v0c0; 177776 |
d=177776 -- ! |
#-------- |
C Exec test 46.3wrc1: DEC - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
005305 -- iut= dec r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! dec 000000 -> n1z0v0c1; 177777 |
d=177777 -- ! |
d=000005 -- ! dec 000001 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! dec 077777 -> n0z0v0c1; 077776 |
d=077776 -- ! |
d=000003 -- ! dec 100000 -> n0z0v1c1; 077777 |
d=077777 -- ! |
d=000011 -- ! dec 177777 -> n1z0v0c1; 177776 |
d=177776 -- ! |
#-------- |
C Exec test 46.4wr: NEG - reg |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
005405 -- iut= neg r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! neg 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000011 -- ! neg 000001 -> n1z0v0c1; 177777 |
d=177777 -- ! |
d=000011 -- ! neg 077777 -> n1z0v0c1; 100001 |
d=100001 -- ! |
d=000013 -- ! neg 100000 -> n1z0v1c1; 100000 |
d=100000 -- ! |
d=000001 -- ! neg 177777 -> n0z0v0c1; 000001 |
d=000001 -- ! |
#-------- |
C Exec test 46.5wrc0: ADC - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
005505 -- iut= adc r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! adc 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! adc 000001 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! adc 077777 -> n0z0v0c0; 077777 |
d=077777 -- ! |
d=000010 -- ! adc 100000 -> n1z0v0c0; 100000 |
d=100000 -- ! |
d=000010 -- ! adc 177777 -> n1z0v0c0; 177777 |
d=177777 -- ! |
#-------- |
C Exec test 46.5wrc1: ADC - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
005505 -- iut= adc r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000000 -- ! adc 000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! adc 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000012 -- ! adc 077777 -> n1z0v1c0; 100000 |
d=100000 -- ! |
d=000010 -- ! adc 100000 -> n1z0v0c0; 100001 |
d=100001 -- ! |
d=000005 -- ! adc 177777 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.6wrc0: SBC - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
005605 -- iut= sbc r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! sbc 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! sbc 000001 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077777 |
d=077777 -- ! |
d=000010 -- ! sbc 100000 -> n1z0v0c0; 100000 |
d=100000 -- ! |
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177777 |
d=177777 -- ! |
#-------- |
C Exec test 46.6wrc1: SBC - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
005605 -- iut= sbc r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! sbc 000000 -> n1z0v0c1; 177777 |
d=177777 -- ! |
d=000004 -- ! sbc 000001 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077776 |
d=077776 -- ! |
d=000002 -- ! sbc 100000 -> n0z0v1c0; 077777 |
d=077777 -- ! |
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177776 |
d=177776 -- ! |
#-------- |
C Exec test 46.7wr: TST - reg |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
005705 -- iut= tst r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! tst 000000 -> n0z1v0c0; |
d=000000 -- ! |
d=000000 -- ! tst 000001 -> n0z0v0c0; |
d=000001 -- ! |
d=000000 -- ! tst 077777 -> n0z0v0c0; |
d=077777 -- ! |
d=000010 -- ! tst 100000 -> n1z0v0c0; |
d=100000 -- ! |
d=000010 -- ! tst 177777 -> n1z0v0c0; |
d=177777 -- ! |
#-------- |
C Exec test 46.7wm: TST - mem |
# |
wal 013224 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
005715 -- iut= tst (r5) |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! tst 000000 -> n0z1v0c0; |
d=000000 -- ! |
d=000000 -- ! tst 000001 -> n0z0v0c0; |
d=000001 -- ! |
d=000000 -- ! tst 077777 -> n0z0v0c0; |
d=077777 -- ! |
d=000010 -- ! tst 100000 -> n1z0v0c0; |
d=100000 -- ! |
d=000010 -- ! tst 177777 -> n1z0v0c0; |
d=177777 -- ! |
#-------- |
C Exec test 46.8wrc0: ROR - reg, C=0 |
# |
wal 036000 -- setup test vector: for ror,rol,ars,asl |
bwm 7 |
000000 -- ror 000000 |
000001 -- ror 000001 |
100000 -- ror 100000 |
000100 -- ror 000100 |
000101 -- ror 000101 |
040100 -- ror 040100 |
100100 -- ror 100100 |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
006005 -- iut= ror r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! ror 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000007 -- ! ror 000001 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! ror 100000 -> n0z0v0c0; 040000 |
d=040000 -- ! |
d=000000 -- ! ror 000100 -> n0z0v0c0; 000040 |
d=000040 -- ! |
d=000003 -- ! ror 000101 -> n0z0v1c1; 000040 |
d=000040 -- ! |
d=000000 -- ! ror 040100 -> n0z0v0c0; 020040 |
d=020040 -- ! |
d=000000 -- ! ror 100100 -> n0z0v0c0; 040040 |
d=040040 -- ! |
#-------- |
C Exec test 46.8wrc1: ROR - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
006005 -- iut= ror r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000012 -- ! ror 000000 -> n1z0v1c0; 100000 |
d=100000 -- ! |
d=000011 -- ! ror 000001 -> n1z0v0c1; 100000 |
d=100000 -- ! |
d=000012 -- ! ror 100000 -> n1z0v1c0; 140000 |
d=140000 -- ! |
d=000012 -- ! ror 000100 -> n1z0v1c0; 100040 |
d=100040 -- ! |
d=000011 -- ! ror 000101 -> n1z0v0c1; 100040 |
d=100040 -- ! |
d=000012 -- ! ror 040100 -> n1z0v1c0; 120040 |
d=120040 -- ! |
d=000012 -- ! ror 100100 -> n1z0v1c0; 140040 |
d=140040 -- ! |
#-------- |
C Exec test 46.9wrc0: ROL - reg, C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
006105 -- iut= rol r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! rol 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! rol 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000007 -- ! rol 100000 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! rol 000100 -> n0z0v0c0; 000200 |
d=000200 -- ! |
d=000000 -- ! rol 000101 -> n0z0v0c0; 000202 |
d=000202 -- ! |
d=000012 -- ! rol 040100 -> n1z0v1c0; 100200 |
d=100200 -- ! |
d=000003 -- ! rol 100100 -> n0z0v1c1; 000200 |
d=000200 -- ! |
#-------- |
C Exec test 46.9wrc1: ROL - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
006105 -- iut= rol r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000000 -- ! rol 000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! rol 000001 -> n0z0v0c0; 000003 |
d=000003 -- ! |
d=000003 -- ! rol 100000 -> n0z0v1c1; 000001 |
d=000001 -- ! |
d=000000 -- ! rol 000100 -> n0z0v0c0; 000201 |
d=000201 -- ! |
d=000000 -- ! rol 000101 -> n0z0v0c0; 000203 |
d=000203 -- ! |
d=000012 -- ! rol 040100 -> n1z0v1c0; 100201 |
d=100201 -- ! |
d=000003 -- ! rol 100100 -> n0z0v1c1; 000201 |
d=000201 -- ! |
#-------- |
C Exec test 46.10wrc0: ASR - reg, C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
006205 -- iut= asr r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000 |
d=140000 -- ! |
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040 |
d=000040 -- ! |
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040 |
d=000040 -- ! |
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040 |
d=020040 -- ! |
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040 |
d=140040 -- ! |
#-------- |
C Exec test 46.10wrc1: ASR - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
006205 -- iut= asr r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000 |
d=140000 -- ! |
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040 |
d=000040 -- ! |
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040 |
d=000040 -- ! |
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040 |
d=020040 -- ! |
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040 |
d=140040 -- ! |
#-------- |
C Exec test 46.11wrc0: ASL - reg, C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
006305 -- iut= asl r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200 |
d=000200 -- ! |
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202 |
d=000202 -- ! |
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200 |
d=100200 -- ! |
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200 |
d=000200 -- ! |
#-------- |
C Exec test 46.11wrc1: ASL - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
006305 -- iut= asl r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200 |
d=000200 -- ! |
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202 |
d=000202 -- ! |
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200 |
d=100200 -- ! |
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200 |
d=000200 -- ! |
#-------- |
C Exec test 46.12wrc0: MOV - reg, C=0 |
# |
wal 036000 -- setup test vector: for mov |
bwm 6 |
000000 -- mov 000000,000000 |
000000 -- |
000001 -- mov 000001,000000 |
000000 -- |
100000 -- mov 100000,000000 |
000000 -- |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
010405 -- iut= mov r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000003 -- r1=3 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 6 |
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000 |
d=100000 -- ! |
#-------- |
C Exec test 46.12wrc1: MOV - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
010405 -- iut= mov r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000003 -- r1=3 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 6 |
d=000005 -- ! mov 000000,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! mov 000001,000000 -> n0z0v0c1; 000001 |
d=000001 -- ! |
d=000011 -- ! mov 100000,000000 -> n1z0v0c1; 100000 |
d=100000 -- ! |
#-------- |
C Exec test 46.12mc0: MOV - mem, C=0 |
# |
wal 013276 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
011415 -- iut= mov (r4),(r5) |
wr0 177776 -- r0=177776 |
wr1 000003 -- r1=3 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 6 |
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000 |
d=100000 -- ! |
#-------- |
C Exec test 46.13wrc0: BIT - reg, C=0 |
# |
wal 036000 -- setup test vector: for bit,bic,bis,xor |
bwm 12 |
000000 -- bit 000000,000000 |
000000 -- |
000011 -- bit 000011,000000 |
000000 -- |
000011 -- bit 000011,000110 |
000110 -- |
000011 -- bit 000011,001100 |
001100 -- |
110000 -- bit 110000,011000 |
011000 -- |
110000 -- bit 110000,110000 |
110000 -- |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
030405 -- iut= bit r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010) |
d=000110 -- ! |
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000) |
d=001100 -- ! |
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000) |
d=011000 -- ! |
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000) |
d=110000 -- ! |
#-------- |
C Exec test 46.13wrc1: BIT - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
030405 -- iut= bit r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000005 -- ! bit 000000,000000 -> n0z1v0c1; (000000) |
d=000000 -- ! |
d=000005 -- ! bit 000011,000000 -> n0z1v0c1; (000000) |
d=000000 -- ! |
d=000001 -- ! bit 000011,000110 -> n0z0v0c1; (000010) |
d=000110 -- ! |
d=000005 -- ! bit 000011,001100 -> n0z1v0c1; (000000) |
d=001100 -- ! |
d=000001 -- ! bit 110000,011000 -> n0z0v0c1; (010000) |
d=011000 -- ! |
d=000011 -- ! bit 110000,110000 -> n1z0v0c1; (100000) |
d=110000 -- ! |
#-------- |
C Exec test 46.13wmc0: BIT - mem, C=0 |
# |
wal 013276 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
031415 -- iut= bit (r4),(r5) |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010) |
d=000110 -- ! |
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000) |
d=001100 -- ! |
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000) |
d=011000 -- ! |
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000) |
d=110000 -- ! |
#-------- |
C Exec test 46.14wrc0: BIC - reg, C=0 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
040405 -- iut= bic r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100 |
d=000100 -- ! |
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100 |
d=001100 -- ! |
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000 |
d=001000 -- ! |
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.14wrc1: BIC - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
040405 -- iut= bic r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000005 -- ! bic 000000,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000005 -- ! bic 000011,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! bic 000011,000110 -> n0z0v0c1; 000100 |
d=000100 -- ! |
d=000001 -- ! bic 000011,001100 -> n0z0v0c1; 001100 |
d=001100 -- ! |
d=000001 -- ! bic 110000,011000 -> n0z0v0c1; 001000 |
d=001000 -- ! |
d=000005 -- ! bic 110000,110000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.14wrc0: BIC - mem, C=0 |
# |
wal 013276 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
041415 -- iut= bic (r4),(r5) |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100 |
d=000100 -- ! |
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100 |
d=001100 -- ! |
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000 |
d=001000 -- ! |
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.15wrc0: BIS - reg, C=0 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
050405 -- iut= bis r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bis 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! bis 000011,000000 -> n0z0v0c0; 000011 |
d=000011 -- ! |
d=000000 -- ! bis 000011,000110 -> n0z0v0c0; 000111 |
d=000111 -- ! |
d=000000 -- ! bis 000011,001100 -> n0z0v0c0; 001111 |
d=001111 -- ! |
d=000010 -- ! bis 110000,011000 -> n1z0v0c0; 111000 |
d=111000 -- ! |
d=000010 -- ! bis 110000,110000 -> n1z0v0c0; 110000 |
d=110000 -- ! |
#-------- |
C Exec test 46.15wrc1: BIS - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
050405 -- iut= bis r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000005 -- ! bis 000000,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! bis 000011,000000 -> n0z0v0c1; 000011 |
d=000011 -- ! |
d=000001 -- ! bis 000011,000110 -> n0z0v0c1; 000111 |
d=000111 -- ! |
d=000001 -- ! bis 000011,001100 -> n0z0v0c1; 001111 |
d=001111 -- ! |
d=000011 -- ! bis 110000,011000 -> n1z0v0c1; 111000 |
d=111000 -- ! |
d=000011 -- ! bis 110000,110000 -> n1z0v0c1; 110000 |
d=110000 -- ! |
#-------- |
C Exec test 46.16wrc0: XOR - reg, C=0 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
074405 -- iut= xor r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! xor 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! xor 000011,000000 -> n0z0v0c0; 000011 |
d=000011 -- ! |
d=000000 -- ! xor 000011,000110 -> n0z0v0c0; 000101 |
d=000101 -- ! |
d=000000 -- ! xor 000011,001100 -> n0z0v0c0; 001111 |
d=001111 -- ! |
d=000010 -- ! xor 110000,011000 -> n1z0v0c0; 101000 |
d=101000 -- ! |
d=000004 -- ! xor 110000,110000 -> n1z0v0c0; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.16wrc1: XOR - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
074405 -- iut= xor r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000005 -- ! xor 000000,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! xor 000011,000000 -> n0z0v0c1; 000011 |
d=000011 -- ! |
d=000001 -- ! xor 000011,000110 -> n0z0v0c1; 000101 |
d=000101 -- ! |
d=000001 -- ! xor 000011,001100 -> n0z0v0c1; 001111 |
d=001111 -- ! |
d=000011 -- ! xor 110000,011000 -> n1z0v0c1; 101000 |
d=101000 -- ! |
d=000005 -- ! xor 110000,110000 -> n1z0v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.17wr: CMP - reg |
# |
wal 036000 -- setup test vector: for cmp,add,sub |
bwm 38 |
000000 -- cmp 000000,000000 |
000000 -- |
000001 -- cmp 000001,000000 |
000000 -- |
177777 -- cmp 177777,000000 |
000000 -- |
000000 -- cmp 000000,000001 |
000001 -- |
000001 -- cmp 000001,000001 |
000001 -- |
177777 -- cmp 177777,000001 |
000001 -- |
077776 -- cmp 077776,077777 |
077777 -- |
077777 -- cmp 077777,077777 |
077777 -- |
100000 -- cmp 100000,077777 |
077777 -- |
000001 -- cmp 000001,077777 |
077777 -- |
177777 -- cmp 177777,077777 |
077777 -- |
077777 -- cmp 077777,100000 |
100000 -- |
100000 -- cmp 100000,100000 |
100000 -- |
100001 -- cmp 100001,100000 |
100000 -- |
000001 -- cmp 000001,100000 |
100000 -- |
177777 -- cmp 177777,100000 |
100000 -- |
000000 -- cmp 000000,177777 |
177777 -- |
000001 -- cmp 000001,177777 |
177777 -- |
177777 -- cmp 177777,177777 |
177777 -- |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
020405 -- iut= cmp r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000023 -- r1=23 (19.) |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned) |
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d) |
brm 38 |
d=000004 -- ! cmp 000000,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000000 -- ! cmp 000001,000000 -> n0z0v0c0; (000001) |
d=000000 -- ! |
d=000010 -- ! cmp 177777,000000 -> n1z0v0c0; (177777) |
d=000000 -- ! |
d=000011 -- ! cmp 000000,000001 -> n1z0v0c1; (177777+C) |
d=000001 -- ! |
d=000004 -- ! cmp 000001,000001 -> n0z1v0c0; (000000) |
d=000001 -- ! |
d=000010 -- ! cmp 177777,000001 -> n1z0v0c0; (177776) |
d=000001 -- ! |
d=000011 -- ! cmp 077776,077777 -> n1z0v0c1; (177777+C) |
d=077777 -- ! |
d=000004 -- ! cmp 077777,077777 -> n0z1v0c0; (000000) |
d=077777 -- ! |
d=000002 -- ! cmp 100000,077777 -> n0z0v1c0; (000001) |
d=077777 -- ! |
d=000011 -- ! cmp 000001,077777 -> n1z0v0c1; (100002+C) |
d=077777 -- ! |
d=000010 -- ! cmp 177777,077777 -> n1z0v0c0; (100000) |
d=077777 -- ! |
d=000013 -- ! cmp 077777,100000 -> n1z0v1c1; (177777+C) |
d=100000 -- ! |
d=000004 -- ! cmp 100000,100000 -> n0z1v0c0; (000000) |
d=100000 -- ! |
d=000000 -- ! cmp 100001,100000 -> n0z0v0c0; (000001) |
d=100000 -- ! |
d=000013 -- ! cmp 000001,100000 -> n1z0v1c1; (100001+C) |
d=100000 -- ! |
d=000000 -- ! cmp 177777,100000 -> n0z0v0c0; (077777) |
d=100000 -- ! |
d=000001 -- ! cmp 000000,177777 -> n0z0v0c1; (000001+C) |
d=177777 -- ! |
d=000001 -- ! cmp 000001,177777 -> n0z0v0c1; (000002+C) |
d=177777 -- ! |
d=000004 -- ! cmp 177777,177777 -> n0z1v0c0; (000000) |
d=177777 -- ! |
#-------- |
C Exec test 46.18r: ADD - reg |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
060405 -- iut= add r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000023 -- r1=23 (19.) |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V=1 if s eq d and r neq d) |
brm 38 |
d=000004 -- ! add 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! add 000001,000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000010 -- ! add 177777,000000 -> n1z0v0c0; 177777 |
d=177777 -- ! |
d=000000 -- ! add 000000,000001 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! add 000001,000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000005 -- ! add 177777,000001 -> n0z1v0c1; 000000+C |
d=000000 -- ! |
d=000012 -- ! add 077776,077777 -> n1z0v1c0; 177775 |
d=177775 -- ! |
d=000012 -- ! add 077777,077777 -> n1z0v1c0; 177776 |
d=177776 -- ! |
d=000010 -- ! add 100000,077777 -> n1z0v0c0; 177777 |
d=177777 -- ! |
d=000012 -- ! add 000001,077777 -> n1z0v1c0; 100000 |
d=100000 -- ! |
d=000001 -- ! add 177777,077777 -> n0z0v0c1; 077776+C |
d=077776 -- ! |
d=000010 -- ! add 077777,100000 -> n1z0v0c1; 177777+C |
d=177777 -- ! |
d=000007 -- ! add 100000,100000 -> n0z1v1c1; 000000+C |
d=000000 -- ! |
d=000003 -- ! add 100001,100000 -> n0z0v1c1; 000001+C |
d=000001 -- ! |
d=000010 -- ! add 000001,100000 -> n1z0v0c0; 100001 |
d=100001 -- ! |
d=000003 -- ! add 177777,100000 -> n0z0v1c1; 077777+C |
d=077777 -- ! |
d=000010 -- ! add 000000,177777 -> n1z0v0c0; 177777 |
d=177777 -- ! |
d=000005 -- ! add 000001,177777 -> n0z1v0c1; 000000+C |
d=000000 -- ! |
d=000011 -- ! add 177777,177777 -> n1z0v0c1; 177776+C |
d=177776 -- ! |
#-------- |
C Exec test 46.19r: SUB - reg |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
160405 -- iut= sub r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000023 -- r1=23 (19.) |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 (Note: C=1 if src > dst unsigned) |
wal 037000 -- check result area (Note: V=1 if s xor d and r eq s) |
brm 38 |
d=000004 -- ! sub 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000011 -- ! sub 000001,000000 -> n1z0v0c1; 177777+C |
d=177777 -- ! |
d=000001 -- ! sub 177777,000000 -> n0z0v0c1; 000001+C |
d=000001 -- ! |
d=000000 -- ! sub 000000,000001 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000004 -- ! sub 000001,000001 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000001 -- ! sub 177777,000001 -> n0z0v0c1; 000002+C |
d=000002 -- ! |
d=000000 -- ! sub 077776,077777 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000004 -- ! sub 077777,077777 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000013 -- ! sub 100000,077777 -> n1z0v1c1; 177777+C |
d=177777 -- ! |
d=000000 -- ! sub 000001,077777 -> n0z0v0c0; 077776 |
d=077776 -- ! |
d=000013 -- ! sub 177777,077777 -> n1z0v1c1; 100000+C |
d=100000 -- ! |
d=000002 -- ! sub 077777,100000 -> n0z0v1c0; 000001 |
d=000001 -- ! |
d=000004 -- ! sub 100000,100000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000011 -- ! sub 100001,100000 -> n1z0v0c1; 177777+C |
d=177777 -- ! |
d=000002 -- ! sub 000001,100000 -> n0z0v1c0; 077777 |
d=077777 -- ! |
d=000011 -- ! sub 177777,100000 -> n1z0v0c1: 100001+C |
d=100001 -- ! |
d=000010 -- ! sub 000000,177777 -> n1z0v0c0; 177777 |
d=177777 -- ! |
d=000010 -- ! sub 000001,177777 -> n1z0v0c0; 177776 |
d=177776 -- ! |
d=000004 -- ! sub 177777,177777 -> n0z1v0c0; 000000 |
d=000000 -- ! |
# |
C Exec test 46.20r: SWAP - reg |
# |
wal 036000 -- setup test vector: for swap |
bwm 9 |
000000 -- swap 000000 |
000001 -- swap 000001 |
000200 -- swap 000200 |
000400 -- swap 000400 |
100000 -- swap 100000 |
000401 -- swap 000401 |
000600 -- swap 000600 |
100001 -- swap 100001 |
100200 -- swap 100200 |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
000305 -- iut= swap r5 |
wr0 177776 -- r0=177776 |
wr1 000011 -- r1=11 (9.) |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: N,Z from lsb of result) |
brm 18 |
d=000004 -- ! swap 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000004 -- ! swap 000001 -> n0z1v0c0; 000400 |
d=000400 -- ! |
d=000004 -- ! swap 000200 -> n0z1v0c0; 100000 |
d=100000 -- ! |
d=000000 -- ! swap 000400 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000010 -- ! swap 100000 -> n1z0v0c0; 000200 |
d=000200 -- ! |
d=000000 -- ! swap 000401 -> n0z0v0c0; 000401 |
d=000401 -- ! |
d=000000 -- ! swap 000600 -> n0z0v0c0; 100001 |
d=100001 -- ! |
d=000010 -- ! swap 100001 -> n1z0v0c0; 000600 |
d=000600 -- ! |
d=000010 -- ! swap 100200 -> n1z0v0c0; 100200 |
d=100200 -- ! |
#-------- |
C Exec code 46 pass 2 (systematic result+cc test of 1+2op instructions; byte) |
C Exec test 46.1br: COMB - reg |
# |
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst (b) |
bwm 5 |
000000 -- comb 000000 |
000001 -- comb 000001 |
000177 -- comb 000177 |
000200 -- comb 000200 |
000377 -- comb 000377 |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
105105 -- iut= comb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377 |
d=000377 -- ! |
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376 |
d=000376 -- ! |
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200 |
d=000200 -- ! |
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177 |
d=000177 -- ! |
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.1bm: COMB - mem |
# |
wal 013224 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
105115 -- iut= comb (r5) |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377 |
d=000377 -- ! |
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376 |
d=000376 -- ! |
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200 |
d=000200 -- ! |
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177 |
d=000177 -- ! |
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.2brc0: INCB - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
105205 -- iut= incb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000000 -- ! incb 000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! incb 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000012 -- ! incb 000177 -> n1z0v1c0; 000200 |
d=000200 -- ! |
d=000010 -- ! incb 000200 -> n1z0v0c0; 000201 |
d=000201 -- ! |
d=000004 -- ! incb 000377 -> n0z1v0c0; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.2brc1: INCB - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
105205 -- iut= incb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000001 -- ! incb 000000 -> n0z0v0c1; 000001 |
d=000001 -- ! |
d=000001 -- ! incb 000001 -> n0z0v0c1; 000002 |
d=000002 -- ! |
d=000013 -- ! incb 000177 -> n1z0v1c1; 000200 |
d=000200 -- ! |
d=000011 -- ! incb 000200 -> n1z0v0c1; 000201 |
d=000201 -- ! |
d=000005 -- ! incb 000377 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.3brc0: DECB - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
105305 -- iut= decb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000010 -- ! decb 000000 -> n1z0v0c0; 000377 |
d=000377 -- ! |
d=000004 -- ! decb 000001 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! decb 000177 -> n0z0v0c0; 000176 |
d=000176 -- ! |
d=000002 -- ! decb 000200 -> n0z0v1c0; 000177 |
d=000177 -- ! |
d=000010 -- ! decb 000377 -> n1z0v0c0; 000376 |
d=000376 -- ! |
#-------- |
C Exec test 46.3brc1: DECB - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
105305 -- iut= decb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! decb 000000 -> n1z0v0c1; 000377 |
d=000377 -- ! |
d=000005 -- ! decb 000001 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! decb 000177 -> n0z0v0c1; 000176 |
d=000176 -- ! |
d=000003 -- ! decb 000200 -> n0z0v1c1; 000177 |
d=000177 -- ! |
d=000011 -- ! decb 000377 -> n1z0v0c1; 000376 |
d=000376 -- ! |
#-------- |
C Exec test 46.4br: NEGB - reg |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
105405 -- iut= negb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! negb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000011 -- ! negb 000001 -> n1z0v0c1; 000377 |
d=000377 -- ! |
d=000011 -- ! negb 000177 -> n1z0v0c1; 000201 |
d=000201 -- ! |
d=000013 -- ! negb 000200 -> n1z0v1c1; 000200 |
d=000200 -- ! |
d=000001 -- ! negb 000377 -> n0z0v0c1; 000001 |
d=000001 -- ! |
#-------- |
C Exec test 46.5brc0: ADCB - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
105505 -- iut= adcb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! adcb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! adcb 000177 -> n0z0v0c0; 000177 |
d=000177 -- ! |
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000200 |
d=000200 -- ! |
d=000010 -- ! adcb 000377 -> n1z0v0c0; 000377 |
d=000377 -- ! |
#-------- |
C Exec test 46.5brc1: ADCB - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
105505 -- iut= adcb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000000 -- ! adcb 000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000012 -- ! adcb 000177 -> n1z0v1c0; 000200 |
d=000200 -- ! |
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000201 |
d=000201 -- ! |
d=000005 -- ! adcb 000377 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.6brc0: SBCB - reg,C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
105605 -- iut= sbcb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! sbcb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! sbcb 000001 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000177 |
d=000177 -- ! |
d=000010 -- ! sbcb 000200 -> n1z0v0c0; 000200 |
d=000200 -- ! |
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000377 |
d=000377 -- ! |
#-------- |
C Exec test 46.6brc1: SBCB - reg,C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
105605 -- iut= sbcb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000011 -- ! sbcb 000000 -> n1z0v0c1; 000377 |
d=000377 -- ! |
d=000004 -- ! sbcb 000001 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000176 |
d=000176 -- ! |
d=000002 -- ! sbcb 000200 -> n0z0v1c0; 000177 |
d=000177 -- ! |
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000376 |
d=000376 -- ! |
#-------- |
C Exec test 46.7br: TSTB - reg |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
105705 -- iut= tstb r5 |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! tstb 000000 -> n0z1v0c0; |
d=000000 -- ! |
d=000000 -- ! tstb 000001 -> n0z0v0c0; |
d=000001 -- ! |
d=000000 -- ! tstb 000177 -> n0z0v0c0; |
d=000177 -- ! |
d=000010 -- ! tstb 000200 -> n1z0v0c0; |
d=000200 -- ! |
d=000010 -- ! tstb 000377 -> n1z0v0c0; |
d=000377 -- ! |
#-------- |
C Exec test 46.7bm: TSTB - mem |
# |
wal 013224 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
105715 -- iut= tstb (r5) |
wr0 177776 -- r0=177776 |
wr1 000005 -- r1=5 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013220 -- start @ 13220 (1op mem) |
wtgo |
rpc d=013240 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 10 |
d=000004 -- ! tstb 000000 -> n0z1v0c0; |
d=000000 -- ! |
d=000000 -- ! tstb 000001 -> n0z0v0c0; |
d=000001 -- ! |
d=000000 -- ! tstb 000177 -> n0z0v0c0; |
d=000177 -- ! |
d=000010 -- ! tstb 000200 -> n1z0v0c0; |
d=000200 -- ! |
d=000010 -- ! tstb 000377 -> n1z0v0c0; |
d=000377 -- ! |
#-------- |
C Exec test 46.8brc0: RORB - reg, C=0 |
# |
wal 036000 -- setup test vector: for ror,rol,ars,asl (b) |
bwm 7 |
000000 -- ror 000000 |
000001 -- ror 000001 |
000200 -- ror 000200 |
000010 -- ror 000010 |
000011 -- ror 000011 |
000110 -- ror 000110 |
000210 -- ror 000210 |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
106005 -- iut= rorb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! rorb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000007 -- ! rorb 000001 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! rorb 000200 -> n0z0v0c0; 000100 |
d=000100 -- ! |
d=000000 -- ! rorb 000010 -> n0z0v0c0; 000004 |
d=000004 -- ! |
d=000003 -- ! rorb 000011 -> n0z0v1c1; 000004 |
d=000004 -- ! |
d=000000 -- ! rorb 000110 -> n0z0v0c0; 000044 |
d=000044 -- ! |
d=000000 -- ! rorb 000210 -> n0z0v0c0; 000104 |
d=000104 -- ! |
#-------- |
C Exec test 46.8brc1: RORB - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
106005 -- iut= rorb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000012 -- ! rorb 000000 -> n1z0v1c0; 000200 |
d=000200 -- ! |
d=000011 -- ! rorb 000001 -> n1z0v0c1; 000200 |
d=000200 -- ! |
d=000012 -- ! rorb 000200 -> n1z0v1c0; 000300 |
d=000300 -- ! |
d=000012 -- ! rorb 000010 -> n1z0v1c0; 000204 |
d=000204 -- ! |
d=000011 -- ! rorb 000011 -> n1z0v0c1; 000204 |
d=000204 -- ! |
d=000012 -- ! rorb 000110 -> n1z0v1c0; 000244 |
d=000244 -- ! |
d=000012 -- ! rorb 000210 -> n1z0v1c0; 000304 |
d=000304 -- ! |
#-------- |
C Exec test 46.9brc0: ROLB - reg, C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
106105 -- iut= rolb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! rolb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000007 -- ! rolb 000200 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000020 |
d=000020 -- ! |
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000022 |
d=000022 -- ! |
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000220 |
d=000220 -- ! |
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000020 |
d=000020 -- ! |
#-------- |
C Exec test 46.9brc1: ROLB - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
106105 -- iut= rolb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000000 -- ! rolb 000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000003 |
d=000003 -- ! |
d=000003 -- ! rolb 000200 -> n0z0v1c1; 000001 |
d=000001 -- ! |
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000021 |
d=000021 -- ! |
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000023 |
d=000023 -- ! |
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000221 |
d=000221 -- ! |
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000021 |
d=000021 -- ! |
#-------- |
C Exec test 46.10brc0: ASRB - reg, C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
106205 -- iut= asrb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300 |
d=000300 -- ! |
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004 |
d=000004 -- ! |
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004 |
d=000004 -- ! |
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044 |
d=000044 -- ! |
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304 |
d=000304 -- ! |
#-------- |
C Exec test 46.10brc1: ASRB - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
106205 -- iut= asrb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300 |
d=000300 -- ! |
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004 |
d=000004 -- ! |
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004 |
d=000004 -- ! |
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044 |
d=000044 -- ! |
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304 |
d=000304 -- ! |
#-------- |
C Exec test 46.11brc0: ASLB - reg, C=0 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
106305 -- iut= aslb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020 |
d=000020 -- ! |
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022 |
d=000022 -- ! |
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220 |
d=000220 -- ! |
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020 |
d=000020 -- ! |
#-------- |
C Exec test 46.11brc1: ASLB - reg, C=1 |
# |
wal 013204 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
106305 -- iut= aslb r5 |
wr0 177776 -- r0=177776 |
wr1 000007 -- r1=7 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013200 -- start @ 13200 (1op reg) |
wtgo |
rpc d=013220 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area (Note: V = N xor C !) |
brm 14 |
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002 |
d=000002 -- ! |
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000 |
d=000000 -- ! |
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020 |
d=000020 -- ! |
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022 |
d=000022 -- ! |
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220 |
d=000220 -- ! |
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020 |
d=000020 -- ! |
#-------- |
C Exec test 46.12brc0: MOVB - reg, C=0 |
# |
wal 036000 -- setup test vector: for mov |
bwm 6 |
000000 -- movb 000000,000000 |
000000 -- |
000001 -- movb 000001,000000 |
000000 -- |
000200 -- movb 000200,000000 |
000000 -- |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
110405 -- iut= movb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000003 -- r1=3 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 6 |
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 177600 |
d=177600 -- ! |
#-------- |
C Exec test 46.12brc1: MOVB - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
110405 -- iut= movb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000003 -- r1=3 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 6 |
d=000005 -- ! movb 000000,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! movb 000001,000000 -> n0z0v0c1; 000001 |
d=000001 -- ! |
d=000011 -- ! movb 000200,000000 -> n1z0v0c1; 177600 |
d=177600 -- ! |
#-------- |
C Exec test 46.12bmc0: MOVB - mem, C=0 |
# |
wal 013276 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
111415 -- iut= movb (r4),(r5) |
wr0 177776 -- r0=177776 |
wr1 000003 -- r1=3 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 6 |
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001 |
d=000001 -- ! |
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 000200 |
d=000200 -- ! |
#-------- |
C Exec test 46.13brc0: BITB - reg, C=0 |
# |
wal 036000 -- setup test vector: for bit,bic,bis (b) |
bwm 12 |
000000 -- bitb 000000,000000 |
000000 -- |
000003 -- bitb 000003,000000 |
000000 -- |
000003 -- bitb 000003,000006 |
000006 -- |
000003 -- bitb 000003,000014 |
000014 -- |
000300 -- bitb 000300,000140 |
000140 -- |
000300 -- bitb 000300,000300 |
000300 -- |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
130405 -- iut= bitb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002) |
d=000006 -- ! |
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000) |
d=000014 -- ! |
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100) |
d=000140 -- ! |
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300) |
d=000300 -- ! |
#-------- |
C Exec test 46.13brc1: BITB - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
130405 -- iut= bitb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000005 -- ! bitb 000000,000000 -> n0z1v0c1; (000000) |
d=000000 -- ! |
d=000005 -- ! bitb 000003,000000 -> n0z1v0c1; (000000) |
d=000000 -- ! |
d=000001 -- ! bitb 000003,000006 -> n0z0v0c1; (000002) |
d=000006 -- ! |
d=000005 -- ! bitb 000003,000014 -> n0z1v0c1; (000000) |
d=000014 -- ! |
d=000001 -- ! bitb 000300,000140 -> n0z0v0c1; (000100) |
d=000140 -- ! |
d=000011 -- ! bitb 000300,000300 -> n1z0v0c1; (000300) |
d=000300 -- ! |
#-------- |
C Exec test 46.13bmc0: BITB - mem, C=0 |
# |
wal 013276 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
131415 -- iut= bitb (r4),(r5) |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002) |
d=000006 -- ! |
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000) |
d=000014 -- ! |
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100) |
d=000140 -- ! |
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300) |
d=000300 -- ! |
#-------- |
C Exec test 46.14brc0: BICB - reg, C=0 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
140405 -- iut= bicb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004 |
d=000004 -- ! |
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014 |
d=000014 -- ! |
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040 |
d=000040 -- ! |
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.14brc1: BICB - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
140405 -- iut= bicb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000005 -- ! bicb 000000,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000005 -- ! bicb 000003,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! bicb 000003,000006 -> n0z0v0c1; 000004 |
d=000004 -- ! |
d=000001 -- ! bicb 000003,000014 -> n0z0v0c1; 000014 |
d=000014 -- ! |
d=000001 -- ! bicb 000300,000140 -> n0z0v0c1; 000040 |
d=000040 -- ! |
d=000005 -- ! bicb 000300,000300 -> n0z1v0c1; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.14bmrc0: BICB - mem, C=0 |
# |
wal 013276 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
141415 -- iut= bicb (r4),(r5) |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 001400 -- r4=1400 |
wr5 001402 -- r5=1402 |
wsp 001400 -- sp=1400 |
stapc 013270 -- start @ 13270 (2op mem) |
wtgo |
rpc d=013312 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004 |
d=000004 -- ! |
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014 |
d=000014 -- ! |
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040 |
d=000040 -- ! |
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000 |
d=000000 -- ! |
#-------- |
C Exec test 46.15brc0: BISB - reg, C=0 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
150405 -- iut= bisb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000004 -- ! bisb 000000,000000 -> n0z1v0c0; 000000 |
d=000000 -- ! |
d=000000 -- ! bisb 000003,000000 -> n0z0v0c0; 000003 |
d=000003 -- ! |
d=000000 -- ! bisb 000003,000006 -> n0z0v0c0; 000007 |
d=000007 -- ! |
d=000000 -- ! bisb 000003,000014 -> n0z0v0c0; 000017 |
d=000017 -- ! |
d=000010 -- ! bisb 000300,000140 -> n1z0v0c0; 000340 |
d=000340 -- ! |
d=000010 -- ! bisb 000300,000300 -> n1z0v0c0; 000300 |
d=000300 -- ! |
#-------- |
C Exec test 46.15brc1: BISB - reg, C=1 |
# |
wal 013246 -- setup test instructions: |
bwm 2 |
000261 -- ccmov= sec |
150405 -- iut= bisb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000006 -- r1=6 |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 |
wal 037000 -- check result area |
brm 12 |
d=000005 -- ! bisb 000000,000000 -> n0z1v0c1; 000000 |
d=000000 -- ! |
d=000001 -- ! bisb 000003,000000 -> n0z0v0c1; 000003 |
d=000003 -- ! |
d=000001 -- ! bisb 000003,000006 -> n0z0v0c1; 000007 |
d=000007 -- ! |
d=000001 -- ! bisb 000003,000014 -> n0z0v0c1; 000017 |
d=000017 -- ! |
d=000011 -- ! bisb 000300,000140 -> n1z0v0c1; 000340 |
d=000340 -- ! |
d=000011 -- ! bisb 000300,000300 -> n1z0v0c1; 000300 |
d=000300 -- ! |
#-------- |
C Exec test 46.17br: CMPB - reg |
# |
wal 036000 -- setup test vector: for cmp (b) |
bwm 38 |
000000 -- cmpb 000000,000000 |
000000 -- |
000001 -- cmpb 000001,000000 |
000000 -- |
000377 -- cmpb 000377,000000 |
000000 -- |
000000 -- cmpb 000000,000001 |
000001 -- |
000001 -- cmpb 000001,000001 |
000001 -- |
000377 -- cmpb 000377,000001 |
000001 -- |
000176 -- cmpb 000176,000177 |
000177 -- |
000177 -- cmpb 000177,000177 |
000177 -- |
000200 -- cmpb 000200,000177 |
000177 -- |
000001 -- cmpb 000001,000177 |
000177 -- |
000377 -- cmpb 000377,000177 |
000177 -- |
000177 -- cmpb 000177,000200 |
000200 -- |
000200 -- cmpb 000200,000200 |
000200 -- |
000201 -- cmpb 000201,000200 |
000200 -- |
000001 -- cmpb 000001,000200 |
000200 -- |
000377 -- cmpb 000377,000200 |
000200 -- |
000000 -- cmpb 000000,000377 |
000377 -- |
000001 -- cmpb 000001,000377 |
000377 -- |
000377 -- cmpb 000377,000377 |
000377 -- |
wal 013246 -- setup test instructions: |
bwm 2 |
000241 -- ccmov= clc |
120405 -- iut= cmpb r4,r5 |
wr0 177776 -- r0=177776 |
wr1 000023 -- r1=23 (19.) |
wr2 036000 -- r2=36000 |
wr3 037000 -- r3=37000 |
wr4 000000 -- r4=0 |
wr5 000000 -- r5=0 |
wsp 001400 -- sp=1400 |
stapc 013240 -- start @ 13240 (2op reg) |
wtgo |
rpc d=013262 -- ! pc=halt |
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned) |
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d) |
brm 38 |
d=000004 -- ! cmpb 000000,000000 -> n0z1v0c0; (000000) |
d=000000 -- ! |
d=000000 -- ! cmpb 000001,000000 -> n0z0v0c0; (000001) |
d=000000 -- ! |
d=000010 -- ! cmpb 000377,000000 -> n1z0v0c0; (000377) |
d=000000 -- ! |
d=000011 -- ! cmpb 000000,000001 -> n1z0v0c1; (000377+C) |
d=000001 -- ! |
d=000004 -- ! cmpb 000001,000001 -> n0z1v0c0; (000000) |
d=000001 -- ! |
d=000010 -- ! cmpb 000377,000001 -> n1z0v0c0; (000376) |
d=000001 -- ! |
d=000011 -- ! cmpb 000176,000177 -> n1z0v0c1; (000377+C) |
d=000177 -- ! |
d=000004 -- ! cmpb 000177,000177 -> n0z1v0c0; (000000) |
d=000177 -- ! |
d=000002 -- ! cmpb 000200,000177 -> n0z0v1c0; (000001) |
d=000177 -- ! |
d=000011 -- ! cmpb 000001,000177 -> n1z0v0c1; (000202+C) |
d=000177 -- ! |
d=000010 -- ! cmpb 000377,000177 -> n1z0v0c0; (000200) |
d=000177 -- ! |
d=000013 -- ! cmpb 000177,000200 -> n1z0v1c1; (000377+C) |
d=000200 -- ! |
d=000004 -- ! cmpb 000200,000200 -> n0z1v0c0; (000000) |
d=000200 -- ! |
d=000000 -- ! cmpb 000201,000200 -> n0z0v0c0; (000001) |
d=000200 -- ! |
d=000013 -- ! cmpb 000001,000200 -> n1z0v1c1; (000201+C) |
d=000200 -- ! |
d=000000 -- ! cmpb 000377,000200 -> n0z0v0c0; (000177) |
d=000200 -- ! |
d=000001 -- ! cmpb 000000,000377 -> n0z0v0c1; (000001+C) |
d=000377 -- ! |
d=000001 -- ! cmpb 000001,000377 -> n0z0v0c1; (000002+C) |
d=000377 -- ! |
d=000004 -- ! cmpb 000377,000377 -> n0z1v0c0; (000000) |
d=000377 -- ! |
#----------------------------------------------------------------------------- |
C Setup code 47 [base 13400] (pipeline torture tests) |
# |
wal 013400 -- data: |
wmi 000077 -- marker |
wal 013402 -- code 1: |
bwm 13 |
016727 -- mov -6(pc),(pc)+ ; |
177772 |
000000 -- halt ; will be overwritten |
016737 -- mov -10(pc),@(pc)+ ; |
177770 |
013400 |
005200 -- inc r0 ; |
#13420 |
010317 -- mov r3,(pc) ; will overwrite next instruction |
000000 -- halt ; will be overwritten |
005200 -- inc r0 ; |
010447 -- mov r4,-(pc) ; will overwrite itself |
005200 -- inc r0 ; |
000000 -- halt ; |
# |
wal 013440 -- code 2: (pipeline tester adapted from KDJ11A.MAC) |
bwm 15 |
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop |
000240 -- nop |
000111 -- jmp (r1) |
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop |
000240 -- nop |
000111 -- jmp (r1) |
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop |
000240 -- nop |
#13460 |
000111 -- jmp (r1) |
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop |
000240 -- nop |
000111 -- jmp (r1) |
000000 -- halt ; should halt here ! |
000000 -- halt ; |
000000 -- halt ; should not jmp here ! |
# |
C Exec code 47 (pipeline torture tests) |
C Exec test 47.1 (some self-modifying code, use (pc)+, (pc), -(pc)): |
# |
wr0 000000 -- r0=0 |
wr1 000000 -- r1=0 |
wr2 000000 -- r2=0 |
wr3 005201 -- r3= inc r1 |
wr4 005202 -- r4= inc r2 |
stapc 013402 -- start @ 13402 |
wtgo |
rpc d=013434 -- ! pc |
rr0 d=000003 -- ! r0 |
rr1 d=000001 -- ! r1 |
rr2 d=000001 -- ! r2 |
rr3 d=005201 -- ! r3 |
rr4 d=005202 -- ! r4 |
# |
wal 013400 -- check data area: |
rmi d=177772 -- ! new marker ; written by mov -10(pc),@(pc)+ |
wal 013402 -- check code area: |
brm 13 |
d=016727 -- ! mov -6(pc),(pc)+ ; |
d=177772 -- ! |
d=000077 -- ! ; written by mov -6(pc),(pc)+ |
d=016737 -- ! mov -10(pc),@(pc)+; |
d=177770 -- ! |
d=013400 -- ! |
d=005200 -- ! inc r0 ; |
#13320 |
d=010317 -- ! mov r3,(pc) ; |
d=005201 -- ! inc r1 ; written by mov r3,(pc); executed |
d=005200 -- ! inc r0 ; |
d=005202 -- ! inc r2 ; written by mov r4,-(pc); executed |
d=005200 -- ! inc r0 ; |
d=000000 -- ! halt ; |
# |
C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70) |
# |
wr1 013474 -- r1=13474 (alternate halt) |
stapc 013440 -- start @ 13440 |
wtgo |
rpc d=013472 -- ! pc |
wal 013440 -- check code area: |
brm 13 |
d=012717 -- ! mov (pc)+,(pc) ; |
d=000240 -- ! nop |
d=000240 -- ! nop ; written; executed |
d=012717 -- ! mov (pc)+,(pc) ; |
d=000240 -- ! nop |
d=000240 -- ! nop ; written; executed |
d=012717 -- ! mov (pc)+,(pc) ; |
d=000240 -- ! nop |
#13360 |
d=000240 -- ! nop ; written; executed |
d=012717 -- ! mov (pc)+,(pc) ; |
d=000240 -- ! nop |
d=000240 -- ! nop ; written; executed |
d=000000 -- ! halt ; |
#----------------------------------------------------------------------------- |
C Setup code 50 [base 13500] (check that all reserved instructions trap to 10) |
# |
wal 013500 -- code (to be single stepped...) |
bwm 17 |
000007 -- 000007 |
000010 -- 000010-000077 |
000077 -- |
000210 -- 000210-000227 |
000227 -- |
007000 -- 007000-007777 |
007777 -- |
075000 -- 075000-076777 |
#13420 |
076777 -- |
106400 -- 106400-106477 |
106477 -- |
106700 -- 106700-106777 |
106777 -- |
107000 -- 107000-107777 |
107777 -- |
170000 -- 170000-177777 (no FPU) |
#13440 |
177777 -- |
# |
C Exec code 50 (check that all reserved instructions trap to 10) |
C Test odd address abort |
# |
rst -- console reset |
wps 000000 -- clear psw |
wal 001374 -- clean stack |
bwm 2 |
000000 -- |
000000 -- |
wsp 001400 -- sp=1400 |
wpc 013500 -- pc=13500 |
step -- step (000007): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013502 -- pc=13502 |
step -- step (000010): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013504 -- pc=13504 |
step -- step (000077): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013506 -- pc=13506 |
step -- step (000210): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013510 -- pc=13510 |
step -- step (000227): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013512 -- pc=13512 |
step -- step (007000): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013514 -- pc=13514 |
step -- step (007777): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013516 -- pc=13516 |
step -- step (075000): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013520 -- pc=13520 |
step -- step (076777): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013522 -- pc=13522 |
step -- step (106400): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013524 -- pc=13524 |
step -- step (106477): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013526 -- pc=13526 |
step -- step (106700): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013530 -- pc=13530 |
step -- step (106777): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013532 -- pc=13532 |
step -- step (107000): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013534 -- pc=13534 |
step -- step (107777): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013536 -- pc=13536 |
step -- step (170000): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
# |
wsp 001400 -- sp=1400 |
wpc 013540 -- pc=13540 |
step -- step (177777): trap 10 [[s:2]] |
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]] |
rsp d=001374 -- ! sp=1374 |
#----------------------------------------------------------------------------- |
# |
C Verify trap catchers integrity |
# |
wal 000004 -- vectors: 4...34 (trap catcher) |
brm 14 |
d=000006 -- ! PC:06 ; vector 4 |
d=000000 -- ! PS:0 |
d=000012 -- ! PC:12 ; vector 10 |
d=000000 -- ! PS:0 |
d=000016 -- ! PC:16 ; vector 14 (T bit; BPT) |
d=000000 -- ! PS:0 |
d=000022 -- ! PC:22 ; vector 20 (IOT) |
d=000000 -- ! PS:0 |
d=000026 -- ! PC:26 ; vector 24 (Power fail, not used) |
d=000000 -- ! PS:0 |
d=000032 -- ! PC:32 ; vector 30 (EMT) |
d=000000 -- ! PS:0 |
d=000036 -- ! PC:36 ; vector 34 (TRAP) |
d=000000 -- ! PS:0 |
wal 000240 -- vectors: 240,244,250 (trap catcher) |
brm 6 |
d=000242 -- ! PC:242 ; vector 240 (PIRQ) |
d=000000 -- ! PS:0 |
d=000246 -- ! PC:246 ; vector 244 (FPU) |
d=000000 -- ! PS:0 |
d=000252 -- ! PC:252 ; vector 250 (MMU) |
d=000000 -- ! PS:0 |
# |
C Verify setup MMU |
# to avoid seeing AIB bits: |
# 1. check ARs; 2. re-write ARs to clear AIBs in DRs; 3. check DRs |
# |
wal 172340 -- kernel I space AR |
brm 8 |
d=000000 -- ! 0 |
d=000200 -- ! 200 020000 base |
d=000400 -- ! 400 040000 base |
d=000600 -- ! 600 060000 base |
d=001000 -- ! 1000 100000 base |
d=001200 -- ! 1200 120000 base |
d=001400 -- ! 1400 140000 base |
d=177600 -- !176000 (map to I/O page) |
# |
wal 172340 -- kernel I space AR |
bwm 8 |
000000 -- 0 |
000200 -- 200 020000 base |
000400 -- 400 040000 base |
000600 -- 600 060000 base |
001000 -- 1000 100000 base |
001200 -- 1200 120000 base |
001400 -- 1400 140000 base |
177600 -- 176000 (map to I/O page) |
# |
wal 172300 -- kernel I space DR |
brm 8 |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r) |
# |
wal 000000 -- last cmd shouldn't be 21 or 23 ... |
/tb/Makefile
0,0 → 1,67
# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2014-07-27 545 1.4.1 make reference board configurable via XTW_BOARD |
# 2011-08-13 405 1.4 use includes from rtl/make |
# 2010-12-30 351 1.3 retire tb_rripdp_pdp11core tb_rriext_pdp11core |
# 2009-11-22 252 1.2 add ISim support |
# 2007-09-16 83 1.1.1 add include *.o.dep_ghdl |
# 2007-07-06 64 1.1 use vbom's |
# 2007-06-17 58 1.0 Initial version |
# |
EXE_all = tb_pdp11core |
# |
# default reference board for test synthesis is Spartan-6 based Nexys3 |
ifndef XTW_BOARD |
XTW_BOARD=nexys3 |
endif |
include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk |
|
# |
.PHONY : all all_ssim all_tsim clean |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
all_tsim : $(EXE_all:=_tsim) |
# |
clean : ise_clean ghdl_clean isim_clean |
# |
#----- |
# |
include $(RETROBASE)/rtl/make/generic_ghdl.mk |
include $(RETROBASE)/rtl/make/generic_isim.mk |
include $(RETROBASE)/rtl/make/generic_xflow.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_isim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
#----- |
# time ~/misc_walter/p11_util/bin/pdp11 $*.scmd > $*.simh_raw_log |
%.simh_log: %.dat |
tbdat2simh $*.dat > $*.scmd |
time pdp11 $*.scmd > $*.simh_raw_log |
simdat_check $*.simh_raw_log > $*.simh_log |
grep FAIL $*.simh_log |
|
check_dsim: tb_pdp11core tb_pdp11core_stim.dat |
time tbw tb_pdp11core |\ |
tee tb_pdp11core_dsim.log |\ |
egrep "(FAIL|DONE)" || true |
@ echo "# diff to reference" |
diff tb_pdp11core_out_ref.dat tb_pdp11core_dsim.log |
|
check_ssim: tb_pdp11core_ssim tb_pdp11core_stim.dat |
time tbw tb_pdp11core_ssim |\ |
tee tb_pdp11core_ssim.log |\ |
egrep "(FAIL|DONE)" || true |
@ echo "# diff to reference" |
diff tb_pdp11core_out_ref.dat tb_pdp11core_ssim.log |
|
check_simh: tb_pdp11core_stim.simh_log |
/tb/tb_pdp11core.vhd
0,0 → 1,676
-- $Id: tb_pdp11core.vhd 444 2011-12-25 10:04:58Z mueller $ |
-- |
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tb_pdp11core - sim |
-- Description: Test bench for pdp11_core |
-- |
-- Dependencies: simlib/simclk |
-- tbd_pdp11core [UUT] |
-- pdp11_intmap |
-- |
-- To test: pdp11_core |
-- |
-- Target Devices: generic |
-- Tool versions: ghdl 0.18-0.29; ISim 11.3 |
-- |
-- Verified (with tb_pdp11core_stim.dat): |
-- Date Rev Code ghdl ise Target Comment |
-- 2010-12-30 351 - 0.29 - - u:ok |
-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok |
-- 2010-06-20 308 - 0.29 - - u:ok |
-- 2009-11-22 252 - 0.26 - - u:ok |
-- 2007-12-30 107 - 0.25 - - u:ok |
-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl |
-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!) |
-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!) |
-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!) |
-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok |
-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok |
-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok |
-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok |
-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok |
-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok |
-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack |
-- 2007-10-07 88 - 0.26 - - c:ok |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-12-23 444 1.4 use new simclk/simclkcnt |
-- 2011-11-18 427 1.3.2 now numeric_std clean |
-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon |
-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core |
-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses |
-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface |
-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old |
-- 'sta' behaviour with new 'stapc' command; rename |
-- lal,lah -> wal,wah and implement locally; new |
-- output format with cpfunc name |
-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon |
-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_ |
-- 2009-11-28 253 1.1.12 add hack for ISim 11.3 |
-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits) |
-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command |
-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust |
-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail |
-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now |
-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits |
-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for |
-- command completion, wtgo waits for CPU to halt. |
-- added .cerr,.merr directive, check cmd(m)err state |
-- added .sdef as ignored directive |
-- 2008-02-24 119 1.1.4 added lah,rps,wps command |
-- 2008-01-26 114 1.1.3 add handling of d=val,msk |
-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core |
-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution |
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned |
-- 2007-09-02 79 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.simbus.all; |
use work.pdp11_sim.all; |
use work.pdp11.all; |
|
entity tb_pdp11core is |
end tb_pdp11core; |
|
architecture sim of tb_pdp11core is |
|
signal CLK : slbit := '0'; |
signal RESET : slbit := '0'; |
signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy |
signal CP_CNTL_req : slbit := '0'; |
signal CP_CNTL_func : slv5 := (others=>'0'); |
signal CP_CNTL_rnum : slv3 := (others=>'0'); |
signal CP_ADDR_addr : slv22_1 := (others=>'0'); |
signal CP_ADDR_racc : slbit := '0'; |
signal CP_ADDR_be : slv2 := "11"; |
signal CP_ADDR_ena_22bit : slbit := '0'; |
signal CP_ADDR_ena_ubmap : slbit := '0'; |
signal CP_DIN : slv16 := (others=>'0'); |
signal CP_STAT_cmdbusy : slbit := '0'; |
signal CP_STAT_cmdack : slbit := '0'; |
signal CP_STAT_cmderr : slbit := '0'; |
signal CP_STAT_cmdmerr : slbit := '0'; |
signal CP_STAT_cpugo : slbit := '0'; |
signal CP_STAT_cpustep : slbit := '0'; |
signal CP_STAT_cpuhalt : slbit := '0'; |
signal CP_STAT_cpurust : slv4 := (others=>'0'); |
signal CP_DOUT : slv16 := (others=>'0'); |
|
signal CLK_STOP : slbit := '0'; |
signal CLK_CYCLE : integer := 0; |
|
signal R_CHKDAT : slv16 := (others=>'0'); |
signal R_CHKMSK : slv16 := (others=>'0'); |
signal R_CHKREQ : slbit := '0'; |
|
signal R_WAITCMD : slbit := '0'; |
signal R_WAITSTEP : slbit := '0'; |
signal R_WAITGO : slbit := '0'; |
signal R_WAITOK : slbit := '0'; |
signal R_CP_STAT : cp_stat_type := cp_stat_init; |
signal R_CP_DOUT : slv16 := (others=>'0'); |
|
begin |
|
CLKGEN : simclk |
generic map ( |
PERIOD => clock_period, |
OFFSET => clock_offset) |
port map ( |
CLK => CLK, |
CLK_STOP => CLK_STOP |
); |
|
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); |
|
UUT: entity work.tbd_pdp11core |
port map ( |
CLK => CLK, |
RESET => RESET, |
CP_CNTL_req => CP_CNTL_req, |
CP_CNTL_func => CP_CNTL_func, |
CP_CNTL_rnum => CP_CNTL_rnum, |
CP_ADDR_addr => CP_ADDR_addr, |
CP_ADDR_racc => CP_ADDR_racc, |
CP_ADDR_be => CP_ADDR_be, |
CP_ADDR_ena_22bit => CP_ADDR_ena_22bit, |
CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap, |
CP_DIN => CP_DIN, |
CP_STAT_cmdbusy => CP_STAT_cmdbusy, |
CP_STAT_cmdack => CP_STAT_cmdack, |
CP_STAT_cmderr => CP_STAT_cmderr, |
CP_STAT_cmdmerr => CP_STAT_cmdmerr, |
CP_STAT_cpugo => CP_STAT_cpugo, |
CP_STAT_cpustep => CP_STAT_cpustep, |
CP_STAT_cpuhalt => CP_STAT_cpuhalt, |
CP_STAT_cpurust => CP_STAT_cpurust, |
CP_DOUT => CP_DOUT |
); |
|
proc_stim: process |
file ifile : text open read_mode is "tb_pdp11core_stim"; |
variable iline : line; |
variable oline : line; |
variable idelta : integer := 0; |
variable idummy : integer := 0; |
variable dcycle : integer := 0; |
variable irqline : integer := 0; |
variable ireq : boolean := false; |
variable ifunc : slv5 := (others=>'0'); |
variable irnum : slv3 := (others=>'0'); |
variable idin : slv16 := (others=>'0'); |
variable imsk : slv16 := (others=>'1'); |
variable ichk : boolean := false; |
variable idosta: slbit := '0'; |
|
variable ok : boolean; |
variable dname : string(1 to 6) := (others=>' '); |
variable rind : integer := 0; |
variable nblk : integer := 0; |
variable xmicmd : string(1 to 3) := (others=>' '); |
variable iwtstp : boolean := false; |
variable iwtgo : boolean := false; |
variable icerr : integer := 0; |
variable imerr : integer := 0; |
variable to_cmd : integer := 50; |
variable to_stp : integer := 100; |
variable to_go : integer := 5000; |
variable ien : slbit := '0'; |
variable ibit : integer := 0; |
variable imemi : boolean := false; |
variable ioff : slv6 := (others=>'0'); |
variable idoibr : boolean := false; |
|
variable r_addr : slv22_1 := (others=>'0'); |
variable r_ena_22bit : slbit := '0'; |
variable r_ena_ubmap : slbit := '0'; |
variable r_ibrbase : slv(c_ibrb_ibf_base) := (others=>'0'); |
variable r_ibrbe : slv2 := (others=>'0'); |
|
|
begin |
|
SB_CNTL <= (others=>'L'); |
|
wait for clock_offset - setup_time; |
|
RESET <= '1'; |
wait for clock_period; |
|
RESET <= '0'; |
wait for 9*clock_period; |
|
file_loop: while not endfile(ifile) loop |
|
-- this logic is a quick hack to implement the 'stapc' command |
if idosta = '0' then |
readline (ifile, iline); |
|
iwtstp := false; |
iwtgo := false; |
|
if nblk>0 and -- outstanding [rw]mi lines ? |
iline'length>=3 and -- and 3 leading blanks |
iline(iline'left to iline'left+2)=" " then |
nblk := nblk - 1; -- than fill [rw]mi command in again |
iline(iline'left to iline'left+2) := xmicmd; |
end if; |
|
readcomment(iline, ok); |
next file_loop when ok; |
|
readword(iline, dname, ok); |
|
else |
idosta := '0'; |
dname := "sta "; |
ok := true; |
end if; |
|
if ok then |
|
case dname is |
when "rsp " => dname := "rr6 "; -- rsp -> rr6 |
when "rpc " => dname := "rr7 "; -- rpc -> rr7 |
when "wsp " => dname := "wr6 "; -- wsp -> wr6 |
when "wpc " => dname := "wr7 "; -- wpc -> wr7 |
when others => null; |
end case; |
|
rind := character'pos(dname(3)) - character'pos('0'); |
|
if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7] |
dname(2)='r' and |
(rind>=0 and rind<=7) then |
dname(3) := '|'; -- replace with [rw]r| |
end if; |
|
if dname(1) = '.' then |
case dname is |
when ".mode " => -- .mode |
readword_ea(iline, dname); |
assert dname="pdpcp " |
report "assert .mode == pdpcp" severity failure; |
|
when ".reset" => -- .reset |
write(oline, string'(".reset")); |
writeline(output, oline); |
RESET <= '1'; |
wait for clock_period; |
|
RESET <= '0'; |
wait for 9*clock_period; |
|
when ".wait " => -- .wait |
read_ea(iline, idelta); |
wait for idelta*clock_period; |
|
when ".tocmd" => -- .tocmd |
read_ea(iline, idelta); |
to_cmd := idelta; |
|
when ".tostp" => -- .tostp |
read_ea(iline, idelta); |
to_stp := idelta; |
|
when ".togo " => -- .togo |
read_ea(iline, idelta); |
to_go := idelta; |
|
when ".sdef " => -- .sdef (ignore it) |
readempty(iline); |
|
when ".cerr " => -- .cerr |
read_ea(iline, icerr); |
when ".merr " => -- .merr |
read_ea(iline, imerr); |
|
when ".anena" => -- .anena (ignore it) |
readempty(iline); |
when ".rlmon" => -- .rlmon (ignore it) |
readempty(iline); |
when ".rbmon" => -- .rbmon (ignore it) |
readempty(iline); |
|
when ".scntl" => -- .scntl |
read_ea(iline, ibit); |
read_ea(iline, ien); |
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high) |
report "assert bit number in range of SB_CNTL" |
severity failure; |
if ien = '1' then |
SB_CNTL(ibit) <= 'H'; |
else |
SB_CNTL(ibit) <= 'L'; |
end if; |
|
when others => -- bad directive |
write(oline, string'("?? unknown directive: ")); |
write(oline, dname); |
writeline(output, oline); |
report "aborting" severity failure; |
end case; |
|
testempty_ea(iline); |
next file_loop; |
|
else |
|
ireq := true; |
ifunc := c_cpfunc_noop; |
irnum := "000"; |
ichk := false; |
idin := (others=>'0'); |
imsk := (others=>'1'); |
imemi := false; |
idoibr := false; |
|
case dname is |
when "brm " => -- brm |
read_ea(iline, nblk); |
xmicmd := "rmi"; |
next file_loop; |
when "bwm " => -- bwm |
read_ea(iline, nblk); |
xmicmd := "wmi"; |
next file_loop; |
|
when "rr| " => -- rr[0-7] |
ifunc := c_cpfunc_rreg; |
irnum := slv(to_unsigned(rind, 3)); |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8); |
|
when "wr| " => -- wr[0-7] |
ifunc := c_cpfunc_wreg; |
irnum := slv(to_unsigned(rind, 3)); |
readoct_ea(iline, idin); |
|
-- Note: there are no field definitions for wal, wah, wibrb because |
-- there is no corresponding cp command. Therefore the |
-- rbus field definitions are used here |
when "wal " => -- wal |
readoct_ea(iline, idin); |
r_addr := (others=>'0'); -- write to al clears ah !! |
r_ena_22bit := '0'; |
r_ena_ubmap := '0'; |
r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr); |
testempty_ea(iline); |
next file_loop; |
|
when "wah " => -- wah |
readoct_ea(iline, idin); |
r_addr(21 downto 16) := idin(c_ah_rbf_addr); |
r_ena_22bit := idin(c_ah_rbf_ena_22bit); |
r_ena_ubmap := idin(c_ah_rbf_ena_ubmap); |
testempty_ea(iline); |
next file_loop; |
|
when "wibrb " => -- wibrb |
readoct_ea(iline, idin); |
r_ibrbase := idin(c_ibrb_ibf_base); |
if idin(c_ibrb_ibf_be) /= "00" then |
r_ibrbe := idin(c_ibrb_ibf_be); |
else |
r_ibrbe := "11"; |
end if; |
testempty_ea(iline); |
next file_loop; |
|
when "rm " => -- rm |
ifunc := c_cpfunc_rmem; |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8); |
when "rmi " => -- rmi |
ifunc := c_cpfunc_rmem; |
imemi := true; |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8); |
|
when "wm " => -- wm |
ifunc := c_cpfunc_wmem; |
readoct_ea(iline, idin); |
when "wmi " => -- wmi |
ifunc := c_cpfunc_wmem; |
imemi := true; |
readoct_ea(iline, idin); |
|
when "ribr " => -- ribr |
ifunc := c_cpfunc_rmem; |
idoibr := true; |
readoct_ea(iline, ioff); |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8); |
when "wibr " => -- wibr |
ifunc := c_cpfunc_wmem; |
idoibr := true; |
readoct_ea(iline, ioff); |
readoct_ea(iline, idin); |
|
when "rps " => -- rps |
ifunc := c_cpfunc_rpsw; |
readtagval2_ea(iline, "d", ichk, idin, imsk, 8); |
when "wps " => -- wps |
ifunc := c_cpfunc_wpsw; |
readoct_ea(iline, idin); |
|
-- Note: in old version 'sta addr' was an atomic operation, loading |
-- the pc and starting the cpu. Now this is action is two step |
-- first a wpc followed by a 'sta'. |
when "stapc " => -- stapc |
ifunc := c_cpfunc_wreg; |
irnum := c_gpr_pc; |
readoct_ea(iline, idin); |
idosta := '1'; -- request 'sta' to be done next |
|
when "sta " => -- sta |
ifunc := c_cpfunc_sta; |
when "sto " => -- sto |
ifunc := c_cpfunc_sto; |
when "cont " => -- cont |
ifunc := c_cpfunc_cont; |
when "step " => -- step |
ifunc := c_cpfunc_step; |
iwtstp := true; |
when "rst " => -- rst |
ifunc := c_cpfunc_rst; |
|
when "wtgo " => -- wtgo |
iwtgo := true; |
ireq := false; -- no cp request ! |
|
when "wtlam " => -- wtlam (ignore it) |
readempty(iline); |
next file_loop; |
|
when others => -- bad directive |
write(oline, string'("?? unknown directive: ")); |
write(oline, dname); |
writeline(output, oline); |
report "aborting" severity failure; |
end case; |
|
end if; |
testempty_ea(iline); |
|
end if; |
|
if idoibr then |
CP_ADDR_addr(15 downto 13) <= "111"; |
CP_ADDR_addr(c_ibrb_ibf_base) <= r_ibrbase; |
CP_ADDR_addr(5 downto 1) <= ioff(5 downto 1); |
CP_ADDR_racc <= '1'; |
CP_ADDR_be <= r_ibrbe; |
CP_ADDR_ena_22bit <= '0'; |
CP_ADDR_ena_ubmap <= '0'; |
else |
CP_ADDR_addr <= r_addr; |
CP_ADDR_racc <= '0'; |
CP_ADDR_be <= "11"; |
CP_ADDR_ena_22bit <= r_ena_22bit; |
CP_ADDR_ena_ubmap <= r_ena_ubmap; |
end if; |
|
if ireq then |
CP_CNTL_req <= '1'; |
CP_CNTL_func <= ifunc; |
CP_CNTL_rnum <= irnum; |
end if; |
|
if ichk then |
CP_DIN <= (others=>'0'); |
R_CHKDAT <= idin; |
R_CHKMSK <= imsk; |
R_CHKREQ <= '1'; |
else |
CP_DIN <= idin; |
R_CHKREQ <= '0'; |
end if; |
|
R_WAITCMD <= '0'; |
R_WAITSTEP <= '0'; |
R_WAITGO <= '0'; |
if iwtgo then |
idelta := to_go; |
R_WAITGO <= '1'; |
elsif iwtstp then |
idelta := to_stp; |
R_WAITSTEP <= '1'; |
else |
idelta := to_cmd; |
R_WAITCMD <= '1'; |
end if; |
|
wait for clock_period; |
CP_CNTL_req <= '0'; |
|
dcycle := 1; |
while idelta>0 and R_WAITOK='0' loop |
wait for clock_period; |
dcycle := dcycle + 1; |
idelta := idelta - 1; |
end loop; |
|
if imemi then -- rmi or wmi seen ? then inc ar |
r_addr := slv(unsigned(r_addr) + 1); |
end if; |
|
write(oline, dcycle, right, 4); |
write(oline, string'(" ")); |
if ireq then |
case ifunc is |
when c_cpfunc_rreg => write(oline, string'("rreg")); |
when c_cpfunc_wreg => write(oline, string'("wreg")); |
when c_cpfunc_rpsw => write(oline, string'("rpsw")); |
when c_cpfunc_wpsw => write(oline, string'("wpsw")); |
when c_cpfunc_rmem => |
if idoibr then |
write(oline, string'("ribr")); |
else |
write(oline, string'("rmem")); |
end if; |
when c_cpfunc_wmem => |
if idoibr then |
write(oline, string'("wibr")); |
else |
write(oline, string'("wmem")); |
end if; |
when c_cpfunc_sta => write(oline, string'("sta ")); |
when c_cpfunc_sto => write(oline, string'("sto ")); |
when c_cpfunc_cont => write(oline, string'("cont")); |
when c_cpfunc_step => write(oline, string'("step")); |
when c_cpfunc_rst => write(oline, string'("rst ")); |
when others => |
write(oline, string'("?")); |
writeoct(oline, ifunc, right, 2); |
write(oline, string'("?")); |
end case; |
writeoct(oline, irnum, right, 2); |
writeoct(oline, idin, right, 8); |
else |
write(oline, string'("---- - ------")); |
end if; |
|
write(oline, R_CP_STAT.cmdbusy, right, 3); |
write(oline, R_CP_STAT.cmdack, right, 2); |
write(oline, R_CP_STAT.cmderr, right, 2); |
write(oline, R_CP_STAT.cmdmerr, right, 2); |
writeoct(oline, R_CP_DOUT, right, 8); |
write(oline, R_CP_STAT.cpugo, right, 3); |
write(oline, R_CP_STAT.cpustep, right, 2); |
write(oline, R_CP_STAT.cpuhalt, right, 2); |
writeoct(oline, R_CP_STAT.cpurust, right, 3); |
|
if R_WAITOK = '1' then |
if R_CP_STAT.cmderr='1' or icerr=1 then |
if R_CP_STAT.cmderr='1' and icerr=0 then |
write(oline, string'(" FAIL CMDERR")); |
elsif R_CP_STAT.cmderr='1' and icerr=1 then |
write(oline, string'(" CHECK CMDERR SEEN")); |
elsif R_CP_STAT.cmderr='0' and icerr=1 then |
write(oline, string'(" FAIL CMDERR EXPECTED,MISSED")); |
end if; |
elsif R_CP_STAT.cmdmerr='1' or imerr=1 then |
if R_CP_STAT.cmdmerr='1' and imerr=0 then |
write(oline, string'(" FAIL CMDMERR")); |
elsif R_CP_STAT.cmdmerr='1' and imerr=1 then |
write(oline, string'(" CHECK CMDMERR SEEN")); |
elsif R_CP_STAT.cmdmerr='0' and imerr=1 then |
write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED")); |
end if; |
elsif R_CHKREQ='1' then |
if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then |
write(oline, string'(" CHECK OK")); |
else |
write(oline, string'(" CHECK FAILED, d=")); |
writeoct(oline, R_CHKDAT, right, 7); |
if unsigned(R_CHKMSK)/=0 then |
write(oline, string'(",")); |
writeoct(oline, R_CHKMSK, right, 7); |
end if; |
end if; |
end if; |
|
if iwtgo then |
write(oline, string'(" WAIT GO OK ")); |
elsif iwtstp then |
write(oline, string'(" WAIT STEP OK")); |
end if; |
|
else |
write(oline, string'(" WAIT FAILED (will reset)")); |
RESET <= '1'; |
wait for clock_period; |
|
RESET <= '0'; |
wait for 9*clock_period; |
|
end if; |
writeline(output, oline); |
|
end loop; |
|
wait for 4*clock_period; |
CLK_STOP <= '1'; |
|
writetimestamp(oline, CLK_CYCLE, ": DONE "); |
writeline(output, oline); |
|
wait; -- suspend proc_stim forever |
-- clock is stopped, sim will end |
|
end process proc_stim; |
|
proc_moni: process |
begin |
|
loop |
wait until rising_edge(CLK); |
wait for c2out_time; |
|
R_WAITOK <= '0'; |
if R_WAITCMD = '1' then |
if CP_STAT_cmdack = '1' then |
R_WAITOK <= '1'; |
end if; |
elsif R_WAITGO = '1' then |
if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then |
R_WAITOK <= '1'; |
end if; |
elsif R_WAITSTEP = '1' then |
if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then |
R_WAITOK <= '1'; |
end if; |
end if; |
|
R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy; |
R_CP_STAT.cmdack <= CP_STAT_cmdack; |
R_CP_STAT.cmderr <= CP_STAT_cmderr; |
R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr; |
R_CP_STAT.cpugo <= CP_STAT_cpugo; |
R_CP_STAT.cpustep <= CP_STAT_cpustep; |
R_CP_STAT.cpuhalt <= CP_STAT_cpuhalt; |
R_CP_STAT.cpurust <= CP_STAT_cpurust; |
R_CP_DOUT <= CP_DOUT; |
|
end loop; |
|
end process proc_moni; |
|
end sim; |
/tb/tb_pdp11core.vbom
0,0 → 1,12
# libs |
../../vlib/slvtypes.vhd |
../../vlib/simlib/simlib.vhd |
../../vlib/simlib/simbus.vhd |
../pdp11_sim.vhd |
../pdp11.vbom |
# components |
../../vlib/simlib/simclk.vbom |
../../vlib/simlib/simclkcnt.vbom |
${tbd_pdp11core := tbd_pdp11core.vbom} |
# design |
tb_pdp11core.vhd |
/tb/tbd_pdp11core.vbom
0,0 → 1,15
# libs |
../../vlib/slvtypes.vhd |
../../vlib/genlib/genlib.vhd |
../../ibus/iblib.vhd |
../../ibus/ibdlib.vhd |
../pdp11.vbom |
${sys_conf := ../sys_conf.vhd} |
# components |
../../vlib/genlib/clkdivce.vbom |
../pdp11_core.vbom |
../pdp11_bram.vbom |
../../ibus/ibdr_minisys.vbom |
[ghdl,isim]../pdp11_tmu_sb.vbom |
# design |
tbd_pdp11core.vhd |
/tb/tbd_pdp11core.vhd
0,0 → 1,225
-- $Id: tbd_pdp11core.vhd 427 2011-11-19 21:04:11Z mueller $ |
-- |
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tbd_pdp11core - syn |
-- Description: Wrapper for pdp11_core to avoid records. It has a port |
-- interface which will not be modified by xst synthesis |
-- (no records, no generic port). |
-- |
-- Dependencies: genlib/clkdivce |
-- pdp11_core |
-- pdp11_bram |
-- ibus/ibdr_minisys |
-- pdp11_tmu_sb [sim only] |
-- |
-- To test: pdp11_core |
-- |
-- Target Devices: generic |
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-06-13 305 11.4 L68 xc3s1000-4 601 2504 206 1428 s 18.6 |
-- 2008-03-01 120 8.2.03 I34 xc3s1000-4 679 2562 206 1465 s 18.5 |
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 605 2324 164 1297 s 18.7 |
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 536 2119 119 1184 s 19.3 |
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 INTERNAL_ERROR -> blog_webpack |
-- 2007-10-27 92 9.1 J30 xc3s1000-4 503 2021 119 - t 18.7 |
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 534 2091 119 1170 s 19.3 |
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 557 2186 119 - s 18.6 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2011-11-18 427 1.5.1 now numeric_std clean |
-- 2010-12-30 351 1.5 rename tbd_pdp11_core -> tbd_pdp11core |
-- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM; |
-- 2010-06-20 307 1.4.1 add CP_ADDR_racc, CP_ADDR_be port |
-- 2010-06-13 305 1.4 add CP_ADDR_... in ports; add CP_CNTL_rnum in port |
-- 2010-06-11 303 1.3.9 use IB_MREQ.racc instead of RRI_REQ |
-- 2009-07-12 233 1.3.8 adapt to ibdr_minisys interface changes |
-- 2009-05-10 214 1.3.7 use pdp11_tmu_sb instead of pdp11_tmu |
-- 2008-08-22 161 1.3.6 use iblib, ibdlib |
-- 2008-05-03 143 1.3.5 rename _cpursta->_cpurust |
-- 2008-04-27 140 1.3.4 use cpursta interface, remove cpufail |
-- 2008-04-19 137 1.3.3 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu |
-- 2008-04-18 136 1.3.2 add RESET for ibdr_minisys |
-- 2008-02-23 118 1.3.1 use sys_conf for bram size |
-- 2008-02-17 117 1.3 adapt to em_ core interface; use pdp11_bram |
-- 2008-01-20 112 1.2.1 rename clkgen->clkdivce; use ibdr_minisys, BRESET; |
-- 2008-01-06 111 1.2 add some external devices: KW11L, DL11, RK11 |
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port |
-- 2007-09-23 85 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.genlib.all; |
use work.iblib.all; |
use work.ibdlib.all; |
use work.pdp11.all; |
use work.sys_conf.all; |
|
entity tbd_pdp11core is -- full core [no records] |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
CP_CNTL_req : in slbit; -- console control port |
CP_CNTL_func : in slv5; -- console control port |
CP_CNTL_rnum : in slv3; -- console control port |
CP_ADDR_addr : in slv22_1; -- console address port |
CP_ADDR_racc : in slbit; -- console address port |
CP_ADDR_be : in slv2; -- console address port |
CP_ADDR_ena_22bit : in slbit; -- console address port |
CP_ADDR_ena_ubmap : in slbit; -- console address port |
CP_DIN : in slv16; -- console data in |
CP_STAT_cmdbusy : out slbit; -- console status port |
CP_STAT_cmdack : out slbit; -- console status port |
CP_STAT_cmderr : out slbit; -- console status port |
CP_STAT_cmdmerr : out slbit; -- console status port |
CP_STAT_cpugo : out slbit; -- console status port |
CP_STAT_cpuhalt : out slbit; -- console status port |
CP_STAT_cpustep : out slbit; -- console status port |
CP_STAT_cpurust : out slv4; -- console status port |
CP_DOUT : out slv16 -- console data out |
); |
end tbd_pdp11core; |
|
|
architecture syn of tbd_pdp11core is |
|
signal CE_USEC : slbit := '0'; |
|
signal EI_PRI : slv3 := (others=>'0'); |
signal EI_VECT : slv9_2 := (others=>'0'); |
signal EI_ACKM : slbit := '0'; |
|
signal CP_CNTL : cp_cntl_type := cp_cntl_init; |
signal CP_ADDR : cp_addr_type := cp_addr_init; |
signal CP_STAT : cp_stat_type := cp_stat_init; |
|
signal EM_MREQ : em_mreq_type := em_mreq_init; |
signal EM_SRES : em_sres_type := em_sres_init; |
|
signal BRESET : slbit := '0'; |
signal IB_MREQ_M : ib_mreq_type := ib_mreq_init; |
signal IB_SRES_M : ib_sres_type := ib_sres_init; |
|
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; |
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init; |
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init; |
signal DM_STAT_SY : dm_stat_sy_type := dm_stat_sy_init; |
|
begin |
|
CP_CNTL.req <= CP_CNTL_req; |
CP_CNTL.func <= CP_CNTL_func; |
CP_CNTL.rnum <= CP_CNTL_rnum; |
|
CP_ADDR.addr <= CP_ADDR_addr; |
CP_ADDR.racc <= CP_ADDR_racc; |
CP_ADDR.be <= CP_ADDR_be; |
CP_ADDR.ena_22bit <= CP_ADDR_ena_22bit; |
CP_ADDR.ena_ubmap <= CP_ADDR_ena_ubmap; |
|
CP_STAT_cmdbusy <= CP_STAT.cmdbusy; |
CP_STAT_cmdack <= CP_STAT.cmdack; |
CP_STAT_cmderr <= CP_STAT.cmderr; |
CP_STAT_cmdmerr <= CP_STAT.cmdmerr; |
CP_STAT_cpugo <= CP_STAT.cpugo; |
CP_STAT_cpuhalt <= CP_STAT.cpuhalt; |
CP_STAT_cpustep <= CP_STAT.cpustep; |
CP_STAT_cpurust <= CP_STAT.cpurust; |
|
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 6, |
USECDIV => 50, |
MSECDIV => 1000) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => open |
); |
|
PDP11 : pdp11_core |
port map ( |
CLK => CLK, |
RESET => RESET, |
CP_CNTL => CP_CNTL, |
CP_ADDR => CP_ADDR, |
CP_DIN => CP_DIN, |
CP_STAT => CP_STAT, |
CP_DOUT => CP_DOUT, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
EI_ACKM => EI_ACKM, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES, |
BRESET => BRESET, |
IB_MREQ_M => IB_MREQ_M, |
IB_SRES_M => IB_SRES_M, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO |
); |
|
MEM : pdp11_bram |
generic map ( |
AWIDTH => sys_conf_bram_awidth) |
port map ( |
CLK => CLK, |
GRESET => RESET, |
EM_MREQ => EM_MREQ, |
EM_SRES => EM_SRES |
); |
|
IBDR_SYS : ibdr_minisys |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !! |
RESET => RESET, |
BRESET => BRESET, |
RB_LAM => open, |
IB_MREQ => IB_MREQ_M, |
IB_SRES => IB_SRES_M, |
EI_ACKM => EI_ACKM, |
EI_PRI => EI_PRI, |
EI_VECT => EI_VECT, |
DISPREG => open |
); |
|
-- synthesis translate_off |
|
DM_STAT_SY.emmreq <= EM_MREQ; |
DM_STAT_SY.emsres <= EM_SRES; |
DM_STAT_SY.chit <= '0'; |
|
TMU : pdp11_tmu_sb |
generic map ( |
ENAPIN => 13) |
port map ( |
CLK => CLK, |
DM_STAT_DP => DM_STAT_DP, |
DM_STAT_VM => DM_STAT_VM, |
DM_STAT_CO => DM_STAT_CO, |
DM_STAT_SY => DM_STAT_SY |
); |
|
-- synthesis translate_on |
|
end syn; |
/tb/tb_pdp11core_ssim.vbom
0,0 → 1,4
# configure for _*sim case |
tbd_pdp11core = tbd_pdp11core_ssim.vhd |
tb_pdp11core.vbom |
@top:tb_pdp11core |
/tb/tbw.dat
0,0 → 1,5
# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $ |
# |
[tb_rlink_tba_pdp11core] |
tb_rlink_tba_stim = tb_rlink_tba_pdp11core_stim.dat |
# |
/tb/.cvsignore
0,0 → 1,12
tb_pdp11core |
tb_pdp11core_stim |
tb_pdp11core_[sft]sim |
tb_pdp11core_ISim |
tb_pdp11core_ISim_[sft]sim |
tb_rlink_tba_pdp11core |
tb_rlink_tba_pdp11core_[sft]sim |
tb_rlink_tba_pdp11core_ISim |
tb_rlink_tba_pdp11core_ISim_[sft]sim |
tb_rlink_tba_stim |
tb_pdp11core_stim.scmd |
tmu_ofile |
tb
Property changes :
Added: svn:ignore
## -0,0 +1,45 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tb_pdp11core
+tb_pdp11core_stim
+tb_pdp11core_[sft]sim
+tb_pdp11core_ISim
+tb_pdp11core_ISim_[sft]sim
+tb_rlink_tba_pdp11core
+tb_rlink_tba_pdp11core_[sft]sim
+tb_rlink_tba_pdp11core_ISim
+tb_rlink_tba_pdp11core_ISim_[sft]sim
+tb_rlink_tba_stim
+tb_pdp11core_stim.scmd
+tmu_ofile
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 26)
@@ -0,0 +1,32 @@
+# $Id: Makefile 575 2014-07-27 20:55:41Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD
+# 2011-08-13 405 1.1 use includes from rtl/make
+# 2007-12-09 100 1.0.1 drop ISE_p def
+# 2007-07-08 65 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+# reference board for test synthesis is Spartan-6 based Nexys3
+ifndef XTW_BOARD
+ XTW_BOARD=nexys3
+endif
+include $(RETROBASE)/rtl/make/xflow_default_$(XTW_BOARD).mk
+#
+.PHONY : all clean
+#
+all : $(NGC_all)
+#
+clean : ise_clean
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+endif
+#
Index: pdp11_sequencer.vhd
===================================================================
--- pdp11_sequencer.vhd (nonexistent)
+++ pdp11_sequencer.vhd (revision 26)
@@ -0,0 +1,2292 @@
+-- $Id: pdp11_sequencer.vhd 569 2014-07-13 14:36:32Z mueller $
+--
+-- Copyright 2006-2014 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_sequencer - syn
+-- Description: pdp11: CPU sequencer
+--
+-- Dependencies: ib_sel
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2-14.7; viv 2014.1; ghdl 0.18-0.31
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2014-07-12 569 1.5.1 rename s_opg_div_zero -> s_opg_div_quit;
+-- use DP_STAT.div_quit; set munit_s_div_sr;
+-- BUGFIX: s_opg_div_sr: check for late div_quit
+-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
+-- 2011-11-18 427 1.4.2 now numeric_std clean
+-- 2010-10-23 335 1.4.1 use ib_sel
+-- 2010-10-17 333 1.4 use ibus V2 interface
+-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
+-- 2010-06-20 307 1.3.1 rename cpacc to cacc in vm_cntl_type
+-- 2010-06-13 305 1.3 remove CPDIN_WE, CPDOUT_WE out ports; set
+-- CNTL.cpdout_we instead of CPDOUT_WE
+-- 2010-06-12 304 1.2.8 signal cpuwait when spinning in s_op_wait
+-- 2009-05-30 220 1.2.7 final removal of snoopers (were already commented)
+-- 2009-05-09 213 1.2.6 BUGFIX: use is_dstkstack1246, stklim for mode=6
+-- 2009-05-02 211 1.2.5 BUGFIX: 11/70 spl semantics again in kernel mode
+-- 2009-04-26 209 1.2.4 BUGFIX: give interrupts priority over trap handling
+-- 2008-12-14 177 1.2.3 BUGFIX: use is_dstkstack124, fix stklim check bug
+-- 2008-12-13 176 1.2.2 BUGFIX: use is_pci in s_dstw_inc if DSTDEF='1'
+-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc; prevent stale DSRC
+-- 2008-08-22 161 1.2 rename ubf_ -> ibf_; use iblib
+-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust; cp reset sets now
+-- c_cpurust_reset; proper c_cpurust_vfail handling
+-- 2008-04-27 140 1.1.8 BUGFIX: halt cpu in case of a vector fetch error
+-- use cpursta to encode why cpu halts, remove cpufail
+-- 2008-04-27 139 1.1.7 BUGFIX: correct bytop handling for address fetches;
+-- BUGFIX: redo mtp flow; add fork_dsta fork and ddst
+-- reload in s_opa_mtp_pop_w;
+-- 2008-04-19 137 1.1.6 BUGFIX: fix loop state in s_rti_getpc_w
+-- 2008-03-30 131 1.1.5 BUGFIX: inc/dec by 2 for byte mode -(sp),(sp)+
+-- inc/dec by 2 for @(R)+ and @-(R) also for bytop's
+-- 2008-03-02 121 1.1.4 remove snoopers; add waitsusp, redo WAIT handling
+-- 2008-02-24 119 1.1.3 add lah,rps,wps command; revamp cp memory access
+-- change WAIT logic, now also bails out on cp command
+-- 2008-01-20 112 1.1.2 rename PRESET->BRESET
+-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_sequencer is -- CPU sequencer
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ PSW : in psw_type; -- processor status
+ PC : in slv16; -- program counter
+ IREG : in slv16; -- IREG
+ ID_STAT : in decode_stat_type; -- instr. decoder status
+ DP_STAT : in dpath_stat_type; -- data path status
+ CP_CNTL : in cp_cntl_type; -- console port control
+ VM_STAT : in vm_stat_type; -- virtual memory status port
+ INT_PRI : in slv3; -- interrupt priority
+ INT_VECT : in slv9_2; -- interrupt vector
+ CRESET : out slbit; -- console reset
+ BRESET : out slbit; -- ibus reset
+ MMU_MONI : out mmu_moni_type; -- mmu monitor port
+ DP_CNTL : out dpath_cntl_type; -- data path control
+ VM_CNTL : out vm_cntl_type; -- virtual memory control port
+ CP_STAT : out cp_stat_type; -- console port status
+ INT_ACK : out slbit; -- interrupt acknowledge
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_sequencer;
+
+architecture syn of pdp11_sequencer is
+
+ constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));
+
+ constant cpuerr_ibf_illhlt : integer := 7;
+ constant cpuerr_ibf_adderr : integer := 6;
+ constant cpuerr_ibf_nxm : integer := 5;
+ constant cpuerr_ibf_iobto : integer := 4;
+ constant cpuerr_ibf_ysv : integer := 3;
+ constant cpuerr_ibf_rsv : integer := 2;
+
+ type state_type is (
+ s_idle,
+ s_cp_regread,
+ s_cp_rps,
+ s_cp_memr_w,
+ s_cp_memw_w,
+ s_ifetch,
+ s_ifetch_w,
+ s_idecode,
+
+ s_srcr_def,
+ s_srcr_def_w,
+ s_srcr_inc,
+ s_srcr_inc_w,
+ s_srcr_dec,
+ s_srcr_dec1,
+ s_srcr_ind,
+ s_srcr_ind1_w,
+ s_srcr_ind2,
+ s_srcr_ind2_w,
+
+ s_dstr_def,
+ s_dstr_def_w,
+ s_dstr_inc,
+ s_dstr_inc_w,
+ s_dstr_dec,
+ s_dstr_dec1,
+ s_dstr_ind,
+ s_dstr_ind1_w,
+ s_dstr_ind2,
+ s_dstr_ind2_w,
+
+ s_dstw_def,
+ s_dstw_def_w,
+ s_dstw_inc,
+ s_dstw_inc_w,
+ s_dstw_incdef_w,
+ s_dstw_dec,
+ s_dstw_dec1,
+ s_dstw_ind,
+ s_dstw_ind_w,
+ s_dstw_def246,
+
+ s_dsta_inc,
+ s_dsta_incdef_w,
+ s_dsta_dec,
+ s_dsta_dec1,
+ s_dsta_ind,
+ s_dsta_ind_w,
+
+ s_op_halt,
+ s_op_wait,
+ s_op_trap,
+ s_op_reset,
+ s_op_rts,
+ s_op_rts_pop,
+ s_op_rts_pop_w,
+ s_op_spl,
+ s_op_mcc,
+ s_op_br,
+ s_op_mark,
+ s_op_mark1,
+ s_op_mark_pop,
+ s_op_mark_pop_w,
+ s_op_sob,
+ s_op_sob1,
+
+ s_opg_gen,
+ s_opg_gen_rmw_w,
+ s_opg_mul,
+ s_opg_mul1,
+ s_opg_div,
+ s_opg_div_cn,
+ s_opg_div_cr,
+ s_opg_div_sq,
+ s_opg_div_sr,
+ s_opg_div_quit,
+ s_opg_ash,
+ s_opg_ash_cn,
+ s_opg_ashc,
+ s_opg_ashc_cn,
+ s_opg_ashc_wl,
+
+ s_opa_jsr,
+ s_opa_jsr1,
+ s_opa_jsr_push,
+ s_opa_jsr_push_w,
+ s_opa_jsr2,
+ s_opa_jmp,
+ s_opa_mtp,
+ s_opa_mtp_pop_w,
+ s_opa_mtp_reg,
+ s_opa_mtp_mem,
+ s_opa_mtp_mem_w,
+ s_opa_mfp_reg,
+ s_opa_mfp_mem,
+ s_opa_mfp_mem_w,
+ s_opa_mfp_dec,
+ s_opa_mfp_push,
+ s_opa_mfp_push_w,
+
+ s_trap_4,
+ s_trap_10,
+ s_trap_disp,
+
+ s_int_ext,
+
+ s_int_getpc,
+ s_int_getpc_w,
+ s_int_getps,
+ s_int_getps_w,
+ s_int_getsp,
+ s_int_decsp,
+ s_int_pushps,
+ s_int_pushps_w,
+ s_int_pushpc,
+ s_int_pushpc_w,
+
+ s_rti_getpc,
+ s_rti_getpc_w,
+ s_rti_getps,
+ s_rti_getps_w,
+ s_rti_newpc,
+
+ s_vmerr,
+ s_cpufail
+ );
+
+ signal R_STATE : state_type := s_idle; -- state register
+ signal N_STATE : state_type := s_idle;
+
+ signal R_STATUS : cpustat_type := cpustat_init;
+ signal N_STATUS : cpustat_type := cpustat_init;
+ signal R_CPUERR : cpuerr_type := cpuerr_init;
+ signal N_CPUERR : cpuerr_type := cpuerr_init;
+
+ signal R_IDSTAT : decode_stat_type := decode_stat_init;
+ signal N_IDSTAT : decode_stat_type := decode_stat_init;
+
+ signal R_VMSTAT : vm_stat_type := vm_stat_init;
+
+ signal IBSEL_CPUERR : slbit := '0';
+
+begin
+
+ SEL : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_cpuerr)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_CPUERR
+ );
+
+ proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)
+ variable idout : slv16 := (others=>'0');
+ begin
+ idout := (others=>'0');
+ if IBSEL_CPUERR = '1' then
+ idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
+ idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
+ idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
+ idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
+ idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
+ idout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
+ end if;
+ IB_SRES.dout <= idout;
+ IB_SRES.ack <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all
+ IB_SRES.busy <= '0';
+ end process proc_ibres;
+
+ proc_status: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if GRESET = '1' then
+ R_STATUS <= cpustat_init;
+ R_CPUERR <= cpuerr_init;
+ R_IDSTAT <= decode_stat_init;
+ R_VMSTAT <= vm_stat_init;
+ else
+ R_STATUS <= N_STATUS;
+ R_CPUERR <= N_CPUERR;
+ R_IDSTAT <= N_IDSTAT;
+ R_VMSTAT <= VM_STAT;
+ end if;
+ end if;
+ end process proc_status;
+
+ proc_state: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if GRESET = '1' then
+ R_STATE <= s_idle;
+ else
+ R_STATE <= N_STATE;
+ end if;
+ end if;
+ end process proc_state;
+
+ proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL,
+ ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,
+ R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,
+ INT_PRI, INT_VECT)
+
+ variable nstate : state_type;
+ variable nstatus : cpustat_type := cpustat_init;
+ variable ncpuerr : cpuerr_type := cpuerr_init;
+
+ variable ncreset : slbit := '0';
+ variable nbreset : slbit := '0';
+ variable nintack : slbit := '0';
+
+ variable ndpcntl : dpath_cntl_type := dpath_cntl_init;
+ variable nvmcntl : vm_cntl_type := vm_cntl_init;
+ variable nidstat : decode_stat_type := decode_stat_init;
+ variable nmmumoni : mmu_moni_type := mmu_moni_init;
+
+ variable imemok : boolean;
+ variable bytop : slbit := '0'; -- local bytop access flag
+ variable macc : slbit := '0'; -- local modify access flag
+
+ variable lvector : slv9_2 := (others=>'0'); -- local trap/interrupt vector
+
+ variable brcode : slv4 := (others=>'0'); -- reduced br opcode (15,10-8)
+ variable brcond : slbit := '0'; -- br condition value
+
+ variable is_kmode : slbit := '0'; -- cmode is kernel mode
+ variable is_dstkstack1246 : slbit := '0'; -- dest is k-stack & mode= 1,2,4,6
+
+ variable int_pending : slbit := '0'; -- an interrupt is pending
+
+ alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
+ alias SRCDEF : slbit is IREG(9); -- src register mode defered
+ alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
+ alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
+ alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
+ alias DSTDEF : slbit is IREG(3); -- dst register mode defered
+ alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
+
+ procedure do_memread_i(nstate : inout state_type;
+ ndpcntl : inout dpath_cntl_type;
+ nvmcntl : inout vm_cntl_type;
+ wstate : in state_type) is
+ begin
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
+ nvmcntl.dspace := '0';
+ nvmcntl.req := '1';
+ ndpcntl.gpr_pcinc := '1'; -- (pc)++
+ nstate := wstate;
+ end procedure do_memread_i;
+
+ procedure do_memread_d(nstate : inout state_type;
+ nvmcntl : inout vm_cntl_type;
+ wstate : in state_type;
+ bytop : in slbit := '0';
+ macc : in slbit := '0';
+ is_pci : in slbit := '0') is
+ begin
+ nvmcntl.dspace := not is_pci; -- ispace if pc immediate modes
+-- bytop := R_IDSTAT.is_bytop and not is_addr;
+ nvmcntl.bytop := bytop;
+ nvmcntl.macc := macc;
+ nvmcntl.req := '1';
+ nstate := wstate;
+ end procedure do_memread_d;
+
+ procedure do_memread_srcinc(nstate : inout state_type;
+ ndpcntl : inout dpath_cntl_type;
+ nvmcntl : inout vm_cntl_type;
+ wstate : in state_type;
+ nmmumoni : inout mmu_moni_type;
+ updt_sp : in slbit := '0') is
+ begin
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ if updt_sp = '1' then
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '0';
+ ndpcntl.gpr_adst := c_gpr_sp; -- update SP too
+ ndpcntl.gpr_we := '1';
+ end if;
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ nvmcntl.dspace := '1';
+ nvmcntl.req := '1';
+ nstate := wstate;
+ end procedure do_memread_srcinc;
+
+ procedure do_memwrite(nstate : inout state_type;
+ nvmcntl : inout vm_cntl_type;
+ wstate : in state_type;
+ macc : in slbit :='0') is
+ begin
+ nvmcntl.dspace := '1';
+ nvmcntl.bytop := R_IDSTAT.is_bytop;
+ nvmcntl.wacc := '1';
+ nvmcntl.macc := macc;
+ nvmcntl.req := '1';
+ nstate := wstate;
+ end procedure do_memwrite;
+
+ procedure do_memcheck(nstate : inout state_type;
+ nstatus : inout cpustat_type;
+ mok : out boolean) is
+ begin
+ nstate := nstate; -- dummy to add driver (vivado)
+ nstatus := nstatus; -- "
+ mok := false;
+ if VM_STAT.ack = '1' then
+ mok := true;
+ nstatus.trap_mmu := VM_STAT.trap_mmu;
+ if R_CPUERR.ysv = '0' then -- ysv trap when cpuerr not yet set
+ nstatus.trap_ysv := VM_STAT.trap_ysv;
+ end if;
+ elsif VM_STAT.err='1' or VM_STAT.fail='1' then
+ nstate := s_vmerr;
+ end if;
+ end procedure do_memcheck;
+
+ procedure do_const_opsize(ndpcntl : inout dpath_cntl_type;
+ bytop : in slbit;
+ isdef : in slbit;
+ regnum : in slv3) is
+ begin
+ ndpcntl := ndpcntl; -- dummy to add driver (vivado)
+ if bytop='0' or isdef='1' or
+ regnum=c_gpr_pc or regnum=c_gpr_sp then
+ ndpcntl.ounit_const := "000000010";
+ else
+ ndpcntl.ounit_const := "000000001";
+ end if;
+ end procedure do_const_opsize;
+
+ procedure do_fork_dstr(nstate : inout state_type;
+ idstat : in decode_stat_type) is
+ begin
+ case idstat.fork_dstr is
+ when c_fork_dstr_def => nstate := s_dstr_def;
+ when c_fork_dstr_inc => nstate := s_dstr_inc;
+ when c_fork_dstr_dec => nstate := s_dstr_dec;
+ when c_fork_dstr_ind => nstate := s_dstr_ind;
+ when others => nstate := s_cpufail;
+ end case;
+ end procedure do_fork_dstr;
+
+ procedure do_fork_opg(nstate : inout state_type;
+ idstat : in decode_stat_type) is
+ begin
+ case idstat.fork_opg is
+ when c_fork_opg_gen => nstate := s_opg_gen;
+ when c_fork_opg_wdef => nstate := s_dstw_def;
+ when c_fork_opg_winc => nstate := s_dstw_inc;
+ when c_fork_opg_wdec => nstate := s_dstw_dec;
+ when c_fork_opg_wind => nstate := s_dstw_ind;
+ when c_fork_opg_mul => nstate := s_opg_mul;
+ when c_fork_opg_div => nstate := s_opg_div;
+ when c_fork_opg_ash => nstate := s_opg_ash;
+ when c_fork_opg_ashc => nstate := s_opg_ashc;
+ when others => nstate := s_cpufail;
+ end case;
+ end procedure do_fork_opg;
+
+ procedure do_fork_opa(nstate : inout state_type;
+ idstat : in decode_stat_type) is
+ begin
+ case idstat.fork_opa is
+ when c_fork_opa_jmp => nstate := s_opa_jmp;
+ when c_fork_opa_jsr => nstate := s_opa_jsr;
+ when c_fork_opa_mtp => nstate := s_opa_mtp_mem;
+ when c_fork_opa_mfp_reg => nstate := s_opa_mfp_reg;
+ when c_fork_opa_mfp_mem => nstate := s_opa_mfp_mem;
+ when others => nstate := s_cpufail;
+ end case;
+ end procedure do_fork_opa;
+
+ procedure do_fork_next(nstate : inout state_type;
+ nstatus : inout cpustat_type;
+ nmmumoni : inout mmu_moni_type) is
+ begin
+ nmmumoni.idone := '1';
+ if unsigned(INT_PRI) > unsigned(PSW.pri) then
+ nstate := s_idle;
+ elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or
+ R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or
+ PSW.tflag='1' then
+ nstate := s_trap_disp;
+ elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then
+ nstate := s_ifetch;
+ else
+ nstate := s_idle;
+ end if;
+ end procedure do_fork_next;
+
+ procedure do_fork_next_pref(nstate : inout state_type;
+ nstatus : inout cpustat_type;
+ ndpcntl : inout dpath_cntl_type;
+ nvmcntl : inout vm_cntl_type;
+ nmmumoni : inout mmu_moni_type) is
+ begin
+ ndpcntl := ndpcntl; -- dummy to add driver (vivado)
+ nvmcntl := nvmcntl; -- "
+ nmmumoni.idone := '1';
+ if unsigned(INT_PRI) > unsigned(PSW.pri) then
+ nstate := s_idle;
+ elsif R_STATUS.trap_mmu='1' or nstatus.trap_mmu='1' or
+ R_STATUS.trap_ysv='1' or nstatus.trap_ysv='1' or
+ PSW.tflag='1' then
+ nstate := s_trap_disp;
+ elsif R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1' then
+ nvmcntl.req := '1';
+ ndpcntl.gpr_pcinc := '1';
+ nmmumoni.istart := '1';
+ nstate := s_ifetch_w;
+ else
+ nstate := s_idle;
+ end if;
+ end procedure do_fork_next_pref;
+
+ procedure do_start_int(nstate : inout state_type;
+ ndpcntl : inout dpath_cntl_type;
+ vector : in slv9_2) is
+ begin
+ ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
+ ndpcntl.dtmp_we := '1';
+ ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
+ ndpcntl.ounit_const := vector & "00"; -- vector
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := '1'; -- DSRC = vector
+ nstate := s_int_getpc;
+ end procedure do_start_int;
+
+ begin
+
+ nstate := R_STATE;
+ nstatus := R_STATUS;
+ ncpuerr := R_CPUERR;
+
+ nstatus.cpuwait := '0'; -- wait flag 0 unless set in s_op_wait
+
+ ncreset := '0';
+ nbreset := '0';
+ nintack := '0';
+
+ nidstat := R_IDSTAT;
+
+ if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !
+ ncpuerr := cpuerr_init;
+ end if;
+
+ int_pending := '0';
+ if unsigned(INT_PRI) > unsigned(PSW.pri) then
+ int_pending := '1';
+ end if;
+
+ imemok := false;
+
+ nmmumoni := mmu_moni_init;
+ nmmumoni.pc := PC;
+
+ macc := '0';
+ bytop := '0';
+ brcode := IREG(15) & IREG(10 downto 8);
+ brcond := '1';
+
+ is_kmode := '0';
+ is_dstkstack1246 := '0';
+
+ if PSW.cmode = c_psw_kmode then
+ is_kmode := '1';
+ if DSTREG = c_gpr_sp and
+ (DSTMODF="001" or DSTMODF="010" or
+ DSTMODF="100" or DSTMODF="110") then
+ is_dstkstack1246 := '1';
+ end if;
+ end if;
+
+ lvector := (others=>'0');
+
+ nvmcntl := vm_cntl_init;
+ nvmcntl.dspace := '1'; -- DEFAULT
+ nvmcntl.mode := PSW.cmode; -- DEFAULT
+ nvmcntl.intrsv := R_STATUS.do_intrsv; -- DEFAULT
+
+ ndpcntl := dpath_cntl_init;
+ ndpcntl.gpr_asrc := SRCREG; -- DEFAULT
+ ndpcntl.gpr_adst := DSTREG; -- DEFAULT
+ ndpcntl.gpr_mode := PSW.cmode; -- DEFAULT
+ ndpcntl.gpr_rset := PSW.rset; -- DEFAULT
+ ndpcntl.gpr_we := '0'; -- DEFAULT
+ ndpcntl.gpr_bytop := '0'; -- DEFAULT
+ ndpcntl.gpr_pcinc := '0'; -- DEFAULT
+
+ ndpcntl.psr_ccwe := '0'; -- DEFAULT
+ ndpcntl.psr_we := '0'; -- DEFAULT
+ ndpcntl.psr_func := "000"; -- DEFAULT
+
+ ndpcntl.dsrc_sel := c_dpath_dsrc_src;
+ ndpcntl.dsrc_we := '0';
+ ndpcntl.ddst_sel := c_dpath_ddst_dst;
+ ndpcntl.ddst_we := '0';
+ ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
+ ndpcntl.dtmp_we := '0';
+
+ ndpcntl.ounit_asel := c_ounit_asel_ddst;
+ ndpcntl.ounit_azero := '0'; -- DEFAULT
+ ndpcntl.ounit_const := (others=>'0'); -- DEFAULT
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;
+ ndpcntl.ounit_opsub := '0'; -- DEFAULT
+
+ ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC
+ ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC
+ ndpcntl.aunit_cimod := R_IDSTAT.aunit_cimod; -- STATIC
+ ndpcntl.aunit_cc1op := R_IDSTAT.aunit_cc1op; -- STATIC
+ ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC
+ ndpcntl.aunit_bytop := R_IDSTAT.is_bytop; -- STATIC
+
+ ndpcntl.lunit_func := R_IDSTAT.lunit_func; -- STATIC
+ ndpcntl.lunit_bytop := R_IDSTAT.is_bytop; -- STATIC
+
+ ndpcntl.munit_func := R_IDSTAT.munit_func; -- STATIC
+
+ ndpcntl.ireg_we := '0';
+
+ ndpcntl.cres_sel := R_IDSTAT.res_sel; -- DEFAULT
+ ndpcntl.dres_sel := c_dpath_res_ounit;
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;
+
+ if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then
+ nstatus.cmdbusy := '1';
+ nstatus.cpfunc := CP_CNTL.func;
+ nstatus.cprnum := CP_CNTL.rnum;
+ end if;
+
+ if R_STATUS.cmdack = '1' then
+ nstatus.cmdack := '0';
+ nstatus.cmderr := '0';
+ nstatus.cmdmerr := '0';
+ end if;
+
+ case R_STATE is
+
+ -- idle and command port states ---------------------------------------------
+
+ -- Note: s_idle was entered from suspended WAIT when waitsusp='1'
+ -- --> all exits must check this and either return to s_op_wait
+ -- or abort the WAIT and set waitsusp='0'
+
+ when s_idle =>
+
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST (do mux early)
+ nstatus.cpustep := '0';
+
+ if R_STATUS.cmdbusy = '1' then
+ case R_STATUS.cpfunc is
+
+ when c_cpfunc_noop => -- noop : no operation --------
+ nstatus.cmdack := '1';
+ nstate := s_idle;
+
+ when c_cpfunc_sta => -- sta : cpu start -----------
+ ncreset := '1';
+ nstatus.cmdack := '1';
+ nstatus.cpugo := '1';
+ nstatus.cpuhalt := '0';
+ nstatus.cpurust := c_cpurust_runs;
+ nstatus.waitsusp := '0';
+ nstate := s_idle;
+
+ when c_cpfunc_sto => -- sto : cpu stop ------------
+ nstatus.cmdack := '1';
+ nstatus.cpugo := '0';
+ nstatus.cpurust := c_cpurust_stop;
+ nstatus.waitsusp := '0';
+ nstate := s_idle;
+
+ when c_cpfunc_cont => -- cont : cpu continue --------
+ nstatus.cmdack := '1';
+ nstatus.cpugo := '1';
+ nstatus.cpuhalt := '0';
+ nstatus.cpurust := c_cpurust_runs;
+ nstatus.waitsusp := '0';
+ nstate := s_idle;
+
+ when c_cpfunc_step => -- step : cpu step ------------
+ nstatus.cmdack := '1';
+ nstatus.cpustep := '1';
+ nstatus.cpuhalt := '0';
+ nstatus.cpurust := c_cpurust_step;
+ nstatus.waitsusp := '0';
+ if int_pending = '1' then
+ nintack := '1';
+ nstatus.intvect := INT_VECT;
+ nstate := s_int_ext;
+ else
+ nstate := s_ifetch;
+ end if;
+
+ when c_cpfunc_rst => -- rst : cpu reset (soft) ----
+ ncreset := '1';
+ nstatus.cmdack := '1';
+ nstatus.cpugo := '0';
+ nstatus.cpuhalt := '0';
+ nstatus.cpurust := c_cpurust_reset;
+ nstatus.waitsusp := '0';
+ nstate := s_idle;
+
+ when c_cpfunc_rreg => -- rreg : read register ------
+ ndpcntl.gpr_adst := R_STATUS.cprnum;
+ ndpcntl.ddst_sel := c_dpath_ddst_dst;
+ ndpcntl.ddst_we := '1';
+ nstate := s_cp_regread;
+
+ when c_cpfunc_wreg => -- wreg : write register -----
+ ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
+ ndpcntl.gpr_adst := R_STATUS.cprnum;
+ ndpcntl.gpr_we := '1';
+ nstatus.cmdack := '1';
+ nstate := s_idle;
+
+ when c_cpfunc_rpsw => -- rpsw : read psw -----------
+ ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
+ ndpcntl.dtmp_we := '1';
+ nstate := s_cp_rps;
+
+ when c_cpfunc_wpsw => -- wpsw : write psw ----------
+ ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
+ ndpcntl.psr_func := c_psr_func_wall; -- write all fields
+ ndpcntl.psr_we := '1'; -- load new PS
+ nstatus.cmdack := '1';
+ nstate := s_idle;
+
+ when c_cpfunc_rmem => -- rmem : read memory --------
+ nvmcntl.cacc := '1';
+ nvmcntl.req := '1';
+ nstate := s_cp_memr_w;
+
+ when c_cpfunc_wmem => -- wmem : write memory -------
+ ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
+ nvmcntl.wacc := '1'; -- write mem
+ nvmcntl.cacc := '1';
+ nvmcntl.req := '1';
+ nstate := s_cp_memw_w;
+
+ when others =>
+ nstatus.cmdack := '1';
+ nstatus.cmderr := '1';
+ nstate := s_idle;
+
+ end case;
+
+ elsif R_STATUS.waitsusp = '1' then
+ nstatus.waitsusp := '0';
+ nstate := s_op_wait;
+
+ elsif R_STATUS.cpugo = '1' then
+ if int_pending = '1' then
+ nintack := '1';
+ nstatus.intvect := INT_VECT;
+ nstate := s_int_ext;
+ else
+ nstate := s_ifetch;
+ end if;
+
+ end if;
+
+ when s_cp_regread =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ nstatus.cmdack := '1';
+ nstate := s_idle;
+
+ when s_cp_rps =>
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ nstatus.cmdack := '1';
+ nstate := s_idle;
+
+ when s_cp_memr_w =>
+ nstate := s_cp_memr_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
+ nstatus.cmdack := '1';
+ nstatus.trap_ysv := '0'; -- suppress traps on console
+ nstatus.trap_mmu := '0';
+ nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
+ nstate := s_idle;
+ end if;
+
+ when s_cp_memw_w =>
+ nstate := s_cp_memw_w;
+ if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
+ nstatus.cmdack := '1';
+ nstatus.trap_ysv := '0'; -- suppress traps on console
+ nstatus.trap_mmu := '0';
+ nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
+ nstate := s_idle;
+ end if;
+
+ -- instruction fetch and decode ---------------------------------------------
+
+ when s_ifetch =>
+ nmmumoni.istart := '1'; -- do here; memread_i inc PC !
+ do_memread_i(nstate, ndpcntl, nvmcntl, s_ifetch_w);
+
+ when s_ifetch_w =>
+ nstate := s_ifetch_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ireg_we := '1';
+ nstate := s_idecode;
+ end if;
+
+ when s_idecode =>
+ nidstat := ID_STAT; -- register decode status
+ if ID_STAT.force_srcsp = '1' then
+ ndpcntl.gpr_asrc := c_gpr_sp;
+ end if;
+ ndpcntl.dsrc_sel := c_dpath_dsrc_src;
+ ndpcntl.dsrc_we := '1';
+ ndpcntl.ddst_sel := c_dpath_ddst_dst;
+ ndpcntl.ddst_we := '1';
+
+ nvmcntl.dspace := '0';
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
+
+ if ID_STAT.do_pref_dec='1' and PSW.tflag='0' and int_pending='0' and
+ R_STATUS.cpugo='1' and not R_STATUS.cmdbusy='1'
+ then
+ nvmcntl.req := '1';
+ ndpcntl.gpr_pcinc := '1'; -- (pc)++
+ nmmumoni.istart := '1';
+ nstatus.prefdone := '1';
+ end if;
+
+ if ID_STAT.do_fork_op = '1' then
+ case ID_STAT.fork_op is
+ when c_fork_op_halt => nstate := s_op_halt;
+ when c_fork_op_wait => nstate := s_op_wait;
+ when c_fork_op_rtti => nstate := s_rti_getpc;
+ when c_fork_op_trap => nstate := s_op_trap;
+ when c_fork_op_reset=> nstate := s_op_reset;
+ when c_fork_op_rts => nstate := s_op_rts;
+ when c_fork_op_spl => nstate := s_op_spl;
+ when c_fork_op_mcc => nstate := s_op_mcc;
+ when c_fork_op_br => nstate := s_op_br;
+ when c_fork_op_mark => nstate := s_op_mark;
+ when c_fork_op_sob => nstate := s_op_sob;
+ when c_fork_op_mtp => nstate := s_opa_mtp;
+ when others => nstate := s_cpufail;
+ end case;
+ elsif ID_STAT.do_fork_srcr = '1' then
+ case ID_STAT.fork_srcr is
+ when c_fork_srcr_def => nstate := s_srcr_def;
+ when c_fork_srcr_inc => nstate := s_srcr_inc;
+ when c_fork_srcr_dec => nstate := s_srcr_dec;
+ when c_fork_srcr_ind => nstate := s_srcr_ind;
+ when others => nstate := s_cpufail;
+ end case;
+ elsif ID_STAT.do_fork_dstr = '1' then
+ do_fork_dstr(nstate, ID_STAT);
+ elsif ID_STAT.do_fork_dsta = '1' then
+ case ID_STAT.fork_dsta is -- 2nd dsta fork in s_opa_mtp_pop_w
+ when c_fork_dsta_def => do_fork_opa(nstate, ID_STAT);
+ when c_fork_dsta_inc => nstate := s_dsta_inc;
+ when c_fork_dsta_dec => nstate := s_dsta_dec;
+ when c_fork_dsta_ind => nstate := s_dsta_ind;
+ when others => nstate := s_cpufail;
+ end case;
+ elsif ID_STAT.do_fork_opg = '1' then
+ do_fork_opg(nstate, ID_STAT);
+ elsif ID_STAT.is_res = '1' then
+ nstate := s_trap_10; -- do trap 10;
+ else
+ nstate := s_cpufail; -- catch mistakes here...
+ end if;
+
+ -- source read states -------------------------------------------------------
+ -- flows:
+ -- 1 (r) s_srcr_def req (r)
+ -- s_srcr_def_w get (r)
+ -- -> do_fork_dstr or do_fork_opg
+ --
+ -- 2 (r)+ s_srcr_inc req (r); r+=s
+ -- s_srcr_inc_w get (r)
+ -- -> do_fork_dstr or do_fork_opg
+ --
+ -- 3 @(r)+ s_srcr_inc req (r); r+=s
+ -- s_srcr_inc_w get (r)
+ -- s_srcr_def req @(r)
+ -- s_srcr_def_w get @(r)
+ -- -> do_fork_dstr or do_fork_opg
+ --
+ -- 4 -(r) s_srcr_dec r-=s
+ -- s_srcr_dec1 req (r)
+ -- s_srcr_inc_w get (r)
+ -- -> do_fork_dstr or do_fork_opg
+ --
+ -- 5 @-(r) s_srcr_dec r-=s
+ -- s_srcr_dec1 req (r)
+ -- s_srcr_inc_w get (r)
+ -- s_srcr_def req @(r)
+ -- s_srcr_def_w get @(r)
+ -- -> do_fork_dstr or do_fork_opg
+ --
+ -- 6 n(r) s_srcr_ind req n
+ -- s_srcr_ind1_w get n; ea=r+n
+ -- s_srcr_ind2 req n(r)
+ -- s_srcr_ind2_w get n(r)
+ -- -> do_fork_dstr or do_fork_opg
+ --
+ -- 7 @n(r) s_srcr_ind req n
+ -- s_srcr_ind1_w get n; ea=r+n
+ -- s_srcr_ind2 req n(r)
+ -- s_srcr_ind2_w get n(r)
+ -- s_srcr_def req @n(r)
+ -- s_srcr_def_w get @n(r)
+ -- -> do_fork_dstr or do_fork_opg
+
+ when s_srcr_def =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ do_memread_d(nstate, nvmcntl, s_srcr_def_w,
+ bytop=>R_IDSTAT.is_bytop,
+ is_pci=>R_IDSTAT.is_srcpcmode1);
+
+ when s_srcr_def_w =>
+ nstate := s_srcr_def_w;
+ do_memcheck(nstate, nstatus, imemok);
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ if imemok then
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ if R_IDSTAT.do_fork_dstr = '1' then
+ do_fork_dstr(nstate, R_IDSTAT);
+ else
+ do_fork_opg(nstate, R_IDSTAT);
+ end if;
+ end if;
+
+ when s_srcr_inc =>
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := SRCREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '0';
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
+ if DSTREG = SRCREG then -- prevent stale DDST copy
+ ndpcntl.ddst_we := '1'; -- update DDST
+ end if;
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ bytop := R_IDSTAT.is_bytop and not SRCDEF;
+ do_memread_d(nstate, nvmcntl, s_srcr_inc_w,
+ bytop=>bytop, is_pci=>R_IDSTAT.is_srcpc);
+
+ when s_srcr_inc_w =>
+ nstate := s_srcr_inc_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ if SRCDEF = '1' then
+ nstate := s_srcr_def;
+ else
+ if R_IDSTAT.do_fork_dstr = '1' then
+ do_fork_dstr(nstate, R_IDSTAT);
+ else
+ do_fork_opg(nstate, R_IDSTAT);
+ end if;
+ end if;
+ end if;
+
+ when s_srcr_dec =>
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ ndpcntl.gpr_adst := SRCREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '1';
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
+ if DSTREG = SRCREG then -- prevent stale DDST copy
+ ndpcntl.ddst_we := '1'; -- update DDST
+ end if;
+ nstate := s_srcr_dec1;
+
+ when s_srcr_dec1 =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ bytop := R_IDSTAT.is_bytop and not SRCDEF;
+ do_memread_d(nstate, nvmcntl, s_srcr_inc_w, bytop=>bytop);
+
+ when s_srcr_ind =>
+ do_memread_i(nstate, ndpcntl, nvmcntl, s_srcr_ind1_w);
+
+ when s_srcr_ind1_w =>
+ nstate := s_srcr_ind1_w;
+ if R_IDSTAT.is_srcpc = '0' then
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A = DSRC
+ else
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
+ end if;
+ ndpcntl.ounit_bsel := c_ounit_bsel_vmdout; -- OUNIT B = VMDOUT
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ ndpcntl.ddst_we := '1'; -- update DDST (to reload PC)
+ nstate := s_srcr_ind2;
+ end if;
+
+ when s_srcr_ind2 =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ bytop := R_IDSTAT.is_bytop and not SRCDEF;
+ do_memread_d(nstate, nvmcntl, s_srcr_ind2_w, bytop=>bytop);
+
+ when s_srcr_ind2_w =>
+ nstate := s_srcr_ind2_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ if SRCDEF = '1' then
+ nstate := s_srcr_def;
+ else
+ if R_IDSTAT.do_fork_dstr = '1' then
+ do_fork_dstr(nstate, R_IDSTAT);
+ else
+ do_fork_opg(nstate, R_IDSTAT);
+ end if;
+ end if;
+ end if;
+
+ -- destination read states --------------------------------------------------
+ -- flows:
+ -- 1 (r) s_dstr_def req (r) (rmw if rmw op)
+ -- s_dstr_def_w get (r)
+ -- -> do_fork_opg
+ --
+ -- 2 (r)+ s_dstr_inc req (r); r+=s (rmw if rmw op)
+ -- s_dstr_inc_w get (r)
+ -- -> do_fork_opg
+ --
+ -- 3 @(r)+ s_dstr_inc req (r); r+=s
+ -- s_dstr_inc_w get (r)
+ -- s_dstr_def req @(r) (rmw if rmw op)
+ -- s_dstr_def_w get @(r)
+ -- -> do_fork_opg
+ --
+ -- 4 -(r) s_dstr_dec r-=s
+ -- s_dstr_dec1 req (r) (rmw if rmw op)
+ -- s_dstr_inc_w get (r)
+ -- -> do_fork_opg
+ --
+ -- 5 @-(r) s_dstr_dec r-=s
+ -- s_dstr_dec1 req (r)
+ -- s_dstr_inc_w get (r)
+ -- s_dstr_def req @(r) (rmw if rmw op)
+ -- s_dstr_def_w get @(r)
+ -- -> do_fork_opg
+ --
+ -- 6 n(r) s_dstr_ind req n
+ -- s_dstr_ind1_w get n; ea=r+n
+ -- s_dstr_ind2 req n(r) (rmw if rmw op)
+ -- s_dstr_ind2_w get n(r)
+ -- -> do_fork_opg
+ --
+ -- 7 @n(r) s_dstr_ind req n
+ -- s_dstr_ind1_w get n; ea=r+n
+ -- s_dstr_ind2 req n(r)
+ -- s_dstr_ind2_w get n(r)
+ -- s_dstr_def req @n(r) (rmw if rmw op)
+ -- s_dstr_def_w get @n(r)
+ -- -> do_fork_opg
+
+ when s_dstr_def =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ do_memread_d(nstate, nvmcntl, s_dstr_def_w,
+ bytop=>R_IDSTAT.is_bytop, macc=>R_IDSTAT.is_rmwop);
+
+ when s_dstr_def_w =>
+ nstate := s_dstr_def_w;
+ do_memcheck(nstate, nstatus, imemok);
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ do_fork_opg(nstate, R_IDSTAT);
+ end if;
+
+ when s_dstr_inc =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := DSTREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '0';
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ macc := R_IDSTAT.is_rmwop and not DSTDEF;
+ bytop := R_IDSTAT.is_bytop and not DSTDEF;
+ do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
+ bytop=>bytop, macc=>macc, is_pci=>R_IDSTAT.is_dstpc);
+
+ when s_dstr_inc_w =>
+ nstate := s_dstr_inc_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ if DSTDEF = '1' then
+ nstate := s_dstr_def;
+ else
+ do_fork_opg(nstate, R_IDSTAT);
+ end if;
+ end if;
+
+ when s_dstr_dec =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ ndpcntl.ddst_we := '1'; -- update DDST
+ ndpcntl.gpr_adst := DSTREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '1';
+ nstate := s_dstr_dec1;
+
+ when s_dstr_dec1 =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ macc := R_IDSTAT.is_rmwop and not DSTDEF;
+ bytop := R_IDSTAT.is_bytop and not DSTDEF;
+ do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
+ bytop=>bytop, macc=>macc);
+
+ when s_dstr_ind =>
+ do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
+
+ when s_dstr_ind1_w =>
+ nstate := s_dstr_ind1_w;
+ if R_IDSTAT.is_dstpc = '0' then
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
+ else
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
+ end if;
+ ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ nstate := s_dstr_ind2;
+ end if;
+
+ when s_dstr_ind2 =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ macc := R_IDSTAT.is_rmwop and not DSTDEF;
+ bytop := R_IDSTAT.is_bytop and not DSTDEF;
+ do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
+ bytop=>bytop, macc=>macc);
+
+ when s_dstr_ind2_w =>
+ nstate := s_dstr_ind2_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ if DSTDEF = '1' then
+ nstate := s_dstr_def;
+ else
+ do_fork_opg(nstate, R_IDSTAT);
+ end if;
+ end if;
+
+ -- destination write states -------------------------------------------------
+ -- flows:
+ -- 1 (r) s_dstw_def wreq (r) check kstack
+ -- s_dstw_def_w ack (r)
+ -- -> do_fork_next
+ --
+ -- 2 (r)+ s_dstw_inc wreq (r) check kstack
+ -- s_dstw_inc_w ack (r); r+=s
+ -- -> do_fork_next
+ --
+ -- 3 @(r)+ s_dstw_inc rreq (r); r+=s
+ -- s_dstw_incdef_w get (r)
+ -- s_dstw_def246 wreq @(r)
+ -- s_dstw_def_w ack @(r)
+ -- -> do_fork_next
+ --
+ -- 4 -(r) s_dstw_dec r-=s
+ -- s_dstw_dec1 wreq (r) check kstack
+ -- s_dstw_def_w ack (r)
+ -- -> do_fork_next
+ --
+ -- 5 @-(r) s_dstw_dec r-=s
+ -- s_dstw_dec1 rreq (r)
+ -- s_dstw_incdef_w get (r)
+ -- s_dstw_def246 wreq @(r)
+ -- s_dstw_def_w ack @(r)
+ -- -> do_fork_next
+ --
+ -- 6 n(r) s_dstw_ind rreq n
+ -- s_dstw_ind_w get n; ea=r+n
+ -- s_dstw_dec1 wreq n(r) check kstack
+ -- s_dstw_def_w ack n(r)
+ -- -> do_fork_next
+ --
+ -- 7 @n(r) s_dstw_ind rreq n
+ -- s_dstw_ind_w get n; ea=r+n
+ -- s_dstw_dec1 rreq n(r)
+ -- s_dstw_incdef_w get n(r)
+ -- s_dstw_def246 wreq @n(r)
+ -- s_dstw_def_w ack @n(r)
+ -- -> do_fork_next
+
+ when s_dstw_def =>
+ ndpcntl.psr_ccwe := '1';
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ nvmcntl.kstack := is_dstkstack1246;
+ do_memwrite(nstate, nvmcntl, s_dstw_def_w);
+
+ when s_dstw_def_w =>
+ nstate := s_dstw_def_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_dstw_inc =>
+ ndpcntl.psr_ccwe := '1';
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for else)
+ do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG); --(...)
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
+ if DSTDEF = '0' then
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ nvmcntl.kstack := is_dstkstack1246;
+ do_memwrite(nstate, nvmcntl, s_dstw_inc_w);
+ nstatus.do_gprwe := '1';
+ else
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := DSTREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '0';
+ do_memread_d(nstate, nvmcntl, s_dstw_incdef_w,
+ is_pci=>R_IDSTAT.is_dstpc);
+ end if;
+
+ when s_dstw_inc_w =>
+ nstate := s_dstw_inc_w;
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := DSTREG;
+ if R_STATUS.do_gprwe = '1' then
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '0';
+ nmmumoni.trace_prev := '1'; -- ssr freeze of prev state
+ ndpcntl.gpr_we := '1'; -- update DST reg
+ end if;
+ nstatus.do_gprwe := '0';
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_dstw_incdef_w =>
+ nstate := s_dstw_incdef_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ nstate := s_dstw_def246;
+ end if;
+
+ when s_dstw_dec =>
+ ndpcntl.psr_ccwe := '1';
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ ndpcntl.ddst_we := '1'; -- update DDST
+ ndpcntl.gpr_adst := DSTREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '1';
+ nstate := s_dstw_dec1;
+
+ when s_dstw_dec1 =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = from idec (for if)
+ if DSTDEF = '0' then
+ nvmcntl.kstack := is_dstkstack1246;
+ do_memwrite(nstate, nvmcntl, s_dstw_def_w);
+ else
+ do_memread_d(nstate, nvmcntl, s_dstw_incdef_w);
+ end if;
+
+ when s_dstw_ind =>
+ ndpcntl.psr_ccwe := '1';
+ do_memread_i(nstate, ndpcntl, nvmcntl, s_dstw_ind_w);
+
+ when s_dstw_ind_w =>
+ nstate := s_dstw_ind_w;
+ if R_IDSTAT.is_dstpc = '0' then
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
+ else
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
+ end if;
+ ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ nstate := s_dstw_dec1;
+ end if;
+
+ when s_dstw_def246 =>
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ do_memwrite(nstate, nvmcntl, s_dstw_def_w);
+
+ -- destination address states -----------------------------------------------
+ -- flows:
+ -- 1 (r) -> do_fork_opa
+ --
+ -- 2 (r)+ s_dsta_inc r+=2
+ -- -> do_fork_opa
+ --
+ -- 3 @(r)+ s_dsta_inc req (r); r+=s
+ -- s_dsta_incdef_w get (r)
+ -- -> do_fork_opa
+ --
+ -- 4 -(r) s_dsta_dec r-=s
+ -- s_dsta_dec1 ?? FIXME ?? what is done here ??
+ -- -> do_fork_opa
+ --
+ -- 5 @-(r) s_dsta_dec r-=s
+ -- s_dsta_dec1 req (r)
+ -- s_dsta_incdef_w get (r)
+ -- -> do_fork_opa
+ --
+ -- 6 n(r) s_dsta_ind req n
+ -- s_dsta_ind_w get n; ea=r+n
+ -- s_dsta_dec1 ?? FIXME ?? what is done here ??
+ -- -> do_fork_opa
+ --
+ -- 7 @n(r) s_dsta_ind req n
+ -- s_dsta_ind_w get n; ea=r+n
+ -- s_dsta_dec1 req n(r)
+ -- s_dsta_incdef_w get n(r)
+ -- -> do_fork_opa
+
+ when s_dsta_inc =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_const := "000000010";
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := DSTREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '0';
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
+ if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ end if;
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ if DSTDEF = '0' then
+ do_fork_opa(nstate, R_IDSTAT);
+ else
+ do_memread_d(nstate, nvmcntl, s_dsta_incdef_w,
+ is_pci=>R_IDSTAT.is_dstpc);
+ end if;
+
+ when s_dsta_incdef_w =>
+ nstate := s_dsta_incdef_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ do_fork_opa(nstate, R_IDSTAT);
+ end if;
+
+ when s_dsta_dec =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_const := "000000010";
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(2)
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ ndpcntl.ddst_we := '1'; -- update DDST
+ ndpcntl.gpr_adst := DSTREG;
+ ndpcntl.gpr_we := '1';
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '1';
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
+ if R_IDSTAT.updt_dstadsrc = '1' then -- prevent stale DSRC copy
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ end if;
+ nstate := s_dsta_dec1;
+
+ when s_dsta_dec1 =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ if DSTDEF = '0' then -- check here used also by
+ do_fork_opa(nstate, R_IDSTAT); -- s_dsta_ind flow !!
+ else
+ do_memread_d(nstate, nvmcntl, s_dsta_incdef_w);
+ end if;
+
+ when s_dsta_ind =>
+ do_memread_i(nstate, ndpcntl, nvmcntl, s_dsta_ind_w);
+
+ when s_dsta_ind_w =>
+ nstate := s_dsta_ind_w;
+ if R_IDSTAT.is_dstpc = '0' then
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
+ else
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
+ end if;
+ ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- update DDST
+ nstate := s_dsta_dec1;
+ end if;
+
+ -- instruction operate states -----------------------------------------------
+
+ when s_op_halt => -- HALT
+ if is_kmode = '1' then -- if in kernel mode execute
+ nmmumoni.idone := '1';
+ nstatus.cpugo := '0';
+ nstatus.cpuhalt := '1';
+ nstatus.cpurust := c_cpurust_halt;
+ nstate := s_idle;
+ else -- otherwise trap
+ ncpuerr.illhlt := '1';
+ nstate := s_trap_4; -- trap 4 like 11/70
+ end if;
+
+ when s_op_wait => -- WAIT
+ nstate := s_op_wait; -- spin here
+ if is_kmode = '0' then -- but act as nop if not in kernel
+ nstate := s_idle;
+ elsif int_pending = '1' or -- bail out if pending interrupt
+ R_STATUS.cpustep='1' then -- or the instruction is only stepped
+ nstate := s_idle;
+ elsif R_STATUS.cmdbusy = '1' then -- suspend if a cp command is pending
+ nstatus.waitsusp := '1';
+ nstate := s_idle;
+ else
+ nstatus.cpuwait := '1'; -- if spinning here, signal with cpuwait
+ end if;
+
+ when s_op_trap => -- traps
+ lvector := "0000" & R_IDSTAT.trap_vec; -- vector
+ do_start_int(nstate, ndpcntl, lvector);
+
+ when s_op_reset => -- RESET
+ if is_kmode = '1' then -- if in kernel mode execute
+ nbreset := '1';
+ end if;
+ nstate := s_idle;
+
+ when s_op_rts => -- RTS
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := c_gpr_pc;
+ ndpcntl.gpr_we := '1'; -- load PC with reg(dst)
+ nstate := s_op_rts_pop;
+
+ when s_op_rts_pop =>
+ do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_rts_pop_w,
+ nmmumoni, updt_sp=>'1');
+
+ when s_op_rts_pop_w =>
+ nstate := s_op_rts_pop_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.gpr_adst := DSTREG;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.gpr_we := '1'; -- load R with (SP)+
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_op_spl => -- SPL
+ ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
+ ndpcntl.psr_func := c_psr_func_wspl;
+ if is_kmode = '1' then -- active only in kernel mode
+ ndpcntl.psr_we := '1';
+ nstate := s_ifetch; -- unconditionally fetch next
+ -- instruction like a 11/70
+ -- no interrupt recognition !
+ else
+ do_fork_next(nstate, nstatus, nmmumoni); -- in non-kernel, noop
+ end if;
+
+ when s_op_mcc => -- CLx/SEx
+ ndpcntl.dres_sel := c_dpath_res_ireg; -- DRES = IREG
+ ndpcntl.psr_func := c_psr_func_wcc;
+ ndpcntl.psr_we := '1';
+ do_fork_next(nstate, nstatus, nmmumoni);
+
+ when s_op_br => -- BR
+ nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
+ ndpcntl.ounit_bsel := c_ounit_bsel_ireg8;-- OUNIT B = IREG8
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ -- note: cc are NZVC
+ case brcode(3 downto 1) is
+ when "000" => -- BR
+ brcond := '1';
+ when "001" => -- BNE/BEQ: if Z = x
+ brcond := PSW.cc(2);
+ when "010" => -- BGE/BLT: if N xor V = x
+ brcond := PSW.cc(3) xor PSW.cc(1);
+ when "011" => -- BGT/BLE: if Z or (N xor V) = x
+ brcond := PSW.cc(2) or (PSW.cc(3) xor PSW.cc(1));
+ when "100" => -- BPL/BMI: if N = x
+ brcond := PSW.cc(3);
+ when "101" => -- BHI/BLOS:if C or Z = x
+ brcond := PSW.cc(2) or PSW.cc(0);
+ when "110" => -- BVC/BVS: if V = x
+ brcond := PSW.cc(1);
+ when "111" => -- BCC/BCS: if C = x
+ brcond := PSW.cc(0);
+ when others => null;
+ end case;
+
+ ndpcntl.gpr_adst := c_gpr_pc;
+ if brcond = brcode(0) then -- this coding creates redundant code
+ ndpcntl.gpr_we := '1'; -- but synthesis optimizes this way !
+ do_fork_next(nstate, nstatus, nmmumoni);
+ else
+ do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
+ end if;
+
+ when s_op_mark => -- MARK
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
+ ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
+ ndpcntl.gpr_adst := c_gpr_r5; -- fetch r5
+ ndpcntl.ddst_sel := c_dpath_ddst_dst;
+ ndpcntl.ddst_we := '1';
+ nstate := s_op_mark1;
+
+ when s_op_mark1 =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := c_gpr_pc;
+ ndpcntl.gpr_we := '1'; -- load PC with r5
+ nstate := s_op_mark_pop;
+
+ when s_op_mark_pop =>
+ do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_op_mark_pop_w,
+ nmmumoni, updt_sp=>'1');
+
+ when s_op_mark_pop_w =>
+ nstate := s_op_mark_pop_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.gpr_adst := c_gpr_r5;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.gpr_we := '1'; -- load R5 with (sp)+
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_op_sob => -- SOB (dec)
+ -- comment fork_next_pref out (blog 2006-10-02) due to synthesis impact
+ --nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
+ --ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
+ ndpcntl.dres_sel := R_IDSTAT.res_sel;
+ ndpcntl.gpr_adst := SRCREG;
+ ndpcntl.gpr_we := '1';
+
+ if DP_STAT.ccout_z = '0' then -- if z=0 branch, if z=1 fall thru
+ nstate := s_op_sob1;
+ else
+ --do_fork_next_pref(nstate, ndpcntl, nvmcntl, nmmumoni);
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_op_sob1 => -- SOB (br)
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
+ ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := c_gpr_pc;
+ ndpcntl.gpr_we := '1';
+ do_fork_next(nstate, nstatus, nmmumoni);
+
+ when s_opg_gen =>
+ nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
+ ndpcntl.gpr_bytop := R_IDSTAT.is_bytop;
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+
+ if R_IDSTAT.op_mov = '1' then -- in case of MOV xx,R
+ ndpcntl.gpr_bytop := '0'; -- no bytop, do sign extend
+ end if;
+
+ ndpcntl.psr_ccwe := '1';
+
+ if R_IDSTAT.is_dstw_reg = '1' then
+ ndpcntl.gpr_we := '1';
+ end if;
+
+ if R_IDSTAT.is_rmwop = '1' then
+ do_memwrite(nstate, nvmcntl, s_opg_gen_rmw_w, macc=>'1');
+ else
+ if R_STATUS.prefdone = '1' then
+ nstatus.prefdone :='0';
+ nstate := s_ifetch_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ireg_we := '1';
+ nstate := s_idecode;
+ end if;
+ else
+ if R_IDSTAT.is_dstw_pc = '1' then
+ nstate := s_idle;
+ else
+ do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
+ end if;
+ end if;
+ end if;
+
+ when s_opg_gen_rmw_w =>
+ nstate := s_opg_gen_rmw_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_opg_mul => -- MUL (oper)
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ ndpcntl.gpr_adst := SRCREG; -- write high order result
+ ndpcntl.gpr_we := '1';
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := '1'; -- capture high order part
+ ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
+ ndpcntl.dtmp_we := '1'; -- capture low order part
+ nstate := s_opg_mul1;
+
+ when s_opg_mul1 => -- MUL (write odd reg)
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
+ ndpcntl.gpr_we := '1';
+ ndpcntl.psr_ccwe := '1';
+ do_fork_next(nstate, nstatus, nmmumoni);
+
+ when s_opg_div => -- DIV (load dd_low)
+ ndpcntl.munit_s_div := '1';
+ ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
+ ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
+ ndpcntl.dtmp_we := '1';
+ nstate := s_opg_div_cn;
+
+ when s_opg_div_cn => -- DIV (1st...16th cycle)
+ ndpcntl.munit_s_div_cn := '1';
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
+ nstate := s_opg_div_cn;
+ if DP_STAT.div_quit = '1' then
+ nstate := s_opg_div_quit;
+ else
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ ndpcntl.dtmp_we := '1'; -- update DTMP
+ end if;
+ if DP_STAT.shc_tc = '1' then
+ nstate := s_opg_div_cr;
+ end if;
+
+ when s_opg_div_cr => -- DIV (remainder correction)
+ ndpcntl.munit_s_div_cr := '1';
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
+ nstate := s_opg_div_sq;
+
+ when s_opg_div_sq => -- DIV (correct and store quotient)
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
+ ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := SRCREG; -- write result
+ ndpcntl.gpr_we := '1';
+ ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
+ ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
+ nstate := s_opg_div_sr;
+
+ when s_opg_div_sr => -- DIV (store remainder)
+ ndpcntl.munit_s_div_sr := '1';
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
+ ndpcntl.gpr_we := '1';
+ ndpcntl.psr_ccwe := '1';
+ if DP_STAT.div_quit = '1' then
+ nstate := s_opg_div_quit;
+ else
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_opg_div_quit => -- DIV (0/ or /0 or V=1 aborts)
+ ndpcntl.psr_ccwe := '1';
+ do_fork_next(nstate, nstatus, nmmumoni);
+
+ when s_opg_ash => -- ASH (load shc)
+ ndpcntl.munit_s_ash := '1';
+ nstate := s_opg_ash_cn;
+
+ when s_opg_ash_cn => -- ASH (shift cycles)
+ nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.gpr_adst := SRCREG; -- write result
+ ndpcntl.munit_s_ash_cn := '1';
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
+ nstate := s_opg_ash_cn;
+ if DP_STAT.shc_tc = '0' then
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ else
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_we := '1';
+ ndpcntl.psr_ccwe := '1';
+ do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
+ end if;
+
+ when s_opg_ashc => -- ASHC (load low, load shc)
+ ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
+ ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
+ ndpcntl.dtmp_we := '1';
+ ndpcntl.munit_s_ashc := '1';
+ nstate := s_opg_ashc_cn;
+
+ when s_opg_ashc_cn => -- ASHC (shift cycles)
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.gpr_adst := SRCREG; -- write result
+ ndpcntl.munit_s_ashc_cn := '1';
+ nstate := s_opg_ashc_cn;
+ if DP_STAT.shc_tc = '0' then
+ ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ ndpcntl.dtmp_we := '1'; -- update DTMP
+ else
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_we := '1';
+ ndpcntl.psr_ccwe := '1';
+ nstate := s_opg_ashc_wl;
+ end if;
+
+ when s_opg_ashc_wl => -- ASHC (write low)
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
+ ndpcntl.gpr_we := '1';
+ do_fork_next(nstate, nstatus, nmmumoni);
+
+ -- dsta mode operations -----------------------------------------------------
+
+ when s_opa_jsr =>
+ ndpcntl.gpr_asrc := c_gpr_sp; -- (for else)
+ ndpcntl.dsrc_sel := c_dpath_dsrc_src; -- DSRC = regfile (for else)
+ if R_IDSTAT.is_dstmode0 = '1' then
+ nstate := s_trap_10; -- trap 10 like 11/70
+ else
+ ndpcntl.dsrc_we := '1';
+ nstate := s_opa_jsr1;
+ end if;
+
+ when s_opa_jsr1 =>
+ ndpcntl.gpr_asrc := SRCREG;
+ ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
+ ndpcntl.dtmp_we := '1';
+
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_const := "000000010";
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
+ ndpcntl.dsrc_we := '1'; -- update DDST
+ ndpcntl.gpr_adst := c_gpr_sp;
+ ndpcntl.gpr_we := '1'; -- update SP
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '1';
+ nstate := s_opa_jsr_push;
+
+ when s_opa_jsr_push =>
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ nvmcntl.dspace := '1';
+ nvmcntl.kstack := is_kmode;
+ nvmcntl.wacc := '1';
+ nvmcntl.req := '1';
+ nstate := s_opa_jsr_push_w;
+
+ when s_opa_jsr_push_w =>
+ nstate := s_opa_jsr_push_w;
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := SRCREG;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.gpr_we := '1'; -- load R with PC
+ nstate := s_opa_jsr2;
+ end if;
+
+ when s_opa_jsr2 =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := c_gpr_pc;
+ ndpcntl.gpr_we := '1'; -- load PC with dsta
+ do_fork_next(nstate, nstatus, nmmumoni);
+
+ when s_opa_jmp =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := c_gpr_pc;
+ if R_IDSTAT.is_dstmode0 = '1' then
+ nstate := s_trap_10; -- trap 10 like 11/70
+ else
+ ndpcntl.gpr_we := '1'; -- load PC with dsta
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_opa_mtp =>
+ do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_opa_mtp_pop_w,
+ nmmumoni, updt_sp=>'1');
+
+ when s_opa_mtp_pop_w =>
+ nstate := s_opa_mtp_pop_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.dtmp_we := '1'; -- load DTMP
+ if R_IDSTAT.is_dstmode0 = '1' then -- handle register access
+ nstate := s_opa_mtp_reg;
+ else
+ case R_IDSTAT.fork_dsta is -- 2nd dsta fork in s_idecode
+ when c_fork_dsta_def => nstate := s_opa_mtp_mem;
+ when c_fork_dsta_inc => nstate := s_dsta_inc;
+ when c_fork_dsta_dec => nstate := s_dsta_dec;
+ when c_fork_dsta_ind => nstate := s_dsta_ind;
+ when others => nstate := s_cpufail;
+ end case;
+ end if;
+ end if;
+ ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
+ ndpcntl.ddst_we := '1'; -- update DDST (needed for sp)
+
+ when s_opa_mtp_reg =>
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
+ ndpcntl.gpr_mode := PSW.pmode; -- load reg in pmode
+ ndpcntl.gpr_we := '1';
+ do_fork_next(nstate, nstatus, nmmumoni);
+
+ when s_opa_mtp_mem =>
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst;-- VA = DDST
+ nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
+ nvmcntl.mode := PSW.pmode;
+ nvmcntl.wacc := '1';
+ nvmcntl.req := '1';
+ nstate := s_opa_mtp_mem_w;
+
+ when s_opa_mtp_mem_w =>
+ nstate := s_opa_mtp_mem_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ when s_opa_mfp_reg =>
+ ndpcntl.gpr_mode := PSW.pmode; -- fetch reg in pmode
+ ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = reg(dst)
+ ndpcntl.ddst_we := '1';
+ nstate := s_opa_mfp_dec;
+
+ when s_opa_mfp_mem =>
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
+ if PSW.cmode=c_psw_umode and -- if cm=pm=user then
+ PSW.cmode=c_psw_umode then -- MFPI works like it
+ nvmcntl.dspace := '1'; -- were MFPD
+ else
+ nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
+ end if;
+ nvmcntl.mode := PSW.pmode;
+ nvmcntl.req := '1';
+ nstate := s_opa_mfp_mem_w;
+
+ when s_opa_mfp_mem_w =>
+ nstate := s_opa_mfp_mem_w;
+ do_memcheck(nstate, nstatus, imemok);
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ if imemok then
+ ndpcntl.ddst_we := '1';
+ nstate := s_opa_mfp_dec;
+ end if;
+
+ when s_opa_mfp_dec =>
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_const := "000000010";
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ ndpcntl.gpr_adst := c_gpr_sp;
+ ndpcntl.gpr_we := '1'; -- update SP
+ nmmumoni.regmod := '1';
+ nmmumoni.isdec := '1';
+ nstate := s_opa_mfp_push;
+
+ when s_opa_mfp_push =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ nvmcntl.dspace := '1';
+ nvmcntl.kstack := is_kmode;
+ nvmcntl.wacc := '1';
+ nvmcntl.req := '1';
+ nstate := s_opa_mfp_push_w;
+
+ when s_opa_mfp_push_w =>
+ nstate := s_opa_mfp_push_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ -- trap and interrupt handling states ---------------------------------------
+
+ when s_trap_4 =>
+ lvector := "0000001"; -- vector (4)
+ do_start_int(nstate, ndpcntl, lvector);
+
+ when s_trap_10 =>
+ lvector := "0000010"; -- vector (10)
+ do_start_int(nstate, ndpcntl, lvector);
+
+ when s_trap_disp =>
+ if R_STATUS.trap_mmu = '1' then
+ nvmcntl.trap_done := '1'; -- mmu trap taken: set ssr0 trap bit
+ lvector := "0101010"; -- mmu trap: vector (250)
+ elsif R_STATUS.trap_ysv = '1' then
+ lvector := "0000001"; -- ysv trap: vector (4)
+ ncpuerr.ysv := '1';
+ else
+ lvector := "0000011"; -- trace trap: vector (14)
+ end if;
+ nstatus.trap_mmu := '0'; -- clear pending trap flags
+ nstatus.trap_ysv := '0'; --
+ do_start_int(nstate, ndpcntl, lvector);
+
+ when s_int_ext =>
+ lvector := R_STATUS.intvect; -- external vector
+ do_start_int(nstate, ndpcntl, lvector);
+
+ when s_int_getpc =>
+ nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
+ do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_int_getpc_w, nmmumoni);
+
+ when s_int_getpc_w =>
+ nstate := s_int_getpc_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if VM_STAT.err = '1' then -- in case of vm-err
+ nstatus.cpugo := '0'; -- non-recoverable error
+ nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
+ nstate := s_idle;
+ end if;
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- DDST = new PC
+ nstate := s_int_getps;
+ end if;
+
+ when s_int_getps =>
+ nvmcntl.mode := c_psw_kmode; -- fetch PS from kernel D space
+ do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_int_getps_w, nmmumoni);
+
+ when s_int_getps_w =>
+ nstate := s_int_getps_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.psr_func := c_psr_func_wint; -- interupt mode write
+ do_memcheck(nstate, nstatus, imemok);
+ if VM_STAT.err = '1' then -- in case of vm-err
+ nstatus.cpugo := '0'; -- non-recoverable error
+ nstatus.cpurust := c_cpurust_vecfet; -- halt CPU
+ nstate := s_idle;
+ end if;
+ if imemok then
+ ndpcntl.psr_we := '1'; -- store new PS
+ nstate := s_int_getsp;
+ end if;
+
+ when s_int_getsp =>
+ ndpcntl.gpr_asrc := c_gpr_sp;
+ ndpcntl.dsrc_we := '1'; -- DSRC = SP (in new mode)
+ nstate := s_int_decsp;
+
+ when s_int_decsp =>
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ ndpcntl.gpr_adst := c_gpr_sp;
+ ndpcntl.gpr_we := '1'; -- update SP too
+ nstate := s_int_pushps;
+
+ when s_int_pushps =>
+ ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP (old PS)
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ nvmcntl.wacc := '1'; -- write mem
+ nvmcntl.dspace := '1';
+ nvmcntl.kstack := is_kmode;
+ nvmcntl.req := '1';
+ nstate := s_int_pushps_w;
+
+ when s_int_pushps_w =>
+ ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
+ ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
+ ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
+ ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
+ ndpcntl.gpr_adst := c_gpr_sp;
+
+ nstate := s_int_pushps_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.dsrc_we := '1'; -- update DSRC
+ ndpcntl.gpr_we := '1'; -- update SP too
+ nstate := s_int_pushpc;
+ end if;
+
+ when s_int_pushpc =>
+ ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
+ nvmcntl.wacc := '1'; -- write mem
+ nvmcntl.dspace := '1';
+ nvmcntl.kstack := is_kmode;
+ nvmcntl.req := '1';
+ nstate := s_int_pushpc_w;
+
+ when s_int_pushpc_w =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := c_gpr_pc;
+
+ nstate := s_int_pushpc_w;
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ nstatus.do_intrsv := '0'; -- signal end of rsv
+ ndpcntl.gpr_we := '1'; -- load new PC
+ do_fork_next(nstate, nstatus, nmmumoni); -- ???
+ end if;
+
+ -- return from trap or interrupt handling states ----------------------------
+
+ when s_rti_getpc =>
+ do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getpc_w,
+ nmmumoni, updt_sp=>'1');
+
+ when s_rti_getpc_w =>
+ nstate := s_rti_getpc_w;
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
+ do_memcheck(nstate, nstatus, imemok);
+ if imemok then
+ ndpcntl.ddst_we := '1'; -- DDST = new PC
+ nstate := s_rti_getps;
+ end if;
+
+ when s_rti_getps =>
+ do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_rti_getps_w,
+ nmmumoni, updt_sp=>'1');
+
+ when s_rti_getps_w =>
+ nstate := s_rti_getps_w;
+ do_memcheck(nstate, nstatus, imemok);
+ ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
+ if is_kmode = '1' then -- if in kernel mode
+ ndpcntl.psr_func := c_psr_func_wall; -- write all fields
+ else
+ ndpcntl.psr_func := c_psr_func_wrti; -- otherwise filter
+ end if;
+ if imemok then
+ ndpcntl.psr_we := '1'; -- load new PS
+ nstate := s_rti_newpc;
+ end if;
+
+ when s_rti_newpc =>
+ ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_adst := c_gpr_pc;
+ ndpcntl.gpr_we := '1'; -- load new PC
+ if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
+ nstate := s_ifetch; -- force fetch
+ else -- otherwise RTI
+ do_fork_next(nstate, nstatus, nmmumoni);
+ end if;
+
+ -- exception abort states ---------------------------------------------------
+
+ when s_vmerr =>
+ nstate := s_cpufail;
+
+ -- setup for R_VMSTAT.err_rsv='1'
+ ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
+ ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
+ ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
+ ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
+ ndpcntl.gpr_mode := c_psw_kmode; -- set kmode SP to 4
+ ndpcntl.gpr_adst := c_gpr_sp;
+
+ nstatus.trap_mmu :='0'; -- drop pending mmu trap
+
+ if R_VMSTAT.fail = '1' then -- vmbox failure
+ nstatus.cpugo := '0'; -- halt cpu
+ nstatus.cpurust := c_cpurust_vfail;
+ nstate := s_idle;
+
+ elsif R_STATUS.do_intrsv = '1' then -- double error
+ nstatus.cpugo := '0'; -- give up, HALT cpu
+ nstatus.cpurust := c_cpurust_recrsv;
+ nstate := s_idle;
+
+ elsif R_VMSTAT.err = '1' then -- normal vm errors
+ if R_VMSTAT.err_rsv = '1' then
+ nstatus.do_intrsv := '1'; -- signal start of rsv
+ ndpcntl.gpr_we := '1';
+
+ if R_VMSTAT.err_odd='1' or R_VMSTAT.err_mmu='1' then
+ ncpuerr.adderr := '1';
+ elsif R_VMSTAT.err_nxm = '1' then
+ ncpuerr.nxm := '1';
+ elsif R_VMSTAT.err_iobto = '1' then
+ ncpuerr.iobto := '1';
+ end if;
+ ncpuerr.rsv := '1';
+ nstate := s_trap_4;
+
+ elsif R_VMSTAT.err_odd = '1' then
+ ncpuerr.adderr := '1';
+ nstate := s_trap_4;
+ elsif R_VMSTAT.err_nxm = '1' then
+ ncpuerr.nxm := '1';
+ nstate := s_trap_4;
+ elsif R_VMSTAT.err_iobto = '1' then
+ ncpuerr.iobto := '1';
+ nstate := s_trap_4;
+
+ elsif R_VMSTAT.err_mmu = '1' then
+ lvector := "0101010"; -- vector (250)
+ do_start_int(nstate, ndpcntl, lvector);
+ end if;
+ end if;
+
+ when s_cpufail =>
+ nstatus.cpugo := '0';
+ nstatus.cpurust := c_cpurust_sfail;
+ nstate := s_idle;
+
+ when others =>
+ nstate := s_cpufail; --!!! catch undefined states !!!
+
+ end case;
+
+ if nstatus.cmdack = '1' then -- cmdack in next cycle ? Yes we test
+ -- nstatus here !!
+ nstatus.cmdbusy := '0';
+ ndpcntl.cpdout_we := '1';
+ end if;
+
+ N_STATE <= nstate;
+ N_STATUS <= nstatus;
+ N_CPUERR <= ncpuerr;
+ N_IDSTAT <= nidstat;
+
+ CRESET <= ncreset;
+ BRESET <= nbreset;
+ INT_ACK <= nintack;
+
+ DP_CNTL <= ndpcntl;
+ VM_CNTL <= nvmcntl;
+
+ nmmumoni.regnum := ndpcntl.gpr_adst;
+ nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
+ MMU_MONI <= nmmumoni;
+
+ end process proc_next;
+
+ proc_cpstat : process (R_STATUS)
+ begin
+ CP_STAT <= cp_stat_init;
+ CP_STAT.cmdbusy <= R_STATUS.cmdbusy;
+ CP_STAT.cmdack <= R_STATUS.cmdack;
+ CP_STAT.cmderr <= R_STATUS.cmderr;
+ CP_STAT.cmdmerr <= R_STATUS.cmdmerr;
+ CP_STAT.cpugo <= R_STATUS.cpugo;
+ CP_STAT.cpustep <= R_STATUS.cpustep;
+ CP_STAT.cpuhalt <= R_STATUS.cpuhalt;
+ CP_STAT.cpuwait <= R_STATUS.cpuwait;
+ CP_STAT.cpurust <= R_STATUS.cpurust;
+ end process proc_cpstat;
+
+end syn;
+
Index: pdp11_munit.vhd
===================================================================
--- pdp11_munit.vhd (nonexistent)
+++ pdp11_munit.vhd (revision 26)
@@ -0,0 +1,481 @@
+-- $Id: pdp11_munit.vhd 577 2014-08-03 20:49:42Z mueller $
+--
+-- Copyright 2006-2014 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_munit - syn
+-- Description: pdp11: mul/div unit for data (munit)
+--
+-- Dependencies: -
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri
+-- 2014-07-12 569 14.7 131013 xc6slx16-2 30 154 0 46 s 6.8
+-- 2014-07-11 568 14.7 131013 xc6slx16-2 28 123 0 47 s 5.6
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2014-08-05 578 1.2.3 fix proc_div sensitivity list
+-- 2014-08-03 577 1.2.2 use DTMP_POS rather signed(Q)>0 (xst bug for S-3)
+-- 2014-07-26 575 1.2.1 fix proc_omux sensitivity list
+-- 2014-07-12 569 1.2 merge DIV_ZERO+DIV_OVFL to DIV_QUIT; add S_DIV_SR
+-- BUGFIX: fix divide logic, dr+q max neg issues
+-- 2011-11-18 427 1.1.1 now numeric_std clean
+-- 2010-09-18 300 1.1 renamed from mbox
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_munit is -- mul/div unit for data (munit)
+ port (
+ CLK : in slbit; -- clock
+ DSRC : in slv16; -- 'src' data in
+ DDST : in slv16; -- 'dst' data in
+ DTMP : in slv16; -- 'tmp' data in
+ GPR_DSRC : in slv16; -- 'src' data from GPR
+ FUNC : in slv2; -- function
+ S_DIV : in slbit; -- s_opg_div state (load dd_low)
+ S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)
+ S_DIV_CR : in slbit; -- s_opg_div_cr state (remainder corr.)
+ S_DIV_SR : in slbit; -- s_opg_div_sr state (store remainder)
+ S_ASH : in slbit; -- s_opg_ash state
+ S_ASH_CN : in slbit; -- s_opg_ash_cn state
+ S_ASHC : in slbit; -- s_opg_ashc state
+ S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
+ SHC_TC : out slbit; -- last shc cycle (shc==0)
+ DIV_CR : out slbit; -- division: remainder correction needed
+ DIV_CQ : out slbit; -- division: quotient correction needed
+ DIV_QUIT : out slbit; -- division: abort (0/ or /0 or V=1)
+ DOUT : out slv16; -- data output
+ DOUTE : out slv16; -- data output extra
+ CCOUT : out slv4 -- condition codes out
+ );
+end pdp11_munit;
+
+architecture syn of pdp11_munit is
+
+ signal R_DD_L : slv16 := (others=>'0'); -- divident, low order part
+ signal R_DDO_LT : slbit := '0'; -- original sign bit of divident
+ signal R_MAXFIX : slbit := '0'; -- maxfix flag for division
+ signal R_QO_LT : slbit := '0'; -- expected q sign for division
+ signal R_DIV_V : slbit := '0'; -- V flag for division
+ signal R_SHC : slv6 := (others=>'0'); -- shift counter for div and ash/c
+ signal R_C1 : slbit := '0'; -- first cycle indicator
+ signal R_MSBO : slbit := '0'; -- original sign bit for ash/c
+ signal R_ASH_V : slbit := '0'; -- V flag for ash/c
+ signal R_ASH_C : slbit := '0'; -- C flag for ash/c
+
+ signal NEXT_DD_L : slv16 := (others=>'0');
+ signal NEXT_DDO_LT : slbit := '0';
+ signal NEXT_MAXFIX : slbit := '0';
+ signal NEXT_QO_LT : slbit := '0';
+ signal NEXT_DIV_V : slbit := '0';
+ signal NEXT_SHC : slv6 := (others=>'0');
+ signal NEXT_C1 : slbit := '0';
+ signal NEXT_MSBO : slbit := '0';
+ signal NEXT_ASH_V : slbit := '0';
+ signal NEXT_ASH_C : slbit := '0';
+
+ signal SHC_TC_L : slbit := '0';
+
+ signal DDST_ZERO : slbit := '0';
+ signal DDST_NMAX : slbit := '0';
+ signal DSRC_ZERO : slbit := '0';
+ signal DSRC_ONES : slbit := '0';
+ signal DTMP_ZERO : slbit := '0';
+ signal DTMP_POS : slbit := '0';
+
+ signal DOUT_DIV : slv16 := (others=>'0');
+ signal DOUTE_DIV : slv16 := (others=>'0');
+
+ alias DR : slv16 is DDST; -- divisor (in DDST)
+ alias DD_H : slv16 is DSRC; -- divident, high order part (in DSRC)
+ alias Q : slv16 is DTMP; -- quotient (accumulated in DTMP)
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ R_DD_L <= NEXT_DD_L;
+ R_DDO_LT <= NEXT_DDO_LT;
+ R_MAXFIX <= NEXT_MAXFIX;
+ R_QO_LT <= NEXT_QO_LT;
+ R_DIV_V <= NEXT_DIV_V;
+ R_SHC <= NEXT_SHC;
+ R_C1 <= NEXT_C1;
+ R_MSBO <= NEXT_MSBO;
+ R_ASH_V <= NEXT_ASH_V;
+ R_ASH_C <= NEXT_ASH_C;
+ end if;
+ end process proc_regs;
+
+ proc_comm: process (DDST, DSRC, DTMP)
+ begin
+
+ DDST_ZERO <= '0';
+ DDST_NMAX <= '0';
+ DSRC_ZERO <= '0';
+ DSRC_ONES <= '0';
+ DTMP_ZERO <= '0';
+ DTMP_POS <= '0';
+
+ if unsigned(DDST) = 0 then
+ DDST_ZERO <= '1';
+ end if;
+ if DDST = "1000000000000000" then
+ DDST_NMAX <= '1';
+ end if;
+ if unsigned(DSRC) = 0 then
+ DSRC_ZERO <= '1';
+ end if;
+ if signed(DSRC) = -1 then
+ DSRC_ONES <= '1';
+ end if;
+ if unsigned(DTMP) = 0 then
+ DTMP_ZERO <= '1';
+ end if;
+ if signed(DTMP) > 0 then
+ DTMP_POS <= '1';
+ end if;
+
+ end process proc_comm;
+
+ proc_shc: process (DDST, R_SHC, R_C1,
+ S_DIV, S_DIV_CN, S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN)
+ begin
+
+ NEXT_SHC <= R_SHC;
+ NEXT_C1 <= R_C1;
+
+ if S_ASH='1' or S_ASHC='1' then
+ NEXT_SHC <= DDST(5 downto 0);
+ NEXT_C1 <= '1';
+ end if;
+ if S_DIV = '1' then
+ NEXT_SHC <= "001111";
+ NEXT_C1 <= '1';
+ end if;
+
+ if S_DIV_CN='1' or S_ASH_CN='1' or S_ASHC_CN='1' then
+ if R_SHC(5) = '0' then
+ NEXT_SHC <= slv(unsigned(R_SHC) - 1);
+ else
+ NEXT_SHC <= slv(unsigned(R_SHC) + 1);
+ end if;
+ NEXT_C1 <= '0';
+ end if;
+
+ SHC_TC_L <= '0';
+ if unsigned(R_SHC) = 0 then
+ SHC_TC_L <= '1';
+ end if;
+
+ end process proc_shc;
+
+ proc_div: process (DDST, DSRC, DTMP, GPR_DSRC, DR, DD_H, Q,
+ R_DD_L, R_DDO_LT, R_MAXFIX, R_QO_LT, R_DIV_V, R_SHC, R_C1,
+ S_DIV, S_DIV_CN, S_DIV_CR, S_DIV_SR,
+ DDST_ZERO, DDST_NMAX, DSRC_ZERO, DTMP_ZERO, DTMP_POS)
+
+ variable div_zero : slbit := '0';
+ variable div_ovfl : slbit := '0';
+ variable shftdd : slbit := '0';
+ variable subadd : slbit := '0';
+
+ variable dd_le : slbit := '0';
+ variable dd_ge : slbit := '0';
+ variable dd_gt : slbit := '0';
+
+ variable qbit : slbit := '0';
+ variable qbit_1 : slbit := '0';
+ variable qbit_n : slbit := '0';
+
+ variable dd_h_old : slv16 := (others=>'0'); -- dd_h before add/sub
+ variable dd_h_new : slv16 := (others=>'0'); -- dd_h after add/sub
+
+ begin
+
+ NEXT_DD_L <= R_DD_L;
+ NEXT_DDO_LT <= R_DDO_LT;
+ NEXT_MAXFIX <= R_MAXFIX;
+ NEXT_QO_LT <= R_QO_LT;
+ NEXT_DIV_V <= R_DIV_V;
+
+ div_zero := '0';
+ div_ovfl := '0';
+
+ qbit_1 := not (DR(15) xor DD_H(15)); -- !(dr<0 ^ dd_h<0)
+
+ shftdd := not S_DIV_CR;
+ if shftdd = '1' then
+ dd_h_old := DD_H(14 downto 0) & R_DD_L(15);
+ else
+ dd_h_old := DD_H(15 downto 0);
+ end if;
+
+ if R_C1 = '1' then
+ subadd := qbit_1;
+ else
+ subadd := Q(0);
+ end if;
+
+ if subadd = '0' then
+ dd_h_new := slv(signed(dd_h_old) + signed(DR));
+ else
+ dd_h_new := slv(signed(dd_h_old) - signed(DR));
+ end if;
+
+ dd_le := '0';
+ if signed(dd_h_new) <= 0 then
+ dd_le := '1'; -- set if dd_new_h <= 0
+ end if;
+
+ dd_ge := '0';
+ if signed(dd_h_new) >= -1 then
+ dd_ge := '1'; -- set if dd_new_h >= -1
+ end if;
+
+ dd_gt := '0';
+ if dd_h_new(15) = '0' and
+ (unsigned(dd_h_new(14 downto 0))/=0 or
+ unsigned(R_DD_L(14 downto 0))/=0)
+ then
+ dd_gt := '1'; -- set if dd_new > 0
+ end if;
+
+ if R_DDO_LT = '0' then
+ qbit_n := DR(15) xor not dd_h_new(15); -- b_dr_lt ^ !b_dd_lt
+ else
+ if R_MAXFIX = '0' then
+ qbit_n := DR(15) xor dd_gt; -- b_dr_lt ^ b_dd_gt
+ else
+ qbit_n := dd_h_new(15); -- b_dd_lt
+ end if;
+ end if;
+
+ if S_DIV = '1' then
+ NEXT_DDO_LT <= DD_H(15);
+ NEXT_DD_L <= GPR_DSRC;
+ NEXT_MAXFIX <= '0';
+ if DDST_NMAX = '1' and GPR_DSRC = "0000000000000000" then
+ NEXT_MAXFIX <= '1'; -- b_dr_nmax && (ddi_l == 0)
+ end if;
+ NEXT_QO_LT <= DD_H(15) xor DR(15); -- b_di_lt ^ b_dr_lt
+ end if;
+
+ if R_C1 = '1' then
+ div_zero := DDST_ZERO or
+ (DSRC_ZERO and DTMP_ZERO); -- note: DTMP here still dd_low !
+
+ if DDST_NMAX='0' and (DD_H(15) xor DD_H(14)) = '1' then
+ div_ovfl := '1'; -- !b_dr_nmax && (b_di_31 != b_di_30)
+ end if;
+
+ if R_DDO_LT = '0' then -- if (!b_di_lt)
+ if R_QO_LT = '0' then -- if (!b_qo_lt)
+ if dd_h_new(15) = '0' then -- if (!b_dd_lt)
+ div_ovfl := '1';
+ end if;
+ else -- else
+ if dd_le = '0' then -- if (!b_dd_le)
+ div_ovfl := '1';
+ end if;
+ end if;
+ else
+ if R_QO_LT = '0' then -- if (!b_qo_lt)
+ if dd_gt = '0' then -- if (!b_dd_gt)
+ div_ovfl := '1';
+ end if;
+ else -- else
+ if dd_ge = '0' then -- if (!b_dd_ge)
+ div_ovfl := '1';
+ end if;
+ end if;
+ end if;
+ NEXT_DIV_V <= div_ovfl;
+
+ elsif S_DIV_SR = '1' then
+ if R_QO_LT='1' and DTMP_POS='1' then
+ div_ovfl := '1';
+ end if;
+ NEXT_DIV_V <= div_ovfl;
+ end if;
+
+ if S_DIV_CN = '1' then
+ NEXT_DD_L <= R_DD_L(14 downto 0) & '0';
+ end if;
+
+ if S_DIV_CN = '1' then
+ qbit := qbit_n;
+ else
+ qbit := qbit_1;
+ end if;
+
+ DIV_QUIT <= div_zero or div_ovfl;
+
+ DIV_CR <= R_MAXFIX or -- b_maxfix | (!(b_ddo_lt ^ (b_dr_lt ^ b_qbit)))
+ (not (R_DDO_LT xor (DR(15) xor Q(0))));
+ DIV_CQ <= R_MAXFIX or -- b_maxfix | (b_ddo_lt ^ b_dr_lt)
+ (R_DDO_LT xor DR(15));
+
+ DOUT_DIV <= dd_h_new;
+ DOUTE_DIV <= Q(14 downto 0) & qbit;
+
+ end process proc_div;
+
+ proc_ash: process (R_MSBO, R_ASH_V, R_ASH_C, R_SHC, DSRC, DTMP, FUNC,
+ S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN, SHC_TC_L)
+ begin
+
+ NEXT_MSBO <= R_MSBO;
+ NEXT_ASH_V <= R_ASH_V;
+ NEXT_ASH_C <= R_ASH_C;
+
+ if S_ASH='1' or S_ASHC='1' then
+ NEXT_MSBO <= DSRC(15);
+ NEXT_ASH_V <= '0';
+ NEXT_ASH_C <= '0';
+ end if;
+
+ if (S_ASH_CN='1' or S_ASHC_CN='1') and SHC_TC_L='0' then
+ if R_SHC(5) = '0' then -- left shift
+ if (R_MSBO xor DSRC(14))='1' then
+ NEXT_ASH_V <= '1';
+ end if;
+ NEXT_ASH_C <= DSRC(15);
+ else -- right shift
+ if FUNC = c_munit_func_ash then
+ NEXT_ASH_C <= DSRC(0);
+ else
+ NEXT_ASH_C <= DTMP(0);
+ end if;
+ end if;
+ end if;
+
+ end process proc_ash;
+
+ proc_omux: process (DSRC, DDST, DTMP, FUNC,
+ R_ASH_V, R_ASH_C, R_SHC, R_DIV_V, R_QO_LT,
+ DOUT_DIV, DOUTE_DIV,
+ DSRC_ZERO, DSRC_ONES, DTMP_ZERO, DDST_ZERO)
+
+ variable prod : slv32 := (others=>'0');
+ variable omux_sel : slv2 := "00";
+ variable ash_dout0 : slbit := '0';
+
+ variable mul_c : slbit := '0';
+
+ begin
+
+ prod := slv(signed(DSRC) * signed(DDST));
+
+ case FUNC is
+ when c_munit_func_mul =>
+ omux_sel := "00";
+ when c_munit_func_div =>
+ omux_sel := "01";
+ when c_munit_func_ash |c_munit_func_ashc =>
+ if R_SHC(5) = '0' then
+ omux_sel := "10";
+ else
+ omux_sel := "11";
+ end if;
+ when others => null;
+ end case;
+
+ if FUNC = c_munit_func_ash then
+ ash_dout0 := '0';
+ else
+ ash_dout0 := DTMP(15);
+ end if;
+
+ case omux_sel is
+ when "00" => -- MUL
+ DOUT <= prod(31 downto 16);
+ DOUTE <= prod(15 downto 0);
+ when "01" => -- DIV
+ DOUT <= DOUT_DIV;
+ DOUTE <= DOUTE_DIV;
+ when "10" => -- shift left
+ DOUT <= DSRC(14 downto 0) & ash_dout0;
+ DOUTE <= DTMP(14 downto 0) & "0";
+ when "11" => -- shift right
+ DOUT <= DSRC(15) & DSRC(15 downto 1);
+ DOUTE <= DSRC(0) & DTMP(15 downto 1);
+ when others => null;
+ end case;
+
+ mul_c := '0'; -- MUL C codes is set if
+ if DSRC(15) = '0' then
+ if DSRC_ZERO='0' or DTMP(15)='1' then -- for positive results when
+ mul_c := '1'; -- product > 2^15-1
+ end if;
+ else -- for negative results when
+ if DSRC_ONES='0' or DTMP(15)='0' then
+ mul_c := '1'; -- product < -2^15
+ end if;
+ end if;
+
+ case FUNC is
+ when c_munit_func_mul =>
+ CCOUT(3) <= DSRC(15); -- N
+ CCOUT(2) <= DSRC_ZERO and DTMP_ZERO;-- Z
+ CCOUT(1) <= '0'; -- V=0
+ CCOUT(0) <= mul_c; -- C
+
+ when c_munit_func_div =>
+ if DDST_ZERO = '1' then
+ CCOUT(3) <= '0'; -- N=0 if div/0
+ CCOUT(2) <= '1'; -- Z=1 if div/0
+ elsif R_DIV_V = '1' then
+ CCOUT(3) <= R_QO_LT; -- N (send expected sign)
+ CCOUT(2) <= '0'; -- Z (from unchanged reg) ??? veri
+ else
+ CCOUT(3) <= DTMP(15); -- N (from Q (DTMP))
+ CCOUT(2) <= DTMP_ZERO; -- Z (from Q (DTMP)) ??? verify
+ end if;
+ CCOUT(1) <= R_DIV_V or DDST_ZERO; -- V
+ CCOUT(0) <= DDST_ZERO; -- C (dst=0)
+
+ when c_munit_func_ash =>
+ CCOUT(3) <= DSRC(15); -- N
+ CCOUT(2) <= DSRC_ZERO; -- Z
+ CCOUT(1) <= R_ASH_V; -- V
+ CCOUT(0) <= R_ASH_C; -- C
+
+ when c_munit_func_ashc =>
+ CCOUT(3) <= DSRC(15); -- N
+ CCOUT(2) <= DSRC_ZERO and DTMP_ZERO;-- Z
+ CCOUT(1) <= R_ASH_V; -- V
+ CCOUT(0) <= R_ASH_C; -- C
+
+ when others => null;
+ end case;
+
+ end process proc_omux;
+
+ SHC_TC <= SHC_TC_L;
+
+end syn;
Index: pdp11.vhd
===================================================================
--- pdp11.vhd (nonexistent)
+++ pdp11.vhd (revision 26)
@@ -0,0 +1,1106 @@
+-- $Id: pdp11.vhd 569 2014-07-13 14:36:32Z mueller $
+--
+-- Copyright 2006-2014 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: pdp11
+-- Description: Definitions for pdp11 components
+--
+-- Dependencies: -
+-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2014-07-12 569 1.4.9 dpath_stat_type: merge div_zero+div_ovfl to div_quit
+-- dpath_cntl_type: add munit_s_div_sr
+-- 2011-11-18 427 1.4.8 now numeric_std clean
+-- 2010-12-30 351 1.4.7 rename pdp11_core_rri->pdp11_core_rbus; use rblib
+-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
+-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
+-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
+-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
+-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
+-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
+-- 2010-06-13 305 1.4 add rnum to cp_cntl_type, cprnum to cpustat_type;
+-- reassign cp command codes and rename: c_cp_func_...
+-- -> c_cpfunc_...; remove cpaddr_(lal|lah|inc) from
+-- dpath_cntl_type; add cpdout_we to dpath_cntl_type;
+-- reassign rbus adresses and rename: c_rb_addr_...
+-- -> c_rbaddr_...; rename rbus fields: c_rb_statf_...
+-- -> c_stat_rbf_...
+-- 2010-06-12 304 1.3.3 add cpuwait to cp_stat_type and cpustat_type
+-- 2010-06-11 303 1.3.2 use IB_MREQ.racc instead of RRI_REQ
+-- 2010-05-02 287 1.3.1 rename RP_STAT->RB_STAT
+-- 2010-05-01 285 1.3 port to rri V2 interface; drop pdp11_rri_2rp;
+-- rename c_rp_addr_* -> c_rb_addr_*
+-- 2010-03-21 270 1.2.6 add pdp11_du_drv
+-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
+-- 2009-05-10 214 1.2.4 add ENA (trace enable) for _tmu; add _pdp11_tmu_sb
+-- 2009-05-09 213 1.2.3 BUGFIX: default for inst_compl now '0'
+-- 2008-12-14 177 1.2.2 add gpr_* fields to DM_STAT_DP
+-- 2008-11-30 174 1.2.1 BUGFIX: add updt_dstadsrc;
+-- 2008-08-22 161 1.2 move slvnn_m subtypes to slvtypes;
+-- move (and rename) intbus defs to iblib package;
+-- move intbus devices to ibdlib package;
+-- rename ubf_ --> ibf_;
+-- 2008-05-09 144 1.1.17 use EI_ACK with _kw11l, _dl11
+-- 2008-05-03 143 1.1.16 rename _cpursta->_cpurust
+-- 2008-04-27 140 1.1.15 add c_cpursta_xxx defs; cpufail->cpursta in cp_stat
+-- 2008-04-25 138 1.1.14 add BRESET port to _mmu, _vmbox, use in _irq
+-- 2008-04-19 137 1.1.13 add _tmu,_sys70 entity, dm_stat_** types and ports
+-- 2008-04-18 136 1.1.12 ibdr_sdreg: use RESET; ibdr_minisys: add RESET
+-- 2008-03-02 121 1.1.11 remove snoopers; add waitsusp in cpustat_type
+-- 2008-02-24 119 1.1.10 add lah,rps,wps commands, cp_addr_type.
+-- _vmbox,_mmu interface changed
+-- 2008-02-17 117 1.1.9 add em_(mreq|sres)_type, pdp11_cache, pdp11_bram
+-- 2008-01-27 115 1.1.8 add pdp11_ubmap, pdp11_mem70
+-- 2008-01-26 114 1.1.7 add c_rp_addr_ibr(b) defs (for ibr addresses)
+-- 2008-01-20 113 1.1.6 _core_rri: use RRI_LAM; _minisys: RRI_LAM vector
+-- 2008-01-20 112 1.1.5 added ibdr_minisys; _ibdr_rri
+-- 2008-01-06 111 1.1.4 rename ibdr_kw11l->ibd_kw11l; add ibdr_(dl11|rk11)
+-- mod pdp11_intmap;
+-- 2008-01-05 110 1.1.3 delete _mmu_regfile; rename _mmu_regs->_mmu_sadr
+-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- add ibdr_kw11l.
+-- 2008-01-01 109 1.1.2 _vmbox w/ IB_SRES_(CPU|EXT); remove vm_regs_type
+-- 2007-12-30 108 1.1.1 add ibdr_sdreg, ubf_byte[01]
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
+-- 2007-08-16 74 1.0.6 add AP_LAM interface to pdp11_core_rri
+-- 2007-08-12 73 1.0.5 add c_rp_addr_xxx and c_rp_statf_xxx def's
+-- 2007-08-10 72 1.0.4 added c_cp_func_xxx constant def's for commands
+-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
+-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.rblib.all;
+
+package pdp11 is
+
+ type psw_type is record -- processor status
+ cmode : slv2; -- current mode
+ pmode : slv2; -- previous mode
+ rset : slbit; -- register set
+ pri : slv3; -- processor priority
+ tflag : slbit; -- trace flag
+ cc : slv4; -- condition codes (NZVC).
+ end record psw_type;
+
+ constant psw_init : psw_type := (
+ "00","00", -- cmode, pmode (=kernel)
+ '0',"111",'0', -- rset, pri (=7), tflag
+ "0000" -- cc NZVC=0
+ );
+
+ constant c_psw_kmode : slv2 := "00"; -- processor mode: kernel
+ constant c_psw_smode : slv2 := "01"; -- processor mode: supervisor
+ constant c_psw_umode : slv2 := "11"; -- processor mode: user
+
+ subtype psw_ibf_cmode is integer range 15 downto 14;
+ subtype psw_ibf_pmode is integer range 13 downto 12;
+ constant psw_ibf_rset: integer := 11;
+ subtype psw_ibf_pri is integer range 7 downto 5;
+ constant psw_ibf_tflag: integer := 4;
+ subtype psw_ibf_cc is integer range 3 downto 0;
+
+ type sarsdr_type is record -- combined SAR/SDR MMU status
+ saf : slv16; -- segment address field
+ slf : slv7; -- segment length field
+ ed : slbit; -- expansion direction
+ acf : slv3; -- access control field
+ end record sarsdr_type;
+
+ constant sarsdr_init : sarsdr_type := (
+ (others=>'0'), -- saf
+ "0000000",'0',"000" -- slf, ed, acf
+ );
+
+ type dpath_cntl_type is record -- data path control
+ gpr_asrc : slv3; -- src register address
+ gpr_adst : slv3; -- dst register address
+ gpr_mode : slv2; -- psw mode for gpr access
+ gpr_rset : slbit; -- register set
+ gpr_we : slbit; -- gpr write enable
+ gpr_bytop : slbit; -- gpr high byte enable
+ gpr_pcinc : slbit; -- pc increment enable
+ psr_ccwe : slbit; -- enable update cc
+ psr_we: slbit; -- write enable psw (from DIN)
+ psr_func : slv3; -- write function psw (from DIN)
+ dsrc_sel : slbit; -- src data register source select
+ dsrc_we : slbit; -- src data register write enable
+ ddst_sel : slbit; -- dst data register source select
+ ddst_we : slbit; -- dst data register write enable
+ dtmp_sel : slv2; -- tmp data register source select
+ dtmp_we : slbit; -- tmp data register write enable
+ ounit_asel : slv2; -- ounit a port selector
+ ounit_azero : slbit; -- ounit a port force zero
+ ounit_const : slv9; -- ounit b port const
+ ounit_bsel : slv2; -- ounit b port selector
+ ounit_opsub : slbit; -- ounit operation
+ aunit_srcmod : slv2; -- aunit src port modifier
+ aunit_dstmod : slv2; -- aunit dst port modifier
+ aunit_cimod : slv2; -- aunit ci port modifier
+ aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
+ aunit_ccmode : slv3; -- aunit cc port mode
+ aunit_bytop : slbit; -- aunit byte operation
+ lunit_func : slv4; -- lunit function
+ lunit_bytop : slbit; -- lunit byte operation
+ munit_func : slv2; -- munit function
+ munit_s_div : slbit; -- munit s_opg_div state
+ munit_s_div_cn : slbit; -- munit s_opg_div_cn state
+ munit_s_div_cr : slbit; -- munit s_opg_div_cr state
+ munit_s_div_sr : slbit; -- munit s_opg_div_sr state
+ munit_s_ash : slbit; -- munit s_opg_ash state
+ munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
+ munit_s_ashc : slbit; -- munit s_opg_ashc state
+ munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
+ ireg_we : slbit; -- ireg register write enable
+ cres_sel : slv3; -- result bus (cres) select
+ dres_sel : slv3; -- result bus (dres) select
+ vmaddr_sel : slv2; -- virtual address select
+ cpdout_we : slbit; -- capture dres for cpdout
+ end record dpath_cntl_type;
+
+ constant dpath_cntl_init : dpath_cntl_type := (
+ "000","000","00",'0','0','0','0', -- gpr
+ '0','0',"000", -- psr
+ '0','0','0','0',"00",'0', -- dsrc,..,dtmp
+ "00",'0',"000000000","00",'0', -- ounit
+ "00","00","00",'0',"000",'0', -- aunit
+ "0000",'0', -- lunit
+ "00",'0','0','0','0','0','0','0','0',-- munit
+ '0',"000","000","00",'0' -- rest
+ );
+
+ constant c_dpath_dsrc_src : slbit := '0'; -- DSRC = R(SRC)
+ constant c_dpath_dsrc_res : slbit := '1'; -- DSRC = DRES
+ constant c_dpath_ddst_dst : slbit := '0'; -- DDST = R(DST)
+ constant c_dpath_ddst_res : slbit := '1'; -- DDST = DRES
+
+ constant c_dpath_dtmp_dsrc : slv2 := "00"; -- DTMP = DSRC
+ constant c_dpath_dtmp_psw : slv2 := "01"; -- DTMP = PSW
+ constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
+ constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
+
+ constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
+ constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
+ constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
+ constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
+ constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
+ constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
+ constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
+ constant c_dpath_res_cpdin : slv3 := "111"; -- D/CRES = CPDIN
+
+ constant c_dpath_vmaddr_dsrc : slv2 := "00"; -- VMADDR = DSRC
+ constant c_dpath_vmaddr_ddst : slv2 := "01"; -- VMADDR = DDST
+ constant c_dpath_vmaddr_pc : slv2 := "10"; -- VMADDR = PC
+ constant c_dpath_vmaddr_dtmp : slv2 := "11"; -- VMADDR = DTMP
+
+ type dpath_stat_type is record -- data path status
+ ccout_z : slbit; -- current effective Z cc flag
+ shc_tc : slbit; -- last shc cycle (shc==0)
+ div_cr : slbit; -- division: remainder correction needed
+ div_cq : slbit; -- division: quotient correction needed
+ div_quit : slbit; -- division: abort (0/ or /0 or V=1)
+ end record dpath_stat_type;
+
+ constant dpath_stat_init : dpath_stat_type := (others=>'0');
+
+ type decode_stat_type is record -- decode status
+ is_dstmode0 : slbit; -- dest. is register mode
+ is_srcpc : slbit; -- source is pc
+ is_srcpcmode1 : slbit; -- source is pc and mode=1
+ is_dstpc : slbit; -- dest. is pc
+ is_dstw_reg : slbit; -- dest. register to be written
+ is_dstw_pc : slbit; -- pc register to be written
+ is_rmwop : slbit; -- read-modify-write operation
+ is_bytop : slbit; -- byte operation
+ is_res : slbit; -- reserved operation code
+ op_rtt : slbit; -- RTT instruction
+ op_mov : slbit; -- MOV instruction
+ trap_vec : slv3; -- trap vector addr bits 4:2
+ force_srcsp : slbit; -- force src register to be sp
+ updt_dstadsrc : slbit; -- update dsrc in dsta flow
+ aunit_srcmod : slv2; -- aunit src port modifier
+ aunit_dstmod : slv2; -- aunit dst port modifier
+ aunit_cimod : slv2; -- aunit ci port modifier
+ aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
+ aunit_ccmode : slv3; -- aunit cc port mode
+ lunit_func : slv4; -- lunit function
+ munit_func : slv2; -- munit function
+ res_sel : slv3; -- result bus (cres/dres) select
+ fork_op : slv4; -- op fork after idecode state
+ fork_srcr : slv2; -- src-read fork after idecode state
+ fork_dstr : slv2; -- dst-read fork after src read state
+ fork_dsta : slv2; -- dst-addr fork after idecode state
+ fork_opg : slv4; -- opg fork
+ fork_opa : slv3; -- opa fork
+ do_fork_op : slbit; -- execute fork_op
+ do_fork_srcr : slbit; -- execute fork_srcr
+ do_fork_dstr : slbit; -- execute fork_dstr
+ do_fork_dsta : slbit; -- execute fork_dsta
+ do_fork_opg : slbit; -- execute fork_opg
+ do_pref_dec : slbit; -- can do prefetch at decode phase
+ end record decode_stat_type;
+
+ constant decode_stat_init : decode_stat_type := (
+ '0','0','0','0','0','0','0','0','0', -- is_
+ '0','0',"000",'0','0', -- op_, trap_, force_, updt_
+ "00","00","00",'0',"000", -- aunit_
+ "0000","00","000", -- lunit_, munit_, res_
+ "0000","00","00","00","0000","000", -- fork_
+ '0','0','0','0','0', -- do_fork_
+ '0' -- do_pref_
+ );
+
+ constant c_fork_op_halt : slv4 := "0000";
+ constant c_fork_op_wait : slv4 := "0001";
+ constant c_fork_op_rtti : slv4 := "0010";
+ constant c_fork_op_trap : slv4 := "0011";
+ constant c_fork_op_reset: slv4 := "0100";
+ constant c_fork_op_rts : slv4 := "0101";
+ constant c_fork_op_spl : slv4 := "0110";
+ constant c_fork_op_mcc : slv4 := "0111";
+ constant c_fork_op_br : slv4 := "1000";
+ constant c_fork_op_mark : slv4 := "1001";
+ constant c_fork_op_sob : slv4 := "1010";
+ constant c_fork_op_mtp : slv4 := "1011";
+
+ constant c_fork_srcr_def : slv2:= "00";
+ constant c_fork_srcr_inc : slv2:= "01";
+ constant c_fork_srcr_dec : slv2:= "10";
+ constant c_fork_srcr_ind : slv2:= "11";
+
+ constant c_fork_dstr_def : slv2:= "00";
+ constant c_fork_dstr_inc : slv2:= "01";
+ constant c_fork_dstr_dec : slv2:= "10";
+ constant c_fork_dstr_ind : slv2:= "11";
+
+ constant c_fork_dsta_def : slv2:= "00";
+ constant c_fork_dsta_inc : slv2:= "01";
+ constant c_fork_dsta_dec : slv2:= "10";
+ constant c_fork_dsta_ind : slv2:= "11";
+
+ constant c_fork_opg_gen : slv4 := "0000";
+ constant c_fork_opg_wdef : slv4 := "0001";
+ constant c_fork_opg_winc : slv4 := "0010";
+ constant c_fork_opg_wdec : slv4 := "0011";
+ constant c_fork_opg_wind : slv4 := "0100";
+ constant c_fork_opg_mul : slv4 := "0101";
+ constant c_fork_opg_div : slv4 := "0110";
+ constant c_fork_opg_ash : slv4 := "0111";
+ constant c_fork_opg_ashc : slv4 := "1000";
+
+ constant c_fork_opa_jsr : slv3 := "000";
+ constant c_fork_opa_jmp : slv3 := "001";
+ constant c_fork_opa_mtp : slv3 := "010";
+ constant c_fork_opa_mfp_reg : slv3 := "011";
+ constant c_fork_opa_mfp_mem : slv3 := "100";
+
+ -- Note: MSB=0 are 'normal' states, MSB=1 are fatal errors
+ constant c_cpurust_init : slv4 := "0000"; -- cpu in init state
+ constant c_cpurust_halt : slv4 := "0001"; -- cpu executed HALT
+ constant c_cpurust_reset : slv4 := "0010"; -- cpu was reset
+ constant c_cpurust_stop : slv4 := "0011"; -- cpu was stopped
+ constant c_cpurust_step : slv4 := "0100"; -- cpu was stepped
+ constant c_cpurust_susp : slv4 := "0101"; -- cpu was suspended
+ constant c_cpurust_runs : slv4 := "0111"; -- cpu running
+ constant c_cpurust_vecfet : slv4 := "1000"; -- vector fetch error halt
+ constant c_cpurust_recrsv : slv4 := "1001"; -- recursive red-stack halt
+ constant c_cpurust_sfail : slv4 := "1100"; -- sequencer failure
+ constant c_cpurust_vfail : slv4 := "1101"; -- vmbox failure
+
+ type cpustat_type is record -- CPU status
+ cmdbusy : slbit; -- command busy
+ cmdack : slbit; -- command acknowledge
+ cmderr : slbit; -- command error
+ cmdmerr : slbit; -- command memory access error
+ cpugo : slbit; -- CPU go state
+ cpustep : slbit; -- CPU step flag
+ cpuhalt : slbit; -- CPU halt flag
+ cpuwait : slbit; -- CPU wait flag
+ cpurust : slv4; -- CPU run status
+ cpfunc : slv5; -- current control port function
+ cprnum : slv3; -- current control port register number
+ waitsusp : slbit; -- WAIT instruction suspended
+ intvect : slv9_2; -- current interrupt vector
+ trap_mmu : slbit; -- mmu trace trap pending
+ trap_ysv : slbit; -- ysv trap pending
+ prefdone : slbit; -- prefetch done
+ do_gprwe : slbit; -- pending gpr_we
+ do_intrsv : slbit; -- active rsv interrupt sequence
+ end record cpustat_type;
+
+ constant cpustat_init : cpustat_type := (
+ '0','0','0','0', -- cmd..
+ '0','0','0','0', -- cpu..
+ c_cpurust_init, -- cpurust
+ "00000","000", -- cpfunc, cprnum
+ '0', -- waitsusp
+ (others=>'0'), -- intvect
+ '0','0','0', -- trap_(mmu|ysv), prefdone
+ '0','0' -- do_gprwe, do_intrsv
+ );
+
+ type cpuerr_type is record -- CPU error register
+ illhlt : slbit; -- illegal halt (in non-kernel mode)
+ adderr : slbit; -- address error (odd, jmp/jsr reg)
+ nxm : slbit; -- non-existent memory
+ iobto : slbit; -- I/O bus timeout (non-exist UB)
+ ysv : slbit; -- yellow stack violation
+ rsv : slbit; -- red stack violation
+ end record cpuerr_type;
+
+ constant cpuerr_init : cpuerr_type := (others=>'0');
+
+ type vm_cntl_type is record -- virt memory control port
+ req : slbit; -- request
+ wacc : slbit; -- write access
+ macc : slbit; -- modify access (r-m-w sequence)
+ cacc : slbit; -- console access
+ bytop : slbit; -- byte operation
+ dspace : slbit; -- dspace operation
+ kstack : slbit; -- access through kernel stack
+ intrsv : slbit; -- active rsv interrupt sequence
+ mode : slv2; -- mode
+ trap_done : slbit; -- mmu trap taken (to set ssr0 bit)
+ end record vm_cntl_type;
+
+ constant vm_cntl_init : vm_cntl_type := (
+ '0','0','0','0', -- req, wacc, macc,cacc
+ '0','0','0', -- bytop, dspace, kstack
+ '0',"00",'0' -- intrsv, mode, trap_done
+ );
+
+ type vm_stat_type is record -- virt memory status port
+ ack : slbit; -- acknowledge
+ err : slbit; -- error (see err_xxx for reason)
+ fail : slbit; -- failure (machine check)
+ err_odd : slbit; -- abort: odd address error
+ err_mmu : slbit; -- abort: mmu reject
+ err_nxm : slbit; -- abort: non-existing memory
+ err_iobto : slbit; -- abort: non-existing I/O resource
+ err_rsv : slbit; -- abort: red stack violation
+ trap_ysv : slbit; -- trap: yellow stack violation
+ trap_mmu : slbit; -- trap: mmu trace trap
+ end record vm_stat_type;
+
+ constant vm_stat_init : vm_stat_type := (others=>'0');
+
+ type em_mreq_type is record -- external memory - master request
+ req : slbit; -- request
+ we : slbit; -- write enable
+ be : slv2; -- byte enables
+ cancel : slbit; -- cancel request
+ addr : slv22_1; -- address
+ din : slv16; -- data in (input to memory)
+ end record em_mreq_type;
+
+ constant em_mreq_init : em_mreq_type := (
+ '0','0',"00",'0', -- req, we, be, cancel
+ (others=>'0'),(others=>'0') -- addr, din
+ );
+
+ type em_sres_type is record -- external memory - slave response
+ ack_r : slbit; -- acknowledge read
+ ack_w : slbit; -- acknowledge write
+ dout : slv16; -- data out (output from memory)
+ end record em_sres_type;
+
+ constant em_sres_init : em_sres_type := (
+ '0','0', -- ack_r, ack_w
+ (others=>'0') -- dout
+ );
+
+ type mmu_cntl_type is record -- mmu control port
+ req : slbit; -- translate request
+ wacc : slbit; -- write access
+ macc : slbit; -- modify access (r-m-w sequence)
+ cacc : slbit; -- console access (bypass mmu)
+ dspace : slbit; -- dspace access
+ mode : slv2; -- processor mode
+ trap_done : slbit; -- mmu trap taken (set ssr0 bit)
+ end record mmu_cntl_type;
+
+ constant mmu_cntl_init : mmu_cntl_type := (
+ '0','0','0','0', -- req, wacc, macc, cacc
+ '0',"00",'0' -- dspace, mode, trap_done
+ );
+
+ type mmu_stat_type is record -- mmu status port
+ vaok : slbit; -- virtual address valid
+ trap : slbit; -- mmu trap request
+ ena_mmu : slbit; -- mmu enable (ssr0 bit 0)
+ ena_22bit : slbit; -- mmu in 22 bit mode (ssr3 bit 4)
+ ena_ubmap : slbit; -- ubmap enable (ssr3 bit 5)
+ end record mmu_stat_type;
+
+ constant mmu_stat_init : mmu_stat_type := (others=>'0');
+
+ type mmu_moni_type is record -- mmu monitor port
+ istart : slbit; -- instruction start
+ idone : slbit; -- instruction done
+ pc : slv16; -- PC of new instruction
+ regmod : slbit; -- register modified
+ regnum : slv3; -- register number
+ delta : slv4; -- register offset
+ isdec : slbit; -- offset to be subtracted
+ trace_prev : slbit; -- use ssr12 trace state of prev. state
+ end record mmu_moni_type;
+
+ constant mmu_moni_init : mmu_moni_type := (
+ '0','0',(others=>'0'), -- istart, idone, pc
+ '0',"000","0000", -- regmod, regnum, delta
+ '0','0' -- isdec, trace_prev
+ );
+
+ type mmu_ssr0_type is record -- MMU ssr0
+ abo_nonres : slbit; -- abort non resident
+ abo_length : slbit; -- abort segment length
+ abo_rdonly : slbit; -- abort read-only
+ trap_mmu : slbit; -- trap management
+ ena_trap : slbit; -- enable traps
+ inst_compl : slbit; -- instruction complete
+ seg_mode : slv2; -- segement mode
+ dspace : slbit; -- address space (D=1, I=0)
+ seg_num : slv3; -- segment number
+ ena_mmu : slbit; -- enable memory management
+ trace_prev : slbit; -- ssr12 trace status in prev. state
+ end record mmu_ssr0_type;
+
+ constant mmu_ssr0_init : mmu_ssr0_type := (
+ inst_compl=>'0', seg_mode=>"00", seg_num=>"000",
+ others=>'0'
+ );
+
+ type mmu_ssr1_type is record -- MMU ssr1
+ rb_delta : slv5; -- RB: amount change
+ rb_num : slv3; -- RB: register number
+ ra_delta : slv5; -- RA: amount change
+ ra_num : slv3; -- RA: register number
+ end record mmu_ssr1_type;
+
+ constant mmu_ssr1_init : mmu_ssr1_type := (
+ "00000","000", -- rb_...
+ "00000","000" -- ra_...
+ );
+
+ type mmu_ssr3_type is record -- MMU ssr3
+ ena_ubmap : slbit; -- enable unibus mapping
+ ena_22bit : slbit; -- enable 22 bit mapping
+ dspace_km : slbit; -- enable dspace kernel
+ dspace_sm : slbit; -- enable dspace supervisor
+ dspace_um : slbit; -- enable dspace user
+ end record mmu_ssr3_type;
+
+ constant mmu_ssr3_init : mmu_ssr3_type := (others=>'0');
+
+-- control port definitions --------------------------------------------------
+
+ type cp_cntl_type is record -- control port control
+ req : slbit; -- request
+ func : slv5; -- function
+ rnum : slv3; -- register number
+ end record cp_cntl_type;
+
+ constant c_cpfunc_noop : slv5 := "00000"; -- noop : no operation
+ constant c_cpfunc_sta : slv5 := "00001"; -- sta : cpu start
+ constant c_cpfunc_sto : slv5 := "00010"; -- sto : cpu stop
+ constant c_cpfunc_cont : slv5 := "00011"; -- cont : cpu continue
+ constant c_cpfunc_step : slv5 := "00100"; -- step : cpu step
+ constant c_cpfunc_rst : slv5 := "01111"; -- rst : cpu reset (soft)
+ constant c_cpfunc_rreg : slv5 := "10000"; -- rreg : read register
+ constant c_cpfunc_wreg : slv5 := "10001"; -- wreg : write register
+ constant c_cpfunc_rpsw : slv5 := "10010"; -- rpsw : read psw
+ constant c_cpfunc_wpsw : slv5 := "10011"; -- wpsw : write psw
+ constant c_cpfunc_rmem : slv5 := "10100"; -- rmem : read memory
+ constant c_cpfunc_wmem : slv5 := "10101"; -- wmem : write memory
+
+ constant cp_cntl_init : cp_cntl_type := ('0',c_cpfunc_noop,"000");
+
+ type cp_stat_type is record -- control port status
+ cmdbusy : slbit; -- command busy
+ cmdack : slbit; -- command acknowledge
+ cmderr : slbit; -- command error
+ cmdmerr : slbit; -- command memory access error
+ cpugo : slbit; -- CPU go state
+ cpustep : slbit; -- CPU step flag
+ cpuhalt : slbit; -- CPU halt flag
+ cpuwait : slbit; -- CPU wait flag
+ cpurust : slv4; -- CPU run status
+ end record cp_stat_type;
+
+ constant cp_stat_init : cp_stat_type := (
+ '0','0','0','0', -- cmd...
+ '0','0','0','0', -- cpu...
+ (others=>'0') -- cpurust
+ );
+
+ type cp_addr_type is record -- control port address
+ addr : slv22_1; -- address
+ racc : slbit; -- ibr access
+ be : slv2; -- byte enables
+ ena_22bit : slbit; -- enable 22 bit mode
+ ena_ubmap : slbit; -- enable unibus mapper
+ end record cp_addr_type;
+
+ constant cp_addr_init : cp_addr_type := (
+ (others=>'0'), -- addr
+ '0',"00", -- racc, be
+ '0','0' -- ena_...
+ );
+
+-- debug and monitoring port definitions -------------------------------------
+
+ type dm_cntl_type is record -- debug and monitor control
+ dum1 : slbit; -- dummy 1
+ dum2 : slbit; -- dummy 2
+ end record dm_cntl_type;
+
+ constant dm_cntl_init : dm_cntl_type := (others=>'0');
+
+ type dm_stat_dp_type is record -- debug and monitor status - dpath
+ pc : slv16; -- pc
+ psw : psw_type; -- psw
+ ireg : slv16; -- ireg
+ ireg_we : slbit; -- ireg we
+ dsrc : slv16; -- dsrc register
+ ddst : slv16; -- ddst register
+ dtmp : slv16; -- dtmp register
+ dres : slv16; -- dres bus
+ gpr_adst : slv3; -- gpr dst regsiter
+ gpr_mode : slv2; -- gpr mode
+ gpr_bytop : slbit; -- gpr bytop
+ gpr_we : slbit; -- gpr we
+ end record dm_stat_dp_type;
+
+ constant dm_stat_dp_init : dm_stat_dp_type := (
+ (others=>'0'), -- pc
+ psw_init, -- psw
+ (others=>'0'),'0', -- ireg, ireg_we
+ (others=>'0'),(others=>'0'), -- dsrc, ddst
+ (others=>'0'),(others=>'0'), -- dtmp, dres
+ (others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
+ '0','0' -- gpr_bytop, gpr_we
+ );
+
+ type dm_stat_vm_type is record -- debug and monitor status - vmbox
+ ibmreq : ib_mreq_type; -- ibus master request
+ ibsres : ib_sres_type; -- ibus slave response
+ end record dm_stat_vm_type;
+
+ constant dm_stat_vm_init : dm_stat_vm_type := (ib_mreq_init,ib_sres_init);
+
+ type dm_stat_co_type is record -- debug and monitor status - core
+ cpugo : slbit; -- cpugo state flag
+ cpuhalt : slbit; -- cpuhalt state flag
+ end record dm_stat_co_type;
+
+ constant dm_stat_co_init : dm_stat_co_type := ('0','0');
+
+ type dm_stat_sy_type is record -- debug and monitor status - system
+ emmreq : em_mreq_type; -- external memory: request
+ emsres : em_sres_type; -- external memory: response
+ chit : slbit; -- cache hit
+ end record dm_stat_sy_type;
+
+ constant dm_stat_sy_init : dm_stat_sy_type := (em_mreq_init,em_sres_init,'0');
+
+-- rbus interface definitions ------------------------------------------------
+
+ constant c_rbaddr_conf : slv5 := "00000"; -- R/W configuration reg
+ constant c_rbaddr_cntl : slv5 := "00001"; -- -/F control reg
+ constant c_rbaddr_stat : slv5 := "00010"; -- R/- status reg
+ constant c_rbaddr_psw : slv5 := "00011"; -- R/W psw access
+ constant c_rbaddr_al : slv5 := "00100"; -- R/W address low reg
+ constant c_rbaddr_ah : slv5 := "00101"; -- R/W address high reg
+ constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
+ constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
+
+ constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
+ constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
+ constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
+ constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
+ constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
+ constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
+ constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
+ constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
+
+ constant c_rbaddr_ibrb : slv5 := "10000"; -- R/W ibr base address
+
+ subtype c_al_rbf_addr is integer range 15 downto 1; -- al: address
+ constant c_ah_rbf_ena_ubmap: integer := 7; -- ah: ubmap
+ constant c_ah_rbf_ena_22bit: integer := 6; -- ah: 22bit
+ subtype c_ah_rbf_addr is integer range 5 downto 0; -- ah: address
+
+ constant c_stat_rbf_cmderr: integer := 0; -- stat field: cmderr
+ constant c_stat_rbf_cmdmerr: integer := 1; -- stat field: cmdmerr
+ constant c_stat_rbf_cpugo: integer := 2; -- stat field: cpugo
+ constant c_stat_rbf_cpuhalt: integer := 3; -- stat field: cpuhalt
+ subtype c_stat_rbf_cpurust is integer range 7 downto 4; -- cpurust
+
+ subtype c_ibrb_ibf_base is integer range 12 downto 6; -- ibrb: base addr
+ subtype c_ibrb_ibf_be is integer range 1 downto 0; -- ibrb: be's
+
+-- -------------------------------------
+
+component pdp11_gpr is -- general purpose registers
+ port (
+ CLK : in slbit; -- clock
+ DIN : in slv16; -- input data
+ ASRC : in slv3; -- source register number
+ ADST : in slv3; -- destination register number
+ MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
+ RSET : in slbit; -- register set
+ WE : in slbit; -- write enable
+ BYTOP : in slbit; -- byte operation (write low byte only)
+ PCINC : in slbit; -- increment PC
+ DSRC : out slv16; -- source register data
+ DDST : out slv16; -- destination register data
+ PC : out slv16 -- current PC value
+ );
+end component;
+
+constant c_gpr_r5 : slv3 := "101"; -- register number of r5
+constant c_gpr_sp : slv3 := "110"; -- register number of SP
+constant c_gpr_pc : slv3 := "111"; -- register number of PC
+
+component pdp11_psr is -- processor status word register
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ DIN : in slv16; -- input data
+ CCIN : in slv4; -- cc input
+ CCWE : in slbit; -- enable update cc
+ WE : in slbit; -- write enable (from DIN)
+ FUNC : in slv3; -- write function (from DIN)
+ PSW : out psw_type; -- current psw
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+constant c_psr_func_wspl : slv3 := "000"; -- SPL mode: set pri
+constant c_psr_func_wcc : slv3 := "001"; -- CC mode: set/clear cc
+constant c_psr_func_wint : slv3 := "010"; -- interupt mode: pmode=cmode
+constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
+constant c_psr_func_wall : slv3 := "100"; -- write all fields
+
+component pdp11_ounit is -- offset adder for addresses (ounit)
+ port (
+ DSRC : in slv16; -- 'src' data for port A
+ DDST : in slv16; -- 'dst' data for port A
+ DTMP : in slv16; -- 'tmp' data for port A
+ PC : in slv16; -- PC data for port A
+ ASEL : in slv2; -- selector for port A
+ AZERO : in slbit; -- force zero for port A
+ IREG8 : in slv8; -- 'ireg' data for port B
+ VMDOUT : in slv16; -- virt. memory data for port B
+ CONST : in slv9; -- sequencer const data for port B
+ BSEL : in slv2; -- selector for port B
+ OPSUB : in slbit; -- operation: 0 add, 1 sub
+ DOUT : out slv16; -- data output
+ NZOUT : out slv2 -- NZ condition codes out
+ );
+end component;
+
+constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
+constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
+constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
+constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
+
+constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
+constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
+constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
+constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
+
+component pdp11_aunit is -- arithmetic unit for data (aunit)
+ port (
+ DSRC : in slv16; -- 'src' data in
+ DDST : in slv16; -- 'dst' data in
+ CI : in slbit; -- carry flag in
+ SRCMOD : in slv2; -- src modifier mode
+ DSTMOD : in slv2; -- dst modifier mode
+ CIMOD : in slv2; -- ci modifier mode
+ CC1OP : in slbit; -- use cc modes (1 op instruction)
+ CCMODE : in slv3; -- cc mode
+ BYTOP : in slbit; -- byte operation
+ DOUT : out slv16; -- data output
+ CCOUT : out slv4 -- condition codes out
+ );
+end component;
+
+constant c_aunit_mod_pass : slv2 := "00"; -- pass data
+constant c_aunit_mod_inv : slv2 := "01"; -- invert data
+constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
+constant c_aunit_mod_one : slv2 := "11"; -- set to 1
+
+-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
+constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
+constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
+constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
+constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
+constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
+constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
+constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
+constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
+
+component pdp11_lunit is -- logic unit for data (lunit)
+ port (
+ DSRC : in slv16; -- 'src' data in
+ DDST : in slv16; -- 'dst' data in
+ CCIN : in slv4; -- condition codes in
+ FUNC : in slv4; -- function
+ BYTOP : in slbit; -- byte operation
+ DOUT : out slv16; -- data output
+ CCOUT : out slv4 -- condition codes out
+ );
+end component;
+
+constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
+constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
+constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
+constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
+constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
+constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
+constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
+constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
+constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
+constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
+constant c_lunit_func_xor : slv4 := "1010"; -- XOR
+
+component pdp11_munit is -- mul/div unit for data (munit)
+ port (
+ CLK : in slbit; -- clock
+ DSRC : in slv16; -- 'src' data in
+ DDST : in slv16; -- 'dst' data in
+ DTMP : in slv16; -- 'tmp' data in
+ GPR_DSRC : in slv16; -- 'src' data from GPR
+ FUNC : in slv2; -- function
+ S_DIV : in slbit; -- s_opg_div state (load dd_low)
+ S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)
+ S_DIV_CR : in slbit; -- s_opg_div_cr state (remainder corr.)
+ S_DIV_SR : in slbit; -- s_opg_div_sr state (store remainder)
+ S_ASH : in slbit; -- s_opg_ash state
+ S_ASH_CN : in slbit; -- s_opg_ash_cn state
+ S_ASHC : in slbit; -- s_opg_ashc state
+ S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
+ SHC_TC : out slbit; -- last shc cycle (shc==0)
+ DIV_CR : out slbit; -- division: remainder correction needed
+ DIV_CQ : out slbit; -- division: quotient correction needed
+ DIV_QUIT : out slbit; -- division: abort (0/ or /0 or V=1)
+ DOUT : out slv16; -- data output
+ DOUTE : out slv16; -- data output extra
+ CCOUT : out slv4 -- condition codes out
+ );
+end component;
+
+constant c_munit_func_mul : slv2 := "00"; -- MUL
+constant c_munit_func_div : slv2 := "01"; -- DIV
+constant c_munit_func_ash : slv2 := "10"; -- ASH
+constant c_munit_func_ashc : slv2 := "11"; -- ASHC
+
+component pdp11_mmu_sadr is -- mmu SAR/SDR register set
+ port (
+ CLK : in slbit; -- clock
+ MODE : in slv2; -- mode
+ ASN : in slv4; -- augmented segment number (1+3 bit)
+ AIB_WE : in slbit; -- update AIB
+ AIB_SETA : in slbit; -- set access AIB
+ AIB_SETW : in slbit; -- set write AIB
+ SARSDR : out sarsdr_type; -- combined SAR/SDR
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ TRACE : in slbit; -- trace enable
+ MONI : in mmu_moni_type; -- MMU monitor port data
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_mmu is -- mmu - memory management unit
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ BRESET : in slbit; -- ibus reset
+ CNTL : in mmu_cntl_type; -- control port
+ VADDR : in slv16; -- virtual address
+ MONI : in mmu_moni_type; -- monitor port
+ STAT : out mmu_stat_type; -- status port
+ PADDRH : out slv16; -- physical address (upper 16 bit)
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_vmbox is -- virtual memory
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ CRESET : in slbit; -- console reset
+ BRESET : in slbit; -- ibus reset
+ CP_ADDR : in cp_addr_type; -- console port address
+ VM_CNTL : in vm_cntl_type; -- vm control port
+ VM_ADDR : in slv16; -- vm address
+ VM_DIN : in slv16; -- vm data in
+ VM_STAT : out vm_stat_type; -- vm status port
+ VM_DOUT : out slv16; -- vm data out
+ EM_MREQ : out em_mreq_type; -- external memory: request
+ EM_SRES : in em_sres_type; -- external memory: response
+ MMU_MONI : in mmu_moni_type; -- mmu monitor port
+ IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
+ IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
+ IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
+ DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
+ );
+end component;
+
+component pdp11_dpath is -- CPU datapath
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ CNTL : in dpath_cntl_type; -- control interface
+ STAT : out dpath_stat_type; -- status interface
+ CP_DIN : in slv16; -- console port data in
+ CP_DOUT : out slv16; -- console port data out
+ PSWOUT : out psw_type; -- current psw
+ PCOUT : out slv16; -- current pc
+ IREG : out slv16; -- ireg out
+ VM_ADDR : out slv16; -- virt. memory address
+ VM_DOUT : in slv16; -- virt. memory data out
+ VM_DIN : out slv16; -- virt. memory data in
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type; -- ibus response
+ DM_STAT_DP : out dm_stat_dp_type -- debug and monitor status
+ );
+end component;
+
+component pdp11_decode is -- instruction decoder
+ port (
+ IREG : in slv16; -- input instruction word
+ STAT : out decode_stat_type -- status output
+ );
+end component;
+
+component pdp11_sequencer is -- cpu sequencer
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ PSW : in psw_type; -- processor status
+ PC : in slv16; -- program counter
+ IREG : in slv16; -- IREG
+ ID_STAT : in decode_stat_type; -- instr. decoder status
+ DP_STAT : in dpath_stat_type; -- data path status
+ CP_CNTL : in cp_cntl_type; -- console port control
+ VM_STAT : in vm_stat_type; -- virtual memory status port
+ INT_PRI : in slv3; -- interrupt priority
+ INT_VECT : in slv9_2; -- interrupt vector
+ CRESET : out slbit; -- console reset
+ BRESET : out slbit; -- ibus reset
+ MMU_MONI : out mmu_moni_type; -- mmu monitor port
+ DP_CNTL : out dpath_cntl_type; -- data path control
+ VM_CNTL : out vm_cntl_type; -- virtual memory control port
+ CP_STAT : out cp_stat_type; -- console port status
+ INT_ACK : out slbit; -- interrupt acknowledge
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_irq is -- interrupt requester
+ port (
+ CLK : in slbit; -- clock
+ BRESET : in slbit; -- ibus reset
+ INT_ACK : in slbit; -- interrupt acknowledge from CPU
+ EI_PRI : in slv3; -- external interrupt priority
+ EI_VECT : in slv9_2; -- external interrupt vector
+ EI_ACKM : out slbit; -- external interrupt acknowledge
+ PRI : out slv3; -- interrupt priority
+ VECT : out slv9_2; -- interrupt vector
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_ubmap is -- 11/70 unibus mapper
+ port (
+ CLK : in slbit; -- clock
+ MREQ : in slbit; -- request mapping
+ ADDR_UB : in slv18_1; -- UNIBUS address (in)
+ ADDR_PM : out slv22_1; -- physical memory address (out)
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_sys70 is -- 11/70 memory system registers
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_mem70 is -- 11/70 memory system registers
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ HM_ENA : in slbit; -- hit/miss enable
+ HM_VAL : in slbit; -- hit/miss value
+ CACHE_FMISS : out slbit; -- cache force miss
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end component;
+
+component pdp11_cache is -- cache
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ EM_MREQ : in em_mreq_type; -- em request
+ EM_SRES : out em_sres_type; -- em response
+ FMISS : in slbit; -- force miss
+ CHIT : out slbit; -- cache hit flag
+ MEM_REQ : out slbit; -- memory: request
+ MEM_WE : out slbit; -- memory: write enable
+ MEM_BUSY : in slbit; -- memory: controller busy
+ MEM_ACK_R : in slbit; -- memory: acknowledge read
+ MEM_ADDR : out slv20; -- memory: address
+ MEM_BE : out slv4; -- memory: byte enable
+ MEM_DI : out slv32; -- memory: data in (memory view)
+ MEM_DO : in slv32 -- memory: data out (memory view)
+ );
+end component;
+
+component pdp11_core is -- full processor core
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CP_CNTL : in cp_cntl_type; -- console control port
+ CP_ADDR : in cp_addr_type; -- console address port
+ CP_DIN : in slv16; -- console data in
+ CP_STAT : out cp_stat_type; -- console status port
+ CP_DOUT : out slv16; -- console data out
+ EI_PRI : in slv3; -- external interrupt priority
+ EI_VECT : in slv9_2; -- external interrupt vector
+ EI_ACKM : out slbit; -- external interrupt acknowledge
+ EM_MREQ : out em_mreq_type; -- external memory: request
+ EM_SRES : in em_sres_type; -- external memory: response
+ BRESET : out slbit; -- ibus reset
+ IB_MREQ_M : out ib_mreq_type; -- ibus master request (master)
+ IB_SRES_M : in ib_sres_type; -- ibus slave response (master)
+ DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
+ DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
+ DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
+ );
+end component;
+
+component pdp11_tmu is -- trace and monitor unit
+ port (
+ CLK : in slbit; -- clock
+ ENA : in slbit := '0'; -- enable trace output
+ DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
+ DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
+ DM_STAT_CO : in dm_stat_co_type; -- DM core
+ DM_STAT_SY : in dm_stat_sy_type -- DM system
+ );
+end component;
+
+component pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
+ generic (
+ ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
+ port (
+ CLK : in slbit; -- clock
+ DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
+ DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
+ DM_STAT_CO : in dm_stat_co_type; -- DM core
+ DM_STAT_SY : in dm_stat_sy_type -- DM system
+ );
+end component;
+
+component pdp11_du_drv is -- display unit low level driver
+ generic (
+ CDWIDTH : positive := 3); -- clock divider width
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ ROW0 : in slv22; -- led row 0 (22 leds, top)
+ ROW1 : in slv16; -- led row 1 (16 leds)
+ ROW2 : in slv16; -- led row 2 (16 leds)
+ ROW3 : in slv10; -- led row 3 (10 leds, bottom)
+ SWOPT : out slv8; -- option pattern from du
+ SWOPT_RDY : out slbit; -- marks update of swopt
+ DU_SCLK : out slbit; -- DU: sclk
+ DU_SS_N : out slbit; -- DU: ss_n
+ DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
+ DU_MISO : in slbit -- DU: miso (master in, slave out)
+ );
+end component;
+
+component pdp11_bram is -- BRAM based ext. memory dummy
+ generic (
+ AWIDTH : positive := 14); -- address width
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ EM_MREQ : in em_mreq_type; -- em request
+ EM_SRES : out em_sres_type -- em response
+ );
+end component;
+
+component pdp11_core_rbus is -- core to rbus interface
+ generic (
+ RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
+ RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ RB_MREQ : in rb_mreq_type; -- rbus: request
+ RB_SRES : out rb_sres_type; -- rbus: response
+ RB_STAT : out slv3; -- rbus: status flags
+ RB_LAM : out slbit; -- remote attention
+ CPU_RESET : out slbit; -- cpu master reset
+ CP_CNTL : out cp_cntl_type; -- console control port
+ CP_ADDR : out cp_addr_type; -- console address port
+ CP_DIN : out slv16; -- console data in
+ CP_STAT : in cp_stat_type; -- console status port
+ CP_DOUT : in slv16 -- console data out
+ );
+end component;
+
+-- ----- move later to pdp11_conf --------------------------------------------
+
+constant conf_vect_pirq : integer := 8#240#;
+constant conf_pri_pirq_1 : integer := 1;
+constant conf_pri_pirq_2 : integer := 2;
+constant conf_pri_pirq_3 : integer := 3;
+constant conf_pri_pirq_4 : integer := 4;
+constant conf_pri_pirq_5 : integer := 5;
+constant conf_pri_pirq_6 : integer := 6;
+constant conf_pri_pirq_7 : integer := 7;
+
+end package pdp11;
Index: pdp11_core_rbus.vhd
===================================================================
--- pdp11_core_rbus.vhd (nonexistent)
+++ pdp11_core_rbus.vhd (revision 26)
@@ -0,0 +1,421 @@
+-- $Id: pdp11_core_rbus.vhd 553 2014-03-17 06:40:08Z mueller $
+--
+-- Copyright 2007-2014 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_core_rbus - syn
+-- Description: pdp11: core to rbus interface
+--
+-- Dependencies: -
+-- Test bench: tb/tb_rlink_tba_pdp11core
+--
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
+-- Revision History: -
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.1.1 now numeric_std clean
+-- 2010-12-29 351 1.1 renamed from pdp11_core_rri; ported to rbv3
+-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
+-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
+-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
+-- add ibrb register and ibr window logic
+-- 2010-06-13 305 1.2 add CP_ADDR in port; mostly rewritten for new
+-- rri <-> cp mapping
+-- 2010-06-03 299 1.1.2 correct rbus init logic (use we, din, RB_ADDR)
+-- 2010-05-02 287 1.1.1 rename RP_STAT->RB_STAT; remove unneeded unsigned()
+-- 2010-05-01 285 1.1 port to rri V2 interface, add RB_ADDR generic;
+-- rename c_rp_addr_* -> c_rb_addr_*
+-- 2008-05-03 143 1.0.8 rename _cpursta->_cpurust
+-- 2008-04-27 140 1.0.7 use cpursta interface, remove cpufail
+-- 2008-03-02 121 1.0.6 set RP_ERR when cmderr or cmdmerr status seen
+-- 2008-02-24 119 1.0.5 support lah,rps,wps cp commands
+-- 2008-01-20 113 1.0.4 use single LAM; change to RRI_LAM interface
+-- 2007-10-12 88 1.0.3 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-08-16 74 1.0.2 add AP_LAM interface to pdp11_core_rri
+-- 2007-08-12 73 1.0.1 use def's; add stat command; wait for step complete
+-- 2007-07-08 65 1.0 Initial version
+------------------------------------------------------------------------------
+--
+-- rbus registers:
+--
+-- Address Bits Name r/w/i Function
+--
+-- bbb00000 conf r/w/- cpu configuration (e.g. cpu type)
+-- (currently unused, all bits MBZ)
+-- bbb00001 cntl -/f/- cpu control
+-- 3:0 func function code
+-- 0000: noop
+-- 0001: start
+-- 0010: stop
+-- 0011: continue
+-- 0100: step
+-- 1111: reset (soft)
+-- bbb00010 stat r/-/- cpu status
+-- 7:04 cpurust r/-/- cp_stat: cpurust
+-- 3 cpuhalt r/-/- cp_stat: cpuhalt
+-- 2 cpugo r/-/- cp_stat: cpugo
+-- 1 cmdmerr r/-/- cp_stat: cmdmerr
+-- 0 cmderr r/-/- cp_stat: cmderr
+-- bbb00011 psw r/w/- processor status word access
+-- bbb00100 al r/w/- address register, low
+-- bbb00101 ah r/w/- address register, high
+-- 7 ubm r/w/- ubmap access
+-- 6 p22 r/w/- 22bit access
+-- 5: 0 addr r/w/- addr(21:16)
+-- bbb00110 mem r/w/- memory access
+-- bbb00111 memi r/w/- memory access, inc address
+-- bbb01rrr gpr[] r/w/- general purpose regs
+-- bbb10000 ibrb r/w/- ibr base address
+-- 12:06 base r/w/- ibr window base address
+-- 1:00 we r/w/- byte enables (00 equivalent to 11)
+-- www----- ibr[] r/w/- ibr window (32 words)
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.rblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_core_rbus is -- core to rbus interface
+ generic (
+ RB_ADDR_CORE : slv8 := slv(to_unsigned(2#00000000#,8));
+ RB_ADDR_IBUS : slv8 := slv(to_unsigned(2#10000000#,8)));
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ RB_MREQ : in rb_mreq_type; -- rbus: request
+ RB_SRES : out rb_sres_type; -- rbus: response
+ RB_STAT : out slv3; -- rbus: status flags
+ RB_LAM : out slbit; -- remote attention
+ CPU_RESET : out slbit; -- cpu master reset
+ CP_CNTL : out cp_cntl_type; -- console control port
+ CP_ADDR : out cp_addr_type; -- console address port
+ CP_DIN : out slv16; -- console data in
+ CP_STAT : in cp_stat_type; -- console status port
+ CP_DOUT : in slv16 -- console data out
+ );
+end pdp11_core_rbus;
+
+
+architecture syn of pdp11_core_rbus is
+
+ type state_type is (
+ s_idle, -- s_idle: wait for rp access
+ s_cpwait, -- s_cpwait: wait for cp port ack
+ s_cpstep -- s_cpstep: wait for cpustep done
+ );
+
+ type regs_type is record
+ state : state_type; -- state
+ rbselc : slbit; -- rbus select for core
+ rbseli : slbit; -- rbus select for ibus
+ cpreq : slbit; -- cp request flag
+ cpfunc : slv5; -- cp function
+ cpugo_1 : slbit; -- prev cycle cpugo
+ addr : slv22_1; -- address register
+ ena_22bit : slbit; -- 22bit enable
+ ena_ubmap : slbit; -- ubmap enable
+ ibrbase : slv(c_ibrb_ibf_base); -- ibr base address
+ ibrbe : slv2; -- ibr byte enables
+ ibrberet : slv2; -- ibr byte enables (for readback)
+ doinc : slbit; -- at cmdack: do addr reg inc
+ waitstep : slbit; -- at cmdack: wait for cpu step complete
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ s_idle, -- state
+ '0','0', -- rbselc,rbseli
+ '0', -- cpreq
+ (others=>'0'), -- cpfunc
+ '0', -- cpugo_1
+ (others=>'0'), -- addr
+ '0','0', -- ena_22bit, ena_ubmap
+ (others=>'0'),"00","00", -- ibrbase, ibrbe, ibrberet
+ '0','0' -- doinc, waitstep
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ begin
+
+ proc_regs: process (CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, RB_MREQ, CP_STAT, CP_DOUT)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable irb_ack : slbit := '0';
+ variable irb_busy : slbit := '0';
+ variable irb_err : slbit := '0';
+ variable irb_dout : slv16 := (others=>'0');
+ variable irb_lam : slbit := '0';
+ variable irbena : slbit := '0';
+
+ variable icpreq : slbit := '0';
+ variable icpureset : slbit := '0';
+ variable icpaddr : cp_addr_type := cp_addr_init;
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ irb_ack := '0';
+ irb_busy := '0';
+ irb_err := '0';
+ irb_dout := (others=>'0');
+ irb_lam := '0';
+
+ irbena := RB_MREQ.re or RB_MREQ.we;
+
+ icpreq := '0';
+ icpureset := '0';
+
+ -- look for init's against the rbus base address, generate subsystem resets
+ if RB_MREQ.init='1' and RB_MREQ.we='1' and RB_MREQ.addr=RB_ADDR_CORE then
+ icpureset := RB_MREQ.din(0);
+ end if;
+
+ -- rbus address decoder
+ n.rbseli := '0';
+ n.rbselc := '0';
+ if RB_MREQ.aval='1' then
+ if RB_MREQ.addr(7 downto 5)=RB_ADDR_CORE(7 downto 5) then
+ n.rbselc := '1';
+ end if;
+ if RB_MREQ.addr(7 downto 5)=RB_ADDR_IBUS(7 downto 5) then
+ n.rbseli := '1';
+ end if;
+ end if;
+
+ if (r.rbselc='1' or r.rbseli='1') and irbena='1' then
+ irb_ack := '1'; -- ack all (maybe rejected later)
+ end if;
+
+ case r.state is
+
+ when s_idle => -- s_idle: wait for rbus access ------
+
+ n.doinc := '0';
+ n.waitstep := '0';
+
+ if r.rbseli = '1' then
+ if irbena = '1' then
+ n.cpfunc := c_cpfunc_rmem;
+ n.cpfunc(0) := RB_MREQ.we;
+ icpreq := '1';
+ end if;
+
+ elsif r.rbselc = '1' then
+
+ case RB_MREQ.addr(4 downto 0) is
+
+ when c_rbaddr_conf => -- conf -------------------------
+ null; -- currently no action
+
+ when c_rbaddr_cntl => -- cntl -------------------------
+ if irbena = '1' then
+ n.cpfunc := RB_MREQ.din(n.cpfunc'range);
+ end if;
+ if RB_MREQ.we = '1' then
+ icpreq := '1';
+ if RB_MREQ.din(3 downto 0) = c_cpfunc_step(3 downto 0) then
+ n.waitstep := '1';
+ end if;
+ end if;
+
+ when c_rbaddr_stat => -- stat -------------------------
+ irb_dout(c_stat_rbf_cmderr) := CP_STAT.cmderr;
+ irb_dout(c_stat_rbf_cmdmerr) := CP_STAT.cmdmerr;
+ irb_dout(c_stat_rbf_cpugo) := CP_STAT.cpugo;
+ irb_dout(c_stat_rbf_cpuhalt) := CP_STAT.cpuhalt;
+ irb_dout(c_stat_rbf_cpurust) := CP_STAT.cpurust;
+
+ when c_rbaddr_psw => -- psw --------------------------
+ if irbena = '1' then
+ n.cpfunc := c_cpfunc_rpsw;
+ n.cpfunc(0) := RB_MREQ.we;
+ icpreq := '1';
+ end if;
+
+ when c_rbaddr_al => -- al ---------------------------
+ irb_dout(c_al_rbf_addr) := r.addr(c_al_rbf_addr);
+ if RB_MREQ.we = '1' then
+ n.addr := (others=>'0'); -- write to al clears ah !!
+ n.ena_22bit := '0';
+ n.ena_ubmap := '0';
+ n.addr(c_al_rbf_addr) := RB_MREQ.din(c_al_rbf_addr);
+ end if;
+
+ when c_rbaddr_ah => -- ah ---------------------------
+ irb_dout(c_ah_rbf_ena_ubmap) := r.ena_ubmap;
+ irb_dout(c_ah_rbf_ena_22bit) := r.ena_22bit;
+ irb_dout(c_ah_rbf_addr) := r.addr(21 downto 16);
+ if RB_MREQ.we = '1' then
+ n.addr(21 downto 16) := RB_MREQ.din(c_ah_rbf_addr);
+ n.ena_22bit := RB_MREQ.din(c_ah_rbf_ena_22bit);
+ n.ena_ubmap := RB_MREQ.din(c_ah_rbf_ena_ubmap);
+ end if;
+
+ when c_rbaddr_mem => -- mem -----------------
+ if irbena = '1' then
+ n.cpfunc := c_cpfunc_rmem;
+ n.cpfunc(0) := RB_MREQ.we;
+ icpreq := '1';
+ end if;
+
+ when c_rbaddr_memi => -- memi ----------------
+ if irbena = '1' then
+ n.cpfunc := c_cpfunc_rmem;
+ n.cpfunc(0) := RB_MREQ.we;
+ n.doinc := '1';
+ icpreq := '1';
+ end if;
+
+ when c_rbaddr_r0 | c_rbaddr_r1 |
+ c_rbaddr_r2 | c_rbaddr_r3 |
+ c_rbaddr_r4 | c_rbaddr_r5 |
+ c_rbaddr_sp | c_rbaddr_pc => -- r* ------------------
+ if irbena = '1' then
+ n.cpfunc := c_cpfunc_rreg;
+ n.cpfunc(0) := RB_MREQ.we;
+ icpreq := '1';
+ end if;
+
+ when c_rbaddr_ibrb => -- ibrb ----------------
+ irb_dout(c_ibrb_ibf_base) := r.ibrbase;
+ irb_dout(c_ibrb_ibf_be) := r.ibrberet;
+ if RB_MREQ.we = '1' then
+ n.ibrbase := RB_MREQ.din(c_ibrb_ibf_base);
+ n.ibrberet := RB_MREQ.din(c_ibrb_ibf_be);
+ if RB_MREQ.din(c_ibrb_ibf_be) = "00" then -- both be=0 ?
+ n.ibrbe := "11";
+ else -- otherwise take 2 LSB's
+ n.ibrbe := RB_MREQ.din(c_ibrb_ibf_be);
+ end if;
+ end if;
+
+ when others =>
+ irb_ack := '0';
+
+ end case;
+
+ end if;
+
+ if icpreq = '1' then
+ irb_busy := '1';
+ n.cpreq := '1';
+ n.state := s_cpwait;
+ end if;
+
+ when s_cpwait => -- s_cpwait: wait for cp port ack ----
+ n.cpreq := '0'; -- cpreq only for 1 cycle
+
+ if (r.rbselc or r.rbseli)='0' or irbena='0' then -- rbus cycle abort
+ n.state := s_idle; -- quit
+ else
+ irb_dout := CP_DOUT;
+ irb_err := CP_STAT.cmderr or CP_STAT.cmdmerr;
+ if CP_STAT.cmdack = '1' then -- normal cycle end
+ if r.doinc = '1' then
+ n.addr := slv(unsigned(r.addr) + 1);
+ end if;
+ if r.waitstep = '1' then
+ irb_busy := '1';
+ n.state := s_cpstep;
+ else
+ n.state := s_idle;
+ end if;
+ else
+ irb_busy := '1';
+ end if;
+ end if;
+
+ when s_cpstep => -- s_cpstep: wait for cpustep done ---
+ if r.rbselc='0' or irbena='0' then -- rbus cycle abort
+ n.state := s_idle; -- quit
+ else
+ if CP_STAT.cpustep = '0' then -- cpustep done
+ n.state := s_idle;
+ else
+ irb_busy := '1';
+ end if;
+ end if;
+
+ when others => null;
+ end case;
+
+ icpaddr := cp_addr_init;
+ icpaddr.addr := r.addr;
+ icpaddr.racc := '0';
+ icpaddr.be := "11";
+ icpaddr.ena_22bit := r.ena_22bit;
+ icpaddr.ena_ubmap := r.ena_ubmap;
+
+ if r.rbseli = '1' and irbena = '1' then
+ icpaddr.addr(15 downto 13) := "111";
+ icpaddr.addr(c_ibrb_ibf_base) := r.ibrbase;
+ icpaddr.addr(5 downto 1) := RB_MREQ.addr(4 downto 0);
+ icpaddr.racc := '1';
+ icpaddr.be := r.ibrbe;
+ icpaddr.ena_22bit := '0';
+ icpaddr.ena_ubmap := '0';
+ end if;
+
+ n.cpugo_1 := CP_STAT.cpugo; -- delay cpugo
+ if CP_STAT.cpugo='0' and r.cpugo_1='1' then -- cpugo 1 -> 0 transition ?
+ irb_lam := '1';
+ end if;
+
+ N_REGS <= n;
+
+ RB_SRES.ack <= irb_ack;
+ RB_SRES.err <= irb_err;
+ RB_SRES.busy <= irb_busy;
+ RB_SRES.dout <= irb_dout;
+
+ RB_STAT(0) <= CP_STAT.cpugo;
+ RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left);
+ RB_STAT(2) <= CP_STAT.cmderr or CP_STAT.cmdmerr;
+
+ RB_LAM <= irb_lam;
+
+ CPU_RESET <= icpureset;
+
+ CP_CNTL.req <= r.cpreq;
+ CP_CNTL.func <= r.cpfunc;
+ CP_CNTL.rnum <= RB_MREQ.addr(2 downto 0);
+
+ CP_ADDR <= icpaddr;
+ CP_DIN <= RB_MREQ.din;
+
+ end process proc_next;
+
+end syn;
Index: pdp11_mem70.vbom
===================================================================
--- pdp11_mem70.vbom (nonexistent)
+++ pdp11_mem70.vbom (revision 26)
@@ -0,0 +1,8 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+${sys_conf := sys_conf.vhd}
+# components
+# design
+pdp11_mem70.vhd
Index: pdp11_vmbox.vbom
===================================================================
--- pdp11_vmbox.vbom (nonexistent)
+++ pdp11_vmbox.vbom (revision 26)
@@ -0,0 +1,13 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+${sys_conf := sys_conf.vhd}
+# components
+pdp11_mmu.vbom
+pdp11_ubmap.vbom
+../ibus/ib_sres_or_4.vbom
+../ibus/ib_sres_or_2.vbom
+../ibus/ib_sel.vbom
+# design
+pdp11_vmbox.vhd
Index: pdp11_tmu.vhd
===================================================================
--- pdp11_tmu.vhd (nonexistent)
+++ pdp11_tmu.vhd (revision 26)
@@ -0,0 +1,229 @@
+-- $Id: pdp11_tmu.vhd 444 2011-12-25 10:04:58Z mueller $
+--
+-- Copyright 2008-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_tmu - sim
+-- Description: pdp11: trace and monitor unit
+--
+-- Dependencies: -
+--
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-12-23 444 1.1 use local clkcycle count instead of simbus global
+-- 2011-11-18 427 1.0.7 now numeric_std clean
+-- 2010-10-17 333 1.0.6 use ibus V2 interface
+-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
+-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
+-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
+-- 2008-12-13 176 1.0.2 write only cycle currently used by tmu_conf
+-- 2008-08-22 161 1.0.1 rename ubf_ -> ibf_
+-- 2008-04-19 137 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.simlib.all;
+use work.simbus.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_tmu is -- trace and monitor unit
+ port (
+ CLK : in slbit; -- clock
+ ENA : in slbit := '0'; -- enable trace output
+ DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
+ DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
+ DM_STAT_CO : in dm_stat_co_type; -- DM core
+ DM_STAT_SY : in dm_stat_sy_type -- DM system
+ );
+end pdp11_tmu;
+
+
+architecture sim of pdp11_tmu is
+
+ signal R_FIRST : slbit := '1';
+
+begin
+
+ proc_tm: process (CLK)
+ variable oline : line;
+ variable clkcycle : integer := 0;
+ variable ipsw : slv16 := (others=>'0');
+ variable ibaddr : slv16 := (others=>'0');
+ variable emaddr : slv22 := (others=>'0');
+ variable dp_ireg_we_last : slbit := '0';
+ variable vm_ibsres_busy_last : slbit := '0';
+ variable vm_ibsres_ack_last : slbit := '0';
+ variable wcycle : boolean := false;
+ file ofile : text open write_mode is "tmu_ofile";
+ begin
+
+ if rising_edge(CLK) then
+
+ clkcycle := clkcycle + 1;
+
+ if R_FIRST = '1' then
+ R_FIRST <= '0';
+ write(oline, string'("#"));
+ write(oline, string'(" clkcycle:d"));
+ write(oline, string'(" cpu:o"));
+ write(oline, string'(" dp.pc:o"));
+ write(oline, string'(" dp.psw:o"));
+ write(oline, string'(" dp.ireg:o"));
+ write(oline, string'(" dp.ireg_we:b"));
+ write(oline, string'(" dp.ireg_we_last:b")); -- is ireg_we last cycle
+ write(oline, string'(" dp.dsrc:o"));
+ write(oline, string'(" dp.ddst:o"));
+ write(oline, string'(" dp.dtmp:o"));
+ write(oline, string'(" dp.dres:o"));
+ write(oline, string'(" dp.gpr_adst:o"));
+ write(oline, string'(" dp.gpr_mode:o"));
+ write(oline, string'(" dp.gpr_bytop:b"));
+ write(oline, string'(" dp.gpr_we:b"));
+
+ write(oline, string'(" vm.ibmreq.aval:b"));
+ write(oline, string'(" vm.ibmreq.re:b"));
+ write(oline, string'(" vm.ibmreq.we:b"));
+ write(oline, string'(" vm.ibmreq.rmw:b"));
+ write(oline, string'(" vm.ibmreq.be0:b"));
+ write(oline, string'(" vm.ibmreq.be1:b"));
+ write(oline, string'(" vm.ibmreq.cacc:b"));
+ write(oline, string'(" vm.ibmreq.racc:b"));
+ write(oline, string'(" vm.ibmreq.addr:o"));
+ write(oline, string'(" vm.ibmreq.din:o"));
+ write(oline, string'(" vm.ibsres.ack:b"));
+ write(oline, string'(" vm.ibsres.busy:b"));
+ write(oline, string'(" vm.ibsres.dout:o"));
+
+ write(oline, string'(" co.cpugo:b"));
+ write(oline, string'(" co.cpuhalt:b"));
+
+ write(oline, string'(" sy.emmreq.req:b"));
+ write(oline, string'(" sy.emmreq.we:b"));
+ write(oline, string'(" sy.emmreq.be:b"));
+ write(oline, string'(" sy.emmreq.cancel:b"));
+ write(oline, string'(" sy.emmreq.addr:o"));
+ write(oline, string'(" sy.emmreq.din:o"));
+ write(oline, string'(" sy.emsres.ack_r:b"));
+ write(oline, string'(" sy.emsres.ack_w:b"));
+ write(oline, string'(" sy.emsres.dout:o"));
+ write(oline, string'(" sy.chit:b"));
+
+ writeline(ofile, oline);
+ end if;
+
+ ipsw := (others=>'0');
+ ipsw(psw_ibf_cmode) := DM_STAT_DP.psw.cmode;
+ ipsw(psw_ibf_pmode) := DM_STAT_DP.psw.pmode;
+ ipsw(psw_ibf_rset) := DM_STAT_DP.psw.rset;
+ ipsw(psw_ibf_pri) := DM_STAT_DP.psw.pri;
+ ipsw(psw_ibf_tflag) := DM_STAT_DP.psw.tflag;
+ ipsw(psw_ibf_cc) := DM_STAT_DP.psw.cc;
+
+ ibaddr := "1110000000000000";
+ ibaddr(DM_STAT_VM.ibmreq.addr'range) := DM_STAT_VM.ibmreq.addr;
+
+ emaddr := (others=>'0');
+ emaddr(DM_STAT_SY.emmreq.addr'range) := DM_STAT_SY.emmreq.addr;
+
+ wcycle := false;
+ if dp_ireg_we_last='1' or
+ DM_STAT_DP.gpr_we='1' or
+ DM_STAT_SY.emmreq.req='1' or
+ DM_STAT_SY.emsres.ack_r='1' or
+ DM_STAT_SY.emsres.ack_w='1' or
+ DM_STAT_SY.emmreq.cancel='1' or
+ DM_STAT_VM.ibmreq.re='1' or
+ DM_STAT_VM.ibmreq.we='1' or
+ DM_STAT_VM.ibsres.ack='1'
+ then
+ wcycle := true;
+ end if;
+
+ if DM_STAT_VM.ibsres.busy='0' and
+ (vm_ibsres_busy_last='1' and vm_ibsres_ack_last='0')
+ then
+ wcycle := true;
+ end if;
+
+ if ENA = '0' then -- if not enabled
+ wcycle := false; -- force to not logged...
+ end if;
+
+ if wcycle then
+ write(oline, clkcycle, right, 9);
+ write(oline, string'(" 0"));
+ writeoct(oline, DM_STAT_DP.pc, right, 7);
+ writeoct(oline, ipsw, right, 7);
+ writeoct(oline, DM_STAT_DP.ireg, right, 7);
+ write(oline, DM_STAT_DP.ireg_we, right, 2);
+ write(oline, dp_ireg_we_last, right, 2);
+ writeoct(oline, DM_STAT_DP.dsrc, right, 7);
+ writeoct(oline, DM_STAT_DP.ddst, right, 7);
+ writeoct(oline, DM_STAT_DP.dtmp, right, 7);
+ writeoct(oline, DM_STAT_DP.dres, right, 7);
+ writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
+ writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
+ write(oline, DM_STAT_DP.gpr_bytop, right, 2);
+ write(oline, DM_STAT_DP.gpr_we, right, 2);
+
+ write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
+ write(oline, DM_STAT_VM.ibmreq.re, right, 2);
+ write(oline, DM_STAT_VM.ibmreq.we, right, 2);
+ write(oline, DM_STAT_VM.ibmreq.rmw, right, 2);
+ write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
+ write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
+ write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
+ write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
+ writeoct(oline, ibaddr, right, 7);
+ writeoct(oline, DM_STAT_VM.ibmreq.din, right, 7);
+ write(oline, DM_STAT_VM.ibsres.ack, right, 2);
+ write(oline, DM_STAT_VM.ibsres.busy, right, 2);
+ writeoct(oline, DM_STAT_VM.ibsres.dout, right, 7);
+
+ write(oline, DM_STAT_CO.cpugo, right, 2);
+ write(oline, DM_STAT_CO.cpuhalt, right, 2);
+
+ write(oline, DM_STAT_SY.emmreq.req, right, 2);
+ write(oline, DM_STAT_SY.emmreq.we, right, 2);
+ write(oline, DM_STAT_SY.emmreq.be, right, 3);
+ write(oline, DM_STAT_SY.emmreq.cancel, right, 2);
+ writeoct(oline, emaddr, right, 9);
+ writeoct(oline, DM_STAT_SY.emmreq.din, right, 7);
+ write(oline, DM_STAT_SY.emsres.ack_r, right, 2);
+ write(oline, DM_STAT_SY.emsres.ack_w, right, 2);
+ writeoct(oline, DM_STAT_SY.emsres.dout, right, 7);
+ write(oline, DM_STAT_SY.chit, right, 2);
+
+ writeline(ofile, oline);
+ end if;
+
+ dp_ireg_we_last := DM_STAT_DP.ireg_we;
+ vm_ibsres_busy_last := DM_STAT_VM.ibsres.busy;
+ vm_ibsres_ack_last := DM_STAT_VM.ibsres.ack;
+
+ end if;
+
+ end process proc_tm;
+
+end sim;
Index: pdp11_sys70.vbom
===================================================================
--- pdp11_sys70.vbom (nonexistent)
+++ pdp11_sys70.vbom (revision 26)
@@ -0,0 +1,8 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+${sys_conf := sys_conf.vhd}
+# components
+# design
+pdp11_sys70.vhd
Index: pdp11_irq.vhd
===================================================================
--- pdp11_irq.vhd (nonexistent)
+++ pdp11_irq.vhd (revision 26)
@@ -0,0 +1,140 @@
+-- $Id: pdp11_irq.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2007-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_irq - syn
+-- Description: pdp11: interrupt requester
+--
+-- Dependencies: ib_sel
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.2.2 now numeric_std clean
+-- 2010-10-23 335 1.2.1 use ib_sel
+-- 2010-10-17 333 1.2 use ibus V2 interface
+-- 2008-08-22 161 1.1.4 use iblib
+-- 2008-04-25 138 1.1.3 use BRESET to clear pirq
+-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
+-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
+-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_irq is -- interrupt requester
+ port (
+ CLK : in slbit; -- clock
+ BRESET : in slbit; -- ibus reset
+ INT_ACK : in slbit; -- interrupt acknowledge from CPU
+ EI_PRI : in slv3; -- external interrupt priority
+ EI_VECT : in slv9_2; -- external interrupt vector
+ EI_ACKM : out slbit; -- external interrupt acknowledge
+ PRI : out slv3; -- interrupt priority
+ VECT : out slv9_2; -- interrupt vector
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_irq;
+
+architecture syn of pdp11_irq is
+
+ constant ibaddr_pirq : slv16 := slv(to_unsigned(8#177772#,16));
+
+ subtype pirq_ubf_pir is integer range 15 downto 9;
+ subtype pirq_ubf_pia_h is integer range 7 downto 5;
+ subtype pirq_ubf_pia_l is integer range 3 downto 1;
+
+ signal IBSEL_PIRQ : slbit := '0';
+ signal R_PIRQ : slv8_1 := (others => '0'); -- pirq register
+ signal PI_PRI : slv3 := (others => '0'); -- prog.int. priority
+
+-- attribute PRIORITY_EXTRACT : string;
+-- attribute PRIORITY_EXTRACT of PI_PRI : signal is "force";
+
+begin
+
+ SEL : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_pirq)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_PIRQ
+ );
+
+ proc_ibres : process (IBSEL_PIRQ, IB_MREQ, R_PIRQ, PI_PRI)
+ variable idout : slv16 := (others=>'0');
+ begin
+ idout := (others=>'0');
+ if IBSEL_PIRQ = '1' then
+ idout(pirq_ubf_pir) := R_PIRQ;
+ idout(pirq_ubf_pia_h) := PI_PRI;
+ idout(pirq_ubf_pia_l) := PI_PRI;
+ end if;
+ IB_SRES.dout <= idout;
+ IB_SRES.ack <= IBSEL_PIRQ and (IB_MREQ.re or IB_MREQ.we); -- ack all
+ IB_SRES.busy <= '0';
+ end process proc_ibres;
+
+ proc_pirq : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if BRESET = '1' then
+ R_PIRQ <= (others => '0');
+ elsif IBSEL_PIRQ='1' and IB_MREQ.we='1'and IB_MREQ.be1='1' then
+ R_PIRQ <= IB_MREQ.din(pirq_ubf_pir);
+ end if;
+ end if;
+ end process proc_pirq;
+
+ PI_PRI <= "111" when R_PIRQ(7)='1' else
+ "110" when R_PIRQ(6)='1' else
+ "101" when R_PIRQ(5)='1' else
+ "100" when R_PIRQ(4)='1' else
+ "011" when R_PIRQ(3)='1' else
+ "010" when R_PIRQ(2)='1' else
+ "001" when R_PIRQ(1)='1' else
+ "000";
+
+ proc_irq : process (PI_PRI, EI_PRI, EI_VECT, INT_ACK)
+ constant vect_default : slv9 := slv(to_unsigned(8#240#,9));
+ begin
+
+ EI_ACKM <= '0';
+
+ if unsigned(EI_PRI) > unsigned(PI_PRI) then
+ PRI <= EI_PRI;
+ VECT <= EI_VECT;
+ EI_ACKM <= INT_ACK;
+ else
+ PRI <= PI_PRI;
+ VECT <= vect_default(8 downto 2);
+ end if;
+
+ end process proc_irq;
+
+end syn;
Index: pdp11_cache.vhd
===================================================================
--- pdp11_cache.vhd (nonexistent)
+++ pdp11_cache.vhd (revision 26)
@@ -0,0 +1,447 @@
+-- $Id: pdp11_cache.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2008-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_cache - syn
+-- Description: pdp11: cache
+--
+-- Dependencies: memlib/ram_2swsr_rfirst_gen
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.0.3 now numeric_std clean
+-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
+-- factor invariants out of if's; fix tag rmiss logic
+-- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem
+-- recode, ghdl doesn't like partial vector port maps
+-- 2008-02-16 116 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+use work.pdp11.all;
+
+entity pdp11_cache is -- cache
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ EM_MREQ : in em_mreq_type; -- em request
+ EM_SRES : out em_sres_type; -- em response
+ FMISS : in slbit; -- force miss
+ CHIT : out slbit; -- cache hit flag
+ MEM_REQ : out slbit; -- memory: request
+ MEM_WE : out slbit; -- memory: write enable
+ MEM_BUSY : in slbit; -- memory: controller busy
+ MEM_ACK_R : in slbit; -- memory: acknowledge read
+ MEM_ADDR : out slv20; -- memory: address
+ MEM_BE : out slv4; -- memory: byte enable
+ MEM_DI : out slv32; -- memory: data in (memory view)
+ MEM_DO : in slv32 -- memory: data out (memory view)
+ );
+end pdp11_cache;
+
+
+architecture syn of pdp11_cache is
+
+ type state_type is (
+ s_idle, -- s_idle: wait for req
+ s_read, -- s_read: read cycle
+ s_rmiss, -- s_rmiss: read miss
+ s_write -- s_write: write cycle
+ );
+
+ type regs_type is record
+ state : state_type; -- state
+ addr_w : slbit; -- address - word select
+ addr_l : slv11; -- address - cache line address
+ addr_t : slv9; -- address - cache tag part
+ be : slv4; -- byte enables (at 4 byte level)
+ di : slv16; -- data
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ s_idle, -- state
+ '0', -- addr_w
+ (others=>'0'), -- addr_l
+ (others=>'0'), -- addr_t
+ (others=>'0'), -- be
+ (others=>'0') -- di
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ signal CMEM_TAG_CEA : slbit := '0';
+ signal CMEM_TAG_CEB : slbit := '0';
+ signal CMEM_TAG_WEA : slbit := '0';
+ signal CMEM_TAG_WEB : slbit := '0';
+ signal CMEM_TAG_DIB : slv9 := (others=>'0');
+ signal CMEM_TAG_DOA : slv9 := (others=>'0');
+ signal CMEM_DAT_CEA : slbit := '0';
+ signal CMEM_DAT_CEB : slbit := '0';
+ signal CMEM_DAT_WEA : slv4 := "0000";
+ signal CMEM_DAT_WEB : slv4 := "0000";
+ signal CMEM_DIA_0 : slv9 := (others=>'0');
+ signal CMEM_DIA_1 : slv9 := (others=>'0');
+ signal CMEM_DIA_2 : slv9 := (others=>'0');
+ signal CMEM_DIA_3 : slv9 := (others=>'0');
+ signal CMEM_DIB_0 : slv9 := (others=>'0');
+ signal CMEM_DIB_1 : slv9 := (others=>'0');
+ signal CMEM_DIB_2 : slv9 := (others=>'0');
+ signal CMEM_DIB_3 : slv9 := (others=>'0');
+ signal CMEM_DOA_0 : slv9 := (others=>'0');
+ signal CMEM_DOA_1 : slv9 := (others=>'0');
+ signal CMEM_DOA_2 : slv9 := (others=>'0');
+ signal CMEM_DOA_3 : slv9 := (others=>'0');
+
+begin
+
+ CMEM_TAG : ram_2swsr_rfirst_gen
+ generic map (
+ AWIDTH => 11,
+ DWIDTH => 9)
+ port map (
+ CLKA => CLK,
+ CLKB => CLK,
+ ENA => CMEM_TAG_CEA,
+ ENB => CMEM_TAG_CEB,
+ WEA => CMEM_TAG_WEA,
+ WEB => CMEM_TAG_WEB,
+ ADDRA => EM_MREQ.addr(12 downto 2),
+ ADDRB => R_REGS.addr_l,
+ DIA => EM_MREQ.addr(21 downto 13),
+ DIB => CMEM_TAG_DIB,
+ DOA => CMEM_TAG_DOA,
+ DOB => open
+ );
+
+ CMEM_DAT0 : ram_2swsr_rfirst_gen
+ generic map (
+ AWIDTH => 11,
+ DWIDTH => 9)
+ port map (
+ CLKA => CLK,
+ CLKB => CLK,
+ ENA => CMEM_DAT_CEA,
+ ENB => CMEM_DAT_CEB,
+ WEA => CMEM_DAT_WEA(0),
+ WEB => CMEM_DAT_WEB(0),
+ ADDRA => EM_MREQ.addr(12 downto 2),
+ ADDRB => R_REGS.addr_l,
+ DIA => CMEM_DIA_0,
+ DIB => CMEM_DIB_0,
+ DOA => CMEM_DOA_0,
+ DOB => open
+ );
+
+ CMEM_DAT1 : ram_2swsr_rfirst_gen
+ generic map (
+ AWIDTH => 11,
+ DWIDTH => 9)
+ port map (
+ CLKA => CLK,
+ CLKB => CLK,
+ ENA => CMEM_DAT_CEA,
+ ENB => CMEM_DAT_CEB,
+ WEA => CMEM_DAT_WEA(1),
+ WEB => CMEM_DAT_WEB(1),
+ ADDRA => EM_MREQ.addr(12 downto 2),
+ ADDRB => R_REGS.addr_l,
+ DIA => CMEM_DIA_1,
+ DIB => CMEM_DIB_1,
+ DOA => CMEM_DOA_1,
+ DOB => open
+ );
+
+ CMEM_DAT2 : ram_2swsr_rfirst_gen
+ generic map (
+ AWIDTH => 11,
+ DWIDTH => 9)
+ port map (
+ CLKA => CLK,
+ CLKB => CLK,
+ ENA => CMEM_DAT_CEA,
+ ENB => CMEM_DAT_CEB,
+ WEA => CMEM_DAT_WEA(2),
+ WEB => CMEM_DAT_WEB(2),
+ ADDRA => EM_MREQ.addr(12 downto 2),
+ ADDRB => R_REGS.addr_l,
+ DIA => CMEM_DIA_2,
+ DIB => CMEM_DIB_2,
+ DOA => CMEM_DOA_2,
+ DOB => open
+ );
+
+ CMEM_DAT3 : ram_2swsr_rfirst_gen
+ generic map (
+ AWIDTH => 11,
+ DWIDTH => 9)
+ port map (
+ CLKA => CLK,
+ CLKB => CLK,
+ ENA => CMEM_DAT_CEA,
+ ENB => CMEM_DAT_CEB,
+ WEA => CMEM_DAT_WEA(3),
+ WEB => CMEM_DAT_WEB(3),
+ ADDRA => EM_MREQ.addr(12 downto 2),
+ ADDRB => R_REGS.addr_l,
+ DIA => CMEM_DIA_3,
+ DIB => CMEM_DIB_3,
+ DOA => CMEM_DOA_3,
+ DOB => open
+ );
+
+ proc_regs: process (CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if GRESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ proc_next: process (R_REGS, EM_MREQ, FMISS,
+ CMEM_TAG_DOA,
+ CMEM_DOA_0, CMEM_DOA_1, CMEM_DOA_2, CMEM_DOA_3,
+ MEM_BUSY, MEM_ACK_R, MEM_DO)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable iaddr_w : slbit := '0';
+ variable iaddr_l : slv11 := (others=>'0');
+ variable iaddr_t : slv9 := (others=>'0');
+
+ variable itagok : slbit := '0';
+ variable ivalok : slbit := '0';
+
+ variable icmem_tag_cea : slbit := '0';
+ variable icmem_tag_ceb : slbit := '0';
+ variable icmem_tag_wea : slbit := '0';
+ variable icmem_tag_web : slbit := '0';
+ variable icmem_tag_dib : slv9 := (others=>'0');
+ variable icmem_dat_cea : slbit := '0';
+ variable icmem_dat_ceb : slbit := '0';
+ variable icmem_dat_wea : slv4 := "0000";
+ variable icmem_dat_web : slv4 := "0000";
+ variable icmem_val_doa : slv4 := "0000";
+ variable icmem_dat_doa : slv32 := (others=>'0');
+ variable icmem_val_dib : slv4 := "0000";
+ variable icmem_dat_dib : slv32 := (others=>'0');
+
+ variable iackr : slbit := '0';
+ variable iackw : slbit := '0';
+ variable ichit : slbit := '0';
+ variable iosel : slv2 := "11";
+
+ variable imem_reqr : slbit := '0';
+ variable imem_reqw : slbit := '0';
+ variable imem_be : slv4 := "0000";
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ iaddr_w := EM_MREQ.addr(1); -- get word select
+ iaddr_l := EM_MREQ.addr(12 downto 2); -- get cache line addr
+ iaddr_t := EM_MREQ.addr(21 downto 13); -- get cache tag part
+
+ icmem_tag_cea := '0';
+ icmem_tag_ceb := '0';
+ icmem_tag_wea := '0';
+ icmem_tag_web := '0';
+ icmem_tag_dib := r.addr_t; -- default, local define whenver used
+ icmem_dat_cea := '0';
+ icmem_dat_ceb := '0';
+ icmem_dat_wea := "0000";
+ icmem_dat_web := "0000";
+ icmem_val_dib := "0000";
+ icmem_dat_dib := MEM_DO; -- default, local define whenver used
+
+ icmem_val_doa(0) := CMEM_DOA_0(8);
+ icmem_dat_doa( 7 downto 0) := CMEM_DOA_0(7 downto 0);
+ icmem_val_doa(1) := CMEM_DOA_1(8);
+ icmem_dat_doa(15 downto 8) := CMEM_DOA_1(7 downto 0);
+ icmem_val_doa(2) := CMEM_DOA_2(8);
+ icmem_dat_doa(23 downto 16) := CMEM_DOA_2(7 downto 0);
+ icmem_val_doa(3) := CMEM_DOA_3(8);
+ icmem_dat_doa(31 downto 24) := CMEM_DOA_3(7 downto 0);
+
+ itagok := '0';
+ if CMEM_TAG_DOA = r.addr_t then -- cache tag hit
+ itagok := '1';
+ end if;
+ ivalok := '0';
+ if (icmem_val_doa and r.be) = r.be then
+ ivalok := '1';
+ end if;
+
+ iackr := '0';
+ iackw := '0';
+ ichit := '0';
+ iosel := "11"; -- default to ext. mem data
+ -- this prevents U's from cache bram's
+ -- to propagate to dout in beginning...
+
+ imem_reqr := '0';
+ imem_reqw := '0';
+ imem_be := r.be;
+
+ case r.state is
+ when s_idle => -- s_idle: wait for req
+ n.addr_w := iaddr_w; -- capture address: word select
+ n.addr_l := iaddr_l; -- capture address: cache line addr
+ n.addr_t := iaddr_t; -- capture address: cache tag part
+ n.be := "0000";
+ icmem_tag_cea := '1'; -- access cache tag port A
+ icmem_dat_cea := '1'; -- access cache data port A
+ if iaddr_w = '0' then -- capture byte enables at 4 byte lvl
+ n.be(1 downto 0) := EM_MREQ.be;
+ else
+ n.be(3 downto 2) := EM_MREQ.be;
+ end if;
+ n.di := EM_MREQ.din; -- capture data
+
+ if EM_MREQ.req = '1' then -- if access requested
+ if EM_MREQ.we = '0' then -- if READ requested
+ n.state := s_read; -- next: read
+
+ else -- if WRITE requested
+ icmem_tag_wea := '1'; -- write tag
+ icmem_dat_wea := n.be; -- write cache data
+ n.state := s_write; -- next: write
+ end if;
+ end if;
+
+ when s_read => -- s_read: read cycle
+ iosel := '0' & r.addr_w; -- output select: cache
+ imem_be := "1111"; -- mem read: all 4 bytes
+ if EM_MREQ.cancel = '0' then
+ if FMISS='0' and itagok='1' and ivalok='1' then -- read tag&val hit
+ iackr := '1'; -- signal read acknowledge
+ ichit := '1'; -- signal cache hit
+ n.state := s_idle; -- next: back to idle
+ else -- read miss
+ if MEM_BUSY = '0' then -- if mem not busy
+ imem_reqr :='1'; -- request mem read
+ n.state := s_rmiss; -- next: rmiss, wait for mem data
+ end if;
+ end if;
+ else
+ n.state := s_idle; -- next: back to idle
+ end if;
+
+ when s_rmiss => -- s_rmiss: read cycle
+ iosel := '1' & r.addr_w; -- output select: memory
+ icmem_tag_web := '1'; -- cache update: write tag
+ icmem_tag_dib := r.addr_t; -- cache update: new tag
+ icmem_val_dib := "1111"; -- cache update: all valid
+ icmem_dat_dib := MEM_DO; -- cache update: data from mem
+ icmem_dat_web := "1111"; -- cache update: write all 4 bytes
+ if MEM_ACK_R = '1' then -- mem data valid
+ iackr := '1'; -- signal read acknowledge
+ icmem_tag_ceb := '1'; -- access cache tag port B
+ icmem_dat_ceb := '1'; -- access cache data port B
+ n.state := s_idle; -- next: back to idle
+ end if;
+
+ when s_write => -- s_write: write cycle
+ icmem_tag_dib := CMEM_TAG_DOA; -- cache restore: last state
+ icmem_dat_dib := icmem_dat_doa; -- cache restore: last state
+ if EM_MREQ.cancel = '0' then -- request ok
+ if MEM_BUSY = '0' then -- if mem not busy
+ if itagok = '0' then -- if write tag miss
+ icmem_dat_ceb := '1'; -- access cache (invalidate)
+ icmem_dat_web := not r.be; -- write missed bytes
+ icmem_val_dib := "0000"; -- invalidate missed bytes
+ end if;
+ imem_reqw := '1'; -- write back to main memory
+ iackw := '1'; -- and done
+ n.state := s_idle; -- next: back to idle
+ end if;
+
+ else -- request canceled -> restore
+ icmem_tag_ceb := '1'; -- access cache line
+ icmem_tag_web := '1'; -- write tag
+ icmem_dat_ceb := '1'; -- access cache line
+ icmem_dat_web := "1111"; -- restore cache line
+ icmem_val_dib := icmem_val_doa; -- cache restore: last state
+ n.state := s_idle; -- next: back to idle
+ end if;
+
+ when others => null;
+ end case;
+
+ N_REGS <= n;
+
+ CMEM_TAG_CEA <= icmem_tag_cea;
+ CMEM_TAG_CEB <= icmem_tag_ceb;
+ CMEM_TAG_WEA <= icmem_tag_wea;
+ CMEM_TAG_WEB <= icmem_tag_web;
+ CMEM_TAG_DIB <= icmem_tag_dib;
+ CMEM_DAT_CEA <= icmem_dat_cea;
+ CMEM_DAT_CEB <= icmem_dat_ceb;
+ CMEM_DAT_WEA <= icmem_dat_wea;
+ CMEM_DAT_WEB <= icmem_dat_web;
+
+ CMEM_DIA_0(8) <= '1';
+ CMEM_DIA_0(7 downto 0) <= EM_MREQ.din( 7 downto 0);
+ CMEM_DIA_1(8) <= '1';
+ CMEM_DIA_1(7 downto 0) <= EM_MREQ.din(15 downto 8);
+ CMEM_DIA_2(8) <= '1';
+ CMEM_DIA_2(7 downto 0) <= EM_MREQ.din( 7 downto 0);
+ CMEM_DIA_3(8) <= '1';
+ CMEM_DIA_3(7 downto 0) <= EM_MREQ.din(15 downto 8);
+
+ CMEM_DIB_0(8) <= icmem_val_dib(0);
+ CMEM_DIB_0(7 downto 0) <= icmem_dat_dib(7 downto 0);
+ CMEM_DIB_1(8) <= icmem_val_dib(1);
+ CMEM_DIB_1(7 downto 0) <= icmem_dat_dib(15 downto 8);
+ CMEM_DIB_2(8) <= icmem_val_dib(2);
+ CMEM_DIB_2(7 downto 0) <= icmem_dat_dib(23 downto 16);
+ CMEM_DIB_3(8) <= icmem_val_dib(3);
+ CMEM_DIB_3(7 downto 0) <= icmem_dat_dib(31 downto 24);
+
+ EM_SRES <= em_sres_init;
+ EM_SRES.ack_r <= iackr;
+ EM_SRES.ack_w <= iackw;
+ case iosel is
+ when "00" => EM_SRES.dout <= icmem_dat_doa(15 downto 0);
+ when "01" => EM_SRES.dout <= icmem_dat_doa(31 downto 16);
+ when "10" => EM_SRES.dout <= MEM_DO(15 downto 0);
+ when "11" => EM_SRES.dout <= MEM_DO(31 downto 16);
+ when others => null;
+ end case;
+
+ CHIT <= ichit;
+
+ MEM_REQ <= imem_reqr or imem_reqw;
+ MEM_WE <= imem_reqw;
+ MEM_ADDR <= r.addr_t & r.addr_l;
+ MEM_BE <= imem_be;
+ MEM_DI <= r.di & r.di;
+
+ end process proc_next;
+
+end syn;
Index: pdp11_mmu_sadr.vhd
===================================================================
--- pdp11_mmu_sadr.vhd (nonexistent)
+++ pdp11_mmu_sadr.vhd (revision 26)
@@ -0,0 +1,287 @@
+-- $Id: pdp11_mmu_sadr.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_mmu_sadr - syn
+-- Description: pdp11: mmu SAR/SDR register set
+--
+-- Dependencies: memlib/ram_1swar_gen
+--
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.3.3 now numeric_std clean
+-- 2010-12-30 351 1.3.2 BUGFIX: fix sensitivity list of proc_eaddr
+-- 2010-10-23 335 1.3.1 change proc_eaddr logic, shorten logic path
+-- 2010-10-17 333 1.3 use ibus V2 interface
+-- 2008-08-22 161 1.2.2 rename ubf_ -> ibf_; use iblib
+-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
+-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- 2008-01-01 109 1.2 renamed from _mmu_regfile.
+-- redesign of _mmu register file, use one large dram.
+-- logic from _mmu_regfile, interface from _mmu_regset
+-- 2007-12-30 108 1.1.1 use ubf_byte[01]; move SADR memory address mux here
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_mmu_sadr is -- mmu SAR/SDR register set
+ port (
+ CLK : in slbit; -- clock
+ MODE : in slv2; -- mode
+ ASN : in slv4; -- augmented segment number (1+3 bit)
+ AIB_WE : in slbit; -- update AIB
+ AIB_SETA : in slbit; -- set access AIB
+ AIB_SETW : in slbit; -- set write AIB
+ SARSDR : out sarsdr_type; -- combined SAR/SDR
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_mmu_sadr;
+
+architecture syn of pdp11_mmu_sadr is
+
+ -- bit 1 111 1
+ -- bit 5 432 109 876 543 210
+ --
+ -- kmdr 172300 -> 1 111 010 011 000 000
+ -- kmar 172340 -> 1 111 010 011 100 000
+ -- smdr 172200 -> 1 111 010 010 000 000
+ -- smar 172240 -> 1 111 010 010 100 000
+ -- umdr 177600 -> 1 111 111 110 000 000
+ -- umar 177640 -> 1 111 111 110 100 000
+ --
+ -- mode => (addr(8), not addr(6)) [Note: km "00" sm "01" um "11"]
+
+ constant ibaddr_kmdar : slv16 := slv(to_unsigned(8#172300#,16));
+ constant ibaddr_smdar : slv16 := slv(to_unsigned(8#172200#,16));
+ constant ibaddr_umdar : slv16 := slv(to_unsigned(8#177600#,16));
+
+ subtype sdr_ibf_slf is integer range 14 downto 8;
+ subtype sdr_ibf_aib is integer range 7 downto 6;
+ subtype sdr_ibf_acf is integer range 3 downto 0;
+
+ signal SADR_ADDR : slv6 := (others=>'0'); -- address (from mmu or ibus)
+
+ signal SAR_HIGH_WE : slbit := '0'; -- write enables
+ signal SAR_LOW_WE : slbit := '0'; -- ...
+ signal SDR_SLF_WE : slbit := '0'; -- ...
+ signal SDR_AIB_WE : slbit := '0'; -- ...
+ signal SDR_LOW_WE : slbit := '0'; -- ...
+
+ signal R_IBSEL_DR : slbit := '0'; -- DR's selected from ibus
+ signal R_IBSEL_AR : slbit := '0'; -- AR's selected from ibus
+
+ signal SAF : slv16 := (others=>'0'); -- current SAF
+ signal SLF : slv7 := (others=>'0'); -- current SLF
+ signal AIB : slv2 := "00"; -- current AIB flags
+ signal N_AIB : slv2 := "00"; -- next AIB flags
+ signal ED_ACF : slv4 := "0000"; -- current ED & ACF
+
+begin
+
+ SAR_HIGH : ram_1swar_gen
+ generic map (
+ AWIDTH => 6,
+ DWIDTH => 8)
+ port map (
+ CLK => CLK,
+ WE => SAR_HIGH_WE,
+ ADDR => SADR_ADDR,
+ DI => IB_MREQ.din(ibf_byte1),
+ DO => SAF(ibf_byte1));
+
+ SAR_LOW : ram_1swar_gen
+ generic map (
+ AWIDTH => 6,
+ DWIDTH => 8)
+ port map (
+ CLK => CLK,
+ WE => SAR_LOW_WE,
+ ADDR => SADR_ADDR,
+ DI => IB_MREQ.din(ibf_byte0),
+ DO => SAF(ibf_byte0));
+
+ SDR_SLF : ram_1swar_gen
+ generic map (
+ AWIDTH => 6,
+ DWIDTH => 7)
+ port map (
+ CLK => CLK,
+ WE => SDR_SLF_WE,
+ ADDR => SADR_ADDR,
+ DI => IB_MREQ.din(sdr_ibf_slf),
+ DO => SLF);
+
+ SDR_AIB : ram_1swar_gen
+ generic map (
+ AWIDTH => 6,
+ DWIDTH => 2)
+ port map (
+ CLK => CLK,
+ WE => SDR_AIB_WE,
+ ADDR => SADR_ADDR,
+ DI => N_AIB,
+ DO => AIB);
+
+ SDR_LOW : ram_1swar_gen
+ generic map (
+ AWIDTH => 6,
+ DWIDTH => 4)
+ port map (
+ CLK => CLK,
+ WE => SDR_LOW_WE,
+ ADDR => SADR_ADDR,
+ DI => IB_MREQ.din(sdr_ibf_acf),
+ DO => ED_ACF);
+
+ -- determine IBSEL's and the address for accessing the SADR's
+
+ proc_ibsel: process (CLK)
+ variable ibsel_dr : slbit := '0';
+ variable ibsel_ar : slbit := '0';
+ begin
+ if rising_edge(CLK) then
+ ibsel_dr := '0';
+ ibsel_ar := '0';
+ if IB_MREQ.aval = '1' then
+ if IB_MREQ.addr(12 downto 6)=ibaddr_kmdar(12 downto 6) or
+ IB_MREQ.addr(12 downto 6)=ibaddr_smdar(12 downto 6) or
+ IB_MREQ.addr(12 downto 6)=ibaddr_umdar(12 downto 6) then
+ if IB_MREQ.addr(5) = '0' then
+ ibsel_dr := '1';
+ else
+ ibsel_ar := '1';
+ end if;
+ end if;
+ end if;
+ R_IBSEL_DR <= ibsel_dr;
+ R_IBSEL_AR <= ibsel_ar;
+ end if;
+ end process proc_ibsel;
+
+ proc_ibres : process (R_IBSEL_DR, R_IBSEL_AR, IB_MREQ, SAF, SLF, AIB, ED_ACF)
+ variable sarout : slv16 := (others=>'0'); -- IB sar out
+ variable sdrout : slv16 := (others=>'0'); -- IB sdr out
+ begin
+
+ sarout := (others=>'0');
+ if R_IBSEL_AR = '1' then
+ sarout := SAF;
+ end if;
+
+ sdrout := (others=>'0');
+ if R_IBSEL_DR = '1' then
+ sdrout(sdr_ibf_slf) := SLF;
+ sdrout(sdr_ibf_aib) := AIB;
+ sdrout(sdr_ibf_acf) := ED_ACF;
+ end if;
+
+ IB_SRES.dout <= sarout or sdrout;
+ IB_SRES.ack <= (R_IBSEL_DR or R_IBSEL_AR) and
+ (IB_MREQ.re or IB_MREQ.we); -- ack all
+ IB_SRES.busy <= '0';
+
+ end process proc_ibres;
+
+ -- the eaddr select should be done as early as possible, it is in the
+ -- mmu paadr logic path. Currently it's derived from 4 flops. If that's
+ -- to slow just use IB_MREQ.we or IB_MREQ.we, that should be sufficient
+ -- and reduce the eaddr mux to a 4-input LUT. Last resort is a 2 cycle ibus
+ -- access with a state flop marking the 2nd cycle of a re/we transaction.
+
+ proc_eaddr: process (IB_MREQ, MODE, ASN, R_IBSEL_DR, R_IBSEL_AR)
+ variable eaddr : slv6 := (others=>'0');
+ variable idr : slbit := '0';
+ variable iar : slbit := '0';
+ begin
+
+ eaddr := MODE & ASN;
+
+ if (R_IBSEL_DR='1' or R_IBSEL_AR='1') and
+ (IB_MREQ.re='1' or IB_MREQ.we='1') then
+ eaddr(5) := IB_MREQ.addr(8);
+ eaddr(4) := not IB_MREQ.addr(6);
+ eaddr(3 downto 0) := IB_MREQ.addr(4 downto 1);
+ end if;
+
+ SADR_ADDR <= eaddr;
+
+ end process proc_eaddr;
+
+ proc_comb : process (R_IBSEL_AR, R_IBSEL_DR, IB_MREQ, AIB_WE,
+ AIB_SETA, AIB_SETW,
+ SAF, SLF, AIB, ED_ACF)
+ begin
+
+ N_AIB <= "00";
+ SAR_HIGH_WE <= '0';
+ SAR_LOW_WE <= '0';
+ SDR_SLF_WE <= '0';
+ SDR_AIB_WE <= '0';
+ SDR_LOW_WE <= '0';
+
+ if IB_MREQ.we = '1' then
+ if R_IBSEL_AR = '1' then
+ if IB_MREQ.be1 = '1' then
+ SAR_HIGH_WE <= '1';
+ end if;
+ if IB_MREQ.be0 = '1' then
+ SAR_LOW_WE <= '1';
+ end if;
+ end if;
+
+ if R_IBSEL_DR = '1' then
+ if IB_MREQ.be1 = '1' then
+ SDR_SLF_WE <= '1';
+ end if;
+ if IB_MREQ.be0 = '1' then
+ SDR_LOW_WE <= '1';
+ end if;
+ end if;
+
+ if (R_IBSEL_AR or R_IBSEL_DR)='1' then
+ N_AIB <= "00";
+ SDR_AIB_WE <= '1';
+ end if;
+ end if;
+
+ if AIB_WE = '1' then
+ N_AIB(0) <= AIB(0) or AIB_SETW;
+ N_AIB(1) <= AIB(1) or AIB_SETA;
+ SDR_AIB_WE <= '1';
+ end if;
+
+ SARSDR.saf <= SAF;
+ SARSDR.slf <= SLF;
+ SARSDR.ed <= ED_ACF(3);
+ SARSDR.acf <= ED_ACF(2 downto 0);
+
+ end process proc_comb;
+
+end syn;
Index: pdp11_bram.vhd
===================================================================
--- pdp11_bram.vhd (nonexistent)
+++ pdp11_bram.vhd (revision 26)
@@ -0,0 +1,139 @@
+-- $Id: pdp11_bram.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2008-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_bram - syn
+-- Description: pdp11: BRAM based ext. memory dummy
+--
+-- Dependencies: memlib/ram_2swsr_rfirst_gen
+-- Test bench: -
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.0.3 now numeric_std clean
+-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
+-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
+-- 2008-02-17 117 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+use work.pdp11.all;
+
+entity pdp11_bram is -- cache
+ generic (
+ AWIDTH : positive := 14); -- address width
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ EM_MREQ : in em_mreq_type; -- em request
+ EM_SRES : out em_sres_type -- em response
+ );
+end pdp11_bram;
+
+
+architecture syn of pdp11_bram is
+
+ type regs_type is record
+ req_r : slbit; -- read request
+ req_w : slbit; -- write request
+ be : slv2; -- byte enables
+ addr : slv(AWIDTH-1 downto 1); -- address
+ end record regs_type;
+
+ constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
+
+ constant regs_init : regs_type := (
+ '0','0', -- req_r,w
+ (others=>'0'), -- be
+ addrzero -- addr
+ );
+
+ signal R_REGS : regs_type := regs_init; -- state registers
+ signal N_REGS : regs_type := regs_init; -- next value state regs
+
+ signal MEM_ENB : slbit := '0';
+ signal MEM_WEA : slv2 := "00";
+ signal MEM_DOA : slv16 := (others=>'0');
+begin
+
+ MEM_BYT0 : ram_2swsr_rfirst_gen
+ generic map (
+ AWIDTH => AWIDTH-1,
+ DWIDTH => 8)
+ port map (
+ CLKA => CLK,
+ CLKB => CLK,
+ ENA => EM_MREQ.req,
+ ENB => MEM_ENB,
+ WEA => MEM_WEA(0),
+ WEB => R_REGS.be(0),
+ ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
+ ADDRB => R_REGS.addr,
+ DIA => EM_MREQ.din(7 downto 0),
+ DIB => MEM_DOA(7 downto 0),
+ DOA => MEM_DOA(7 downto 0),
+ DOB => open
+ );
+
+ MEM_BYT1 : ram_2swsr_rfirst_gen
+ generic map (
+ AWIDTH => AWIDTH-1,
+ DWIDTH => 8)
+ port map (
+ CLKA => CLK,
+ CLKB => CLK,
+ ENA => EM_MREQ.req,
+ ENB => MEM_ENB,
+ WEA => MEM_WEA(1),
+ WEB => R_REGS.be(1),
+ ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
+ ADDRB => R_REGS.addr,
+ DIA => EM_MREQ.din(15 downto 8),
+ DIB => MEM_DOA(15 downto 8),
+ DOA => MEM_DOA(15 downto 8),
+ DOB => open
+ );
+
+ proc_regs: process (CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if GRESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+
+ end process proc_regs;
+
+ N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
+ N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
+ N_REGS.be <= EM_MREQ.be;
+ N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
+
+ MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
+ MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
+ MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
+
+ EM_SRES.ack_r <= R_REGS.req_r;
+ EM_SRES.ack_w <= R_REGS.req_w;
+ EM_SRES.dout <= MEM_DOA;
+
+end syn;
Index: pdp11_decode.vhd
===================================================================
--- pdp11_decode.vhd (nonexistent)
+++ pdp11_decode.vhd (revision 26)
@@ -0,0 +1,564 @@
+-- $Id: pdp11_decode.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_decode - syn
+-- Description: pdp11: instruction decoder
+--
+-- Dependencies: -
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.0.6 now numeric_std clean
+-- 2010-09-18 300 1.0.5 rename (adlm)box->(oalm)unit
+-- 2008-11-30 174 1.0.4 BUGFIX: add updt_dstadsrc; set for MFP(I/D)
+-- 2008-05-03 143 1.0.3 get fork_srcr,fork_dstr,fork_dsta assign out of if
+-- 2008-04-27 139 1.0.2 BUGFIX: mtp now via do_fork_op; is_dsta logic mods
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_decode is -- instruction decoder
+ port (
+ IREG : in slv16; -- input instruction word
+ STAT : out decode_stat_type -- status output
+ );
+end pdp11_decode;
+
+architecture syn of pdp11_decode is
+
+begin
+
+ proc_idecode: process (IREG)
+
+ alias OPCODE : slv4 is IREG(15 downto 12); -- basic opcode (upper 4 bits)
+ alias OPPRIM : slv3 is IREG(14 downto 12); -- basic opcode without B bit
+ alias OPBYTE : slbit is IREG(15); -- byte flag of basic opcode
+ alias OPEXT1 : slv3 is IREG(11 downto 9); -- extended opcode, part 1
+ alias OPEXT2 : slv3 is IREG(8 downto 6); -- extended opcode, part 2
+ alias OPEXT3 : slv3 is IREG(5 downto 3); -- extended opcode, part 3
+ alias OPEXT4 : slv3 is IREG(2 downto 0); -- extended opcode, part 4
+
+ alias SRCMODF : slv3 is IREG(11 downto 9); -- src register full mode
+ alias DSTMODF : slv3 is IREG(5 downto 3); -- dst register full mode
+
+ alias SRCMOD : slv2 is IREG(11 downto 10); -- src register mode high
+ alias SRCDEF : slbit is IREG(9); -- src register mode defered
+ alias SRCREG : slv3 is IREG(8 downto 6); -- src register number
+ alias DSTMOD : slv2 is IREG(5 downto 4); -- dst register mode high
+ alias DSTDEF : slbit is IREG(3); -- dst register mode defered
+ alias DSTREG : slv3 is IREG(2 downto 0); -- dst register number
+
+ variable nstat : decode_stat_type;
+
+ variable is_srcr : slbit := '0'; -- source is read
+ variable is_dstr : slbit := '0'; -- destination is read
+ variable is_dstm : slbit := '0'; -- destination is modified
+ variable is_dstw : slbit := '0'; -- destination is written
+
+ variable is_srcmode0 : slbit := '0'; -- source is register mode
+ variable is_dstmode0notpc : slbit := '0'; -- dest. is register mode, not PC
+
+ begin
+
+ is_srcr := '0';
+ is_dstr := '0';
+ is_dstm := '0';
+ is_dstw := '0';
+
+ is_srcmode0 := '0';
+ is_dstmode0notpc := '0';
+
+ nstat.is_dstmode0 := '0';
+ nstat.is_srcpc := '0';
+ nstat.is_srcpcmode1 := '0';
+ nstat.is_dstpc := '0';
+ nstat.is_dstw_reg := '0';
+ nstat.is_dstw_pc := '0';
+ nstat.is_rmwop := '0';
+ nstat.is_bytop := '0';
+ nstat.is_res := '1';
+ nstat.op_rtt := '0';
+ nstat.op_mov := '0';
+ nstat.trap_vec := "000";
+ nstat.force_srcsp := '0';
+ nstat.updt_dstadsrc := '0';
+
+ nstat.aunit_srcmod := c_aunit_mod_pass;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_pass;
+ nstat.aunit_cc1op := '0';
+ nstat.aunit_ccmode := IREG(8 downto 6); -- STATIC
+ nstat.lunit_func := (others=>'0');
+ nstat.munit_func := (others=>'0');
+ nstat.res_sel := c_dpath_res_ounit;
+
+ nstat.fork_op := (others=>'0');
+ nstat.fork_srcr := (others=>'0');
+ nstat.fork_dstr := (others=>'0');
+ nstat.fork_dsta := (others=>'0');
+ nstat.fork_opg := (others=>'0');
+ nstat.fork_opa := (others=>'0');
+
+ nstat.do_fork_op := '0';
+ nstat.do_fork_srcr := '0';
+ nstat.do_fork_dstr := '0';
+ nstat.do_fork_dsta := '0';
+ nstat.do_fork_opg := '0';
+
+ nstat.do_pref_dec := '0';
+
+ if SRCMODF = "000" then
+ is_srcmode0 := '1';
+ end if;
+
+ if DSTMODF = "000" then
+ nstat.is_dstmode0 := '1';
+ if DSTREG /= c_gpr_pc then
+ is_dstmode0notpc := '1';
+ end if;
+ end if;
+
+ if SRCREG = c_gpr_pc then
+ nstat.is_srcpc := '1';
+ if SRCMODF = "001" then
+ nstat.is_srcpcmode1 := '1';
+ end if;
+ end if;
+
+ if DSTREG = c_gpr_pc then
+ nstat.is_dstpc := '1';
+ end if;
+
+ if OPPRIM = "000" then
+
+ if OPBYTE='0' and OPEXT1="000" then
+
+ if OPEXT2="000" and OPEXT3="000" then -- HALT,...,RTT
+ nstat.is_res := '0';
+ case OPEXT4 is
+
+ when "000" => -- HALT
+ nstat.fork_op := c_fork_op_halt;
+ nstat.do_fork_op := '1';
+
+ when "001" => -- WAIT
+ nstat.fork_op := c_fork_op_wait;
+ nstat.do_fork_op := '1';
+
+ when "010" => -- RTI
+ nstat.force_srcsp := '1';
+ nstat.fork_op := c_fork_op_rtti;
+ nstat.do_fork_op := '1';
+
+ when "011" => -- BPT (trap to 14)
+ nstat.trap_vec := "011";
+ nstat.fork_op := c_fork_op_trap;
+ nstat.do_fork_op := '1';
+
+ when "100" => -- IOT (trap to 20)
+ nstat.trap_vec := "100";
+ nstat.fork_op := c_fork_op_trap;
+ nstat.do_fork_op := '1';
+
+ when "101" => -- RESET
+ nstat.fork_op := c_fork_op_reset;
+ nstat.do_fork_op := '1';
+
+ when "110" => -- RTT
+ nstat.op_rtt := '1';
+ nstat.force_srcsp := '1';
+ nstat.fork_op := c_fork_op_rtti;
+ nstat.do_fork_op := '1';
+
+ when others =>
+ nstat.is_res := '1';
+
+ end case;
+ end if;
+
+ if OPEXT2 = "001" then -- JMP
+ nstat.is_res := '0';
+ nstat.fork_opa := c_fork_opa_jmp;
+ nstat.do_fork_dsta := '1';
+ end if;
+
+ if OPEXT2 = "010" then
+ if OPEXT3 = "000" then -- RTS
+ nstat.is_res := '0';
+ nstat.force_srcsp := '1';
+ nstat.fork_op := c_fork_op_rts;
+ nstat.do_fork_op := '1';
+ end if;
+ if OPEXT3 = "011" then -- SPL
+ nstat.is_res := '0';
+ nstat.fork_op := c_fork_op_spl;
+ nstat.do_fork_op := '1';
+ end if;
+ end if;
+
+ if OPEXT2 = "010" then
+ if OPEXT3(2) = '1' then -- SEx/CLx
+ nstat.is_res := '0';
+ nstat.fork_op := c_fork_op_mcc;
+ nstat.do_fork_op := '1';
+ --!!!nstat.do_pref_dec := '1'; --??? ensure ireg_we ....
+ end if;
+ end if;
+
+ if OPEXT2 = "011" then -- SWAP
+ nstat.is_res := '0';
+ is_dstm := '1';
+ nstat.fork_opg := c_fork_opg_gen;
+ nstat.do_fork_opg := '1';
+ nstat.do_pref_dec := is_dstmode0notpc;
+ nstat.lunit_func := c_lunit_func_swap;
+ nstat.res_sel := c_dpath_res_lunit;
+ end if;
+
+ end if; -- OPBYTE='0' and OPEXT1="000"
+
+ if OPEXT1(2)='0' and -- BR class instructions
+ ((OPBYTE='0' and OPEXT2(2)='1') or -- BR
+ (OPBYTE='0' and (OPEXT1(0)='1' or OPEXT1(1)='1')) or -- BNE,..,BLE
+ OPBYTE='1') then -- BPL,..,BCS
+ nstat.is_res := '0';
+ nstat.fork_op := c_fork_op_br;
+ nstat.do_fork_op := '1';
+ end if;
+
+ if OPBYTE='0' and OPEXT1="100" then -- JSR
+ nstat.is_res := '0';
+ nstat.fork_opa := c_fork_opa_jsr;
+ nstat.do_fork_dsta := '1';
+ end if;
+
+ if OPBYTE='1' and OPEXT1="100" then -- EMT, TRAP
+ nstat.is_res := '0';
+ if OPEXT2(2) = '0' then -- EMT (trap tp 30)
+ nstat.trap_vec := "110";
+ else -- TRAP (trap to 34)
+ nstat.trap_vec := "111";
+ end if;
+ nstat.fork_op := c_fork_op_trap;
+ nstat.do_fork_op := '1';
+ end if;
+
+ if OPEXT1 = "101" then -- CLR(B),...,TST(B)
+ nstat.is_res := '0';
+ nstat.res_sel := c_dpath_res_aunit;
+ if OPBYTE = '1' then
+ nstat.is_bytop := '1';
+ end if;
+
+ nstat.aunit_cc1op := '1';
+
+ case OPEXT2 is
+ when "000" => -- CLR: 0 + 0 + 0 (0)
+ is_dstw := '1';
+ nstat.aunit_srcmod := c_aunit_mod_zero;
+ nstat.aunit_dstmod := c_aunit_mod_zero;
+ nstat.aunit_cimod := c_aunit_mod_zero;
+ when "001" => -- COM: 0 + ~DST + 0 (~dst)
+ is_dstm := '1';
+ nstat.aunit_srcmod := c_aunit_mod_zero;
+ nstat.aunit_dstmod := c_aunit_mod_inv;
+ nstat.aunit_cimod := c_aunit_mod_zero;
+ when "010" => -- INC: 0 + DST + 1 (dst+1)
+ is_dstm := '1';
+ nstat.aunit_srcmod := c_aunit_mod_zero;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_one;
+ when "011" => -- DEC: ~0 + DST + 0 (dst-1)
+ is_dstm := '1';
+ nstat.aunit_srcmod := c_aunit_mod_one;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_zero;
+ when "100" => -- NEG: 0 + ~DST + 1 (-dst)
+ is_dstm := '1';
+ nstat.aunit_srcmod := c_aunit_mod_zero;
+ nstat.aunit_dstmod := c_aunit_mod_inv;
+ nstat.aunit_cimod := c_aunit_mod_one;
+ when "101" => -- ADC: 0 + DST + CI (dst+ci)
+ is_dstm := '1';
+ nstat.aunit_srcmod := c_aunit_mod_zero;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_pass;
+ when "110" => -- SBC: ~0 + DST + ~CI (dst-ci)
+ is_dstm := '1';
+ nstat.aunit_srcmod := c_aunit_mod_one;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_inv;
+ when "111" => -- TST: 0 + DST + 0 (dst)
+ is_dstr := '1';
+ nstat.aunit_srcmod := c_aunit_mod_zero;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_zero;
+ when others => null;
+ end case;
+
+ nstat.fork_opg := c_fork_opg_gen;
+ nstat.do_fork_opg := '1';
+ nstat.do_pref_dec := is_dstmode0notpc;
+
+ end if;
+
+ if OPEXT1 = "110" then
+ if OPEXT2(2) = '0' then -- ROR(B),...,ASL(B)
+ nstat.is_res := '0';
+ is_dstm := '1';
+ nstat.fork_opg := c_fork_opg_gen;
+ nstat.do_fork_opg := '1';
+ nstat.do_pref_dec := is_dstmode0notpc;
+ if OPBYTE = '1' then
+ nstat.is_bytop := '1';
+ end if;
+ nstat.res_sel := c_dpath_res_lunit;
+ case OPEXT2(1 downto 0) is
+ when "00" => -- ROR
+ nstat.lunit_func := c_lunit_func_ror;
+ when "01" => -- ROL
+ nstat.lunit_func := c_lunit_func_rol;
+ when "10" => -- ASR
+ nstat.lunit_func := c_lunit_func_asr;
+ when "11" => -- ASL
+ nstat.lunit_func := c_lunit_func_asl;
+ when others => null;
+ end case;
+ end if;
+
+ if OPBYTE='0' and OPEXT2="100" then -- MARK
+ nstat.is_res := '0';
+ nstat.fork_op := c_fork_op_mark;
+ nstat.do_fork_op := '1';
+ end if;
+
+ if OPEXT2 = "101" then -- MFP(I/D)
+ nstat.is_res := '0';
+ nstat.force_srcsp := '1';
+ if DSTREG = c_gpr_sp then -- is dst reg == sp ?
+ nstat.updt_dstadsrc := '1'; -- ensure DSRC update in dsta flow
+ end if;
+ nstat.res_sel := c_dpath_res_ounit;
+ if nstat.is_dstmode0 = '1' then
+ nstat.fork_opa := c_fork_opa_mfp_reg;
+ else
+ nstat.fork_opa := c_fork_opa_mfp_mem;
+ end if;
+ nstat.do_fork_dsta := '1';
+ end if;
+
+ if OPEXT2 = "110" then -- MTP(I/D)
+ nstat.is_res := '0';
+ nstat.force_srcsp := '1';
+ nstat.res_sel := c_dpath_res_ounit;
+ nstat.fork_opa := c_fork_opa_mtp;
+ nstat.fork_op := c_fork_op_mtp;
+ nstat.do_fork_op := '1';
+ end if;
+
+ if OPBYTE='0' and OPEXT2="111" then -- SXT
+ nstat.is_res := '0';
+ is_dstw := '1';
+ nstat.fork_opg := c_fork_opg_gen;
+ nstat.do_fork_opg := '1';
+ nstat.do_pref_dec := is_dstmode0notpc;
+ nstat.lunit_func := c_lunit_func_sxt;
+ nstat.res_sel := c_dpath_res_lunit;
+ end if;
+ end if;
+
+ end if; -- OPPRIM="000"
+
+ if OPPRIM/="000" and OPPRIM/="111" then
+ nstat.is_res := '0';
+ case OPPRIM is
+ when "001" => -- MOV
+ is_srcr := '1';
+ is_dstw := '1';
+ nstat.op_mov := '1';
+ nstat.lunit_func := c_lunit_func_mov;
+ nstat.res_sel := c_dpath_res_lunit;
+ nstat.is_bytop := OPBYTE;
+ when "010" => -- CMP
+ is_srcr := '1';
+ is_dstr := '1';
+ nstat.res_sel := c_dpath_res_aunit;
+ nstat.aunit_srcmod := c_aunit_mod_pass;
+ nstat.aunit_dstmod := c_aunit_mod_inv;
+ nstat.aunit_cimod := c_aunit_mod_one;
+ nstat.is_bytop := OPBYTE;
+ when "011" => -- BIT
+ is_srcr := '1';
+ is_dstr := '1';
+ nstat.lunit_func := c_lunit_func_bit;
+ nstat.res_sel := c_dpath_res_lunit;
+ nstat.is_bytop := OPBYTE;
+ when "100" => -- BIC
+ is_srcr := '1';
+ is_dstm := '1';
+ nstat.lunit_func := c_lunit_func_bic;
+ nstat.res_sel := c_dpath_res_lunit;
+ nstat.is_bytop := OPBYTE;
+ when "101" => -- BIS
+ is_srcr := '1';
+ is_dstm := '1';
+ nstat.lunit_func := c_lunit_func_bis;
+ nstat.res_sel := c_dpath_res_lunit;
+ nstat.is_bytop := OPBYTE;
+ when "110" =>
+ is_srcr := '1';
+ is_dstm := '1';
+ nstat.res_sel := c_dpath_res_aunit;
+ if OPBYTE = '0' then -- ADD
+ nstat.aunit_srcmod := c_aunit_mod_pass;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_zero;
+ else -- SUB
+ nstat.aunit_srcmod := c_aunit_mod_inv;
+ nstat.aunit_dstmod := c_aunit_mod_pass;
+ nstat.aunit_cimod := c_aunit_mod_one;
+ end if;
+ when others => null;
+ end case;
+
+ nstat.fork_opg := c_fork_opg_gen;
+ nstat.do_fork_opg := '1';
+ nstat.do_pref_dec := is_srcmode0 and is_dstmode0notpc;
+
+ end if;
+
+ if OPBYTE='0' and OPPRIM="111" then
+ case OPEXT1 is
+ when "000" => -- MUL
+ nstat.is_res := '0';
+ is_dstr := '1';
+ nstat.munit_func := c_munit_func_mul;
+ nstat.res_sel := c_dpath_res_munit;
+ nstat.fork_opg := c_fork_opg_mul;
+ nstat.do_fork_opg := '1';
+ when "001" => -- DIV
+ nstat.is_res := '0';
+ is_dstr := '1';
+ nstat.munit_func := c_munit_func_div;
+ nstat.res_sel := c_dpath_res_munit;
+ nstat.fork_opg := c_fork_opg_div;
+ nstat.do_fork_opg := '1';
+ when "010" => -- ASH
+ nstat.is_res := '0';
+ is_dstr := '1';
+ nstat.munit_func := c_munit_func_ash;
+ nstat.res_sel := c_dpath_res_munit;
+ nstat.fork_opg := c_fork_opg_ash;
+ nstat.do_fork_opg := '1';
+ when "011" => -- ASHC
+ nstat.is_res := '0';
+ is_dstr := '1';
+ nstat.munit_func := c_munit_func_ashc;
+ nstat.res_sel := c_dpath_res_munit;
+ nstat.fork_opg := c_fork_opg_ashc;
+ nstat.do_fork_opg := '1';
+ when "100" => -- XOR
+ nstat.is_res := '0';
+ is_dstm := '1';
+ nstat.lunit_func := c_lunit_func_xor;
+ nstat.res_sel := c_dpath_res_lunit;
+ nstat.fork_opg := c_fork_opg_gen;
+ nstat.do_fork_opg := '1';
+ nstat.do_pref_dec := is_dstmode0notpc;
+ when "111" => -- SOB: SRC + ~0 + 0 (src-1)
+ nstat.is_res := '0';
+ nstat.aunit_srcmod := c_aunit_mod_pass;
+ nstat.aunit_dstmod := c_aunit_mod_one;
+ nstat.aunit_cimod := c_aunit_mod_zero;
+ nstat.res_sel := c_dpath_res_aunit;
+ nstat.fork_op := c_fork_op_sob;
+ nstat.do_fork_op := '1';
+ when others => null;
+ end case;
+
+ end if;
+
+ if OPBYTE='1' and OPPRIM="111" then -- FPU
+ nstat.is_res := '1'; -- ??? FPU not yet handled
+ end if;
+
+ case SRCMOD is
+ when "00" => nstat.fork_srcr := c_fork_srcr_def;
+ when "01" => nstat.fork_srcr := c_fork_srcr_inc;
+ when "10" => nstat.fork_srcr := c_fork_srcr_dec;
+ when "11" => nstat.fork_srcr := c_fork_srcr_ind;
+ when others => null;
+ end case;
+
+ if is_srcr='1' and SRCMODF /="000" then
+ nstat.do_fork_srcr := '1';
+ end if;
+
+ case DSTMOD is
+ when "00" => nstat.fork_dstr := c_fork_dstr_def;
+ when "01" => nstat.fork_dstr := c_fork_dstr_inc;
+ when "10" => nstat.fork_dstr := c_fork_dstr_dec;
+ when "11" => nstat.fork_dstr := c_fork_dstr_ind;
+ when others => null;
+ end case;
+
+ if (is_dstr or is_dstm)='1' and nstat.is_dstmode0='0' then
+ nstat.do_fork_dstr := '1';
+ end if;
+
+ if is_dstw='1' and nstat.is_dstmode0='0' then
+ case DSTMOD is
+ when "00" => nstat.fork_opg := c_fork_opg_wdef;
+ when "01" => nstat.fork_opg := c_fork_opg_winc;
+ when "10" => nstat.fork_opg := c_fork_opg_wdec;
+ when "11" => nstat.fork_opg := c_fork_opg_wind;
+ when others => null;
+ end case;
+ end if;
+
+ if is_dstm='1' and nstat.is_dstmode0='0' then
+ nstat.is_rmwop := '1';
+ end if;
+
+ case DSTMOD is
+ when "00" => nstat.fork_dsta := c_fork_dsta_def;
+ when "01" => nstat.fork_dsta := c_fork_dsta_inc;
+ when "10" => nstat.fork_dsta := c_fork_dsta_dec;
+ when "11" => nstat.fork_dsta := c_fork_dsta_ind;
+ when others => null;
+ end case;
+
+ if (is_dstw or is_dstm)='1' and nstat.is_dstmode0='1' then
+ nstat.is_dstw_reg := '1';
+ if DSTREG = c_gpr_pc then
+ nstat.is_dstw_pc := '1'; --??? hack rename -> is_dstw_pc
+ end if;
+ end if;
+
+ STAT <= nstat;
+
+ end process proc_idecode;
+
+end syn;
Index: pdp11_mem70.vhd
===================================================================
--- pdp11_mem70.vhd (nonexistent)
+++ pdp11_mem70.vhd (revision 26)
@@ -0,0 +1,181 @@
+-- $Id: pdp11_mem70.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2008-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_mem70 - syn
+-- Description: pdp11: 11/70 memory system registers
+--
+-- Dependencies: -
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.1.1 now numeric_std clean
+-- 2010-10-17 333 1.1 use ibus V2 interface
+-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
+-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
+-- 2008-01-27 115 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_mem70 is -- 11/70 memory system registers
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ HM_ENA : in slbit; -- hit/miss enable
+ HM_VAL : in slbit; -- hit/miss value
+ CACHE_FMISS : out slbit; -- cache force miss
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_mem70;
+
+architecture syn of pdp11_mem70 is
+
+ constant ibaddr_loaddr : slv16 := slv(to_unsigned(8#177740#,16));
+ constant ibaddr_hiaddr : slv16 := slv(to_unsigned(8#177742#,16));
+ constant ibaddr_syserr : slv16 := slv(to_unsigned(8#177744#,16));
+ constant ibaddr_cntl : slv16 := slv(to_unsigned(8#177746#,16));
+ constant ibaddr_maint : slv16 := slv(to_unsigned(8#177750#,16));
+ constant ibaddr_hm : slv16 := slv(to_unsigned(8#177752#,16));
+ constant ibaddr_losize : slv16 := slv(to_unsigned(8#177760#,16));
+ constant ibaddr_hisize : slv16 := slv(to_unsigned(8#177762#,16));
+
+ subtype cntl_ibf_frep is integer range 5 downto 4;
+ subtype cntl_ibf_fmiss is integer range 3 downto 2;
+ constant cntl_ibf_disutrap : integer := 1;
+ constant cntl_ibf_distrap : integer := 0;
+
+ type regs_type is record -- state registers
+ ibsel_cr : slbit; -- ibus select cntl
+ ibsel_hm : slbit; -- ibus select hitmiss
+ ibsel_ls : slbit; -- ibus select losize
+ ibsel_nn : slbit; -- ibus select others
+ hm_data : slv6; -- hit/miss: data
+ cr_frep : slv2; -- cntl: force replacement bits
+ cr_fmiss : slv2; -- cntl: force miss bits
+ cr_disutrap: slbit; -- cntl: disable unibus trap
+ cr_distrap: slbit; -- cntl: disable traps
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ '0','0','0','0', -- ibsel_*
+ (others=>'0'), -- hm_data
+ "00","00", -- cr_freq,_fmiss
+ '0','0' -- dis(u)trap
+ );
+
+ signal R_REGS : regs_type := regs_init;
+ signal N_REGS : regs_type := regs_init;
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if CRESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+ end process proc_regs;
+
+ proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+ variable idout : slv16 := (others=>'0');
+ variable ibreq : slbit := '0';
+ variable ibw0 : slbit := '0';
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ idout := (others=>'0');
+ ibreq := IB_MREQ.re or IB_MREQ.we;
+ ibw0 := IB_MREQ.we and IB_MREQ.be0;
+
+ -- ibus address decoder
+ n.ibsel_cr := '0';
+ n.ibsel_hm := '0';
+ n.ibsel_ls := '0';
+ n.ibsel_nn := '0';
+ if IB_MREQ.aval = '1' then
+ if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
+ n.ibsel_cr := '1';
+ end if;
+ if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
+ n.ibsel_hm := '1';
+ end if;
+ if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
+ n.ibsel_ls := '1';
+ end if;
+ if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
+ IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
+ IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
+ IB_MREQ.addr=ibaddr_maint(12 downto 1) or
+ IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
+ n.ibsel_nn := '1';
+ end if;
+ end if;
+
+ -- ibus transactions
+ if r.ibsel_cr = '1' then
+ idout(cntl_ibf_frep) := r.cr_frep;
+ idout(cntl_ibf_fmiss) := r.cr_fmiss;
+ idout(cntl_ibf_disutrap) := r.cr_disutrap;
+ idout(cntl_ibf_distrap) := r.cr_distrap;
+ end if;
+ if r.ibsel_hm = '1' then
+ idout(r.hm_data'range) := r.hm_data;
+ end if;
+ if r.ibsel_ls = '1' then
+ idout := slv(to_unsigned(sys_conf_mem_losize,16));
+ end if;
+
+ if r.ibsel_cr='1' and ibw0='1' then
+ n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
+ n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
+ n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
+ n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
+ end if;
+
+ if HM_ENA = '1' then
+ n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
+ end if;
+
+ N_REGS <= n;
+
+ IB_SRES.dout <= idout;
+ IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
+ r.ibsel_ls or r.ibsel_nn) and ibreq;
+ IB_SRES.busy <= '0';
+
+ end process proc_next;
+
+ CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
+
+end syn;
Index: pdp11_core.vhd
===================================================================
--- pdp11_core.vhd (nonexistent)
+++ pdp11_core.vhd (revision 26)
@@ -0,0 +1,235 @@
+-- $Id: pdp11_core.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_core - syn
+-- Description: pdp11: full processor core
+--
+-- Dependencies: pdp11_vmbox
+-- pdp11_dpath
+-- pdp11_decode
+-- pdp11_sequencer
+-- pdp11_irq
+-- pdp11_sys70
+-- ibus/ib_sres_or_4
+--
+-- Test bench: tb/tb_pdp11core
+-- tb/tb_rlink_tba_pdp11core
+--
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.3.1 now numeric_std clean
+-- 2010-06-13 305 1.3 add CP_ADDR in port; drop R_CPDIN, R_CPOUT; _vmbox
+-- CP_ADDR now from in port; dpath CP_DIN now from in
+-- port; out port CP_DOUT now from _dpath
+-- 2009-05-30 220 1.2.5 final removal of snoopers (were already commented)
+-- 2008-08-22 161 1.2.4 rename pdp11_ibres_ -> ib_sres_
+-- 2008-04-25 138 1.2.3 BRESET: add for _vmbox, use for _irq
+-- 2008-04-19 137 1.2.2 add DM_STAT_(DP|VM|CO) port; added pdp11_sys70
+-- 2008-03-02 121 1.2.1 remove snoopers
+-- 2008-02-17 117 1.2 add em_(mreq|sres) interface for memory
+-- 2008-01-20 112 1.1.3 add BRESET port (intbus reset), rename P->BRESET
+-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
+-- 2008-01-01 109 1.1.1 _vmbox w/ IB_SRES_(CPU|EXT)
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now; remove DMA port
+-- 2007-07-15 66 1.0.3 rename pdp11_top -> pdp11_core
+-- 2007-07-02 63 1.0.2 reordered ports on pdp11_top (by function, not i/o)
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_core is -- full processor core
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CP_CNTL : in cp_cntl_type; -- console control port
+ CP_ADDR : in cp_addr_type; -- console address port
+ CP_DIN : in slv16; -- console data in
+ CP_STAT : out cp_stat_type; -- console status port
+ CP_DOUT : out slv16; -- console data out
+ EI_PRI : in slv3; -- external interrupt priority
+ EI_VECT : in slv9_2; -- external interrupt vector
+ EI_ACKM : out slbit; -- external interrupt acknowledge
+ EM_MREQ : out em_mreq_type; -- external memory: request
+ EM_SRES : in em_sres_type; -- external memory: response
+ BRESET : out slbit; -- ibus reset
+ IB_MREQ_M : out ib_mreq_type; -- inbus master request (master)
+ IB_SRES_M : in ib_sres_type; -- inbus slave response (master)
+ DM_STAT_DP : out dm_stat_dp_type; -- debug and monitor status - dpath
+ DM_STAT_VM : out dm_stat_vm_type; -- debug and monitor status - vmbox
+ DM_STAT_CO : out dm_stat_co_type -- debug and monitor status - core
+ );
+end pdp11_core;
+
+architecture syn of pdp11_core is
+
+ signal GRESET : slbit := '0';
+ signal CRESET : slbit := '0';
+ signal BRESET_L : slbit := '0';
+ signal SEQ_CRESET : slbit := '0';
+ signal SEQ_BRESET : slbit := '0';
+ signal VM_CNTL : vm_cntl_type := vm_cntl_init;
+ signal VM_STAT : vm_stat_type := vm_stat_init;
+ signal MMU_MONI : mmu_moni_type := mmu_moni_init;
+ signal DP_CNTL : dpath_cntl_type := dpath_cntl_init;
+ signal DP_STAT : dpath_stat_type := dpath_stat_init;
+ signal DP_PSW : psw_type := psw_init;
+ signal DP_PC : slv16 := (others=>'0');
+ signal DP_IREG : slv16 := (others=>'0');
+ signal VM_DIN : slv16 := (others=>'0');
+ signal VM_ADDR : slv16 := (others=>'0');
+ signal VM_DOUT : slv16 := (others=>'0');
+ signal ID_STAT : decode_stat_type := decode_stat_init;
+ signal INT_PRI : slv3 := (others=>'0');
+ signal INT_VECT : slv9_2 := (others=>'0');
+ signal CP_STAT_L : cp_stat_type := cp_stat_init;
+ signal INT_ACK : slbit := '0';
+
+ signal IB_SRES_DP : ib_sres_type := ib_sres_init;
+ signal IB_SRES_SEQ : ib_sres_type := ib_sres_init;
+ signal IB_SRES_IRQ : ib_sres_type := ib_sres_init;
+ signal IB_SRES_SYS : ib_sres_type := ib_sres_init;
+
+ signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
+ signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
+
+begin
+
+ GRESET <= RESET;
+ CRESET <= RESET or SEQ_CRESET;
+ BRESET_L <= RESET or SEQ_CRESET or SEQ_BRESET;
+
+ VMBOX : pdp11_vmbox
+ port map (
+ CLK => CLK,
+ GRESET => GRESET,
+ CRESET => CRESET,
+ BRESET => BRESET_L,
+ CP_ADDR => CP_ADDR,
+ VM_CNTL => VM_CNTL,
+ VM_ADDR => VM_ADDR,
+ VM_DIN => VM_DIN,
+ VM_STAT => VM_STAT,
+ VM_DOUT => VM_DOUT,
+ EM_MREQ => EM_MREQ,
+ EM_SRES => EM_SRES,
+ MMU_MONI => MMU_MONI,
+ IB_MREQ_M => IB_MREQ,
+ IB_SRES_CPU => IB_SRES,
+ IB_SRES_EXT => IB_SRES_M,
+ DM_STAT_VM => DM_STAT_VM
+ );
+
+ DPATH : pdp11_dpath
+ port map (
+ CLK => CLK,
+ CRESET => CRESET,
+ CNTL => DP_CNTL,
+ STAT => DP_STAT,
+ CP_DIN => CP_DIN,
+ CP_DOUT => CP_DOUT,
+ PSWOUT => DP_PSW,
+ PCOUT => DP_PC,
+ IREG => DP_IREG,
+ VM_ADDR => VM_ADDR,
+ VM_DOUT => VM_DOUT,
+ VM_DIN => VM_DIN,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_DP,
+ DM_STAT_DP => DM_STAT_DP
+ );
+
+ IDEC : pdp11_decode
+ port map (
+ IREG => DP_IREG,
+ STAT => ID_STAT
+ );
+
+ SEQ : pdp11_sequencer
+ port map (
+ CLK => CLK,
+ GRESET => GRESET,
+ PSW => DP_PSW,
+ PC => DP_PC,
+ IREG => DP_IREG,
+ ID_STAT => ID_STAT,
+ DP_STAT => DP_STAT,
+ CP_CNTL => CP_CNTL,
+ VM_STAT => VM_STAT,
+ INT_PRI => INT_PRI,
+ INT_VECT => INT_VECT,
+ CRESET => SEQ_CRESET,
+ BRESET => SEQ_BRESET,
+ MMU_MONI => MMU_MONI,
+ DP_CNTL => DP_CNTL,
+ VM_CNTL => VM_CNTL,
+ CP_STAT => CP_STAT_L,
+ INT_ACK => INT_ACK,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_SEQ
+ );
+
+ IRQ : pdp11_irq
+ port map (
+ CLK => CLK,
+ BRESET => BRESET_L,
+ INT_ACK => INT_ACK,
+ EI_PRI => EI_PRI,
+ EI_VECT => EI_VECT,
+ EI_ACKM => EI_ACKM,
+ PRI => INT_PRI,
+ VECT => INT_VECT,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_IRQ
+ );
+
+ SYS70 : pdp11_sys70
+ port map (
+ CLK => CLK,
+ CRESET => CRESET,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_SYS
+ );
+
+ IB_SRES_OR : ib_sres_or_4
+ port map (
+ IB_SRES_1 => IB_SRES_DP,
+ IB_SRES_2 => IB_SRES_SEQ,
+ IB_SRES_3 => IB_SRES_IRQ,
+ IB_SRES_4 => IB_SRES_SYS,
+ IB_SRES_OR => IB_SRES
+ );
+
+ IB_MREQ_M <= IB_MREQ;
+
+ CP_STAT <= CP_STAT_L;
+
+ BRESET <= BRESET_L;
+
+ DM_STAT_CO.cpugo <= CP_STAT_L.cpugo;
+ DM_STAT_CO.cpuhalt <= CP_STAT_L.cpuhalt;
+
+end syn;
+
Index: pdp11_mmu_ssr12.vhd
===================================================================
--- pdp11_mmu_ssr12.vhd (nonexistent)
+++ pdp11_mmu_ssr12.vhd (revision 26)
@@ -0,0 +1,192 @@
+-- $Id: pdp11_mmu_ssr12.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_mmu_ssr12 - syn
+-- Description: pdp11: mmu register ssr1 and ssr2
+--
+-- Dependencies: ib_sel
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.2.2 now numeric_std clean
+-- 2010-10-23 335 1.2.1 use ib_sel
+-- 2010-10-17 333 1.2 use ibus V2 interface
+-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
+-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
+-- 2008-03-02 121 1.1.2 remove snoopers
+-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_mmu_ssr12 is -- mmu register ssr1 and ssr2
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ TRACE : in slbit; -- trace enable
+ MONI : in mmu_moni_type; -- MMU monitor port data
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_mmu_ssr12;
+
+architecture syn of pdp11_mmu_ssr12 is
+
+ constant ibaddr_ssr1 : slv16 := slv(to_unsigned(8#177574#,16));
+ constant ibaddr_ssr2 : slv16 := slv(to_unsigned(8#177576#,16));
+
+ subtype ssr1_ibf_rb_delta is integer range 15 downto 11;
+ subtype ssr1_ibf_rb_num is integer range 10 downto 8;
+ subtype ssr1_ibf_ra_delta is integer range 7 downto 3;
+ subtype ssr1_ibf_ra_num is integer range 2 downto 0;
+
+ signal IBSEL_SSR1 : slbit := '0';
+ signal IBSEL_SSR2 : slbit := '0';
+ signal R_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
+ signal R_SSR2 : slv16 := (others=>'0');
+ signal N_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
+ signal N_SSR2 : slv16 := (others=>'0');
+
+begin
+
+ SEL_SSR1 : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_ssr1)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_SSR1
+ );
+ SEL_SSR2 : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_ssr2)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_SSR2
+ );
+
+ proc_ibres : process (IBSEL_SSR1, IBSEL_SSR2, IB_MREQ, R_SSR1, R_SSR2)
+ variable ssr1out : slv16 := (others=>'0');
+ variable ssr2out : slv16 := (others=>'0');
+ begin
+
+ ssr1out := (others=>'0');
+ if IBSEL_SSR1 = '1' then
+ ssr1out(ssr1_ibf_rb_delta) := R_SSR1.rb_delta;
+ ssr1out(ssr1_ibf_rb_num) := R_SSR1.rb_num;
+ ssr1out(ssr1_ibf_ra_delta) := R_SSR1.ra_delta;
+ ssr1out(ssr1_ibf_ra_num) := R_SSR1.ra_num;
+ end if;
+
+ ssr2out := (others=>'0');
+ if IBSEL_SSR2 = '1' then
+ ssr2out := R_SSR2;
+ end if;
+
+ IB_SRES.dout <= ssr1out or ssr2out;
+ IB_SRES.ack <= (IBSEL_SSR1 or IBSEL_SSR2) and
+ (IB_MREQ.re or IB_MREQ.we); -- ack all
+ IB_SRES.busy <= '0';
+
+ end process proc_ibres;
+
+ proc_regs : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ R_SSR1 <= N_SSR1;
+ R_SSR2 <= N_SSR2;
+ end if;
+ end process proc_regs;
+
+ proc_comb : process (CRESET, IBSEL_SSR1, IB_MREQ,
+ R_SSR1, R_SSR2, TRACE, MONI)
+
+ variable nssr1 : mmu_ssr1_type := mmu_ssr1_init;
+ variable nssr2 : slv16 := (others=>'0');
+ variable delta : slv5 := (others=>'0');
+ variable use_rb : slbit := '0';
+
+ begin
+
+ nssr1 := R_SSR1;
+ nssr2 := R_SSR2;
+ delta := "0" & MONI.delta;
+
+ use_rb := '0';
+ if MONI.regnum/=nssr1.ra_num and unsigned(nssr1.ra_delta)/=0 then
+ use_rb := '1';
+ end if;
+
+ if CRESET = '1' then
+ nssr1 := mmu_ssr1_init;
+ nssr2 := (others=>'0');
+
+ elsif IBSEL_SSR1='1' and IB_MREQ.we='1' then
+
+ if IB_MREQ.be1 = '1' then
+ nssr1.rb_delta := IB_MREQ.din(ssr1_ibf_rb_delta);
+ nssr1.rb_num := IB_MREQ.din(ssr1_ibf_rb_num);
+ end if;
+ if IB_MREQ.be0 = '1' then
+ nssr1.ra_delta := IB_MREQ.din(ssr1_ibf_ra_delta);
+ nssr1.ra_num := IB_MREQ.din(ssr1_ibf_ra_num);
+ end if;
+
+ elsif TRACE = '1' then
+
+ if MONI.istart = '1' then
+ nssr1 := mmu_ssr1_init;
+ nssr2 := MONI.pc;
+
+ elsif MONI.regmod = '1' then
+ if use_rb = '0' then
+ nssr1.ra_num := MONI.regnum;
+ if MONI.isdec = '0' then
+ nssr1.ra_delta := slv(signed(nssr1.ra_delta) + signed(delta));
+ else
+ nssr1.ra_delta := slv(signed(nssr1.ra_delta) - signed(delta));
+ end if;
+ else
+ nssr1.rb_num := MONI.regnum;
+ if MONI.isdec = '0' then
+ nssr1.rb_delta := slv(signed(nssr1.rb_delta) + signed(delta));
+ else
+ nssr1.rb_delta := slv(signed(nssr1.rb_delta) - signed(delta));
+ end if;
+ end if;
+ end if;
+
+ end if;
+
+ N_SSR1 <= nssr1;
+ N_SSR2 <= nssr2;
+
+ end process proc_comb;
+
+end syn;
Index: pdp11_vmbox.vhd
===================================================================
--- pdp11_vmbox.vhd (nonexistent)
+++ pdp11_vmbox.vhd (revision 26)
@@ -0,0 +1,683 @@
+-- $Id: pdp11_vmbox.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_vmbox - syn
+-- Description: pdp11: virtual memory
+--
+-- Dependencies: pdp11_mmu
+-- pdp11_ubmap
+-- ibus/ib_sres_or_4
+-- ibus/ib_sres_or_2
+-- ibus/ib_sel
+--
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.6.3 now numeric_std clean
+-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
+-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
+-- 2010-10-17 333 1.6 implement ibus V2 interface
+-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
+-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
+-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
+-- from CP_ADDR; now all ibr handling via vmbox
+-- 2010-06-13 305 1.4 rename CPADDR -> CP_ADDR
+-- 2009-06-01 221 1.3.8 add dip signal in ib_mreq (set in s_ib)
+-- 2009-05-30 220 1.3.7 final removal of snoopers (were already commented)
+-- 2009-05-01 211 1.3.6 BUGFIX: add 177776 stack protect (SCCE)
+-- 2008-08-22 161 1.3.5 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
+-- 2008-04-25 138 1.3.4 add BRESET port, clear stklim with BRESET
+-- 2008-04-20 137 1.3.3 add DM_STAT_VM port
+-- 2008-03-19 127 1.3.2 ignore ack state when waiting on a busy IB in s_ib
+-- 2008-03-02 121 1.3.1 remove snoopers
+-- 2008-02-24 119 1.3 revamp paddr generation; add _ubmap
+-- 2008-02-23 118 1.2.1 use sys_conf_mem_losize
+-- 2008-02-17 117 1.2 use em_(mreq|sres) interface for external memory
+-- 2008-01-26 114 1.1.4 rename 'ubus' to 'ib' (proper name of intbus now)
+-- 2008-01-05 110 1.1.3 update snooper.
+-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- 2008-01-01 109 1.1.2 Use IB_SRES_(CPU|EXT); use r./n. coding style, move
+-- all status into regs_type. add intbus HOLD support.
+-- 2007-12-30 108 1.1.1 use ubf_byte[01]
+-- 2007-12-30 107 1.1 Use IB_MREQ/IB_SRES interface now; remove DMA port
+-- 2007-09-16 83 1.0.2 Use ram_1swsr_wfirst_gen, not ram_2swsr_wfirst_gen
+-- 2nd port was unused, connected ADDR caused slow net
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_vmbox is -- virtual memory
+ port (
+ CLK : in slbit; -- clock
+ GRESET : in slbit; -- global reset
+ CRESET : in slbit; -- console reset
+ BRESET : in slbit; -- ibus reset
+ CP_ADDR : in cp_addr_type; -- console port address
+ VM_CNTL : in vm_cntl_type; -- vm control port
+ VM_ADDR : in slv16; -- vm address
+ VM_DIN : in slv16; -- vm data in
+ VM_STAT : out vm_stat_type; -- vm status port
+ VM_DOUT : out slv16; -- vm data out
+ EM_MREQ : out em_mreq_type; -- external memory: request
+ EM_SRES : in em_sres_type; -- external memory: response
+ MMU_MONI : in mmu_moni_type; -- mmu monitor port
+ IB_MREQ_M : out ib_mreq_type; -- ibus request (master)
+ IB_SRES_CPU : in ib_sres_type; -- ibus response (CPU registers)
+ IB_SRES_EXT : in ib_sres_type; -- ibus response (external devices)
+ DM_STAT_VM : out dm_stat_vm_type -- debug and monitor status
+ );
+end pdp11_vmbox;
+
+architecture syn of pdp11_vmbox is
+
+ constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
+ constant atowidth : natural := 5; -- size of access timeout counter
+
+ type state_type is (
+ s_idle, -- s_idle: wait for vm_cntl request
+ s_mem_w, -- s_mem_w: check mmu, wait for memory
+ s_ib_w, -- s_ib_w: wait for ibus
+ s_ib_wend, -- s_ib_wend: ibus write completion
+ s_ib_rend, -- s_ib_rend: ibus read completion
+ s_idle_mw_ib, -- s_idle_mw_ib: wait macc write (ibus)
+ s_idle_mw_mem, -- s_idle_mw_mem: wait macc write (mem)
+ s_mem_mw_w, -- s_mem_mw_w: wait for memory (macc)
+ s_fail, -- s_fail: vmbox fatal error catcher
+ s_errrsv, -- s_errrsv: red stack violation
+ s_errib -- s_errib: ibus error handler
+ );
+
+ type regs_type is record -- state registers
+ state : state_type; -- state
+ wacc : slbit; -- write access
+ macc : slbit; -- modify access (r-m-w sequence)
+ cacc : slbit; -- console access
+ bytop : slbit; -- byte operation
+ kstack : slbit; -- access through kernel stack
+ ysv : slbit; -- yellow stack violation detected
+ vaok : slbit; -- virtual address valid (from MMU)
+ trap_mmu : slbit; -- mmu trace trap requested
+ mdin : slv16; -- data input (memory order)
+ paddr : slv22; -- physical address register
+ paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
+ atocnt : slv(atowidth-1 downto 0); -- access timeout counter
+ ibre : slbit; -- ibus re signal
+ ibwe : slbit; -- ibus we signal
+ ibbe : slv2; -- ibus be0,be1 signals
+ ibrmw : slbit; -- ibus rmw signal
+ ibcacc : slbit; -- ibus cacc signal
+ ibracc : slbit; -- ibus racc signal
+ ibdout : slv16; -- ibus dout register
+ end record regs_type;
+
+ constant atocnt_init : slv(atowidth-1 downto 0) := (others=>'1');
+ constant regs_init : regs_type := (
+ s_idle, -- state
+ '0','0','0','0', -- wacc,macc,cacc,bytop
+ '0','0','0','0', -- kstack,ysv,vaok,trap_mmu
+ (others=>'0'), -- mdin
+ (others=>'0'), -- paddr
+ (others=>'0'), -- paddr_iopage
+ atocnt_init, -- atocnt
+ '0','0',"00", -- ibre,ibwe,ibbe
+ '0','0','0', -- ibrmw,ibcacc,ibracc
+ (others=>'0') -- ibdout
+ );
+
+ signal R_REGS : regs_type := regs_init;
+ signal N_REGS : regs_type := regs_init;
+
+ signal R_SLIM : slv8 := (others=>'0'); -- stack limit register
+
+ signal MMU_CNTL : mmu_cntl_type := mmu_cntl_init;
+ signal MMU_STAT : mmu_stat_type := mmu_stat_init;
+ signal PADDRH : slv16 := (others=>'0');
+
+ signal IBSEL_SLIM :slbit := '0'; -- select stack limit reg
+ signal IB_SRES_SLIM : ib_sres_type := ib_sres_init;
+ signal IB_SRES_MMU : ib_sres_type := ib_sres_init;
+ signal IB_SRES_UBMAP : ib_sres_type := ib_sres_init;
+
+ signal UBMAP_MREQ : slbit := '0';
+ signal UBMAP_ADDR_PM : slv22_1 := (others=>'0');
+
+ signal IB_MREQ : ib_mreq_type := ib_mreq_init; -- ibus request (local)
+ signal IB_SRES : ib_sres_type := ib_sres_init; -- ibus response (local)
+ signal IB_SRES_INT : ib_sres_type := ib_sres_init; -- ibus response (cpu)
+
+begin
+
+ MMU : pdp11_mmu
+ port map (
+ CLK => CLK,
+ CRESET => CRESET,
+ BRESET => BRESET,
+ CNTL => MMU_CNTL,
+ VADDR => VM_ADDR,
+ MONI => MMU_MONI,
+ STAT => MMU_STAT,
+ PADDRH => PADDRH,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_MMU
+ );
+
+ UBMAP : pdp11_ubmap
+ port map (
+ CLK => CLK,
+ MREQ => UBMAP_MREQ,
+ ADDR_UB => CP_ADDR.addr(17 downto 1),
+ ADDR_PM => UBMAP_ADDR_PM,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_UBMAP
+ );
+
+ SRES_OR_INT : ib_sres_or_4
+ port map (
+ IB_SRES_1 => IB_SRES_CPU,
+ IB_SRES_2 => IB_SRES_SLIM,
+ IB_SRES_3 => IB_SRES_MMU,
+ IB_SRES_4 => IB_SRES_UBMAP,
+ IB_SRES_OR => IB_SRES_INT
+ );
+
+ SRES_OR_ALL : ib_sres_or_2
+ port map (
+ IB_SRES_1 => IB_SRES_INT,
+ IB_SRES_2 => IB_SRES_EXT,
+ IB_SRES_OR => IB_SRES
+ );
+
+ SEL : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_slim)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_SLIM
+ );
+
+ proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
+ variable idout : slv16 := (others=>'0');
+ begin
+ idout := (others=>'0');
+ if IBSEL_SLIM = '1' then
+ idout(ibf_byte1) := R_SLIM;
+ end if;
+ IB_SRES_SLIM.dout <= idout;
+ IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
+ IB_SRES_SLIM.busy <= '0';
+ end process proc_ibres;
+
+ proc_slim: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if BRESET = '1' then
+ R_SLIM <= (others=>'0');
+ elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
+ if IB_MREQ.be1 = '1' then
+ R_SLIM <= IB_MREQ.din(ibf_byte1);
+ end if;
+ end if;
+ end if;
+ end process proc_slim;
+
+ proc_regs: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if GRESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+ end process proc_regs;
+
+ proc_next: process (R_REGS, R_SLIM, CP_ADDR, VM_CNTL, VM_DIN, VM_ADDR,
+ IB_SRES, UBMAP_ADDR_PM,
+ EM_SRES, MMU_STAT, PADDRH)
+
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+
+ variable ivm_stat : vm_stat_type := vm_stat_init;
+ variable ivm_dout : slv16 := (others=>'0');
+ variable iem_mreq : em_mreq_type := em_mreq_init;
+ variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
+
+ variable ipaddr : slv22 := (others=>'0');
+ variable ipaddr_iopage : slv9 := (others=>'0');
+
+ variable iib_aval : slbit := '0';
+
+ variable ato_go : slbit := '0';
+ variable ato_end : slbit := '0';
+
+ variable is_stackyellow : slbit := '1'; -- VM_ADDR in yellow stack zone
+ variable is_stackred : slbit := '1'; -- VM_ADDR in red stack zone
+
+ variable iubmap_mreq : slbit := '0';
+ variable paddr_mmu : slbit := '0';
+ variable paddr_sel : slv2 := "00";
+ constant c_paddr_sel_vmaddr : slv2 := "00";
+ constant c_paddr_sel_rpaddr : slv2 := "01";
+ constant c_paddr_sel_cacc : slv2 := "10";
+ constant c_paddr_sel_ubmap : slv2 := "11";
+
+
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ n.state := s_fail;
+
+ ivm_stat := vm_stat_init;
+ ivm_dout := EM_SRES.dout;
+ immu_cntl := mmu_cntl_init;
+
+ iib_aval := '0';
+
+ iem_mreq := em_mreq_init;
+ iem_mreq.din := VM_DIN;
+
+ if VM_CNTL.bytop = '0' then -- if word access
+ iem_mreq.be := "11"; -- both be's
+ else
+ if VM_ADDR(0) = '0' then -- if low byte
+ iem_mreq.be := "01";
+ else -- if high byte
+ iem_mreq.be := "10";
+ iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
+ end if;
+ end if;
+
+ iubmap_mreq :='0';
+
+ paddr_mmu := '1'; -- ipaddr selector, used in s_idle
+ -- and overwritten in s_idle_mw_mem
+ paddr_sel := "00";
+ if MMU_STAT.ena_mmu='0' or VM_CNTL.cacc='1' then
+ paddr_mmu := '0';
+ paddr_sel := c_paddr_sel_vmaddr;
+ if VM_CNTL.cacc = '1' then
+ if CP_ADDR.ena_ubmap='1' and MMU_STAT.ena_ubmap='1' then
+ paddr_sel := c_paddr_sel_ubmap;
+ else
+ paddr_sel := c_paddr_sel_cacc;
+ end if;
+ end if;
+ end if;
+
+ -- the iopage base is determined based on mmu regs and request type
+ -- r.paddr_iopage is updated during s_idle. This way the iopage base
+ -- address is determined in parallel to paddr and latched at end of s_idle.
+ -- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
+
+ ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
+ if VM_CNTL.cacc = '1' then
+ if CP_ADDR.ena_22bit = '0' then
+ ipaddr_iopage := "000000111"; -- 16 bit cacc
+ end if;
+ else
+ if MMU_STAT.ena_mmu = '0' then
+ ipaddr_iopage := "000000111"; -- 16 bit mode
+ else
+ if MMU_STAT.ena_22bit = '0' then
+ ipaddr_iopage := "000011111"; -- 18 bit mode
+ end if;
+ end if;
+ end if;
+
+ ato_go := '0'; -- default: keep access timeout in reset
+ ato_end := '0';
+ if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
+ ato_end := '1'; -- signal expiration
+ end if;
+
+ is_stackyellow := '0';
+ is_stackred := '0';
+ if unsigned(VM_ADDR(15 downto 8)) <= unsigned(R_SLIM) then
+ is_stackyellow := '1';
+ if unsigned(VM_ADDR(7 downto 5)) /= 7 then -- below 340
+ is_stackred := '1';
+ end if;
+ end if;
+
+ if VM_ADDR(15 downto 1) = "111111111111111" then -- vaddr == 177776
+ is_stackred := '1';
+ end if;
+
+ immu_cntl.wacc := VM_CNTL.wacc;
+ immu_cntl.macc := VM_CNTL.macc;
+ immu_cntl.cacc := VM_CNTL.cacc;
+ immu_cntl.dspace := VM_CNTL.dspace;
+ immu_cntl.mode := VM_CNTL.mode;
+ immu_cntl.trap_done := VM_CNTL.trap_done;
+
+ case r.state is
+ when s_idle => -- s_idle: wait for vm_cntl request --
+ n.state := s_idle;
+ iubmap_mreq := '1'; -- activate ubmap always in s_idle
+
+ if VM_CNTL.req = '1' then
+ n.wacc := VM_CNTL.wacc;
+ n.macc := VM_CNTL.macc;
+ n.cacc := VM_CNTL.cacc;
+ n.bytop := VM_CNTL.bytop;
+ n.kstack := VM_CNTL.kstack;
+ n.ysv := '0';
+ n.vaok := MMU_STAT.vaok;
+ n.trap_mmu := MMU_STAT.trap;
+ n.mdin := iem_mreq.din;
+ -- n.paddr assignment handled separately in 'if state=s_idle' at the
+ -- end.
+
+ immu_cntl.req := '1';
+
+ if VM_CNTL.wacc='1' and VM_CNTL.macc='1' then
+ n.state := s_fail;
+
+ elsif VM_CNTL.kstack='1' and VM_CNTL.intrsv='0' and
+ is_stackred='1' then
+ n.state := s_errrsv;
+
+ else
+ iem_mreq.req := '1';
+ iem_mreq.we := VM_CNTL.wacc;
+ if VM_CNTL.kstack='1'and VM_CNTL.intrsv='0' then
+ n.ysv := is_stackyellow;
+ end if;
+ n.state := s_mem_w;
+ end if;
+ end if;
+
+ when s_mem_w => -- s_mem_w: check mmu, wait for memory
+
+ if r.bytop='0' and r.paddr(0)='1' then -- odd address ?
+ ivm_stat.err := '1';
+ ivm_stat.err_odd := '1';
+ ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
+ iem_mreq.cancel := '1'; -- cancel pending mem request
+ n.state := s_idle;
+
+ elsif r.vaok = '0' then -- MMU abort ?
+ ivm_stat.err := '1';
+ ivm_stat.err_mmu := '1';
+ ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
+ iem_mreq.cancel := '1'; -- cancel pending mem request
+ n.state := s_idle;
+
+ else
+ if r.paddr(21 downto 13) = r.paddr_iopage then
+ -- I/O page decoded
+ iem_mreq.cancel := '1'; -- cancel pending mem request
+ iib_aval := '1'; -- declare ibus addr valid
+ n.ibre := not r.wacc;
+ n.ibwe := r.wacc;
+ n.ibcacc := r.cacc;
+ n.ibracc := r.cacc and CP_ADDR.racc;
+ n.ibbe := "11";
+ if r.cacc = '1' then -- console access ?
+ n.ibbe := CP_ADDR.be;
+ else -- cpu access ?
+ if r.bytop = '1' then
+ if r.paddr(0) = '0' then
+ n.ibbe(1) := '0';
+ else
+ n.ibbe(0) := '0';
+ end if;
+ end if;
+ end if;
+ n.ibrmw := r.macc;
+ n.state := s_ib_w;
+
+ else
+ if unsigned(r.paddr(21 downto 6)) > sys_conf_mem_losize then
+ ivm_stat.err := '1';
+ ivm_stat.err_nxm := '1';
+ ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
+ iem_mreq.cancel := '1'; -- cancel pending mem request
+ n.state := s_idle;
+
+ else
+
+ if EM_SRES.ack_r='1' or EM_SRES.ack_w='1' then
+ ivm_stat.ack := '1';
+ ivm_stat.trap_ysv := r.ysv;
+ ivm_stat.trap_mmu := r.trap_mmu;
+ if r.macc='1' and r.wacc='0' then
+ n.state := s_idle_mw_mem;
+ else
+ n.state := s_idle;
+ end if;
+ else
+ n.state := s_mem_w; -- keep waiting
+ end if;
+
+ end if;
+ end if;
+ end if;
+
+ when s_ib_w => -- s_ib_w: wait for ibus -------------
+ ato_go := '1'; -- activate timeout counter
+
+ iib_aval := '1'; -- declare ibus addr valid
+
+ n.ibre := '0'; -- end cycle, unless busy seen
+ n.ibwe := '0';
+ n.ibrmw := '0';
+ n.ibbe := "00";
+ n.ibcacc := '0';
+ n.ibracc := '0';
+
+ if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
+ if r.wacc = '1' then
+ n.state := s_ib_wend;
+ else
+ if r.macc = '1' then -- if first part of rmw
+ n.ibrmw := r.macc; -- keep rmw
+ n.ibbe := r.ibbe; -- keep be's
+ n.ibcacc := r.ibcacc;
+ n.ibracc := r.ibracc;
+ end if;
+ n.ibdout := IB_SRES.dout;
+ n.state := s_ib_rend;
+ end if;
+ elsif IB_SRES.busy='1' and ato_end='0' then
+ n.ibre := r.ibre; -- continue ibus cycle
+ n.ibwe := r.ibwe;
+ n.ibrmw := r.ibrmw;
+ n.ibbe := r.ibbe;
+ n.ibcacc := r.ibcacc;
+ n.ibracc := r.ibracc;
+ n.state := s_ib_w;
+ else
+ n.state := s_errib;
+ end if;
+
+ when s_ib_wend => -- s_ib_wend: ibus write completion --
+ ivm_stat.ack := '1';
+ n.state := s_idle;
+
+ when s_ib_rend => -- s_ib_rend: ibus read completion ---
+ ivm_stat.ack := '1';
+ ivm_dout := r.ibdout;
+ if r.macc='1' then -- first part of read-mod-write
+ iib_aval := '1'; -- keep ibus addr valid
+ n.state := s_idle_mw_ib;
+ else
+ n.state := s_idle;
+ end if;
+
+ when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
+ n.state := s_idle_mw_ib;
+ iib_aval := '1'; -- keep ibus addr valid
+ if r.ibbe = "10" then
+ iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
+ end if;
+ if VM_CNTL.req = '1' then
+ n.wacc := VM_CNTL.wacc;
+ n.macc := VM_CNTL.macc;
+ n.mdin := iem_mreq.din;
+ if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
+ n.state := s_fail;
+ else
+ n.ibwe := '1'; -- Note: all other ibus drivers
+ -- already set in 1st part
+ n.state := s_ib_w;
+ end if;
+ end if;
+
+ when s_idle_mw_mem => -- s_idle_mw_mem: wait macc write (mem)
+ n.state := s_idle_mw_mem;
+
+ paddr_mmu := '0';
+ paddr_sel := c_paddr_sel_rpaddr;
+
+ if VM_CNTL.bytop = '0' then -- if word access
+ iem_mreq.be := "11"; -- both be's
+ else
+ if r.paddr(0) = '0' then -- if low byte
+ iem_mreq.be := "01";
+ else -- if high byte
+ iem_mreq.be := "10";
+ iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
+ end if;
+ end if;
+
+ if VM_CNTL.req = '1' then
+ n.wacc := VM_CNTL.wacc;
+ n.macc := VM_CNTL.macc;
+ n.bytop := VM_CNTL.bytop;
+ n.mdin := iem_mreq.din;
+
+ if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
+ n.state := s_fail;
+ else
+ iem_mreq.req := '1';
+ iem_mreq.we := '1';
+ n.state := s_mem_mw_w;
+ end if;
+ end if;
+
+ when s_mem_mw_w => -- s_mem_mw_w: wait for memory (macc)
+ if EM_SRES.ack_w = '1' then
+ ivm_stat.ack := '1';
+ n.state := s_idle;
+ else
+ n.state := s_mem_mw_w; -- keep waiting
+ end if;
+
+ when s_fail => -- s_fail: vmbox fatal error catcher
+ ivm_stat.fail := '1';
+ n.state := s_idle;
+
+ when s_errrsv => -- s_errrsv: red stack violation -----
+ ivm_stat.err := '1';
+ ivm_stat.err_rsv := '1';
+ n.state := s_idle;
+
+ when s_errib => -- s_errib: ibus error handler -------
+ ivm_stat.err := '1';
+ ivm_stat.err_iobto := '1';
+ ivm_stat.err_rsv := r.kstack; -- escalate to rsv if kstack
+ n.state := s_idle;
+
+ when others => null;
+ end case;
+
+ if r.bytop='1' and r.paddr(0)='1' then
+ ivm_dout(ibf_byte0) := ivm_dout(ibf_byte1);
+ end if;
+
+ if ato_go = '0' then -- handle access timeout counter
+ n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
+ else
+ n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
+ end if;
+
+ ipaddr := (others=>'0');
+ if paddr_mmu = '1' then
+ ipaddr( 5 downto 0) := VM_ADDR(5 downto 0);
+ ipaddr(21 downto 6) := PADDRH;
+ if MMU_STAT.ena_22bit = '0' then
+ ipaddr(21 downto 18) := (others=>'0');
+ end if;
+ else
+ case paddr_sel is
+ when c_paddr_sel_vmaddr =>
+ ipaddr(15 downto 0) := VM_ADDR(15 downto 0);
+ when c_paddr_sel_rpaddr =>
+ ipaddr := r.paddr;
+ when c_paddr_sel_cacc =>
+ ipaddr := CP_ADDR.addr & '0';
+ if CP_ADDR.ena_22bit = '0' then
+ ipaddr(21 downto 16) := (others=>'0');
+ end if;
+ when c_paddr_sel_ubmap =>
+ ipaddr := UBMAP_ADDR_PM & '0';
+ when others => null;
+ end case;
+ end if;
+
+ if r.state = s_idle then
+ n.paddr := ipaddr;
+ n.paddr_iopage := ipaddr_iopage;
+ end if;
+
+ iem_mreq.addr := ipaddr(21 downto 1);
+
+ N_REGS <= n;
+
+ UBMAP_MREQ <= iubmap_mreq;
+
+ IB_MREQ.aval <= iib_aval;
+ IB_MREQ.re <= r.ibre;
+ IB_MREQ.we <= r.ibwe;
+ IB_MREQ.be0 <= r.ibbe(0);
+ IB_MREQ.be1 <= r.ibbe(1);
+ IB_MREQ.rmw <= r.ibrmw;
+ IB_MREQ.cacc <= r.ibcacc;
+ IB_MREQ.racc <= r.ibracc;
+ IB_MREQ.addr <= r.paddr(12 downto 1);
+ IB_MREQ.din <= r.mdin;
+
+ VM_DOUT <= ivm_dout;
+ VM_STAT <= ivm_stat;
+ MMU_CNTL <= immu_cntl;
+
+ EM_MREQ <= iem_mreq;
+
+ end process proc_next;
+
+ IB_MREQ_M <= IB_MREQ; -- external drive master port
+
+ DM_STAT_VM.ibmreq <= IB_MREQ;
+ DM_STAT_VM.ibsres <= IB_SRES;
+
+end syn;
Index: pdp11_lunit.vhd
===================================================================
--- pdp11_lunit.vhd (nonexistent)
+++ pdp11_lunit.vhd (revision 26)
@@ -0,0 +1,233 @@
+-- $Id: pdp11_lunit.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_lunit - syn
+-- Description: pdp11: logic unit for data (lunit)
+--
+-- Dependencies: -
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.1.1 now numeric_std clean
+-- 2010-09-18 300 1.1 renamed from lbox
+-- 2008-03-30 131 1.0.2 BUGFIX: SXT clears V condition code
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_lunit is -- logic unit for data (lunit)
+ port (
+ DSRC : in slv16; -- 'src' data in
+ DDST : in slv16; -- 'dst' data in
+ CCIN : in slv4; -- condition codes in
+ FUNC : in slv4; -- function
+ BYTOP : in slbit; -- byte operation
+ DOUT : out slv16; -- data output
+ CCOUT : out slv4 -- condition codes out
+ );
+end pdp11_lunit;
+
+architecture syn of pdp11_lunit is
+
+-- --------------------------------------
+
+begin
+
+ process (DSRC, DDST, CCIN, FUNC, BYTOP)
+ variable iout : slv16 := (others=>'0');
+ variable inzstd : slbit := '0';
+ variable ino : slbit := '0';
+ variable izo : slbit := '0';
+ variable ivo : slbit := '0';
+ variable ico : slbit := '0';
+
+ alias DSRC_L : slv8 is DSRC(7 downto 0);
+ alias DSRC_H : slv8 is DSRC(15 downto 8);
+ alias DDST_L : slv8 is DDST(7 downto 0);
+ alias DDST_H : slv8 is DDST(15 downto 8);
+ alias NI : slbit is CCIN(3);
+ alias ZI : slbit is CCIN(2);
+ alias VI : slbit is CCIN(1);
+ alias CI : slbit is CCIN(0);
+ alias iout_l : slv8 is iout(7 downto 0);
+ alias iout_h : slv8 is iout(15 downto 8);
+
+ begin
+
+ iout := (others=>'0');
+ inzstd := '1'; -- use standard logic by default
+ ino := '0';
+ izo := '0';
+ ivo := '0';
+ ico := '0';
+
+--
+-- the decoding of FUNC is done "manually" to get a structure based on
+-- a 8->1 pattern. This matches the opcode structure and seems most
+-- efficient.
+--
+
+ if FUNC(3) = '0' then
+ if BYTOP = '0' then
+
+ case FUNC(2 downto 0) is
+ when "000" => -- ASR
+ iout := DDST(15) & DDST(15 downto 1);
+ ico := DDST(0);
+ ivo := iout(15) xor ico;
+
+ when "001" => -- ASL
+ iout := DDST(14 downto 0) & '0';
+ ico := DDST(15);
+ ivo := iout(15) xor ico;
+
+ when "010" => -- ROR
+ iout := CI & DDST(15 downto 1);
+ ico := DDST(0);
+ ivo := iout(15) xor ico;
+
+ when "011" => -- ROL
+ iout := DDST(14 downto 0) & CI;
+ ico := DDST(15);
+ ivo := iout(15) xor ico;
+
+ when "100" => -- BIS
+ iout := DDST or DSRC;
+ ico := CI;
+
+ when "101" => -- BIC
+ iout := DDST and not DSRC;
+ ico := CI;
+
+ when "110" => -- BIT
+ iout := DDST and DSRC;
+ ico := CI;
+
+ when "111" => -- MOV
+ iout := DSRC;
+ ico := CI;
+ when others => null;
+ end case;
+
+ else
+
+ case FUNC(2 downto 0) is
+ when "000" => -- ASRB
+ iout_l := DDST_L(7) & DDST_L(7 downto 1);
+ ico := DDST_L(0);
+ ivo := iout_l(7) xor ico;
+
+ when "001" => -- ASLB
+ iout_l := DDST(6 downto 0) & '0';
+ ico := DDST(7);
+ ivo := iout_l(7) xor ico;
+
+ when "010" => -- RORB
+ iout_l := CI & DDST_L(7 downto 1);
+ ico := DDST_L(0);
+ ivo := iout_l(7) xor ico;
+
+ when "011" => -- ROLB
+ iout_l := DDST_L(6 downto 0) & CI;
+ ico := DDST_L(7);
+ ivo := iout_l(7) xor ico;
+
+ when "100" => -- BISB
+ iout_l := DDST_L or DSRC_L;
+ ico := CI;
+
+ when "101" => -- BICB
+ iout_l := DDST_L and not DSRC_L;
+ ico := CI;
+
+ when "110" => -- BITB
+ iout_l := DDST_L and DSRC_L;
+ ico := CI;
+
+ when "111" => -- MOVB
+ iout_l := DSRC_L;
+ iout_h := (others=>DSRC_L(7));
+ ico := CI;
+ when others => null;
+ end case;
+ end if;
+
+ else
+ case FUNC(2 downto 0) is
+ when "000" => -- SXT
+ iout := (others=>NI);
+ inzstd := '0';
+ ino := NI;
+ izo := not NI;
+ ivo := '0';
+ ico := CI;
+
+ when "001" => -- SWAP
+ iout := DDST_L & DDST_H;
+ inzstd := '0';
+ ino := iout(7);
+ if unsigned(iout(7 downto 0)) = 0 then
+ izo := '1';
+ else
+ izo := '0';
+ end if;
+
+ when "010" => -- XOR
+ iout := DDST xor DSRC;
+ ico := CI;
+
+ when others => null;
+
+ end case;
+ end if;
+
+ DOUT <= iout;
+
+ if inzstd = '1' then
+ if BYTOP = '1' then
+ ino := iout(7);
+ if unsigned(iout(7 downto 0)) = 0 then
+ izo := '1';
+ else
+ izo := '0';
+ end if;
+ else
+ ino := iout(15);
+ if unsigned(iout) = 0 then
+ izo := '1';
+ else
+ izo := '0';
+ end if;
+ end if;
+ end if;
+
+ CCOUT(3) <= ino;
+ CCOUT(2) <= izo;
+ CCOUT(1) <= ivo;
+ CCOUT(0) <= ico;
+
+ end process;
+
+end syn;
Index: pdp11_ounit.vhd
===================================================================
--- pdp11_ounit.vhd (nonexistent)
+++ pdp11_ounit.vhd (revision 26)
@@ -0,0 +1,114 @@
+-- $Id: pdp11_ounit.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_ounit - syn
+-- Description: pdp11: arithmetic unit for addresses (ounit)
+--
+-- Dependencies: -
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.1.1 now numeric_std clean
+-- 2010-09-18 300 1.1 renamed from abox
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_ounit is -- offset adder for addresses (ounit)
+ port (
+ DSRC : in slv16; -- 'src' data for port A
+ DDST : in slv16; -- 'dst' data for port A
+ DTMP : in slv16; -- 'tmp' data for port A
+ PC : in slv16; -- PC data for port A
+ ASEL : in slv2; -- selector for port A
+ AZERO : in slbit; -- force zero for port A
+ IREG8 : in slv8; -- 'ireg' data for port B
+ VMDOUT : in slv16; -- virt. memory data for port B
+ CONST : in slv9; -- sequencer const data for port B
+ BSEL : in slv2; -- selector for port B
+ OPSUB : in slbit; -- operation: 0 add, 1 sub
+ DOUT : out slv16; -- data output
+ NZOUT : out slv2 -- NZ condition codes out
+ );
+end pdp11_ounit;
+
+architecture syn of pdp11_ounit is
+
+-- --------------------------------------
+
+begin
+
+ process (DSRC, DDST, DTMP, PC, ASEL, AZERO,
+ IREG8, VMDOUT, CONST, BSEL, OPSUB)
+
+ variable ma : slv16 := (others=>'0'); -- effective port a data
+ variable mb : slv16 := (others=>'0'); -- effective port b data
+ variable sum : slv16 := (others=>'0'); -- sum
+ variable nzo : slbit := '0';
+
+ begin
+
+ if AZERO = '0' then
+ case ASEL is
+ when c_ounit_asel_dsrc => ma := DSRC;
+ when c_ounit_asel_ddst => ma := DDST;
+ when c_ounit_asel_dtmp => ma := DTMP;
+ when c_ounit_asel_pc => ma := PC;
+ when others => null;
+ end case;
+ else
+ ma := (others=>'0');
+ end if;
+
+ case BSEL is
+ when c_ounit_bsel_ireg6 => mb := "000000000" & IREG8(5 downto 0) & "0";
+ when c_ounit_bsel_ireg8 => mb := IREG8(7) & IREG8(7) & IREG8(7) &
+ IREG8(7) & IREG8(7) & IREG8(7) &
+ IREG8(7) & IREG8 & "0";
+ when c_ounit_bsel_vmdout => mb := VMDOUT;
+ when c_ounit_bsel_const => mb := "0000000" & CONST;
+ when others => null;
+ end case;
+
+ if OPSUB = '0' then
+ sum := slv(unsigned(ma) + unsigned(mb));
+ else
+ sum := slv(unsigned(ma) - unsigned(mb));
+ end if;
+
+ nzo := '0';
+ if unsigned(sum) = 0 then
+ nzo := '1';
+ else
+ nzo := '0';
+ end if;
+
+ DOUT <= sum;
+ NZOUT(1) <= sum(15);
+ NZOUT(0) <= nzo;
+
+ end process;
+
+end syn;
Index: pdp11_mmu.vhd
===================================================================
--- pdp11_mmu.vhd (nonexistent)
+++ pdp11_mmu.vhd (revision 26)
@@ -0,0 +1,415 @@
+-- $Id: pdp11_mmu.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_mmu - syn
+-- Description: pdp11: mmu - memory management unit
+--
+-- Dependencies: pdp11_mmu_sadr
+-- pdp11_mmu_ssr12
+-- ibus/ib_sres_or_3
+-- ibus/ib_sel
+--
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.4.2 now numeric_std clean
+-- 2010-10-23 335 1.4.1 use ib_sel
+-- 2010-10-17 333 1.4 use ibus V2 interface
+-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
+-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
+-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
+-- BUGFIX: set ssr0 trap_mmu even when traps disabled
+-- 2008-08-22 161 1.3.4 rename pdp11_ibres_ -> ib_sres_, ubf_ -> ibf_
+-- 2008-04-27 139 1.3.3 allow ssr1/2 tracing even with mmu_ena=0
+-- 2008-04-25 138 1.3.2 add BRESET port, clear ssr0/3 with BRESET
+-- 2008-03-02 121 1.3.1 remove snoopers
+-- 2008-02-24 119 1.3 return always mapped address in PADDRH; remove
+-- cpacc handling; PADDR generation now on _vmbox
+-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
+-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- 2008-01-01 109 1.2 use pdp11_mmu_regs (rather than _regset)
+-- 2007-12-31 108 1.1.1 remove SADR memory address mux (-> _mmu_regfile)
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_mmu is -- mmu - memory management unit
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ BRESET : in slbit; -- ibus reset
+ CNTL : in mmu_cntl_type; -- control port
+ VADDR : in slv16; -- virtual address
+ MONI : in mmu_moni_type; -- monitor port
+ STAT : out mmu_stat_type; -- status port
+ PADDRH : out slv16; -- physical address (upper 16 bit)
+ IB_MREQ: in ib_mreq_type; -- ibus request
+ IB_SRES: out ib_sres_type -- ibus response
+ );
+end pdp11_mmu;
+
+architecture syn of pdp11_mmu is
+
+ constant ibaddr_ssr0 : slv16 := slv(to_unsigned(8#177572#,16));
+ constant ibaddr_ssr3 : slv16 := slv(to_unsigned(8#172516#,16));
+
+ constant ssr0_ibf_abo_nonres : integer := 15;
+ constant ssr0_ibf_abo_length : integer := 14;
+ constant ssr0_ibf_abo_rdonly : integer := 13;
+ constant ssr0_ibf_trap_mmu : integer := 12;
+ constant ssr0_ibf_ena_trap : integer := 9;
+ constant ssr0_ibf_inst_compl : integer := 7;
+ subtype ssr0_ibf_seg_mode is integer range 6 downto 5;
+ constant ssr0_ibf_dspace : integer := 4;
+ subtype ssr0_ibf_seg_num is integer range 3 downto 1;
+ constant ssr0_ibf_ena_mmu : integer := 0;
+
+ constant ssr3_ibf_ena_ubmap : integer := 5;
+ constant ssr3_ibf_ena_22bit : integer := 4;
+ constant ssr3_ibf_dspace_km : integer := 2;
+ constant ssr3_ibf_dspace_sm : integer := 1;
+ constant ssr3_ibf_dspace_um : integer := 0;
+
+ signal IBSEL_SSR0 : slbit := '0'; -- ibus select SSR0
+ signal IBSEL_SSR3 : slbit := '0'; -- ibus select SSR3
+
+ signal R_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
+ signal N_SSR0 : mmu_ssr0_type := mmu_ssr0_init;
+
+ signal R_SSR3 : mmu_ssr3_type := mmu_ssr3_init;
+
+ signal ASN : slv4 := "0000"; -- augmented segment number (1+3 bit)
+ signal AIB_WE : slbit := '0'; -- update AIB
+ signal AIB_SETA : slbit := '0'; -- set A bit in access information bits
+ signal AIB_SETW : slbit := '0'; -- set W bit in access information bits
+
+ signal TRACE : slbit := '0'; -- enable tracing in ssr1/2
+ signal DSPACE : slbit := '0'; -- use dspace
+
+ signal IB_SRES_SADR : ib_sres_type := ib_sres_init;
+ signal IB_SRES_SSR12 : ib_sres_type := ib_sres_init;
+ signal IB_SRES_SSR03 : ib_sres_type := ib_sres_init;
+
+ signal SARSDR : sarsdr_type := sarsdr_init;
+
+begin
+
+ SADR : pdp11_mmu_sadr port map (
+ CLK => CLK,
+ MODE => CNTL.mode,
+ ASN => ASN,
+ AIB_WE => AIB_WE,
+ AIB_SETA => AIB_SETA,
+ AIB_SETW => AIB_SETW,
+ SARSDR => SARSDR,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_SADR);
+
+ SSR12 : pdp11_mmu_ssr12 port map (
+ CLK => CLK,
+ CRESET => CRESET,
+ TRACE => TRACE,
+ MONI => MONI,
+ IB_MREQ => IB_MREQ,
+ IB_SRES => IB_SRES_SSR12);
+
+ SRES_OR : ib_sres_or_3
+ port map (
+ IB_SRES_1 => IB_SRES_SADR,
+ IB_SRES_2 => IB_SRES_SSR12,
+ IB_SRES_3 => IB_SRES_SSR03,
+ IB_SRES_OR => IB_SRES);
+
+ SEL_SSR0 : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_ssr0)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_SSR0
+ );
+ SEL_SSR3 : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_ssr3)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_SSR3
+ );
+
+ proc_ibres : process (IBSEL_SSR0, IBSEL_SSR3, IB_MREQ, R_SSR0, R_SSR3)
+
+ variable ssr0out : slv16 := (others=>'0');
+ variable ssr3out : slv16 := (others=>'0');
+
+ begin
+
+ ssr0out := (others=>'0');
+ if IBSEL_SSR0 = '1' then
+ ssr0out(ssr0_ibf_abo_nonres) := R_SSR0.abo_nonres;
+ ssr0out(ssr0_ibf_abo_length) := R_SSR0.abo_length;
+ ssr0out(ssr0_ibf_abo_rdonly) := R_SSR0.abo_rdonly;
+ ssr0out(ssr0_ibf_trap_mmu) := R_SSR0.trap_mmu;
+ ssr0out(ssr0_ibf_ena_trap) := R_SSR0.ena_trap;
+ ssr0out(ssr0_ibf_inst_compl) := R_SSR0.inst_compl;
+ ssr0out(ssr0_ibf_seg_mode) := R_SSR0.seg_mode;
+ ssr0out(ssr0_ibf_dspace) := R_SSR0.dspace;
+ ssr0out(ssr0_ibf_seg_num) := R_SSR0.seg_num;
+ ssr0out(ssr0_ibf_ena_mmu) := R_SSR0.ena_mmu;
+ end if;
+
+ ssr3out := (others=>'0');
+ if IBSEL_SSR3 = '1' then
+ ssr3out(ssr3_ibf_ena_ubmap) := R_SSR3.ena_ubmap;
+ ssr3out(ssr3_ibf_ena_22bit) := R_SSR3.ena_22bit;
+ ssr3out(ssr3_ibf_dspace_km) := R_SSR3.dspace_km;
+ ssr3out(ssr3_ibf_dspace_sm) := R_SSR3.dspace_sm;
+ ssr3out(ssr3_ibf_dspace_um) := R_SSR3.dspace_um;
+ end if;
+
+ IB_SRES_SSR03.dout <= ssr0out or ssr3out;
+ IB_SRES_SSR03.ack <= (IBSEL_SSR0 or IBSEL_SSR3) and
+ (IB_MREQ.re or IB_MREQ.we); -- ack all
+ IB_SRES_SSR03.busy <= '0';
+
+ end process proc_ibres;
+
+ proc_ssr0 : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if BRESET = '1' then
+ R_SSR0 <= mmu_ssr0_init;
+ else
+ R_SSR0 <= N_SSR0;
+ end if;
+ end if;
+ end process proc_ssr0;
+
+ proc_ssr3 : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if BRESET = '1' then
+ R_SSR3 <= mmu_ssr3_init;
+ elsif IBSEL_SSR3='1' and IB_MREQ.we='1' then
+ if IB_MREQ.be0 = '1' then
+ R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap);
+ R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit);
+ R_SSR3.dspace_km <= IB_MREQ.din(ssr3_ibf_dspace_km);
+ R_SSR3.dspace_sm <= IB_MREQ.din(ssr3_ibf_dspace_sm);
+ R_SSR3.dspace_um <= IB_MREQ.din(ssr3_ibf_dspace_um);
+ end if;
+ end if;
+ end if;
+ end process proc_ssr3;
+
+ proc_paddr : process (R_SSR0, R_SSR3, CNTL, SARSDR, VADDR)
+
+ variable ipaddrh : slv16 := (others=>'0');
+ variable dspace_ok : slbit := '0';
+ variable dspace_en : slbit := '0';
+ variable asf : slv3 := (others=>'0'); -- va: active segment field
+ variable bn : slv7 := (others=>'0'); -- va: block number
+ variable iasn : slv4 := (others=>'0');-- augmented segment number
+
+ begin
+
+ asf := VADDR(15 downto 13);
+ bn := VADDR(12 downto 6);
+
+ dspace_en := '0';
+ case CNTL.mode is
+ when "00" => dspace_en := R_SSR3.dspace_km;
+ when "01" => dspace_en := R_SSR3.dspace_sm;
+ when "11" => dspace_en := R_SSR3.dspace_um;
+ when others => null;
+ end case;
+ dspace_ok := CNTL.dspace and dspace_en;
+
+ iasn(3) := dspace_ok;
+ iasn(2 downto 0) := asf;
+
+ ipaddrh := slv(unsigned("000000000"&bn) + unsigned(SARSDR.saf));
+
+ DSPACE <= dspace_ok;
+ ASN <= iasn;
+ PADDRH <= ipaddrh;
+
+ end process proc_paddr;
+
+ proc_nssr0 : process (R_SSR0, R_SSR3, IB_MREQ, IBSEL_SSR0, DSPACE,
+ CNTL, MONI, SARSDR, VADDR)
+
+ variable nssr0 : mmu_ssr0_type := mmu_ssr0_init;
+ variable asf : slv3 := (others=>'0');
+ variable bn : slv7 := (others=>'0');
+ variable abo_nonres : slbit := '0';
+ variable abo_length : slbit := '0';
+ variable abo_rdonly : slbit := '0';
+ variable ssr_freeze : slbit := '0';
+ variable doabort : slbit := '0';
+ variable dotrap : slbit := '0';
+ variable dotrace : slbit := '0';
+
+ begin
+
+ nssr0 := R_SSR0;
+
+ AIB_WE <= '0';
+ AIB_SETA <= '0';
+ AIB_SETW <= '0';
+
+ ssr_freeze := R_SSR0.abo_nonres or R_SSR0.abo_length or R_SSR0.abo_rdonly;
+ dotrace := not(CNTL.cacc or ssr_freeze);
+
+ asf := VADDR(15 downto 13);
+ bn := VADDR(12 downto 6);
+
+ abo_nonres := '0';
+ abo_length := '0';
+ abo_rdonly := '0';
+ doabort := '0';
+ dotrap := '0';
+
+ if SARSDR.ed = '0' then -- ed=0: upward expansion
+ if unsigned(bn) > unsigned(SARSDR.slf) then
+ abo_length := '1';
+ end if;
+ else -- ed=0: downward expansion
+ if unsigned(bn) < unsigned(SARSDR.slf) then
+ abo_length := '1';
+ end if;
+ end if;
+
+ case SARSDR.acf is -- evaluate accecc control field
+
+ when "000" => -- segment non-resident
+ abo_nonres := '1';
+
+ when "001" => -- read-only; trap on read
+ if CNTL.wacc='1' or CNTL.macc='1' then
+ abo_rdonly := '1';
+ end if;
+ dotrap := '1';
+
+ when "010" => -- read-only
+ if CNTL.wacc='1' or CNTL.macc='1' then
+ abo_rdonly := '1';
+ end if;
+
+ when "100" => -- read/write; trap on read&write
+ dotrap := '1';
+
+ when "101" => -- read/write; trap on write
+ dotrap := CNTL.wacc or CNTL.macc;
+
+ when "110" => null; -- read/write;
+
+ when others => -- unused codes: abort access
+ abo_nonres := '1';
+ end case;
+
+ if IBSEL_SSR0='1' and IB_MREQ.we='1' then
+
+ if IB_MREQ.be1 = '1' then
+ nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres);
+ nssr0.abo_length := IB_MREQ.din(ssr0_ibf_abo_length);
+ nssr0.abo_rdonly := IB_MREQ.din(ssr0_ibf_abo_rdonly);
+ nssr0.trap_mmu := IB_MREQ.din(ssr0_ibf_trap_mmu);
+ nssr0.ena_trap := IB_MREQ.din(ssr0_ibf_ena_trap);
+ end if;
+ if IB_MREQ.be0 = '1' then
+ nssr0.ena_mmu := IB_MREQ.din(ssr0_ibf_ena_mmu);
+ end if;
+
+ elsif nssr0.ena_mmu='1' and CNTL.cacc='0' then
+
+ if dotrace = '1' then
+ if MONI.istart = '1' then
+ nssr0.inst_compl := '0';
+ elsif MONI.idone = '1' then
+ nssr0.inst_compl := '0'; -- disable instr.compl logic
+ end if;
+ end if;
+
+ if CNTL.req = '1' then
+ AIB_WE <= '1';
+ if ssr_freeze = '0' then
+ nssr0.abo_nonres := abo_nonres;
+ nssr0.abo_length := abo_length;
+ nssr0.abo_rdonly := abo_rdonly;
+ end if;
+ doabort := abo_nonres or abo_length or abo_rdonly;
+
+ if doabort = '0' then
+ AIB_SETA <= '1';
+ AIB_SETW <= CNTL.wacc or CNTL.macc;
+ end if;
+
+ if ssr_freeze = '0' then
+ nssr0.dspace := DSPACE;
+ nssr0.seg_num := asf;
+ nssr0.seg_mode := CNTL.mode;
+ end if;
+ end if;
+ end if;
+
+ if CNTL.req='1' and R_SSR0.ena_mmu='1' and CNTL.cacc='0' and
+ dotrap='1' then
+ nssr0.trap_mmu := '1';
+ end if;
+
+ nssr0.trace_prev := dotrace;
+
+ if MONI.trace_prev = '0' then
+ TRACE <= dotrace;
+ else
+ TRACE <= R_SSR0.trace_prev;
+ end if;
+
+ N_SSR0 <= nssr0;
+
+ if R_SSR0.ena_mmu='1' and CNTL.cacc='0' then
+ STAT.vaok <= not doabort;
+ else
+ STAT.vaok <= '1';
+ end if;
+
+ if R_SSR0.ena_mmu='1' and CNTL.cacc='0' and doabort='0' and
+ R_SSR0.ena_trap='1' and R_SSR0.trap_mmu='0' and dotrap='1' then
+ STAT.trap <= '1';
+ else
+ STAT.trap <= '0';
+ end if;
+
+ STAT.ena_mmu <= R_SSR0.ena_mmu;
+ STAT.ena_22bit <= R_SSR3.ena_22bit;
+ STAT.ena_ubmap <= R_SSR3.ena_ubmap;
+
+ end process proc_nssr0;
+
+end syn;
Index: pdp11_psr.vhd
===================================================================
--- pdp11_psr.vhd (nonexistent)
+++ pdp11_psr.vhd (revision 26)
@@ -0,0 +1,170 @@
+-- $Id: pdp11_psr.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_psr - syn
+-- Description: pdp11: processor status word register
+--
+-- Dependencies: ib_sel
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.2.2 now numeric_std clean
+-- 2010-10-23 335 1.2.1 use ib_sel
+-- 2010-10-17 333 1.2 use ibus V2 interface
+-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
+-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
+-- 2008-03-02 121 1.1.2 remove snoopers
+-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
+-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_psr is -- processor status word register
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ DIN : in slv16; -- input data
+ CCIN : in slv4; -- cc input
+ CCWE : in slbit; -- enable update cc
+ WE : in slbit; -- write enable (from DIN)
+ FUNC : in slv3; -- write function (from DIN)
+ PSW : out psw_type; -- current psw
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_psr;
+
+architecture syn of pdp11_psr is
+
+ constant ibaddr_psr : slv16 := slv(to_unsigned(8#177776#,16));
+
+ signal IBSEL_PSR : slbit := '0';
+ signal R_PSW : psw_type := psw_init; -- ps register
+
+begin
+
+ SEL : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_psr)
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_PSR
+ );
+
+ proc_ibres: process (IBSEL_PSR, IB_MREQ, R_PSW)
+ variable idout : slv16 := (others=>'0');
+ begin
+ idout := (others=>'0');
+ if IBSEL_PSR = '1' then
+ idout(psw_ibf_cmode) := R_PSW.cmode;
+ idout(psw_ibf_pmode) := R_PSW.pmode;
+ idout(psw_ibf_rset) := R_PSW.rset;
+ idout(psw_ibf_pri) := R_PSW.pri;
+ idout(psw_ibf_tflag) := R_PSW.tflag;
+ idout(psw_ibf_cc) := R_PSW.cc;
+ end if;
+ IB_SRES.dout <= idout;
+ IB_SRES.ack <= IBSEL_PSR and (IB_MREQ.re or IB_MREQ.we); -- ack all
+ IB_SRES.busy <= '0';
+ end process proc_ibres;
+
+ proc_psw : process (CLK)
+ begin
+
+ if rising_edge(CLK) then
+
+ if CRESET = '1' then
+ R_PSW <= psw_init;
+
+ else
+
+ if CCWE = '1' then
+ R_PSW.cc <= CCIN;
+ end if;
+
+ if WE = '1' then
+ case FUNC is
+ when c_psr_func_wspl => -- wspl
+ R_PSW.pri <= DIN(2 downto 0);
+
+ when c_psr_func_wcc => -- wcc
+ if DIN(4) = '1' then -- set cc opcodes
+ R_PSW.cc <= R_PSW.cc or DIN(3 downto 0);
+ else -- clear cc opcodes
+ R_PSW.cc <= R_PSW.cc and not DIN(3 downto 0);
+ end if;
+
+ when c_psr_func_wint => -- wint (interupt handling)
+ R_PSW.cmode <= DIN(psw_ibf_cmode);
+ R_PSW.pmode <= R_PSW.cmode; -- save current mode
+ R_PSW.rset <= DIN(psw_ibf_rset);
+ R_PSW.pri <= DIN(psw_ibf_pri);
+ R_PSW.tflag <= DIN(psw_ibf_tflag);
+ R_PSW.cc <= DIN(psw_ibf_cc);
+
+ when c_psr_func_wrti => -- wrti (rti/rtt in non-kernel mode)
+ R_PSW.cmode <= R_PSW.cmode or DIN(psw_ibf_cmode);
+ R_PSW.pmode <= R_PSW.pmode or DIN(psw_ibf_pmode) or
+ R_PSW.cmode or DIN(psw_ibf_cmode);
+ R_PSW.rset <= R_PSW.rset or DIN(psw_ibf_rset);
+ R_PSW.tflag <= DIN(psw_ibf_tflag);
+ R_PSW.cc <= DIN(psw_ibf_cc);
+
+ when c_psr_func_wall => -- wall (rti/rtt kernel mode)
+ R_PSW.cmode <= DIN(psw_ibf_cmode);
+ R_PSW.pmode <= DIN(psw_ibf_pmode);
+ R_PSW.rset <= DIN(psw_ibf_rset);
+ R_PSW.pri <= DIN(psw_ibf_pri);
+ R_PSW.tflag <= DIN(psw_ibf_tflag);
+ R_PSW.cc <= DIN(psw_ibf_cc);
+
+ when others => null;
+ end case;
+ end if;
+ end if;
+
+ if IBSEL_PSR='1' and IB_MREQ.we='1' then
+ if IB_MREQ.be1 = '1' then
+ R_PSW.cmode <= IB_MREQ.din(psw_ibf_cmode);
+ R_PSW.pmode <= IB_MREQ.din(psw_ibf_pmode);
+ R_PSW.rset <= IB_MREQ.din(psw_ibf_rset);
+ end if;
+ if IB_MREQ.be0 = '1' then
+ R_PSW.pri <= IB_MREQ.din(psw_ibf_pri);
+ R_PSW.cc <= IB_MREQ.din(psw_ibf_cc);
+ end if;
+ end if;
+
+ end if;
+
+ end process proc_psw;
+
+ PSW <= R_PSW;
+
+end syn;
Index: pdp11_ubmap.vhd
===================================================================
--- pdp11_ubmap.vhd (nonexistent)
+++ pdp11_ubmap.vhd (revision 26)
@@ -0,0 +1,174 @@
+-- $Id: pdp11_ubmap.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2008-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_ubmap - syn
+-- Description: pdp11: 11/70 unibus mapper
+--
+-- Dependencies: memlib/ram_1swar_gen
+-- ib_sel
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.1.2 now numeric_std clean
+-- 2010-10-23 335 1.1.1 use ib_sel
+-- 2010-10-17 333 1.1 use ibus V2 interface
+-- 2008-08-22 161 1.0.1 use iblib
+-- 2008-01-27 115 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_ubmap is -- 11/70 unibus mapper
+ port (
+ CLK : in slbit; -- clock
+ MREQ : in slbit; -- request mapping
+ ADDR_UB : in slv18_1; -- UNIBUS address (in)
+ ADDR_PM : out slv22_1; -- physical memory address (out)
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_ubmap;
+
+architecture syn of pdp11_ubmap is
+
+ constant ibaddr_ubmap : slv16 := slv(to_unsigned(8#170200#,16));
+
+ signal IBSEL_UBMAP : slbit := '0';
+
+ signal MAP_2_WE : slbit := '0';
+ signal MAP_1_WE : slbit := '0';
+ signal MAP_0_WE : slbit := '0';
+ signal MAP_ADDR : slv5 := (others => '0'); -- map regs address
+ signal MAP_DOUT : slv22_1 := (others => '0'); -- map regs output
+
+begin
+
+ MAP_2 : ram_1swar_gen -- bit 21:16 of map regs
+ generic map (
+ AWIDTH => 5,
+ DWIDTH => 6)
+ port map (
+ CLK => CLK,
+ WE => MAP_2_WE,
+ ADDR => MAP_ADDR,
+ DI => IB_MREQ.din(5 downto 0),
+ DO => MAP_DOUT(21 downto 16));
+
+ MAP_1 : ram_1swar_gen -- bit 15:08 of map regs
+ generic map (
+ AWIDTH => 5,
+ DWIDTH => 8)
+ port map (
+ CLK => CLK,
+ WE => MAP_1_WE,
+ ADDR => MAP_ADDR,
+ DI => IB_MREQ.din(15 downto 8),
+ DO => MAP_DOUT(15 downto 8));
+
+ MAP_0 : ram_1swar_gen -- bit 07:01 of map regs
+ generic map (
+ AWIDTH => 5,
+ DWIDTH => 7)
+ port map (
+ CLK => CLK,
+ WE => MAP_0_WE,
+ ADDR => MAP_ADDR,
+ DI => IB_MREQ.din(7 downto 1),
+ DO => MAP_DOUT(7 downto 1));
+
+ SEL : ib_sel
+ generic map (
+ IB_ADDR => ibaddr_ubmap,
+ SAWIDTH => 6) -- 2^6 = 64 = 2*32 words
+ port map (
+ CLK => CLK,
+ IB_MREQ => IB_MREQ,
+ SEL => IBSEL_UBMAP
+ );
+
+ proc_comb: process (MREQ, ADDR_UB, IBSEL_UBMAP, IB_MREQ, MAP_DOUT)
+ variable ibusy : slbit := '0';
+ variable idout : slv16 := (others=>'0');
+ variable iwe2 : slbit := '0';
+ variable iwe1 : slbit := '0';
+ variable iwe0 : slbit := '0';
+ variable iaddr : slv5 := (others=>'0');
+ begin
+
+ ibusy := '0';
+ idout := (others=>'0');
+ iwe2 := '0';
+ iwe1 := '0';
+ iwe0 := '0';
+ iaddr := (others=>'0');
+
+ if IBSEL_UBMAP = '1' then
+ if IB_MREQ.addr(1) = '1' then
+ idout(5 downto 0) := MAP_DOUT(21 downto 16);
+ else
+ idout(15 downto 1) := MAP_DOUT(15 downto 1);
+ end if;
+ if MREQ = '1' then -- if map request, stall ib cycle
+ ibusy := '1';
+ end if;
+ end if;
+
+ if IBSEL_UBMAP='1' and IB_MREQ.we='1' then
+ if IB_MREQ.addr(1)='1' then
+ if IB_MREQ.be0 = '1' then
+ iwe2 := '1';
+ end if;
+ else
+ if IB_MREQ.be1 = '1' then
+ iwe1 := '1';
+ end if;
+ if IB_MREQ.be0 = '1' then
+ iwe0 := '1';
+ end if;
+ end if;
+ end if;
+
+ if MREQ = '1' then
+ iaddr := ADDR_UB(17 downto 13);
+ else
+ iaddr := IB_MREQ.addr(6 downto 2);
+ end if;
+
+ MAP_ADDR <= iaddr;
+ MAP_2_WE <= iwe2;
+ MAP_1_WE <= iwe1;
+ MAP_0_WE <= iwe0;
+
+ ADDR_PM <= slv(unsigned(MAP_DOUT) +
+ unsigned("000000000"&ADDR_UB(12 downto 1)));
+
+ IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we);
+ IB_SRES.busy <= ibusy;
+ IB_SRES.dout <= idout;
+
+ end process proc_comb;
+
+end syn;
Index: pdp11_sys70.vhd
===================================================================
--- pdp11_sys70.vhd (nonexistent)
+++ pdp11_sys70.vhd (revision 26)
@@ -0,0 +1,130 @@
+-- $Id: pdp11_sys70.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2008-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_sys70 - syn
+-- Description: pdp11: 11/70 system registers
+--
+-- Dependencies: -
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.1.1 now numeric_std clean
+-- 2010-10-17 333 1.1 use ibus V2 interface
+-- 2008-08-22 161 1.0.1 use iblib
+-- 2008-04-20 137 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.pdp11.all;
+use work.iblib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_sys70 is -- 11/70 memory system registers
+ port (
+ CLK : in slbit; -- clock
+ CRESET : in slbit; -- console reset
+ IB_MREQ : in ib_mreq_type; -- ibus request
+ IB_SRES : out ib_sres_type -- ibus response
+ );
+end pdp11_sys70;
+
+architecture syn of pdp11_sys70 is
+
+ constant ibaddr_mbrk : slv16 := slv(to_unsigned(8#177770#,16));
+ constant ibaddr_sysid : slv16 := slv(to_unsigned(8#177764#,16));
+
+ type regs_type is record -- state registers
+ ibsel_mbrk : slbit; -- ibus select mbrk
+ ibsel_sysid : slbit; -- ibus select sysid
+ mbrk : slv8; -- status of mbrk register
+ end record regs_type;
+
+ constant regs_init : regs_type := (
+ '0','0', -- ibsel_*
+ mbrk=>(others=>'0') -- mbrk
+ );
+
+ signal R_REGS : regs_type := regs_init;
+ signal N_REGS : regs_type := regs_init;
+
+begin
+
+ proc_regs: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if CRESET = '1' then
+ R_REGS <= regs_init;
+ else
+ R_REGS <= N_REGS;
+ end if;
+ end if;
+ end process proc_regs;
+
+ proc_next: process (R_REGS, IB_MREQ)
+ variable r : regs_type := regs_init;
+ variable n : regs_type := regs_init;
+ variable idout : slv16 := (others=>'0');
+ variable ibreq : slbit := '0';
+ variable ibw0 : slbit := '0';
+ begin
+
+ r := R_REGS;
+ n := R_REGS;
+
+ idout := (others=>'0');
+ ibreq := IB_MREQ.re or IB_MREQ.we;
+ ibw0 := IB_MREQ.we and IB_MREQ.be0;
+
+ -- ibus address decoder
+ n.ibsel_mbrk := '0';
+ n.ibsel_sysid := '0';
+ if IB_MREQ.aval = '1' then
+ if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then
+ n.ibsel_mbrk := '1';
+ end if;
+ if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then
+ n.ibsel_sysid := '1';
+ end if;
+ end if;
+
+ -- ibus transactions
+ if r.ibsel_mbrk = '1' then
+ idout(r.mbrk'range) := r.mbrk;
+ end if;
+ if r.ibsel_sysid = '1' then
+ idout := slv(to_unsigned(8#123456#,16));
+ end if;
+
+ if r.ibsel_mbrk='1' and ibw0='1' then
+ n.mbrk := IB_MREQ.din(n.mbrk'range);
+ end if;
+
+ N_REGS <= n;
+
+ IB_SRES.dout <= idout;
+ IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq;
+ IB_SRES.busy <= '0';
+
+ end process proc_next;
+
+end syn;
Index: pdp11_gpr.vhd
===================================================================
--- pdp11_gpr.vhd (nonexistent)
+++ pdp11_gpr.vhd (revision 26)
@@ -0,0 +1,160 @@
+-- $Id: pdp11_gpr.vhd 427 2011-11-19 21:04:11Z mueller $
+--
+-- Copyright 2006-2011 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_gpr - syn
+-- Description: pdp11: general purpose registers
+--
+-- Dependencies: memlib/ram_1swar_1ar_gen
+--
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
+-- Revision History:
+-- Date Rev Version Comment
+-- 2011-11-18 427 1.0.4 now numeric_std clean
+-- 2008-08-22 161 1.0.3 rename ubf_ -> ibf_; use iblib
+-- 2007-12-30 108 1.0.2 use ubf_byte[01]
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.memlib.all;
+use work.iblib.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+entity pdp11_gpr is -- general purpose registers
+ port (
+ CLK : in slbit; -- clock
+ DIN : in slv16; -- input data
+ ASRC : in slv3; -- source register number
+ ADST : in slv3; -- destination register number
+ MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
+ RSET : in slbit; -- register set
+ WE : in slbit; -- write enable
+ BYTOP : in slbit; -- byte operation (write low byte only)
+ PCINC : in slbit; -- increment PC
+ DSRC : out slv16; -- source register data
+ DDST : out slv16; -- destination register data
+ PC : out slv16 -- current PC value
+ );
+end pdp11_gpr;
+
+architecture syn of pdp11_gpr is
+
+-- --------------------------------------
+-- the register map determines the internal register file storage address
+-- of a register. The mapping is
+-- ADDR RNUM SET MODE
+-- 0000 000 0 -- R0 set 0
+-- 0001 001 0 -- R1 set 0
+-- 0010 010 0 -- R2 set 0
+-- 0011 011 0 -- R3 set 0
+-- 0100 100 0 -- R4 set 0
+-- 0101 101 0 -- R5 set 0
+-- 0110 110 - 00 SP kernel mode
+-- 0111 110 - 01 SP supervisor mode
+-- 1000 000 1 -- R0 set 1
+-- 1001 001 1 -- R1 set 1
+-- 1010 010 1 -- R2 set 1
+-- 1011 011 1 -- R3 set 1
+-- 1100 100 1 -- R4 set 1
+-- 1101 101 1 -- R5 set 1
+-- 1110 111 - -- PC
+-- 1111 110 - 11 SP user mode
+
+ procedure do_regmap (
+ signal RNUM : in slv3; -- register number
+ signal MODE : in slv2; -- processor mode (k=>00,s=>01,u=>11)
+ signal RSET : in slbit; -- register set
+ signal ADDR : out slv4 -- internal address in regfile
+ ) is
+ begin
+ if RNUM = c_gpr_pc then
+ ADDR <= "1110";
+ elsif RNUM = c_gpr_sp then
+ ADDR <= MODE(1) & "11" & MODE(0);
+ else
+ ADDR <= RSET & RNUM;
+ end if;
+ end procedure do_regmap;
+
+-- --------------------------------------
+
+ signal MASRC : slv4 := (others=>'0'); -- mapped source register address
+ signal MADST : slv4 := (others=>'0'); -- mapped destination register address
+ signal WE1 : slbit := '0'; -- write enable high byte
+ signal MEMSRC : slv16 := (others=>'0');-- source reg data from memory
+ signal MEMDST : slv16 := (others=>'0');-- destination reg data from memory
+ signal R_PC : slv16 := (others=>'0'); -- PC register
+
+begin
+
+ do_regmap(RNUM => ASRC, MODE => MODE, RSET => RSET, ADDR => MASRC);
+ do_regmap(RNUM => ADST, MODE => MODE, RSET => RSET, ADDR => MADST);
+
+ WE1 <= WE and not BYTOP;
+
+ GPR_LOW : ram_1swar_1ar_gen
+ generic map (
+ AWIDTH => 4,
+ DWIDTH => 8)
+ port map (
+ CLK => CLK,
+ WE => WE,
+ ADDRA => MADST,
+ ADDRB => MASRC,
+ DI => DIN(ibf_byte0),
+ DOA => MEMDST(ibf_byte0),
+ DOB => MEMSRC(ibf_byte0));
+
+ GPR_HIGH : ram_1swar_1ar_gen
+ generic map (
+ AWIDTH => 4,
+ DWIDTH => 8)
+ port map (
+ CLK => CLK,
+ WE => WE1,
+ ADDRA => MADST,
+ ADDRB => MASRC,
+ DI => DIN(ibf_byte1),
+ DOA => MEMDST(ibf_byte1),
+ DOB => MEMSRC(ibf_byte1));
+
+ proc_pc : process (CLK)
+ alias R_PC15 : slv15 is R_PC(15 downto 1); -- upper 15 bit of PC
+ begin
+ if rising_edge(CLK) then
+ if WE='1' and ADST=c_gpr_pc then
+ R_PC(ibf_byte0) <= DIN(ibf_byte0);
+ if BYTOP = '0' then
+ R_PC(ibf_byte1) <= DIN(ibf_byte1);
+ end if;
+ elsif PCINC = '1' then
+ R_PC15 <= slv(unsigned(R_PC15) + 1);
+ end if;
+ end if;
+ end process proc_pc;
+
+ DSRC <= R_PC when ASRC=c_gpr_pc else MEMSRC;
+ DDST <= R_PC when ADST=c_gpr_pc else MEMDST;
+ PC <= R_PC;
+
+end syn;
Index: pdp11.vbom
===================================================================
--- pdp11.vbom (nonexistent)
+++ pdp11.vbom (revision 26)
@@ -0,0 +1,5 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+../vlib/rbus/rblib.vhd
+pdp11.vhd
Index: pdp11_core_rbus.vbom
===================================================================
--- pdp11_core_rbus.vbom (nonexistent)
+++ pdp11_core_rbus.vbom (revision 26)
@@ -0,0 +1,6 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/rbus/rblib.vhd
+pdp11.vbom
+# design
+pdp11_core_rbus.vhd
Index: pdp11_lunit.vbom
===================================================================
--- pdp11_lunit.vbom (nonexistent)
+++ pdp11_lunit.vbom (revision 26)
@@ -0,0 +1,5 @@
+# libs
+../vlib/slvtypes.vhd
+pdp11.vbom
+# design
+pdp11_lunit.vhd
Index: pdp11_aunit.vhd
===================================================================
--- pdp11_aunit.vhd (nonexistent)
+++ pdp11_aunit.vhd (revision 26)
@@ -0,0 +1,244 @@
+-- $Id: pdp11_aunit.vhd 330 2010-09-19 17:43:53Z mueller $
+--
+-- Copyright 2006-2007 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_aunit - syn
+-- Description: pdp11: arithmetic unit for data (aunit)
+--
+-- Dependencies: -
+-- Test bench: tb/tb_pdp11_core (implicit)
+-- Target Devices: generic
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.26
+-- Revision History:
+-- Date Rev Version Comment
+-- 2010-09-18 300 1.1 renamed from abox
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+use work.slvtypes.all;
+use work.pdp11.all;
+
+-- ----------------------------------------------------------------------------
+
+-- arithmetic unit for data, usage:
+-- ADD: SRC + DST + 0 (dst+src)
+-- SUB: ~SRC + DST + 1 (dst-src)
+-- ADC: 0 + DST + CI (dst+ci)
+-- SBC: ~0 + DST + ~CI (dst-ci)
+-- CMP: SRC + ~DST + 1 (src-dst)
+-- COM: 0 + ~DST + 0 (~dst)
+-- NEG: 0 + ~DST + 1 (-dst)
+-- INC: 0 + DST + 1 (dst+1)
+-- DEC: ~0 + DST + 0 (dst-1)
+-- CLR: 0 + 0 + 0 (0)
+-- SOB: SRC + ~0 + 0 (src-1)
+
+entity pdp11_aunit is -- arithmetic unit for data (aunit)
+ port (
+ DSRC : in slv16; -- 'src' data in
+ DDST : in slv16; -- 'dst' data in
+ CI : in slbit; -- carry flag in
+ SRCMOD : in slv2; -- src modifier mode
+ DSTMOD : in slv2; -- dst modifier mode
+ CIMOD : in slv2; -- ci modifier mode
+ CC1OP : in slbit; -- use cc modes (1 op instruction)
+ CCMODE : in slv3; -- cc mode
+ BYTOP : in slbit; -- byte operation
+ DOUT : out slv16; -- data output
+ CCOUT : out slv4 -- condition codes out
+ );
+end pdp11_aunit;
+
+architecture syn of pdp11_aunit is
+
+-- --------------------------------------
+
+begin
+
+ process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
+
+ variable msrc : slv16 := (others=>'0'); -- effective src data
+ variable mdst : slv16 := (others=>'0'); -- effective dst data
+ variable mci : slbit := '0'; -- effective ci
+ variable sum : slv16 := (others=>'0'); -- sum
+ variable co8 : slbit := '0'; -- co 8 bit
+ variable co16 : slbit := '0'; -- co 16 bit
+
+ variable nno : slbit := '0'; -- local no
+ variable nzo : slbit := '0'; -- local zo
+ variable nvo : slbit := '0'; -- local vo
+ variable nco : slbit := '0'; -- local co
+
+ variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
+ variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
+ variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
+
+ alias NO : slbit is CCOUT(3);
+ alias ZO : slbit is CCOUT(2);
+ alias VO : slbit is CCOUT(1);
+ alias CO : slbit is CCOUT(0);
+
+ -- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
+ -- implemented following the recommended pattern for XST ISE V8.1
+
+ procedure do_add8_ci_co (
+ variable a : in slv8; -- input a
+ variable b : in slv8; -- input b
+ variable ci : in slbit; -- carry in
+ variable sum : out slv8; -- sum out
+ variable co : out slbit -- carry out
+ ) is
+
+ variable tmp: slv9;
+
+ begin
+
+ tmp := conv_std_logic_vector((conv_integer(a) + conv_integer(b) +
+ conv_integer(ci)),9);
+ sum := tmp(7 downto 0);
+ co := tmp(8);
+
+ end procedure do_add8_ci_co;
+
+ begin
+
+ case SRCMOD is
+ when c_aunit_mod_pass => msrc := DSRC;
+ when c_aunit_mod_inv => msrc := not DSRC;
+ when c_aunit_mod_zero => msrc := (others=>'0');
+ when c_aunit_mod_one => msrc := (others=>'1');
+ when others => null;
+ end case;
+
+ case DSTMOD is
+ when c_aunit_mod_pass => mdst := DDST;
+ when c_aunit_mod_inv => mdst := not DDST;
+ when c_aunit_mod_zero => mdst := (others=>'0');
+ when c_aunit_mod_one => mdst := (others=>'1');
+ when others => null;
+ end case;
+
+ case CIMOD is
+ when c_aunit_mod_pass => mci := CI;
+ when c_aunit_mod_inv => mci := not CI;
+ when c_aunit_mod_zero => mci := '0';
+ when c_aunit_mod_one => mci := '1';
+ when others => null;
+ end case;
+
+ do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
+ sum(7 downto 0), co8);
+ do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
+ sum(15 downto 8), co16);
+
+ DOUT <= sum;
+
+-- V ('overflow) bit set if
+-- ADD : both operants of same sign but has result opposite sign
+-- SUB : both operants of opposide sign and sign source equals sign result
+-- CMP : both operants of opposide sign and sign dest. equals sign result
+
+ nno := '0';
+ nzo := '0';
+ nvo := '0';
+ nco := '0';
+
+ if BYTOP = '1' then
+ nno := sum(7);
+ if unsigned(sum(7 downto 0)) = 0 then
+ nzo := '1';
+ else
+ nzo := '0';
+ end if;
+ nco := co8;
+
+ src_msb := DSRC(7);
+ dst_msb := DDST(7);
+ sum_msb := sum(7);
+
+ else
+ nno := sum(15);
+ if unsigned(sum) = 0 then
+ nzo := '1';
+ else
+ nzo := '0';
+ end if;
+ nco := co16;
+
+ src_msb := DSRC(15);
+ dst_msb := DDST(15);
+ sum_msb := sum(15);
+ end if;
+
+ -- the logic for 2 operand V+C is ugly. It is reverse engineered from
+ -- the MOD's the operation type.
+
+ if CC1OP = '0' then -- 2 operand cases
+ if unsigned(CIMOD) = unsigned(c_aunit_mod_zero) then -- case ADD
+ nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
+ else
+ if unsigned(SRCMOD) = unsigned(c_aunit_mod_inv) then -- case SUB
+ nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
+ else -- case CMP
+ nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
+ end if;
+ nco := not nco; -- invert C for SUB and CMP
+ end if;
+
+ else -- 1 operand cases
+ case CCMODE is
+ when c_aunit_ccmode_clr|c_aunit_ccmode_tst =>
+ nvo := '0'; -- force v=0 for tst and clr
+ nco := '0'; -- force c=0 for tst and clr
+
+ when c_aunit_ccmode_com =>
+ nvo := '0'; -- force v=0 for com
+ nco := '1'; -- force c=1 for com
+
+ when c_aunit_ccmode_inc =>
+ nvo := sum_msb and not dst_msb;
+ nco := CI; -- C not affected for INC
+
+ when c_aunit_ccmode_dec =>
+ nvo := not sum_msb and dst_msb;
+ nco := CI; -- C not affected for DEC
+
+ when c_aunit_ccmode_neg =>
+ nvo := sum_msb and dst_msb;
+ nco := not nzo;
+
+ when c_aunit_ccmode_adc =>
+ nvo := sum_msb and not dst_msb;
+
+ when c_aunit_ccmode_sbc =>
+ nvo := not sum_msb and dst_msb;
+ nco := not nco;
+
+ when others => null;
+ end case;
+ end if;
+
+ NO <= nno;
+ ZO <= nzo;
+ VO <= nvo;
+ CO <= nco;
+
+ end process;
+
+end syn;
Index: pdp11_dpath.vbom
===================================================================
--- pdp11_dpath.vbom (nonexistent)
+++ pdp11_dpath.vbom (revision 26)
@@ -0,0 +1,13 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+pdp11_gpr.vbom
+pdp11_psr.vbom
+pdp11_ounit.vbom
+pdp11_aunit.vbom
+pdp11_lunit.vbom
+pdp11_munit.vbom
+# design
+pdp11_dpath.vhd
Index: pdp11_aunit.vbom
===================================================================
--- pdp11_aunit.vbom (nonexistent)
+++ pdp11_aunit.vbom (revision 26)
@@ -0,0 +1,5 @@
+# libs
+../vlib/slvtypes.vhd
+pdp11.vbom
+# design
+pdp11_aunit.vhd
Index: pdp11_mmu_ssr12.vbom
===================================================================
--- pdp11_mmu_ssr12.vbom (nonexistent)
+++ pdp11_mmu_ssr12.vbom (revision 26)
@@ -0,0 +1,8 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+../ibus/ib_sel.vbom
+# design
+pdp11_mmu_ssr12.vhd
Index: pdp11_sequencer.vbom
===================================================================
--- pdp11_sequencer.vbom (nonexistent)
+++ pdp11_sequencer.vbom (revision 26)
@@ -0,0 +1,8 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+../ibus/ib_sel.vbom
+# design
+pdp11_sequencer.vhd
Index: pdp11_irq.vbom
===================================================================
--- pdp11_irq.vbom (nonexistent)
+++ pdp11_irq.vbom (revision 26)
@@ -0,0 +1,8 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+../ibus/ib_sel.vbom
+# design
+pdp11_irq.vhd
Index: pdp11_munit.vbom
===================================================================
--- pdp11_munit.vbom (nonexistent)
+++ pdp11_munit.vbom (revision 26)
@@ -0,0 +1,5 @@
+# libs
+../vlib/slvtypes.vhd
+pdp11.vbom
+# design
+pdp11_munit.vhd
Index: pdp11_mmu.vbom
===================================================================
--- pdp11_mmu.vbom (nonexistent)
+++ pdp11_mmu.vbom (revision 26)
@@ -0,0 +1,11 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+pdp11_mmu_sadr.vbom
+pdp11_mmu_ssr12.vbom
+../ibus/ib_sres_or_3.vbom
+../ibus/ib_sel.vbom
+# design
+pdp11_mmu.vhd
Index: pdp11_ounit.vbom
===================================================================
--- pdp11_ounit.vbom (nonexistent)
+++ pdp11_ounit.vbom (revision 26)
@@ -0,0 +1,5 @@
+# libs
+../vlib/slvtypes.vhd
+pdp11.vbom
+# design
+pdp11_ounit.vhd
Index: pdp11_psr.vbom
===================================================================
--- pdp11_psr.vbom (nonexistent)
+++ pdp11_psr.vbom (revision 26)
@@ -0,0 +1,8 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+../ibus/ib_sel.vbom
+# design
+pdp11_psr.vhd
Index: pdp11_ubmap.vbom
===================================================================
--- pdp11_ubmap.vbom (nonexistent)
+++ pdp11_ubmap.vbom (revision 26)
@@ -0,0 +1,11 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/memlib/memlib.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+[ghdl,isim]../vlib/memlib/ram_1swar_gen.vbom
+[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom
+../ibus/ib_sel.vbom
+# design
+pdp11_ubmap.vhd
Index: pdp11_bram.vbom
===================================================================
--- pdp11_bram.vbom (nonexistent)
+++ pdp11_bram.vbom (revision 26)
@@ -0,0 +1,9 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/memlib/memlib.vhd
+pdp11.vbom
+# components
+[ghdl,isim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom
+[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom
+# design
+pdp11_bram.vhd
Index: pdp11_decode.vbom
===================================================================
--- pdp11_decode.vbom (nonexistent)
+++ pdp11_decode.vbom (revision 26)
@@ -0,0 +1,5 @@
+# libs
+../vlib/slvtypes.vhd
+pdp11.vbom
+# design
+pdp11_decode.vhd
Index: pdp11_gpr.vbom
===================================================================
--- pdp11_gpr.vbom (nonexistent)
+++ pdp11_gpr.vbom (revision 26)
@@ -0,0 +1,10 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/memlib/memlib.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+[ghdl,isim]../vlib/memlib/ram_1swar_1ar_gen.vbom
+[xst]../vlib/memlib/ram_1swar_1ar_gen_unisim.vbom
+# design
+pdp11_gpr.vhd
Index: pdp11_tmu_sb.vbom
===================================================================
--- pdp11_tmu_sb.vbom (nonexistent)
+++ pdp11_tmu_sb.vbom (revision 26)
@@ -0,0 +1,9 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/simlib/simlib.vhd
+../vlib/simlib/simbus.vhd
+pdp11.vbom
+# components
+pdp11_tmu.vbom
+# design
+pdp11_tmu_sb.vhd
Index: pdp11_tmu.vbom
===================================================================
--- pdp11_tmu.vbom (nonexistent)
+++ pdp11_tmu.vbom (revision 26)
@@ -0,0 +1,8 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/simlib/simlib.vhd
+../vlib/simlib/simbus.vhd
+pdp11.vbom
+# components
+# design
+pdp11_tmu.vhd
Index: pdp11_sim.vhd
===================================================================
--- pdp11_sim.vhd (nonexistent)
+++ pdp11_sim.vhd (revision 26)
@@ -0,0 +1,40 @@
+-- $Id: pdp11_sim.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2006-2007 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: pdp11_sim
+-- Description: Definitions for simulations
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
+-- 2007-06-14 56 1.0.1 Use slvtypes.all
+-- 2007-05-12 26 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+package pdp11_sim is
+
+ constant clock_period : time := 20 ns;
+ constant clock_offset : time := 200 ns;
+ constant setup_time : time := 5 ns;
+ constant c2out_time : time := 5 ns;
+
+end package pdp11_sim;
+
Index: pdp11_tmu_sb.vhd
===================================================================
--- pdp11_tmu_sb.vhd (nonexistent)
+++ pdp11_tmu_sb.vhd (revision 26)
@@ -0,0 +1,68 @@
+-- $Id: pdp11_tmu_sb.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2009- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: pdp11_tmu - sim
+-- Description: pdp11: trace and monitor unit; simbus wrapper
+--
+-- Dependencies: simbus
+-- Test bench: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2009-05-10 214 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.simlib.all;
+use work.simbus.all;
+use work.pdp11.all;
+
+entity pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
+ generic (
+ ENAPIN : integer := 13); -- SB_CNTL signal to use for enable
+ port (
+ CLK : in slbit; -- clock
+ DM_STAT_DP : in dm_stat_dp_type; -- DM dpath
+ DM_STAT_VM : in dm_stat_vm_type; -- DM vmbox
+ DM_STAT_CO : in dm_stat_co_type; -- DM core
+ DM_STAT_SY : in dm_stat_sy_type -- DM system
+ );
+end pdp11_tmu_sb;
+
+
+architecture sim of pdp11_tmu_sb is
+
+ signal ENA : slbit := '0';
+
+begin
+
+ assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
+ report "assert(ENAPIN in SB_CNTL'range)" severity failure;
+
+ ENA <= to_x01(SB_CNTL(ENAPIN));
+
+ CPMON : pdp11_tmu
+ port map (
+ CLK => CLK,
+ ENA => ENA,
+ DM_STAT_DP => DM_STAT_DP,
+ DM_STAT_VM => DM_STAT_VM,
+ DM_STAT_CO => DM_STAT_CO,
+ DM_STAT_SY => DM_STAT_SY
+ );
+
+end sim;
Index: pdp11_core.vbom
===================================================================
--- pdp11_core.vbom (nonexistent)
+++ pdp11_core.vbom (revision 26)
@@ -0,0 +1,14 @@
+# libs
+../vlib/slvtypes.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+pdp11_vmbox.vbom
+pdp11_dpath.vbom
+pdp11_decode.vbom
+pdp11_sequencer.vbom
+pdp11_irq.vbom
+pdp11_sys70.vbom
+../ibus/ib_sres_or_4.vbom
+# design
+pdp11_core.vhd
Index: sys_conf.vhd
===================================================================
--- sys_conf.vhd (nonexistent)
+++ sys_conf.vhd (revision 26)
@@ -0,0 +1,47 @@
+-- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $
+--
+-- Copyright 2007-2008 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Default definitions for pdp11core (for simple test benches)
+--
+-- Dependencies: -
+-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
+-- Revision History:
+-- Date Rev Version Comment
+-- 2008-02-23 118 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_bram_awidth : integer := 15; -- 32 kB BRAM
+ constant sys_conf_mem_losize : integer := 8#000777#;-- 32 kByte
+-- constant sys_conf_bram_awidth : integer := 14; -- 16 kB BRAM
+-- constant sys_conf_mem_losize : integer := 8#000377#;-- 16 kByte
+
+end package sys_conf;
+
+-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
+-- 2 211 111 111 110 000 000 000
+-- 1 098 765 432 109 876 543 210
+--
+-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
+-- 0 000 000 011 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
+-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
+-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
+-- upper 256 kB excluded for 11/70 UB
Index: pdp11_cache.vbom
===================================================================
--- pdp11_cache.vbom (nonexistent)
+++ pdp11_cache.vbom (revision 26)
@@ -0,0 +1,9 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/memlib/memlib.vhd
+pdp11.vbom
+# components
+[ghdl,isim]../vlib/memlib/ram_2swsr_rfirst_gen.vbom
+[xst]../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vbom
+# design
+pdp11_cache.vhd
Index: pdp11_mmu_sadr.vbom
===================================================================
--- pdp11_mmu_sadr.vbom (nonexistent)
+++ pdp11_mmu_sadr.vbom (revision 26)
@@ -0,0 +1,10 @@
+# libs
+../vlib/slvtypes.vhd
+../vlib/memlib/memlib.vhd
+../ibus/iblib.vhd
+pdp11.vbom
+# components
+[ghdl,isim]../vlib/memlib/ram_1swar_gen.vbom
+[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom
+# design
+pdp11_mmu_sadr.vhd
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 26)
.
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log