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/lib/syncdelay.h

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/lib/usb_common.c

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/lib/isr.h

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/lib/delay.h

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/lib/i2c.c

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/lib/usb_descriptors.h

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/lib/timer.c

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/lib/fx2utils.c

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/lib/i2c.h

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/lib/fx2regs.h

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/lib/timer.h

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/lib/fx2utils.h

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/lib/usb_requests.h

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/lib/.cvsignore

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/lib/Makefile

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/lib/isr.c

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/lib

lib Property changes : Added: svn:ignore ## -0,0 +1,43 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +libfx2.lib Index: README_iso_jtag.txt =================================================================== --- README_iso_jtag.txt (nonexistent) +++ README_iso_jtag.txt (revision 26) @@ -0,0 +1,123 @@ +$Id: README_iso_jtag.txt 525 2013-07-06 12:19:39Z mueller $ + +usb_jtag using Cypress FX2 chip +=============================== + +== General information == + +The code in this directory is for Cypress FX2 (e.g. CY7C68013A) and can be +compiled with the SDCC compiler (I tried version 2.6 as shipped with Ubuntu +6.10). Once I had a version that could be compiled with Keil tools (until early +2007), but switched to SDCC because I usually develop on a Linux host. + +No logic beside the FX2 itself and only a few external components are required +for a basic JTAG adapter. I don't have detailed schematics available; my test +setup consists of a FX2 on a custom board where it's directly connected to a +Cyclone FPGA. + + ____________ + | | + | Cypress | + USB__| EZ-USB FX2 |__JTAG(TDI,TDO,TCK,TMS) + | CY7C68013A | + |____________| + __|__________ + | | + | 24 MHz XTAL | + |_____________| + + +Similar boards are available from fpga4fun.com - the boards named "Saxo-L" and +"Xylo-EM" are pre-wired for use with an adapted version of my code, while +"Saxo" and "Xylo" can be used after soldering 4 extra wires: + + http://www.fpga4fun.com/board_Xylo.html + +There's a discussion thread in the fpga4fun forum about this firmware: + + http://www.fpga4fun.com/forum/viewtopic.php?t=483 + + +== Use with Nexys 1 / 2 Boards == + +Through a contribution by Sune Mai, this code can be used with the Digilent +Nexys / Nexys2 boards. + + http://www.digilentinc.com/nexys/ + http://www.digilentinc.com/nexys2/ + +The hardware-specific code file is hw_nexys.c, just change the line +"HARDWARE=hw_basic" to "HARDWARE=hw_nexys" in the file "Makefile" to use it. + +Also, you may use the "nexys2prog" script by Andy Ross, available from the +same place this code is available from: + + http://ixo-jtag.sourceforge.net/ + + +== Adapting the code to your hardware == + +As is, the code assumes the following pin assignment: + + Port C.0: TDI + Port C.1: TDO + Port C.2: TCK + Port C.3: TMS + +Other assignments are possible. If you have your signals connected to +bit-addressable I/O pins (port A,B,C or D), I suggest you make a copy of +hw_basic.c and adapt the definitions and ProgIO_Init() in it to your needs. +The file hw_saxo_l is even simpler to adapt if you want only JTAG and no AS/PS +mode. If your signals are not on bit-addressable I/Os (that is, you're using +port E), you could base your adaptation on the slower hw_xpcu_i.c. You may +specify the name of your adapted hardware-specific file when "make"ing, e.g.: + + make HARDWARE=hw_saxo_l + + +The USB identification data (vendor/product ID, strings, ...) can be modified +in dscr.a51. The firmware emulates the 128 byte EEPROM that usually holds +configuration data for the FT245 and which can be read from the host; its +content (including checksum) is computed from the data in dscr.a51 as well. + +The WAKEUP pin should be high for the re-numeration to work reliably (thanks +Jean/fpga4fun!). + + +== Using it with Xilinx JTAG cable == + +There is code to support running in the "Xilinx Platform Cable USB". If you +select HARDWARE=hw_xpcu_i or hw_xpcu_x at the top of the Makefile, a firmware +for the XPCU will be built. I've tested this only with unmodified CPLD version +18 (0x12) on a Spartan-3E starter kit, as it was programmed by my WebPack 8.2i. +The code needs optimization; yet it is merely a proof of concept. +Compile for the XPCU with e.g. "make HARDWARE=hw_xpcu_x". + + hw_xpcu_i: Access "internal" chain (the XPCU CPLD, IC3, itself) + hw_xpcu_x: Access "external" chain (the Spartan 3E, PROM, etc.) + + +== History == + +Changes since previous release 2008-07-05: + - Imported to SourceForge, please see the project page: + http://ixo-jtag.sourceforge.net/ + +Changes since previous release on 2007-02-15: + - Jean Nicolle contributed hw_saxo_l.c for the FX2 boards from fpga4fun.com + - fx2/Makefile fixed to build correct libfx2.lib even under Windows. + +Changes since previous release on 2007-01-28: + - Initial suppport for running on Xilinx XPCU. + - New FX2 code, based on USRP2 from the GNU Radio Project; + - Firmware can now be compiled using SDCC 2.6. No more Keil support. + - EEPROM content is automatically computed from dscr.a51, including checksum. + +Changes since initial release on 2006-04-23: + - added this readme.txt + - reorganized my project folder: diff now created from Subversion repository + - stripped *.dist extension from eeprom.c and dscr.a51 + - added unique proper product and vendor ID (thanks to Antti Lukats!) + - fixed checksum in eeprom.c + - added comments about AS/PS mode pins in usbjtag.c + Index: main.c =================================================================== --- main.c (nonexistent) +++ main.c (revision 26) @@ -0,0 +1,376 @@ +/* $Id: main.c 472 2013-01-06 14:39:10Z mueller $ */ +/* + * Copyright 2011-2013 by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * + * - original copyright and licence disclaimer -------------------------------- + * - Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter + * - Copyright (C) 2005..2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + *----------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + *----------------------------------------------------------------------------- + * + * EZ-USB FX2 controller main program + * + * Revision History: + * + * Date Rev Version Comment + * 2013-01-05 472 1.1.1 BUGFIX: explicitly set FIFOPINPOLAR=0 + * 2011-07-23 397 1.1 factor out usb_fifo_init() code + * 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204) + * + *----------------------------------------------------------------------------- + */ + +#include "isr.h" +#include "timer.h" +#include "delay.h" +#include "fx2regs.h" +#include "fx2utils.h" +#include "usb_common.h" +#include "usb_descriptors.h" +#include "usb_requests.h" + +#include "syncdelay.h" + +#include "eeprom.h" +#include "hardware.h" + +//----------------------------------------------------------------------------- +// Define USE_MOD256_OUTBUFFER: +// Saves about 256 bytes in code size, improves speed a little. +// A further optimization could be not to use an extra output buffer at +// all, but to write directly into EP1INBUF. Not implemented yet. When +// downloading large amounts of data _to_ the target, there is no output +// and thus the output buffer isn't used at all and doesn't slow down things. + +#define USE_MOD256_OUTBUFFER 1 + +//----------------------------------------------------------------------------- +// Global data + +typedef bit BOOL; +#define FALSE 0 +#define TRUE 1 +static BOOL Running; +static BOOL WriteOnly; + +static BYTE ClockBytes; +static WORD Pending; + +#ifdef USE_MOD256_OUTBUFFER + static BYTE FirstDataInOutBuffer; + static BYTE FirstFreeInOutBuffer; +#else + static WORD FirstDataInOutBuffer; + static WORD FirstFreeInOutBuffer; +#endif + +#ifdef USE_MOD256_OUTBUFFER + /* Size of output buffer must be exactly 256 */ + #define OUTBUFFER_LEN 0x100 + /* Output buffer must begin at some address with lower 8 bits all zero */ + xdata at 0xE000 BYTE OutBuffer[OUTBUFFER_LEN]; +#else + #define OUTBUFFER_LEN 0x200 + static xdata BYTE OutBuffer[OUTBUFFER_LEN]; +#endif + +//----------------------------------------------------------------------------- + +void usb_jtag_init(void) // Called once at startup +{ + WORD tmp; + + Running = FALSE; + ClockBytes = 0; + Pending = 0; + WriteOnly = TRUE; + FirstDataInOutBuffer = 0; + FirstFreeInOutBuffer = 0; + + ProgIO_Init(); + + ProgIO_Enable(); + + // Make Timer2 reload at 100 Hz to trigger Keepalive packets + + tmp = 65536 - ( 48000000 / 12 / 100 ); + RCAP2H = tmp >> 8; + RCAP2L = tmp & 0xFF; + CKCON = 0; // Default Clock + T2CON = 0x04; // Auto-reload mode using internal clock, no baud clock. + + // Enable Autopointer + + EXTACC = 1; // Enable + APTR1FZ = 1; // Don't freeze + APTR2FZ = 1; // Don't freeze +} + +void OutputByte(BYTE d) +{ +#ifdef USE_MOD256_OUTBUFFER + OutBuffer[FirstFreeInOutBuffer] = d; + FirstFreeInOutBuffer = ( FirstFreeInOutBuffer + 1 ) & 0xFF; +#else + OutBuffer[FirstFreeInOutBuffer++] = d; + if(FirstFreeInOutBuffer >= OUTBUFFER_LEN) FirstFreeInOutBuffer = 0; +#endif + Pending++; +} + +//----------------------------------------------------------------------------- +// usb_jtag_activity does most of the work. It now happens to behave just like +// the combination of FT245BM and Altera-programmed EPM7064 CPLD in Altera's +// USB-Blaster. The CPLD knows two major modes: Bit banging mode and Byte +// shift mode. It starts in Bit banging mode. While bytes are received +// from the host on EP2OUT, each byte B of them is processed as follows: +// +// Please note: nCE, nCS, LED pins and DATAOUT actually aren't supported here. +// Support for these would be required for AS/PS mode and isn't too complicated, +// but I haven't had the time yet. +// +// Bit banging mode: +// +// 1. Remember bit 6 (0x40) in B as the "Read bit". +// +// 2. If bit 7 (0x40) is set, switch to Byte shift mode for the coming +// X bytes ( X := B & 0x3F ), and don't do anything else now. +// +// 3. Otherwise, set the JTAG signals as follows: +// TCK/DCLK high if bit 0 was set (0x01), otherwise low +// TMS/nCONFIG high if bit 1 was set (0x02), otherwise low +// nCE high if bit 2 was set (0x04), otherwise low +// nCS high if bit 3 was set (0x08), otherwise low +// TDI/ASDI/DATA0 high if bit 4 was set (0x10), otherwise low +// Output Enable/LED active if bit 5 was set (0x20), otherwise low +// +// 4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and +// DATAOUT(nSTATUS) pins and put it as a byte ((DATAOUT<<1)|TDO) in the +// output FIFO _to_ the host (the code here reads TDO only and assumes +// DATAOUT=1) +// +// Byte shift mode: +// +// 1. Load shift register with byte from host +// +// 2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51) +// 2a) if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT +// 2b) Rotate shift register through carry bit +// 2c) TDI := Carry bit +// 2d) Raise TCK, then lower TCK. +// +// 3. If "Read bit" was set when switching into byte shift mode, +// record the shift register content and put it into the FIFO +// _to_ the host. +// +// Some more (minor) things to consider to emulate the FT245BM: +// +// a) The FT245BM seems to transmit just packets of no more than 64 bytes +// (which perfectly matches the USB spec). Each packet starts with +// two non-data bytes (I use 0x31,0x60 here). A USB sniffer on Windows +// might show a number of packets to you as if it was a large transfer +// because of the way that Windows understands it: it _is_ a large +// transfer until terminated with an USB packet smaller than 64 byte. +// +// b) The Windows driver expects to get some data packets (with at least +// the two leading bytes 0x31,0x60) immediately after "resetting" the +// FT chip and then in regular intervals. Otherwise a blue screen may +// appear... In the code below, I make sure that every 10ms there is +// some packet. +// +// c) Vendor specific commands to configure the FT245 are mostly ignored +// in my code. Only those for reading the EEPROM are processed. See +// DR_GetStatus and DR_VendorCmd below for my implementation. +// +// All other TD_ and DR_ functions remain as provided with CY3681. +// +//----------------------------------------------------------------------------- + +void usb_jtag_activity(void) // Called repeatedly while the device is idle +{ + if(!Running) return; + + ProgIO_Poll(); + + if(!(EP1INCS & bmEPBUSY)) { + if(Pending > 0) { + BYTE o, n; + + AUTOPTRH2 = MSB( EP1INBUF ); + AUTOPTRL2 = LSB( EP1INBUF ); + + XAUTODAT2 = 0x31; + XAUTODAT2 = 0x60; + + if(Pending > 0x3E) { n = 0x3E; Pending -= n; } + else { n = Pending; Pending = 0; }; + + o = n; + +#ifdef USE_MOD256_OUTBUFFER + APTR1H = MSB( OutBuffer ); + APTR1L = FirstDataInOutBuffer; + while(n--) { + XAUTODAT2 = XAUTODAT1; + APTR1H = MSB( OutBuffer ); // Stay within 256-Byte-Buffer + } + FirstDataInOutBuffer = APTR1L; +#else + APTR1H = MSB( &(OutBuffer[FirstDataInOutBuffer]) ); + APTR1L = LSB( &(OutBuffer[FirstDataInOutBuffer]) ); + while(n--) { + XAUTODAT2 = XAUTODAT1; + + if(++FirstDataInOutBuffer >= OUTBUFFER_LEN) { + FirstDataInOutBuffer = 0; + APTR1H = MSB( OutBuffer ); + APTR1L = LSB( OutBuffer ); + } + } +#endif + SYNCDELAY; + EP1INBC = 2 + o; + TF2 = 1; // Make sure there will be a short transfer soon + } else if(TF2) { + EP1INBUF[0] = 0x31; + EP1INBUF[1] = 0x60; + SYNCDELAY; + EP1INBC = 2; + TF2 = 0; + } + } + + if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F)) { + //BYTE i, n = EP2BCL; // bugfix by Sune Mai (Oct 2008, + // https://sourceforge.net/projects/urjtag/forums/forum/682993/topic/2312452) + WORD i, n = EP2BCL|EP2BCH<<8; + + APTR1H = MSB( EP2FIFOBUF ); + APTR1L = LSB( EP2FIFOBUF ); + + for(i=0;i 0) { + //BYTE m; // bugfix by Sune Mai, see above + WORD m; + + m = n-i; + if(ClockBytes < m) m = ClockBytes; + ClockBytes -= m; + i += m; + + /* Shift out 8 bits from d */ + + if(WriteOnly) { /* Shift out 8 bits from d */ + while(m--) ProgIO_ShiftOut(XAUTODAT1); + } else { /* Shift in 8 bits at the other end */ + while(m--) OutputByte(ProgIO_ShiftInOut(XAUTODAT1)); + } + } else { + BYTE d = XAUTODAT1; + WriteOnly = (d & bmBIT6) ? FALSE : TRUE; + + if(d & bmBIT7) { + /* Prepare byte transfer, do nothing else yet */ + + ClockBytes = d & 0x3F; + } else { + if(WriteOnly) + ProgIO_Set_State(d); + else + OutputByte(ProgIO_Set_Get_State(d)); + } + i++; + } + } + + SYNCDELAY; + EP2BCL = 0x80; // Re-arm endpoint 2 + }; +} + +//----------------------------------------------------------------------------- +// Handler for Vendor Requests ( +//----------------------------------------------------------------------------- + +unsigned char app_vendor_cmd(void) +{ + // OUT requests. Pretend we handle them all... + + if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT) { + if(bRequest == RQ_GET_STATUS) { + Running = 1; + } + return 1; + } + + // IN requests. + + if(bRequest == 0x90) { + BYTE addr = (wIndexL<<1) & 0x7F; + EP0BUF[0] = eeprom[addr]; + EP0BUF[1] = eeprom[addr+1]; + } else { + // dummy data + EP0BUF[0] = 0x36; + EP0BUF[1] = 0x83; + } + + EP0BCH = 0; + EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer + + return 1; +} + +//----------------------------------------------------------------------------- + +static void main_loop(void) +{ + while(1) { + if(usb_setup_packet_avail()) usb_handle_setup_packet(); + usb_jtag_activity(); + } +} + +//----------------------------------------------------------------------------- + +extern void usb_fifo_init(void); + +void main(void) +{ + EA = 0; // disable all interrupts + + // Digilent nexys3 and atlys boards change FIFOPINPOLAR such that + // EE and FF are active high. In nexys2 boards they are active low + // All config regs should be set (even when power on defaults are + // use, but this one especially.... + FIFOPINPOLAR = 0; + + usb_jtag_init(); + usb_fifo_init(); + eeprom_init(); + setup_autovectors (); + usb_install_handlers (); + + + EA = 1; // enable interrupts + + fx2_renumerate(); // simulates disconnect / reconnect + + main_loop(); +} + + + + Index: usb_fifo_init.c =================================================================== --- usb_fifo_init.c (nonexistent) +++ usb_fifo_init.c (revision 26) @@ -0,0 +1,210 @@ +/* $Id: usb_fifo_init.c 450 2012-01-05 23:21:41Z mueller $ */ +/* + * Copyright 2011-2012 by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * The data fifo treatment is partially inspired by work of Marco Oster + * done at ZITI, Heidelberg in 2010. + * + * - original copyright and licence disclaimer (of usb_jtag_init) ------------- + * - Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter + * - Copyright (C) 2005..2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + *----------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + *----------------------------------------------------------------------------- + * + * USB FIFO setup + * + * Revision History: + * + * Date Rev Version Comment + * 2012-01-04 450 1.5 new FLAGS layout (D=8-FF,C=4-EF,B=6-FF,A=indexed) + * 2012-01-02 448 1.4 add support for sync fifo w/ int. clock (_ic) + * 2011-07-24 398 1.1 support 0,2, or 3 data FIFO's + * 2011-07-23 397 1.0 Initial version, factored out from usb_jtag_init() + * + *----------------------------------------------------------------------------- + */ + +#include "fx2regs.h" +#include "syncdelay.h" + +//----------------------------------------------------------------------------- + +void usb_fifo_init(void) // Called once at startup +{ + // set the CPU clock to 48MHz, enable USB clock output to FPGA + // Note: CLKOUT not connected on nexys2, nexys3 and atlys... + CPUCS = bmCLKOE | bmCLKSPD1; + + // setup FIFO mode + // bmIFCLKSRC clock source: 0 external clock; 1 internal clock + // bm3048MHZ clock frequency: 0 30 MHz; 1 48 MHz + // bmIFCLKOE IFCLK pin output enable: 0 tri-state; 1 drive + // bmIFCLKPOL clock polarity: 0 rising edge active; 1 falling edge active + // bmASYNC fifo mode: 0 synchrounous; 1 asynchronous + // IFCFG interface mode: bmIFCFGMASK=11->slave fifo + +#if defined(USE_IC30) + // Use internal 30 MHz, enable output, slave sync FIFO, slave FIFO mode + IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmIFCFGMASK; +#else + // Use internal 30 MHz, enable output, slave async FIFO, slave FIFO mode + IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC | bmIFCFGMASK; +#endif + + // Setup PA7 as FLAGD + PORTACFG = 0x80; SYNCDELAY; // 1000 0000: FLAGD=1, SLCS=0 + + // setup usage of FLAG pins + // goal is to support EP4(out) and EP6/EP8(in) synchronous slave fifos + // for synchronous operation usage of empty/full and almost empty/full + // flags is needed, the later are realized with the programmable flags. + // the three empty/full flags are setup as fixed flags, while the three + // almost (or programmable) flags are channeled over one indexed flag pin. + // FLAGA = indexed, PF (the default) + // FLAGB = EP6 FF + // FLAGC = EP4 EF + // FLAGD = EP8 FF + + PINFLAGSAB = 0xE0; SYNCDELAY; // 1110 0000: B EP6 FF, A indexed + PINFLAGSCD = 0xF9; SYNCDELAY; // 1111 1001: D EP8 FF, C EP4 EF + + // define endpoint configuration + + FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all + REVCTL = 3; SYNCDELAY; // Allow FW access to FIFO buffer + + // FIFOs used for JTAG emulation + // EP1 IN + // EP2 OUT + + EP1OUTCFG = 0x00; SYNCDELAY; // EP1 OUT: inactive + EP1INCFG = 0xA0; SYNCDELAY; // EP1 IN: active, bulk + + EP2FIFOCFG = 0x00; SYNCDELAY; // EP2 slave: 0, not used as slave + FIFORESET = 0x02; SYNCDELAY; // EP2 reset (0x02! see comment below) + EP2CFG = 0xA2; SYNCDELAY; // EP2: 1010 0010: VAL,OUT,BULK,DOUBLE + + // TMR (Rev *D) page 117: auto in/out initialization sequence + // Auto IN transfers + // 1. setup EPxCFG + // 2. reset the FIFO + // 3. set EPxFIFOCFG.3 = 1 + // 4. set EPxAUTOINLENH:L + // Auto OUT transfers + // 1. setup EPxCFG + // 2. reset the FIFO + // 3. arm OUT buffers by writing OUTPKTEND N times w/ skip=1 (N=buf depth) + // 4. set EPxFIFOCFG.4 = 1 + + // 2 FIFOs used for DATA transfer: + // EP4 OUT DOUBLE + // EP6 IN QUAD + +#if defined(USE_2FIFO) || defined(USE_3FIFO) + EP4CFG = 0xA2; SYNCDELAY; // EP4: 1010 0010: VAL,OUT,BULK,DOUBLE +#if defined(USE_3FIFO) + EP6CFG = 0xE2; SYNCDELAY; // EP6: 1110 0010: VAL,IN,BULK,DOUBLE + EP8CFG = 0xE2; SYNCDELAY; // EP8: 1110 0010: VAL,IN,BULK,DOUBLE +#else + EP6CFG = 0xE0; SYNCDELAY; // EP6: 1110 0000: VAL,IN,BULK,QUAD + EP8CFG = 0x02; SYNCDELAY; // EP8: disabled +#endif + + // Note: the description of the FIFORESET in the TMR, Rev *D (2011) is + // wrong. The TMR asks to write 0x80,0x82,0x84,0x86,0x88,0x00, e.g + // on page 117, also in other contexts. + // This doesn't work, FIFO's are in fact not reset ! + // The proper sequence is 0x80,0x02,0x04,0x06,0x08,0x00, as for + // example stated in http://www.cypress.com/?id=4&rID=32093 + FIFORESET = 0x04; SYNCDELAY; // EP4 reset + FIFORESET = 0x06; SYNCDELAY; // EP6 reset + FIFORESET = 0x08; SYNCDELAY; // EP8 reset + FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour + + // !! really needed here, before buffers are armed !! + REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer + + // EP4 OUT setup --------------------------------------------------- + OUTPKTEND = 0x84; SYNCDELAY; // arm all EP4 buffers + OUTPKTEND = 0x84; SYNCDELAY; + // !! hardware only arms endpoint when AUTOOUT 0->1 transition seen + // !! --> clean AUTOOUT to handle for example back-to-back firmware loads + EP4FIFOCFG = 0x00; SYNCDELAY; // EP4: force AUTOOUT 0->1 transition + EP4FIFOCFG = 0x10; SYNCDELAY; // EP4: 0001 0000: AUTOOUT, BYTE + // setup programmable fifo threshold as 'almost empty' at 3 bytes to go + // --> keep active low logic for prgrammable flags + // --> set flag 1 when fill >= threshold (DECIS=1) + // --> almost empty thus at fill<4, effective threshold thus 3 !! + EP4FIFOPFH = 0x80; SYNCDELAY; // 0000 0000: DECIS=1, PFC8=0 + EP4FIFOPFL = 0x04; SYNCDELAY; // PFC = 4 = 0 0000 0100 + + // EP6 IN setup --------------------------------------------------- + EP6FIFOCFG = 0x0C; SYNCDELAY; // EP6: 0000 1100: AUTOIN, ZEROLEN, BYTE + EP6AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers + EP6AUTOINLENL = 0x00; SYNCDELAY; + + // setup programmable fifo threshold as 'almost full' at 3 bytes to go + // --> keep active low logic for prgrammable flags + // --> set flag 1 when fill <= threshold (DECIS=0) + // --> use full buffer fill + // --> for dual buffered: (PKSTAT=0, PKTS=1) [in case 3 fifo's used] + // --> for quad buffered: (PKSTAT=0, PKTS=3) [in case 2 fifo's used] + // --> effective threshold thus 3 in both bases +#if defined(USE_3FIFO) + EP6FIFOPFH = 0x09; SYNCDELAY; // 0000 1001: DECIS=0, PK=0:1, PFC8=1 +#else + EP6FIFOPFH = 0x19; SYNCDELAY; // 0001 1001: DECIS=0, PK=0:3, PFC8=1 +#endif + EP6FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100 + +#if defined(USE_3FIFO) + // EP8 IN setup --------------------------------------------------- + EP8FIFOCFG = 0x0C; SYNCDELAY; // EP8: 0000 1100: AUTOIN, ZEROLEN, BYTE + EP8AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers + EP8AUTOINLENL = 0x00; SYNCDELAY; + // setup programmable fifo threshold as 'almost full' at 4 bytes to go + // like for EP6 above + EP8FIFOPFH = 0x41; SYNCDELAY; // 0100 0001: DECIS=0, PKSTAT=1, PFC8=1 + EP8FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100 + +#else + // EP8 setup + EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave +#endif + +#else + // no FIFOs used for DATA transfer + // EP4,6,8 inactive + EP4CFG = 0x02; SYNCDELAY; // EP4: disabled + EP6CFG = 0x02; SYNCDELAY; // EP6: disabled + EP8CFG = 0x02; SYNCDELAY; // EP8: disabled + + FIFORESET = 0x04; SYNCDELAY; // EP4 reset + FIFORESET = 0x06; SYNCDELAY; // EP6 reset + FIFORESET = 0x08; SYNCDELAY; // EP8 reset + FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour + + EP4FIFOCFG = 0x00; SYNCDELAY; // EP4 slave: 0, not used as slave + EP6FIFOCFG = 0x00; SYNCDELAY; // EP6 slave: 0, not used as slave + EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave + + REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer +#endif + + // the EP2 endpoint does not come up armed. It is used with double buffering + // so write dummy byte counts twice. + SYNCDELAY; // + EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT + EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT +} Index: hardware.h =================================================================== --- hardware.h (nonexistent) +++ hardware.h (revision 26) @@ -0,0 +1,35 @@ +/* $Id: hardware.h 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _HARDWARE_H +#define _HARDWARE_H 1 + +extern void ProgIO_Init(void); +extern void ProgIO_Poll(void); +extern void ProgIO_Enable(void); +extern void ProgIO_Disable(void); +extern void ProgIO_Deinit(void); + +extern void ProgIO_Set_State(unsigned char d); +extern unsigned char ProgIO_Set_Get_State(unsigned char d); +extern void ProgIO_ShiftOut(unsigned char x); +extern unsigned char ProgIO_ShiftInOut(unsigned char x); + +#endif /* _HARDWARE_H */ + Index: hw_nexys2.c =================================================================== --- hw_nexys2.c (nonexistent) +++ hw_nexys2.c (revision 26) @@ -0,0 +1,284 @@ +/* $Id: hw_nexys2.c 447 2011-12-31 19:41:32Z mueller $ */ +/* + * Copyright 2011- by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * + * - original copyright and licence disclaimer -------------------------------- + * - Copyright (C) 2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + * - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2) + * - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling + * - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50 + * ---------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * ---------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + * + * Revision History: + * + * Date Rev Version Comment + * 2011-12-30 447 1.2.1 move JTAG pin OE intoProgIO_Set_State() + * 2011-12-29 446 1.2 clean-out all code not relevant for nexys2 + * 2011-07-23 397 1.1 move IFCONFIG and CPUCS init to usb_fifo_init + * 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204) + * + *----------------------------------------------------------------------------- + */ + +#include +#include "hardware.h" +#include "delay.h" + +//----------------------------------------------------------------------------- + +/* JTAG TCK, AS/PS DCLK */ + +sbit at 0xB4 TCK; /* Port D.4 */ +#define bmTCKOE bmBIT4 +#define SetTCK(x) do{TCK=(x);}while(0) + +/* JTAG TDI, AS ASDI, PS DATA0 */ + +sbit at 0xB2 TDI; /* Port D.2 */ +#define bmTDIOE bmBIT2 +#define SetTDI(x) do{TDI=(x);}while(0) + +/* JTAG TMS, AS/PS nCONFIG */ + +sbit at 0xB3 TMS; /* Port D.3 */ +#define bmTMSOE bmBIT3 +#define SetTMS(x) do{TMS=(x);}while(0) + +/* JTAG TDO, AS/PS CONF_DONE */ + +sbit at 0xB0 TDO; /* Port D.0 */ +#define bmTDOOE bmBIT0 +#define GetTDO(x) TDO + +/* USB Power-On (Nexys2 specific !!) */ + +sbit at 0xB7 USBPOW; /* Port D.7 */ +#define bmUSBPOWOE bmBIT7 +#define SetUSBPOW(x) do{USBPOW=(x);}while(0) + +//----------------------------------------------------------------------------- + +#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE) +#define bmPROGINOE (bmTDOOE) + +//----------------------------------------------------------------------------- + +void ProgIO_Poll(void) {} +void ProgIO_Enable(void) {} +// These aren't called anywhere in usbjtag.c so far, might come... +void ProgIO_Disable(void) {} +void ProgIO_Deinit(void) {} + + +void ProgIO_Init(void) +{ + /* The following code depends on your actual circuit design. + Make required changes _before_ you try the code! */ + + // power on the onboard FPGA: + // output enable and set to 1 the Nexys2 USB-Power-enable signal + SetUSBPOW(1); + OED=bmUSBPOWOE; + // Note: JTAG signal output enables are in ProgIO_Set_State() below. + + mdelay(500); // wait for supply to come up +} + +void ProgIO_Set_State(unsigned char d) +{ + /* Set state of output pins: + * + * d.0 => TCK + * d.1 => TMS + * d.4 => TDI + */ + + // JTAG signal output enables done at first request: + // this allows to use the JTAG connector with another JTAG cable + // alternatively. + OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable + + SetTCK((d & bmBIT0) ? 1 : 0); + SetTMS((d & bmBIT1) ? 1 : 0); + SetTDI((d & bmBIT4) ? 1 : 0); +} + +//----------------------------------------------------------------------------- +// dummied AS/PS code +#define GetASDO(x) 1 + +unsigned char ProgIO_Set_Get_State(unsigned char d) +{ + /* Set state of output pins (s.a.) + * then read state of input pins: + * + * TDO => d.0 + * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE) + */ + + ProgIO_Set_State(d); + return (GetASDO()<<1)|GetTDO(); +} + +//----------------------------------------------------------------------------- + +void ProgIO_ShiftOut(unsigned char c) +{ + /* Shift out byte C: + * + * 8x { + * Output least significant bit on TDI + * Raise TCK + * Shift c right + * Lower TCK + * } + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + ;; Bit0 + RRC A + MOV _TDI,C + SETB _TCK + ;; Bit1 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit2 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit3 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit4 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit5 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit6 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit7 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + ret + _endasm; +} + +/* +;; For ShiftInOut, the timing is a little more +;; critical because we have to read _TDO/shift/set _TDI +;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz +;; is just like 50% at 6 Mhz, and that's still acceptable +*/ + +unsigned char ProgIO_ShiftInOut(unsigned char c) +{ + /* Shift out byte C, shift in from TDO: + * + * 8x { + * Read carry from TDO + * Output least significant bit on TDI + * Raise TCK + * Shift c right, append carry (TDO) at left + * Lower TCK + * } + * Return c. + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + + ;; Bit0 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit1 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit2 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit3 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit4 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit5 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit6 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit7 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + + MOV DPL,A + ret + _endasm; + + /* return value in DPL */ + + return c; +} + Index: startup.a51 =================================================================== --- startup.a51 (nonexistent) +++ startup.a51 (revision 26) @@ -0,0 +1,79 @@ +;;; -*- asm -*- +;;; $Id: startup.a51 395 2011-07-17 22:02:55Z mueller $ +;;; +;;;----------------------------------------------------------------------------- +;;; Startup code +;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; The default external memory initialization provided by sdcc is not +;;; appropriate to the FX2. This is derived from the sdcc code, but uses +;;; the FX2 specific _MPAGE sfr. + + + ;; .area XISEG (XDATA) ; the initialized external data area + ;; .area XINIT (CODE) ; the code space consts to init XISEG + .area XSEG (XDATA) ; zero initialized xdata + .area USBDESCSEG (XDATA) ; usb descriptors + + + .area CSEG (CODE) + + ;; sfr that sets upper address byte of MOVX using @r0 or @r1 + _MPAGE = 0x0092 + +__sdcc_external_startup:: + ;; This system is now compiled with the --no-xinit-opt + ;; which means that any initialized XDATA is handled + ;; inline by code in the GSINIT segs emitted for each file. + ;; + ;; We zero XSEG and all of the internal ram to ensure + ;; a known good state for uninitialized variables. + +; _mcs51_genRAMCLEAR() start + mov r0,#l_XSEG + mov a,r0 + orl a,#(l_XSEG >> 8) + jz 00002$ + mov r1,#((l_XSEG + 255) >> 8) + mov dptr,#s_XSEG + clr a + +00001$: movx @dptr,a + inc dptr + djnz r0,00001$ + djnz r1,00001$ + + ;; We're about to clear internal memory. This will overwrite + ;; the stack which contains our return address. + ;; Pop our return address into DPH, DPL +00002$: pop dph + pop dpl + + ;; R0 and A contain 0. This loop will execute 256 times. + ;; + ;; FWIW the first iteration writes direct address 0x00, + ;; which is the location of r0. We get lucky, we're + ;; writing the correct value (0) + +00003$: mov @r0,a + djnz r0,00003$ + + push dpl ; restore our return address + push dph + + mov dpl,#0 ; indicate that data init is still required + ret Index: eeprom.c =================================================================== --- eeprom.c (nonexistent) +++ eeprom.c (revision 26) @@ -0,0 +1,78 @@ +/* $Id: eeprom.c 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "eeprom.h" +#include "usb_descriptors.h" + +xdata unsigned char eeprom[128]; + +extern xdata char dscr_vidpidver[6]; +extern xdata char dscr_attrpow[2]; +extern xdata char dscr_usbver[2]; +extern xdata char dscr_strorder[4]; +extern xdata char str1[]; +extern xdata char str2[]; +extern xdata char str3[]; + +static unsigned char ee_ptr; +static unsigned short ee_cksum; + +void eeprom_append(unsigned char nb) +{ + unsigned char pree_ptr = ee_ptr & ~1; + if(pree_ptr != ee_ptr) + { + ee_cksum = ee_cksum ^((unsigned short)nb << 8); + ee_cksum = ee_cksum ^ eeprom[pree_ptr]; + ee_cksum = (ee_cksum << 1) | (ee_cksum >> 15); + }; + eeprom[ee_ptr++] = nb; +} + +void eeprom_init(void) +{ + char j,sofs; + ee_ptr = 0; + ee_cksum = 0xAAAA; + + eeprom_append(0x00); + eeprom_append(0x00); + for(j=0;j<6;j++) eeprom_append(dscr_vidpidver[j]); + for(j=0;j<2;j++) eeprom_append(dscr_attrpow[j]); + eeprom_append(0x1C); + eeprom_append(0x00); + for(j=0;j<2;j++) eeprom_append(dscr_usbver[j]); + sofs = 0x80 + ee_ptr + 6; + eeprom_append(sofs); + eeprom_append(str1[0]); + sofs += str1[0]; + eeprom_append(sofs); + eeprom_append(str2[0]); + sofs += str2[0]; + eeprom_append(sofs); + eeprom_append(str3[0]); + for(j=0;j>8)&0xFF; +} + Index: hw_nexys3.c =================================================================== --- hw_nexys3.c (nonexistent) +++ hw_nexys3.c (revision 26) @@ -0,0 +1,274 @@ +/* $Id: hw_nexys3.c 447 2011-12-31 19:41:32Z mueller $ */ +/* + * Copyright 2011- by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * + * - original copyright and licence disclaimer -------------------------------- + * - Copyright (C) 2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + * - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2) + * - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling + * - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50 + * ---------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * ---------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + * + * Revision History: + * + * Date Rev Version Comment + * 2011-12-30 447 1.0.1 move JTAG pin OE intoProgIO_Set_State() + * 2011-12-29 446 1.0 Initial version (adapt&cleanup from hw_nexys2.c) + * + *----------------------------------------------------------------------------- + */ + +#include +#include "hardware.h" +#include "delay.h" + +//----------------------------------------------------------------------------- + +/* JTAG TCK, AS/PS DCLK */ + +sbit at 0xB4 TCK; /* Port D.4 */ +#define bmTCKOE bmBIT4 +#define SetTCK(x) do{TCK=(x);}while(0) + +/* JTAG TDI, AS ASDI, PS DATA0 */ + +sbit at 0xB2 TDI; /* Port D.2 */ +#define bmTDIOE bmBIT2 +#define SetTDI(x) do{TDI=(x);}while(0) + +/* JTAG TMS, AS/PS nCONFIG */ + +sbit at 0xB3 TMS; /* Port D.3 */ +#define bmTMSOE bmBIT3 +#define SetTMS(x) do{TMS=(x);}while(0) + +/* JTAG TDO, AS/PS CONF_DONE */ + +sbit at 0xB0 TDO; /* Port D.0 */ +#define bmTDOOE bmBIT0 +#define GetTDO(x) TDO + +//----------------------------------------------------------------------------- + +#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE) +#define bmPROGINOE (bmTDOOE) + +//----------------------------------------------------------------------------- + +void ProgIO_Poll(void) {} +void ProgIO_Enable(void) {} +// These aren't called anywhere in usbjtag.c so far, might come... +void ProgIO_Disable(void) {} +void ProgIO_Deinit(void) {} + + +void ProgIO_Init(void) +{ + /* The following code depends on your actual circuit design. + Make required changes _before_ you try the code! */ + + // Note: JTAG signal output enables are in ProgIO_Set_State() below. + + mdelay(500); // wait for supply to come up + +} + +void ProgIO_Set_State(unsigned char d) +{ + /* Set state of output pins: + * + * d.0 => TCK + * d.1 => TMS + * d.4 => TDI + */ + + // JTAG signal output enables done at first request: + // this allows to use the JTAG connector with another JTAG cable + // alternatively. + OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable + + SetTCK((d & bmBIT0) ? 1 : 0); + SetTMS((d & bmBIT1) ? 1 : 0); + SetTDI((d & bmBIT4) ? 1 : 0); +} + +//----------------------------------------------------------------------------- +// dummied AS/PS code +#define GetASDO(x) 1 + +unsigned char ProgIO_Set_Get_State(unsigned char d) +{ + /* Set state of output pins (s.a.) + * then read state of input pins: + * + * TDO => d.0 + * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE) + */ + + ProgIO_Set_State(d); + return (GetASDO()<<1)|GetTDO(); +} + +//----------------------------------------------------------------------------- + +void ProgIO_ShiftOut(unsigned char c) +{ + /* Shift out byte C: + * + * 8x { + * Output least significant bit on TDI + * Raise TCK + * Shift c right + * Lower TCK + * } + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + ;; Bit0 + RRC A + MOV _TDI,C + SETB _TCK + ;; Bit1 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit2 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit3 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit4 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit5 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit6 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit7 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + ret + _endasm; +} + +/* +;; For ShiftInOut, the timing is a little more +;; critical because we have to read _TDO/shift/set _TDI +;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz +;; is just like 50% at 6 Mhz, and that's still acceptable +*/ + +unsigned char ProgIO_ShiftInOut(unsigned char c) +{ + /* Shift out byte C, shift in from TDO: + * + * 8x { + * Read carry from TDO + * Output least significant bit on TDI + * Raise TCK + * Shift c right, append carry (TDO) at left + * Lower TCK + * } + * Return c. + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + + ;; Bit0 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit1 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit2 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit3 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit4 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit5 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit6 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit7 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + + MOV DPL,A + ret + _endasm; + + /* return value in DPL */ + + return c; +} + + Index: dscr_gen.A51 =================================================================== --- dscr_gen.A51 (nonexistent) +++ dscr_gen.A51 (revision 26) @@ -0,0 +1,455 @@ +;;; -*- asm -*- +;;; $Id: dscr_gen.A51 457 2012-02-12 22:34:20Z mueller $ +;;; +;;; Copyright 2011-2012 by Walter F.J. Mueller +;;; Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 +;;; +;;;- original copyright and licence disclaimer --------------------------------- +;;;- Copyright 2005..2007 Kolja Waschk, ixo.de +;;;- Code based on USRP2 firmware (GNU Radio Project), version 3.0.2, +;;;- Copyright 2003 Free Software Foundation, Inc. +;;;- This code is part of usbjtag. usbjtag is free software; +;;;- --------------------------------------------------------------------------- +;;; +;;; This program is free software; you may redistribute and/or modify it under +;;; the terms of the GNU General Public License as published by the Free +;;; Software Foundation, either version 2, or at your option any later version. +;;; +;;; This program is distributed in the hope that it will be useful, but +;;; WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +;;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;;; for complete details. +;;; +;;;----------------------------------------------------------------------------- +;;; USB Descriptor, common source for jtag + 0, 2, or 3 hardware fifo interface +;;; +;;; Use C preprocessor to create an assembler source for the configurations: +;;; +;;; Endpoint Usage Comment +;;; EP1 IN jtag always defined +;;; EP2 OUT jtag always defined +;;; EP4 OUT data defined if USE_2FIFO or USE_3FIFO +;;; EP6 IN data defined if USE_2FIFO or USE_3FIFO +;;; EP8 IN data defined if USE_3FIFO +;;; +;;; Available preprocessor options +;;; +;;; USE_VID USB Vendor ID +;;; USE_PID USB Product ID +;;; +;;; USE_2FIFO if given EP4 OUT and EP6 IN created +;;; USE_3FIFO if given EP4 OUT, EP6 IN and EP8 IN created +;;; USE_DID=0xhhhh for product version (default 0x0004) +;;; USE_MAXPOWER=nnn for USB max current (in units of 2 mA; default 250) +;;; +;;; USE_NEXYS2 prefix 'nexys2_' in iProduct string +;;; USE_NEXYS3 prefix 'nexys3_' in iProduct string +;;; USE_AS suffix '_as' in iProduct string +;;; USE_IC suffix '_ic' in iProduct string +;;; +;;; Usage +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 > ... +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 -DUSE_2FIFO > ... +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 -DUSE_3FIFO > ... +;;; +;;; +;;; Revision History: +;;; +;;; Date Rev Version Comment +;;; 2012-02-11 457 2.1 iVendor string now reflects firmware file name; +;;; iSerial string now 00000000; +;;; VID/PID now via USE_VID/USE_PID defines +;;; 2011-07-24 398 2.0 Convert all *.a51 to one common source +;;; 2011-07-17 395 1.1 Use USB 2.0; New string values; use 512 byte for +;;; all high speed endpoints +;;; 2011-07-17 395 1.0 Initial version (derived from dscr_jtag.a51) +;;;----------------------------------------------------------------------------- + +#ifndef USE_DID +#define USE_DID 0x0004 +#endif + +#ifndef USE_MAXPOWER +#define USE_MAXPOWER 250 +#endif + +#ifdef USE_3FIFO +#define NUM_EPS 5 +#elif USE_2FIFO +#define NUM_EPS 4 +#else +#define NUM_EPS 2 +#endif + + .module usb_descriptors + + VID = USE_VID ; Vendor ID + PID = USE_PID ; Product ID + VERSION = USE_DID ; Version + + USB_VER = 0x0200 ; Support USB version 2.00 + USB_ATTR = 0x80 ; Bus powered, no remote wakeup + FTD_ATTR = 0x001C ; Set USB version, use version string, enable suspend PD + MAX_POWER = USE_MAXPOWER + + DSCR_DEVICE = 1 ; Descriptor type: Device + DSCR_CONFIG = 2 ; Descriptor type: Configuration + DSCR_STRING = 3 ; Descriptor type: String + DSCR_INTRFC = 4 ; Descriptor type: Interface + DSCR_ENDPNT = 5 ; Descriptor type: Endpoint + DSCR_DEVQUAL = 6 ; Descriptor type: Device Qualifier + + DSCR_DEVICE_LEN = 18 + DSCR_CONFIG_LEN = 9 + DSCR_INTRFC_LEN = 9 + DSCR_ENDPNT_LEN = 7 + DSCR_DEVQUAL_LEN = 10 + + ET_CONTROL = 0 ; Endpoint type: Control + ET_ISO = 1 ; Endpoint type: Isochronous + ET_BULK = 2 ; Endpoint type: Bulk + ET_INT = 3 ; Endpoint type: Interrupt + +;;; -------------------------------------------------------- +;;; external ram data +;;;-------------------------------------------------------- + + .area USBDESCSEG (XDATA) + + .even ; descriptors must be 2-byte aligned for SUDPTR{H,L} to work + + ;; The .even directive isn't really honored by the linker. Bummer! + ;; (There's no way to specify an alignment requirement for a given area, + ;; hence when they're concatenated together, even doesn't work.) + ;; + ;; We work around this by telling the linker to put USBDESCSEG + ;; at absolute address 0xE100 (see LDFLAGS in Makefile). + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at high speed (480Mbps) +;;; ---------------------------------------------------------------- + +_high_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE +_dscr_usbver:: + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 +_dscr_vidpidver:: + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice +_dscr_strorder:: + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + + .even +_high_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB (MSB) + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 12Mbps) + .db 0 ; bReserved + + .even +_high_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_high_speed_config_descr_end - _high_speed_config_descr) + .db >(_high_speed_config_descr_end - _high_speed_config_descr) + .db 1 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration +_dscr_attrpow:: + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 2 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db NUM_EPS ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor (jtag response) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (EP 1 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) !! use only 64 byte + .db >512 ; wMaxPacketSize (MSB) !! use only 64 byte + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor (jtag request) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (EP 2 OUT) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) !! use only 64 byte + .db >512 ; wMaxPacketSize (MSB) !! use only 64 byte + .db 0 ; bInterval (iso only) + +#if defined(USE_2FIFO) || defined(USE_3FIFO) + + ;; endpoint descriptor (RXFIFO HOST->FPGA) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x04 ; bEndpointAddress (EP 4 OUT) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor (TXFIFO FPGA->HOST) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x86 ; bEndpointAddress (EP 6 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +#endif + +#if defined(USE_3FIFO) + + ;; endpoint descriptor (extra FIFO FPGA->HOST) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x88 ; bEndpointAddress (EP 8 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +#endif + +_high_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at full speed (12Mbps) +;;; no data fifo endpoints defined, if we are in full speed mode this will be no +;;; fun anyway. Shouldn't happen anyway, unless stone age USB hubs interfere... +;;; ---------------------------------------------------------------- + + .even +_full_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + +;;; describes the other speed (480Mbps) + .even +_full_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 480Mbps) + .db 0 ; bReserved + + .even +_full_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_full_speed_config_descr_end - _full_speed_config_descr) + .db >(_full_speed_config_descr_end - _full_speed_config_descr) + .db 1 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 2 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 2 ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (EP 1 IN) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (EP 2 OUT) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +_full_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; string descriptors +;;; ---------------------------------------------------------------- + +_nstring_descriptors:: + .db (_string_descriptors_end - _string_descriptors) / 2 + +_string_descriptors:: + .db str0 + .db str1 + .db str2 + .db str3 +_string_descriptors_end: + + SI_NONE = 0 + ;; str0 contains the language ID's. + .even +_str0:: +str0: .db str0_end - str0 + .db DSCR_STRING + .db 0 + .db 0 + .db <0x0409 ; magic code for US English (LSB) + .db >0x0409 ; magic code for US English (MSB) +str0_end: + + SI_VENDOR = 1 + .even +_str1:: +str1: .db str1_end - str1 + .db DSCR_STRING + .db 'w, 0 ; 16-bit unicode + .db 'w, 0 + .db 'w, 0 + .db '., 0 + .db 'r, 0 + .db 'e, 0 + .db 't, 0 + .db 'r, 0 + .db 'o, 0 + .db '1, 0 + .db '1, 0 + .db '., 0 + .db 'd, 0 + .db 'e, 0 +str1_end: + + SI_PRODUCT = 2 + .even +_str2:: +str2: .db str2_end - str2 + .db DSCR_STRING +#if defined(USE_NEXYS2) + .db 'n, 0 + .db 'e, 0 + .db 'x, 0 + .db 'y, 0 + .db 's, 0 + .db '2, 0 + .db '_, 0 +#endif +#if defined(USE_NEXYS3) + .db 'n, 0 + .db 'e, 0 + .db 'x, 0 + .db 'y, 0 + .db 's, 0 + .db '3, 0 + .db '_, 0 +#endif + .db 'j, 0 + .db 't, 0 + .db 'a, 0 + .db 'g, 0 +#if defined(USE_2FIFO) + .db '_, 0 + .db '2, 0 + .db 'f, 0 + .db 'i, 0 + .db 'f, 0 + .db 'o, 0 +#endif +#if defined(USE_3FIFO) + .db '_, 0 + .db '3, 0 + .db 'f, 0 + .db 'i, 0 + .db 'f, 0 + .db 'o, 0 +#endif +#if defined(USE_AS) + .db '_, 0 + .db 'a, 0 + .db 's, 0 +#endif +#if defined(USE_IC) + .db '_, 0 + .db 'i, 0 + .db 'c, 0 +#endif +str2_end: + + SI_SERIAL = 3 + .even +_str3:: +str3: .db str3_end - str3 + .db DSCR_STRING + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 +str3_end: Index: vectors.a51 =================================================================== --- vectors.a51 (nonexistent) +++ vectors.a51 (revision 26) @@ -0,0 +1,177 @@ +;;; -*- asm -*- +;;; $Id: vectors.a51 395 2011-07-17 22:02:55Z mueller $ +;;; +;;;----------------------------------------------------------------------------- +;;; Interrupt vectors +;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; N.B. This object module must come first in the list of modules + + .module vectors + +;;; ---------------------------------------------------------------- +;;; standard FX2 interrupt vectors +;;; ---------------------------------------------------------------- + + .area CSEG (CODE) + .area GSINIT (CODE) + .area CSEG (CODE) +__standard_interrupt_vector:: +__reset_vector:: + ljmp s_GSINIT + + ;; 13 8-byte entries. We point them all at __isr_nop + ljmp __isr_nop ; 3 bytes + .ds 5 ; + 5 = 8 bytes for vector slot + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + +__isr_nop:: + reti + +;;; ---------------------------------------------------------------- +;;; the FIFO/GPIF autovector. 14 4-byte entries. +;;; must start on a 128 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0080 + +__fifo_gpif_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + + +;;; ---------------------------------------------------------------- +;;; the USB autovector. 32 4-byte entries. +;;; must start on a 256 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0100 + +__usb_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop Index: README.txt =================================================================== --- README.txt (nonexistent) +++ README.txt (revision 26) @@ -0,0 +1,25 @@ +# $Id: README.txt 395 2011-07-17 22:02:55Z mueller $ +# + +The FX2 software is based on the Sourceforge project ixo-jtag + + http://sourceforge.net/projects/ixo-jtag/ + +The usb_jtag sub project was checked out on 2011-07-17 (Rev 204) +from Sourceforge and take as the basis for the further developement. +The original README.txt is preserved under README_iso_jtag.txt. +Only the hw_nexys.c branch is kept on the import. + +Change log: + +2011-07-17 (Rev 395) + - Makefile: reorganized to support multiple target/fifo configs + - renames: + dscr.a51->dscr_jtag.a51 + hw_nexys.c->hw_nexys2.c + usbjtag.c->main.c + - dscr_jtag.a51 + - Use USB 2.0; New string values + - use 512 byte for all high speed endpoints + - dscr_jtag_2fifo.a51 + - dscr with EP4 as HOST->FPGA and EP6 as FPGA->HOST hardware fifo Index: Makefile =================================================================== --- Makefile (nonexistent) +++ Makefile (revision 26) @@ -0,0 +1,219 @@ +# $Id: Makefile 461 2012-04-09 21:17:54Z mueller $ +# +# Copyright 2011-2012 by Walter F.J. Mueller +# Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 +# +# - original copyright and licence disclaimer -------------------------------- +# - Copyright 2007 Kolja Waschk, ixo.de +# - This code is part of usbjtag. usbjtag is free software; +#----------------------------------------------------------------------------- +# +# This program is free software; you may redistribute and/or modify it under +# the terms of the GNU General Public License as published by the Free +# Software Foundation, either version 2, or at your option any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for complete details. +#----------------------------------------------------------------------------- +# +# Makefile for FX2 Firmware on Digilent Nexys2, Nexys3, and Atlys boards +# +# Revision History: +# Date Rev Version Comment +# 2012-04-09 461 1.5.1 fixed nexys3_jtag_3fifo_ic.ihx rule,used _2fifo code +# 2012-02-11 457 1.5 re-organize VID/PID and descriptor handling +# 2012-01-02 448 1.4 add support for sync fifo w/ int. clock (_ic) +# 2011-12-29 446 1.3 add nexys3 support +# 2011-07-23 397 1.2 add usb_fifo_init.c +# 2011-07-17 395 1.1 reorganized to support multiple target/fifo configs +# 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204) +#----------------------------------------------------------------------------- +# +# handle USB VID/PID +# - normaly given via the environment variables (as 4 digit hex number) +# RETRO_FX2_VID +# RETRO_FX2_PID +# +# - in the retro11 project the default is: +# VID: 16c0 (VOTI) +# PID: 03ef (VOTI free for internal lab use 1007) +# +# !! Important Note on Usage of this USB VID/PID !! +# This VID/PID is owned by VOTI, a small dutch company. Usage is granted +# for 'internal lab use only' by VOTI under the conditions: +# - the gadgets in which you use those PIDs do not leave your desk +# - you won't complain to VOTI if you get in trouble with duplicate PIDs +# (for instance because someone else did not follow the previous rule). +# See also http://www.voti.nl/pids/pidfaq.html +# +ifndef RETRO_FX2_VID +RETRO_FX2_VID = 16c0 +endif +ifndef RETRO_FX2_PID +RETRO_FX2_PID = 03ef +endif +# +DEFVIDPID=-DUSE_VID=0x${RETRO_FX2_VID} -DUSE_PID=0x${RETRO_FX2_PID} +# +# compiler and assembler flags +# +LIBDIR=lib +LIB=libfx2.lib + +CC=sdcc +CFLAGS+=-mmcs51 --no-xinit-opt -I${LIBDIR} + +AS=asx8051 +ASFLAGS+=-plosgff + +LDFLAGS=--code-loc 0x0000 --code-size 0x1800 +LDFLAGS+=--xram-loc 0x1800 --xram-size 0x0800 +LDFLAGS+=-Wl '-b USBDESCSEG = 0xE100' +LDFLAGS+=-L ${LIBDIR} +# +# compile rules +# +%.rel : %.a51 + $(AS) $(ASFLAGS) $< + +%.rel : %.c + $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@ +# +# link rule +# +%.ihx : + $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $+ +# +# primary target rules +# +ALLIHX =nexys2_jtag.ihx +ALLIHX +=nexys2_jtag_2fifo_as.ihx +ALLIHX +=nexys2_jtag_3fifo_as.ihx +ALLIHX +=nexys2_jtag_2fifo_ic.ihx +ALLIHX +=nexys2_jtag_3fifo_ic.ihx +ALLIHX +=nexys3_jtag.ihx +ALLIHX +=nexys3_jtag_2fifo_as.ihx +ALLIHX +=nexys3_jtag_3fifo_as.ihx +ALLIHX +=nexys3_jtag_2fifo_ic.ihx +ALLIHX +=nexys3_jtag_3fifo_ic.ihx + +.PHONY: all install + +all: $(ALLIHX) + +install: $(ALLIHX) + cp -p $(ALLIHX) ../bin +# +# rules to create USB descriptor sources +# +CPPA51=cpp -P -x assembler-with-cpp + +dscr_nexys2_jtag.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 $< > $@ +dscr_nexys2_jtag_2fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_2FIFO -DUSE_AS $< > $@ +dscr_nexys2_jtag_3fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_3FIFO -DUSE_AS $< > $@ +dscr_nexys2_jtag_2fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_2FIFO -DUSE_IC $< > $@ +dscr_nexys2_jtag_3fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_3FIFO -DUSE_IC $< > $@ + +dscr_nexys3_jtag.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 $< > $@ +dscr_nexys3_jtag_2fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_2FIFO -DUSE_AS $< > $@ +dscr_nexys3_jtag_3fifo_as.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_3FIFO -DUSE_AS $< > $@ +dscr_nexys3_jtag_2fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_2FIFO -DUSE_IC $< > $@ +dscr_nexys3_jtag_3fifo_ic.a51 : dscr_gen.A51 + $(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_3FIFO -DUSE_IC $< > $@ +# +# rules to create usb_fifo_init variants +# +usb_fifo_init_jtag.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) $< -o $@ +# +usb_fifo_init_jtag_2fifo_as.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_2FIFO $< -o $@ +usb_fifo_init_jtag_3fifo_as.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_3FIFO $< -o $@ +# +usb_fifo_init_jtag_2fifo_ic.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_2FIFO -DUSE_IC30 $< -o $@ +usb_fifo_init_jtag_3fifo_ic.rel : usb_fifo_init.c + $(CC) -c $(CFLAGS) -DUSE_3FIFO -DUSE_IC30 $< -o $@ +# +COM_REL=vectors.rel main.rel eeprom.rel startup.rel +# +I0_REL=usb_fifo_init_jtag.rel +# +IAS2_REL=usb_fifo_init_jtag_2fifo_as.rel +IAS3_REL=usb_fifo_init_jtag_3fifo_as.rel +# +IIC2_REL=usb_fifo_init_jtag_2fifo_ic.rel +IIC3_REL=usb_fifo_init_jtag_3fifo_ic.rel +# +N2_REL=hw_nexys2.rel +N3_REL=hw_nexys3.rel +# +LIB_REL=$(LIBDIR)/$(LIB) +# +# rules to compile all code +# +$(LIBDIR)/$(LIB) : + make -C $(LIBDIR) + +eeprom.rel : eeprom.c eeprom.h +main.rel : main.c hardware.h eeprom.h + +$(N2_REL) : hw_nexys2.c hardware.h +$(N3_REL) : hw_nexys3.c hardware.h + +# +# rules to build Nexys2 firmware images +# +nexys2_jtag.ihx : $(COM_REL) dscr_nexys2_jtag.rel \ + $(N2_REL) $(I0_REL) $(LIB_REL) +# +nexys2_jtag_2fifo_as.ihx : $(COM_REL) dscr_nexys2_jtag_2fifo_as.rel \ + $(N2_REL) $(IAS2_REL) $(LIB_REL) +nexys2_jtag_3fifo_as.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_as.rel \ + $(N2_REL) $(IAS3_REL) $(LIB_REL) +# +nexys2_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_2fifo_ic.rel \ + $(N2_REL) $(IIC2_REL) $(LIB_REL) +nexys2_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_ic.rel \ + $(N2_REL) $(IIC3_REL) $(LIB_REL) +# +# rules to build Nexys3 firmware images +# +nexys3_jtag.ihx : $(COM_REL) dscr_nexys3_jtag.rel \ + $(N3_REL) $(I0_REL) $(LIB_REL) +# +nexys3_jtag_2fifo_as.ihx : $(COM_REL) dscr_nexys3_jtag_2fifo_as.rel \ + $(N3_REL) $(IAS2_REL) $(LIB_REL) +nexys3_jtag_3fifo_as.ihx : $(COM_REL) dscr_nexys3_jtag_3fifo_as.rel \ + $(N3_REL) $(IAS3_REL) $(LIB_REL) +# +nexys3_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_2fifo_ic.rel \ + $(N3_REL) $(IIC2_REL) $(LIB_REL) +nexys3_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_3fifo_ic.rel \ + $(N3_REL) $(IIC3_REL) $(LIB_REL) +# +# cleanup phony's +# +.PHONY : clean distclean + +clean : + make -C ${LIBDIR} clean + rm -f *.lst *.asm *.lib *.sym *.rel *.mem *.map *.rst *.lnk + rm -f dscr_*.a51 + +distclean : clean + rm -f *.ihx + + Index: eeprom.h =================================================================== --- eeprom.h (nonexistent) +++ eeprom.h (revision 26) @@ -0,0 +1,27 @@ +/* $Id: eeprom.h 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _EEPROM_H +#define _EEPROM_H 1 + +extern xdata unsigned char eeprom[128]; +extern void eeprom_init(void); + +#endif /* _EEPROM_H */ + Index: .cvsignore =================================================================== --- .cvsignore (nonexistent) +++ .cvsignore (revision 26) @@ -0,0 +1,10 @@ +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +dscr_*.a51 Index: . =================================================================== --- . (nonexistent) +++ . (revision 26)

. Property changes : Added: svn:ignore ## -0,0 +1,43 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +dscr_*.a51

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