OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.7/rtl/bplib/nexys2
    from Rev 30 to Rev 33
    ↔ Reverse comparison
  •

Rev 30 → Rev 33

/tb/tb_nexys2_fusp_cuff.vbom
0,0 → 1,26
# Not meant for direct top level usage. Used with
# tb_nexys2_fusp_cuff_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_master.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom}
# design
tb_nexys2_fusp_cuff.vhd
@top:tb_nexys2_fusp_cuff
/tb/tb_nexys2_fusp.vhd
0,0 → 1,270
-- $Id: tb_nexys2_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys2_core
-- serport/serport_master
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
 
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
 
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
 
signal RX_HOLD : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
 
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
 
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
 
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
 
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
 
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
 
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
 
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
 
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
 
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
 
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
 
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
 
end sim;
/tb/tb_nexys2_fusp.vbom
0,0 → 1,25
# Not meant for direct top level usage. Used with
# tb_nexys2_fusp_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_master.vbom
${nexys2_fusp_aif := nexys2_fusp_dummy.vbom}
# design
tb_nexys2_fusp.vhd
@top:tb_nexys2_fusp
/tb/tb_nexys2_fusp_cuff.vhd
0,0 → 1,336
-- $Id: tb_nexys2_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp_cuff - sim
-- Description: Test bench for nexys2 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink_dcm
-- tb_nexys2_core
-- serport/serport_master
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys2_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-01-03 469 1.1 add fx2 model and data path
-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
 
entity tb_nexys2_fusp_cuff is
end tb_nexys2_fusp_cuff;
 
architecture sim of tb_nexys2_fusp_cuff is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
 
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
 
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
 
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
 
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
 
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
 
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
 
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
 
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
 
SB_CLKSTOP <= CLK_STOP;
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
 
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
 
UUT : nexys2_fusp_cuff_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
 
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXOK => '1',
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
 
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
 
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
 
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
 
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
 
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
 
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
 
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
end if;
end if;
end process proc_simbus;
 
end sim;
/tb/tb_nexys2_core.vhd
0,0 → 1,99
-- $Id: tb_nexys2_core.vhd 649 2015-02-21 21:10:16Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_core - sim
-- Description: Test bench for nexys2 - core device handling
--
-- Dependencies: vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 1.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 1.1 update O_FLA_CE_N usage
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
 
entity tb_nexys2_core is
port (
I_SWI : out slv8; -- n2 switches
I_BTN : out slv4; -- n2 buttons
O_MEM_CE_N : in slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : in slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : in slbit; -- cram: write enable (act.low)
O_MEM_OE_N : in slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : in slbit; -- cram: address valid (act.low)
O_MEM_CLK : in slbit; -- cram: clock
O_MEM_CRE : in slbit; -- cram: command register enable
I_MEM_WAIT : out slbit; -- cram: mem wait
O_MEM_ADDR : in slv23; -- cram: address lines
IO_MEM_DATA : inout slv16 -- cram: data lines
);
end tb_nexys2_core;
 
architecture sim of tb_nexys2_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
 
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
 
begin
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
 
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
/tb/Makefile
0,0 → 1,44
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2014-07-27 545 1.2.2 make reference board configurable via XTW_BOARD
# 2013-01-01 467 1.2.1 add tb_nexys2_fusp_cuff_dummy
# 2011-11-26 433 1.2 remove tb_n2_cram_memctl_as (moved to nxcramlib)
# 2011-08-13 405 1.1 use includes from rtl/make
# 2010-05-30 297 1.0.2 use tb_n2_cram_memctl_as now
# 2010-05-28 295 1.0.1 add tb_.._dummy's
# 2007-09-23 84 1.0 Initial version
#
EXE_all = tb_nexys2_dummy
EXE_all += tb_nexys2_fusp_dummy
EXE_all += tb_nexys2_fusp_cuff_dummy
#
ifndef XTW_BOARD
XTW_BOARD=nexys2
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
endif
#
/tb/tb_nexys2_core.vbom
0,0 → 1,10
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
../../micron/mt45w8mw16b.vbom
# design
tb_nexys2_core.vhd
/tb/.cvsignore
0,0 → 1,3
tb_nexys2_dummy
tb_nexys2_fusp_dummy
tb_nexys2_fusp_cuff_dummy
/tb
tb Property changes : Added: svn:ignore ## -0,0 +1,36 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nexys2_dummy +tb_nexys2_fusp_dummy +tb_nexys2_fusp_cuff_dummy Index: nexys2lib.vhd =================================================================== --- nexys2lib.vhd (nonexistent) +++ nexys2lib.vhd (revision 33) @@ -0,0 +1,162 @@ +-- $Id: nexys2lib.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2010-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nexys2lib +-- Description: Nexys 2 components +-- +-- Dependencies: - +-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-01-01 467 1.4 add nexys2_cuff_aif, nexys2_fusp_cuff_aif +-- 2011-12-23 444 1.3 remove clksys output hack +-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib +-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram driver/dummy +-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock) +-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50 +-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy +-- 2010-05-23 294 1.0.2 add n2_cram_dummy; +-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl +-- 2010-05-21 292 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nexys2lib is + +component nexys2_aif is -- NEXYS 2, abstract iface, base + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit -- flash ce.. (act.low) + ); +end component; + +component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end component; + +component nexys2_cuff_aif is -- NEXYS 2, abstract iface, base+cuff + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +component nexys2_fusp_cuff_aif is -- NEXYS 2, abstract iface, +fusp+cuff + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n2 switches + I_BTN : in slv4; -- n2 buttons + O_LED : out slv8; -- n2 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_FLA_CE_N : out slbit; -- flash ce.. (act.low) + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end component; + +end package nexys2lib; Index: Makefile =================================================================== --- Makefile (nonexistent) +++ Makefile (revision 33) @@ -0,0 +1,30 @@ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-05-23 293 1.0 Initial version (cloned..) +# +VBOM_all = $(wildcard *.vbom) +NGC_all = $(VBOM_all:.vbom=.ngc) +# +ifndef XTW_BOARD + XTW_BOARD=nexys2 +endif +include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk +# +.PHONY : all clean +# +all : $(NGC_all) +# +clean : ise_clean +# +#---- +# +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +endif +# Index: nexys2_time_fx2_ic.ucf =================================================================== --- nexys2_time_fx2_ic.ucf (nonexistent) +++ nexys2_time_fx2_ic.ucf (revision 33) @@ -0,0 +1,27 @@ +## $Id: nexys2_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-05 537 1.1 add VALID for hold time check +## 2012-01-01 448 1.0 Initial version +## +## timing rules for a 30 MHz internal clock design: +## Period: 30 MHz +## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns +## clk->out < 33.3-18.7 = 14.6 ns +## --> use 10 ns +## + +## The nexys2 board has unfortunately the FX2 IFCLK *not* connected to a +## clock capable pin -> not ok when FX2 uses internal clock. So allow par +## to route from a 'normal' pin to a clock net. Not nice, compromizes the +## timing, but unavoidable on nexys2 (Note: nexys3 and atlys are ok). +## In practice IFCLK to pad times are quite similar on nexys2 and nexys3... + +NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE; + +## +NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK"; +TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %; +OFFSET = IN 2.5 ns VALID 33 ns BEFORE "I_FX2_IFCLK"; +OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK"; Index: nexys2_pins_fx2.ucf =================================================================== --- nexys2_pins_fx2.ucf (nonexistent) +++ nexys2_pins_fx2.ucf (revision 33) @@ -0,0 +1,36 @@ +## $Id: nexys2_pins_fx2.ucf 397 2011-07-24 09:43:07Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2011-07-05 389 1.0 Initial version +## +## Cypress EZ-USB FX2 Interface ---------------------------------------------- +## +## +NET "I_FX2_IFCLK" LOC = "t15" | IOSTANDARD=LVCMOS33; +## +NET "IO_FX2_DATA<0>" LOC = "r14" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<1>" LOC = "r13" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<2>" LOC = "p13" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<3>" LOC = "t12" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<4>" LOC = "n11" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<5>" LOC = "r11" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<6>" LOC = "p10" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<7>" LOC = "r10" | IOSTANDARD=LVCMOS33; +NET "IO_FX2_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## +NET "O_FX2_SLWR_N" LOC = "v9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLRD_N" LOC = "n9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_SLOE_N" LOC = "v15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_PKTEND_N" LOC = "v12" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_FX2_FIFO<0>" LOC = "t14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_FX2_FIFO<1>" LOC = "v13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +## assume that PA.7 is used a FLAGD (and not as SLCS#) +NET "I_FX2_FLAG<0>" LOC = "v14" | IOSTANDARD=LVCMOS33; ## flag a (program) +NET "I_FX2_FLAG<1>" LOC = "u14" | IOSTANDARD=LVCMOS33; ## flag b (full) +NET "I_FX2_FLAG<2>" LOC = "v16" | IOSTANDARD=LVCMOS33; ## flag c (empty) +NET "I_FX2_FLAG<3>" LOC = "t16" | IOSTANDARD=LVCMOS33; ## flag d (slcs) +## Index: nexys2_pins.ucf =================================================================== --- nexys2_pins.ucf (nonexistent) +++ nexys2_pins.ucf (revision 33) @@ -0,0 +1,127 @@ +## $Id: nexys2_pins.ucf 444 2011-12-25 10:04:58Z mueller $ +## +## Pin locks for Nexys 2 core functionality (for 1200k FPGA) +## - internal RS232 +## - human I/O (switches, buttons, leds, display) +## - cram +## +## Revision History: +## Date Rev Version Comment +## 2011-11-23 444 1.1 remove clksys output hack +## 2010-11-13 338 1.0.3 add O_CLKSYS (for DCM derived system clock) +## 2010-11-06 336 1.0.2 Rename CLK -> I_CLK50 +## 2010-05-23 294 1.0.1 use ADV_N rather ADV +## 2010-05-16 291 1.0 Initial version +## +## Note: default is DRIVE=12 | SLEW=SLOW +## +## clocks -------------------------------------------------------------------- +NET "I_CLK50" LOC = "b8" | IOSTANDARD=LVCMOS33; +## +## RS232 interface ----------------------------------------------------------- +NET "I_RXD" LOC = "u6" | IOSTANDARD=LVCMOS33; +NET "O_TXD" LOC = "p9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW; +## +## switches and buttons ------------------------------------------------------ +NET "I_SWI<0>" LOC = "g18" | IOSTANDARD=LVCMOS33; +NET "I_SWI<1>" LOC = "h18" | IOSTANDARD=LVCMOS33; +NET "I_SWI<2>" LOC = "k18" | IOSTANDARD=LVCMOS33; +NET "I_SWI<3>" LOC = "k17" | IOSTANDARD=LVCMOS33; +NET "I_SWI<4>" LOC = "l14" | IOSTANDARD=LVCMOS33; +NET "I_SWI<5>" LOC = "l13" | IOSTANDARD=LVCMOS33; +NET "I_SWI<6>" LOC = "n17" | IOSTANDARD=LVCMOS33; +NET "I_SWI<7>" LOC = "r17" | IOSTANDARD=LVCMOS33; +## +NET "I_BTN<0>" LOC = "b18" | IOSTANDARD=LVCMOS33; +NET "I_BTN<1>" LOC = "d18" | IOSTANDARD=LVCMOS33; +NET "I_BTN<2>" LOC = "e18" | IOSTANDARD=LVCMOS33; +NET "I_BTN<3>" LOC = "h13" | IOSTANDARD=LVCMOS33; +## +## LEDs ---------------------------------------------------------------------- +NET "O_LED<0>" LOC = "j14" | IOSTANDARD=LVCMOS33; +NET "O_LED<1>" LOC = "j15" | IOSTANDARD=LVCMOS33; +NET "O_LED<2>" LOC = "k15" | IOSTANDARD=LVCMOS33; +NET "O_LED<3>" LOC = "k14" | IOSTANDARD=LVCMOS33; +NET "O_LED<4>" LOC = "e16" | IOSTANDARD=LVCMOS33; +NET "O_LED<5>" LOC = "p16" | IOSTANDARD=LVCMOS33; +NET "O_LED<6>" LOC = "e4" | IOSTANDARD=LVCMOS33; +NET "O_LED<7>" LOC = "p4" | IOSTANDARD=LVCMOS33; +NET "O_LED<*>" DRIVE=12 | SLEW=SLOW; +## +## 7 segment display --------------------------------------------------------- +NET "O_ANO_N<0>" LOC = "f17" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<1>" LOC = "h17" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<2>" LOC = "c18" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<3>" LOC = "f15" | IOSTANDARD=LVCMOS33; +NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW; +## +NET "O_SEG_N<0>" LOC = "l18" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<1>" LOC = "f18" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<2>" LOC = "d17" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<3>" LOC = "d16" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<4>" LOC = "g14" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<5>" LOC = "j17" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<6>" LOC = "h14" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<7>" LOC = "c17" | IOSTANDARD=LVCMOS33; +NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW; +## +## CRAM ---------------------------------------------------------------------- +NET "O_MEM_CE_N" LOC = "r6" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_WE_N" LOC = "n7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_OE_N" LOC = "t2" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_BE_N<0>" LOC = "k5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<1>" LOC = "k4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST; +## +NET "O_MEM_ADV_N" LOC = "j4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CLK" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "O_MEM_CRE" LOC = "p7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST; +NET "I_MEM_WAIT" LOC = "f5" | IOSTANDARD=LVCMOS33 | PULLDOWN; +## +NET "O_MEM_ADDR<0>" LOC = "j1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<1>" LOC = "j2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<2>" LOC = "h4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<3>" LOC = "h1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<4>" LOC = "h2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<5>" LOC = "j5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<6>" LOC = "h3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<7>" LOC = "h6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<8>" LOC = "f1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<9>" LOC = "g3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<10>" LOC = "g6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<11>" LOC = "g5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<12>" LOC = "g4" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<13>" LOC = "f2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<14>" LOC = "e1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<15>" LOC = "m5" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<16>" LOC = "e2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<17>" LOC = "c2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<18>" LOC = "c1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<19>" LOC = "d2" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<20>" LOC = "k3" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<21>" LOC = "d1" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<22>" LOC = "k6" | IOSTANDARD=LVCMOS33; +NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST; +## +NET "IO_MEM_DATA<0>" LOC = "l1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<1>" LOC = "l4" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<2>" LOC = "l6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<3>" LOC = "m4" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<4>" LOC = "n5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<5>" LOC = "p1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<6>" LOC = "p2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<7>" LOC = "r2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<8>" LOC = "l3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<9>" LOC = "l5" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<10>" LOC = "m3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<11>" LOC = "m6" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<12>" LOC = "l2" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<13>" LOC = "n4" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<14>" LOC = "r3" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<15>" LOC = "t1" | IOSTANDARD=LVCMOS33; +NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER; +## +## Flash --------------------------------------------------------------------- +NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW; +## Index: nexys2_pins_pmb0_rs232.ucf =================================================================== --- nexys2_pins_pmb0_rs232.ucf (nonexistent) +++ nexys2_pins_pmb0_rs232.ucf (revision 33) @@ -0,0 +1,12 @@ +## $Id: nexys2_pins_pmb0_rs232.ucf 297 2010-05-30 20:10:16Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-05-28 295 1.0 Initial version +## +## Pmod connector B top / usage RS232 for FTDI USB serport ------------------- +## +NET "O_FUSP_RTS_N" LOC = "m13" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; +NET "I_FUSP_CTS_N" LOC = "r18" | IOSTANDARD=LVCMOS33 | PULLDOWN; +NET "I_FUSP_RXD" LOC = "r15" | IOSTANDARD=LVCMOS33 | PULLUP; +NET "O_FUSP_TXD" LOC = "t17" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW; Index: . =================================================================== --- . (nonexistent) +++ . (revision 33)
. Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.