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  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.7/rtl/bplib/nexys4
    from Rev 30 to Rev 33
    ↔ Reverse comparison
  •

Rev 30 → Rev 33

/tb/tb_nexys4.vhd
0,0 → 1,207
-- $Id: tb_nexys4.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4 - sim
-- Description: Test bench for nexys4 (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_nexys4_core
-- serport/serport_master
-- nexys4_aif [UUT]
--
-- To test: generic, any nexys4_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
 
entity tb_nexys4 is
end tb_nexys4;
 
architecture sim of tb_nexys4 is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
 
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
 
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
 
UUT : nexys4_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
 
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
 
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
 
end sim;
/tb/tb_nexys4.vbom
0,0 → 1,25
# Not meant for direct top level usage. Used with
# tb_nexys4_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_nexys4_core.vbom
../../../vlib/serport/serport_master.vbom
${nexys4_aif := nexys4_dummy.vbom}
# design
tb_nexys4.vhd
@top:tb_nexys4
/tb/tb_nexys4_cram.vhd
0,0 → 1,233
-- $Id: tb_nexys4_cram.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_cram - sim
-- Description: Test bench for nexys4 (base+cram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_nexys4_core
-- serport/serport_master
-- nexys4_cram_aif [UUT]
-- vlib/parts/micron/mt45w8mw16b
--
-- To test: generic, any nexys4_cram_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
 
entity tb_nexys4_cram is
end tb_nexys4_cram;
 
architecture sim of tb_nexys4_cram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
 
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
 
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
 
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
 
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
 
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
 
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
 
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
 
TBCORE : tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
 
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
 
UUT : nexys4_cram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
MEM : entity work.mt45w8mw16b
port map (
CLK => O_MEM_CLK,
CE_N => O_MEM_CE_N,
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADV_N => O_MEM_ADV_N,
CRE => O_MEM_CRE,
MWAIT => I_MEM_WAIT,
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA
);
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
 
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
 
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
 
end sim;
/tb/tb_nexys4_cram.vbom
0,0 → 1,26
# Not meant for direct top level usage. Used with
# tb_nexys4_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4lib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_nexys4_core.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/serport_master.vbom
${nexys4_cram_aif := nexys4_cram_dummy.vbom}
# design
tb_nexys4_cram.vhd
@top:tb_nexys4_cram
/tb/tb_nexys4_core.vhd
0,0 → 1,77
-- $Id: tb_nexys4_core.vhd 643 2015-02-07 17:41:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_core - sim
-- Description: Test bench for nexys4 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any nexys4 target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3_core)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
 
entity tb_nexys4_core is
port (
I_SWI : out slv16; -- n4 switches
I_BTN : out slv5; -- n4 buttons
I_BTNRST_N : out slbit -- n4 reset button
);
end tb_nexys4_core;
 
architecture sim of tb_nexys4_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
signal R_BTNRST : slbit := '0';
 
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
 
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
R_BTNRST <= to_x01(SB_DATA(5));
end if;
end if;
end process proc_simbus;
 
I_SWI <= R_SWI;
I_BTN <= R_BTN;
I_BTNRST_N <= not R_BTNRST;
end sim;
/tb/tb_nexys4_core.vbom
0,0 → 1,9
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
# design
tb_nexys4_core.vhd
/tb/Makefile.ise
0,0 → 1,39
# $Id: Makefile.ise 648 2015-02-20 20:16:21Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-02-06 643 1.2 add nexys4_cram_aif
# 2015-02-01 641 1.1 drop nexys4_fusp_aif
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2013-09-21 534 1.0 Initial version
#
EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy
#
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
endif
#
/tb/.cvsignore
0,0 → 1,5
tb_nexys4_dummy
tb_nexys4_cram_dummy
nexys4_dummy.ucf
nexys4_cram_dummy.ucf
*.dep_ucf_cpp
/tb
tb Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_nexys4_dummy +tb_nexys4_cram_dummy +nexys4_dummy.ucf +nexys4_cram_dummy.ucf +*.dep_ucf_cpp Index: nexys4_pins.xdc =================================================================== --- nexys4_pins.xdc (nonexistent) +++ nexys4_pins.xdc (revision 33) @@ -0,0 +1,132 @@ +# -*- tcl -*- +# $Id: nexys4_pins.xdc 643 2015-02-07 17:41:53Z mueller $ +# +# Pin locks for Nexys 4 core functionality +# - USB UART +# - human I/O (switches, buttons, leds, display) +# +# Revision History: +# Date Rev Version Comment +# 2015-02-06 643 1.3 factor out cram +# 2015-02-01 641 1.2 separate I_BTNRST_N +# 2015-01-31 640 1.1 fix RTS/CTS +# 2013-10-12 539 1.0 Initial version (converted from ucf) +# + +# config setup -------------------------------------------------------------- +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] + +# clocks -- in bank 35 ------------------------------------------------------ +set_property PACKAGE_PIN e3 [get_ports {I_CLK100}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}] + +# +# USB UART Interface -- in bank 35 ------------------------------------------ +set_property PACKAGE_PIN c4 [get_ports {I_RXD}] +set_property PACKAGE_PIN d4 [get_ports {O_TXD}] +set_property PACKAGE_PIN d3 [get_ports {O_RTS_N}] +set_property PACKAGE_PIN e5 [get_ports {I_CTS_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD O_RTS_N I_CTS_N}] +set_property DRIVE 12 [get_ports {O_TXD O_RTS_N}] +set_property SLEW SLOW [get_ports {O_TXD O_RTS_N}] + +# +# switches -- in bank 34 ---------------------------------------------------- +set_property PACKAGE_PIN u9 [get_ports {I_SWI[0]}] +set_property PACKAGE_PIN u8 [get_ports {I_SWI[1]}] +set_property PACKAGE_PIN r7 [get_ports {I_SWI[2]}] +set_property PACKAGE_PIN r6 [get_ports {I_SWI[3]}] +set_property PACKAGE_PIN r5 [get_ports {I_SWI[4]}] +set_property PACKAGE_PIN v7 [get_ports {I_SWI[5]}] +set_property PACKAGE_PIN v6 [get_ports {I_SWI[6]}] +set_property PACKAGE_PIN v5 [get_ports {I_SWI[7]}] +set_property PACKAGE_PIN u4 [get_ports {I_SWI[8]}] +set_property PACKAGE_PIN v2 [get_ports {I_SWI[9]}] +set_property PACKAGE_PIN u2 [get_ports {I_SWI[10]}] +set_property PACKAGE_PIN t3 [get_ports {I_SWI[11]}] +set_property PACKAGE_PIN t1 [get_ports {I_SWI[12]}] +set_property PACKAGE_PIN r3 [get_ports {I_SWI[13]}] +set_property PACKAGE_PIN p3 [get_ports {I_SWI[14]}] +set_property PACKAGE_PIN p4 [get_ports {I_SWI[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}] + +# +# buttons -- in bank 15+14 -------------------------------------------------- +# sequence: clockwise(U-R-D-L) - middle - reset +set_property PACKAGE_PIN f15 [get_ports {I_BTN[0]}] +set_property PACKAGE_PIN r10 [get_ports {I_BTN[1]}] +set_property PACKAGE_PIN v10 [get_ports {I_BTN[2]}] +set_property PACKAGE_PIN t16 [get_ports {I_BTN[3]}] +set_property PACKAGE_PIN e16 [get_ports {I_BTN[4]}] +set_property PACKAGE_PIN c12 [get_ports {I_BTNRST_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_BTNRST_N}] + +# +# LEDs -- in bank 34 -------------------------------------------------------- +set_property PACKAGE_PIN t8 [get_ports {O_LED[0]}] +set_property PACKAGE_PIN v9 [get_ports {O_LED[1]}] +set_property PACKAGE_PIN r8 [get_ports {O_LED[2]}] +set_property PACKAGE_PIN t6 [get_ports {O_LED[3]}] +set_property PACKAGE_PIN t5 [get_ports {O_LED[4]}] +set_property PACKAGE_PIN t4 [get_ports {O_LED[5]}] +set_property PACKAGE_PIN u7 [get_ports {O_LED[6]}] +set_property PACKAGE_PIN u6 [get_ports {O_LED[7]}] +set_property PACKAGE_PIN v4 [get_ports {O_LED[8]}] +set_property PACKAGE_PIN u3 [get_ports {O_LED[9]}] +set_property PACKAGE_PIN v1 [get_ports {O_LED[10]}] +set_property PACKAGE_PIN r1 [get_ports {O_LED[11]}] +set_property PACKAGE_PIN p5 [get_ports {O_LED[12]}] +set_property PACKAGE_PIN u1 [get_ports {O_LED[13]}] +set_property PACKAGE_PIN r2 [get_ports {O_LED[14]}] +set_property PACKAGE_PIN p2 [get_ports {O_LED[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}] +set_property DRIVE 12 [get_ports {O_LED[*]}] +set_property SLEW SLOW [get_ports {O_LED[*]}] + +# +# RGB-LEDs -- in bank 15+34+35 ---------------------------------------------- +set_property PACKAGE_PIN k5 [get_ports {O_RGBLED0[0]}] +set_property PACKAGE_PIN f13 [get_ports {O_RGBLED0[1]}] +set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[2]}] +set_property PACKAGE_PIN k6 [get_ports {O_RGBLED1[0]}] +set_property PACKAGE_PIN h6 [get_ports {O_RGBLED1[1]}] +set_property PACKAGE_PIN l16 [get_ports {O_RGBLED1[2]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] +set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}] + +# +# 7 segment display -- in bank 34 ------------------------------------------- +set_property PACKAGE_PIN n6 [get_ports {O_ANO_N[0]}] +set_property PACKAGE_PIN m6 [get_ports {O_ANO_N[1]}] +set_property PACKAGE_PIN m3 [get_ports {O_ANO_N[2]}] +set_property PACKAGE_PIN n5 [get_ports {O_ANO_N[3]}] +set_property PACKAGE_PIN n2 [get_ports {O_ANO_N[4]}] +set_property PACKAGE_PIN n4 [get_ports {O_ANO_N[5]}] +set_property PACKAGE_PIN l1 [get_ports {O_ANO_N[6]}] +set_property PACKAGE_PIN m1 [get_ports {O_ANO_N[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_ANO_N[*]}] +set_property DRIVE 12 [get_ports {O_ANO_N[*]}] +set_property SLEW SLOW [get_ports {O_ANO_N[*]}] +# +set_property PACKAGE_PIN l3 [get_ports {O_SEG_N[0]}] +set_property PACKAGE_PIN n1 [get_ports {O_SEG_N[1]}] +set_property PACKAGE_PIN l5 [get_ports {O_SEG_N[2]}] +set_property PACKAGE_PIN l4 [get_ports {O_SEG_N[3]}] +set_property PACKAGE_PIN k3 [get_ports {O_SEG_N[4]}] +set_property PACKAGE_PIN m2 [get_ports {O_SEG_N[5]}] +set_property PACKAGE_PIN l6 [get_ports {O_SEG_N[6]}] +set_property PACKAGE_PIN m4 [get_ports {O_SEG_N[7]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_SEG_N[*]}] +set_property DRIVE 12 [get_ports {O_SEG_N[*]}] +set_property SLEW SLOW [get_ports {O_SEG_N[*]}] +# Index: nexys4_pclk.xdc =================================================================== --- nexys4_pclk.xdc (nonexistent) +++ nexys4_pclk.xdc (revision 33) @@ -0,0 +1,13 @@ +# $Id: nexys4_pclk.xdc 640 2015-02-01 09:56:53Z mueller $ +# +# Copyright 2015- by Walter F.J. Mueller +# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory +# +# Primary clocks for Nexys4 +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 639 1.0 Initial version +# + +create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100] Index: nexys4lib.vhd =================================================================== --- nexys4lib.vhd (nonexistent) +++ nexys4lib.vhd (revision 33) @@ -0,0 +1,81 @@ +-- $Id: nexys4lib.vhd 643 2015-02-07 17:41:53Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: nexys4lib +-- Description: Nexys 4 components +-- +-- Dependencies: - +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.2 factor out memory, add nexys4_cram_aif +-- 2015-02-01 641 1.1 drop nexys4_fusp_aif; separate I_BTNRST_N +-- 2013-09-21 534 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package nexys4lib is + +component nexys4_aif is -- NEXYS 4, abstract iface, base + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end component; + +component nexys4_cram_aif is -- NEXYS 4, abstract iface, base+cram + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end component; + +end package nexys4lib; Index: nexys4_pins_cram.xdc =================================================================== --- nexys4_pins_cram.xdc (nonexistent) +++ nexys4_pins_cram.xdc (revision 33) @@ -0,0 +1,90 @@ +# -*- tcl -*- +# $Id: nexys4_pins_cram.xdc 643 2015-02-07 17:41:53Z mueller $ +# +# Pin locks for Nexys 4 cram +# +# Revision History: +# Date Rev Version Comment +# 2015-02-06 643 1.0 Initial version (derived from nexys4_pins.xdc) +# + +# CRAM -- in bank 14+15 ----------------------------------------------------- +set_property PACKAGE_PIN l18 [get_ports {O_MEM_CE_N}] +set_property PACKAGE_PIN r11 [get_ports {O_MEM_WE_N}] +set_property PACKAGE_PIN h14 [get_ports {O_MEM_OE_N}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +set_property DRIVE 12 [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +set_property SLEW FAST [get_ports {O_MEM_CE_N O_MEM_WE_N O_MEM_OE_N}] +# +set_property PACKAGE_PIN j15 [get_ports {O_MEM_BE_N[0]}] +set_property PACKAGE_PIN j13 [get_ports {O_MEM_BE_N[1]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_BE_N[*]}] +set_property DRIVE 12 [get_ports {O_MEM_BE_N[*]}] +set_property SLEW FAST [get_ports {O_MEM_BE_N[*]}] +# +set_property PACKAGE_PIN t13 [get_ports {O_MEM_ADV_N}] +set_property PACKAGE_PIN t15 [get_ports {O_MEM_CLK}] +set_property PACKAGE_PIN j14 [get_ports {O_MEM_CRE}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}] +set_property DRIVE 12 [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}] +set_property SLEW FAST [get_ports {O_MEM_ADV_N O_MEM_CLK O_MEM_CRE}] + +# +set_property PACKAGE_PIN t14 [get_ports {I_MEM_WAIT}] +set_property IOSTANDARD LVCMOS33 [get_ports {I_MEM_WAIT}] + +# +set_property PACKAGE_PIN j18 [get_ports {O_MEM_ADDR[0]}] +set_property PACKAGE_PIN h17 [get_ports {O_MEM_ADDR[1]}] +set_property PACKAGE_PIN h15 [get_ports {O_MEM_ADDR[2]}] +set_property PACKAGE_PIN j17 [get_ports {O_MEM_ADDR[3]}] +set_property PACKAGE_PIN h16 [get_ports {O_MEM_ADDR[4]}] +set_property PACKAGE_PIN k15 [get_ports {O_MEM_ADDR[5]}] +set_property PACKAGE_PIN k13 [get_ports {O_MEM_ADDR[6]}] +set_property PACKAGE_PIN n15 [get_ports {O_MEM_ADDR[7]}] +set_property PACKAGE_PIN v16 [get_ports {O_MEM_ADDR[8]}] +set_property PACKAGE_PIN u14 [get_ports {O_MEM_ADDR[9]}] +set_property PACKAGE_PIN v14 [get_ports {O_MEM_ADDR[10]}] +set_property PACKAGE_PIN v12 [get_ports {O_MEM_ADDR[11]}] +set_property PACKAGE_PIN p14 [get_ports {O_MEM_ADDR[12]}] +set_property PACKAGE_PIN u16 [get_ports {O_MEM_ADDR[13]}] +set_property PACKAGE_PIN r15 [get_ports {O_MEM_ADDR[14]}] +set_property PACKAGE_PIN n14 [get_ports {O_MEM_ADDR[15]}] +set_property PACKAGE_PIN n16 [get_ports {O_MEM_ADDR[16]}] +set_property PACKAGE_PIN m13 [get_ports {O_MEM_ADDR[17]}] +set_property PACKAGE_PIN v17 [get_ports {O_MEM_ADDR[18]}] +set_property PACKAGE_PIN u17 [get_ports {O_MEM_ADDR[19]}] +set_property PACKAGE_PIN t10 [get_ports {O_MEM_ADDR[20]}] +set_property PACKAGE_PIN m16 [get_ports {O_MEM_ADDR[21]}] +set_property PACKAGE_PIN u13 [get_ports {O_MEM_ADDR[22]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {O_MEM_ADDR[*]}] +set_property DRIVE 8 [get_ports {O_MEM_ADDR[*]}] +set_property SLEW FAST [get_ports {O_MEM_ADDR[*]}] + +# +set_property PACKAGE_PIN r12 [get_ports {IO_MEM_DATA[0]}] +set_property PACKAGE_PIN t11 [get_ports {IO_MEM_DATA[1]}] +set_property PACKAGE_PIN u12 [get_ports {IO_MEM_DATA[2]}] +set_property PACKAGE_PIN r13 [get_ports {IO_MEM_DATA[3]}] +set_property PACKAGE_PIN u18 [get_ports {IO_MEM_DATA[4]}] +set_property PACKAGE_PIN r17 [get_ports {IO_MEM_DATA[5]}] +set_property PACKAGE_PIN t18 [get_ports {IO_MEM_DATA[6]}] +set_property PACKAGE_PIN r18 [get_ports {IO_MEM_DATA[7]}] +set_property PACKAGE_PIN f18 [get_ports {IO_MEM_DATA[8]}] +set_property PACKAGE_PIN g18 [get_ports {IO_MEM_DATA[9]}] +set_property PACKAGE_PIN g17 [get_ports {IO_MEM_DATA[10]}] +set_property PACKAGE_PIN m18 [get_ports {IO_MEM_DATA[11]}] +set_property PACKAGE_PIN m17 [get_ports {IO_MEM_DATA[12]}] +set_property PACKAGE_PIN p18 [get_ports {IO_MEM_DATA[13]}] +set_property PACKAGE_PIN n17 [get_ports {IO_MEM_DATA[14]}] +set_property PACKAGE_PIN p17 [get_ports {IO_MEM_DATA[15]}] + +set_property IOSTANDARD LVCMOS33 [get_ports {IO_MEM_DATA[*]}] +set_property DRIVE 8 [get_ports {IO_MEM_DATA[*]}] +set_property SLEW SLOW [get_ports {IO_MEM_DATA[*]}] +set_property KEEPER true [get_ports {IO_MEM_DATA[*]}] +# Index: nexys4_setup.tcl =================================================================== --- nexys4_setup.tcl (nonexistent) +++ nexys4_setup.tcl (revision 33) @@ -0,0 +1,4 @@ +# $ Id: $ +# +set rvtb_part "xc7a100tcsg324-1" +set rvtb_board "nexys4" Index: . =================================================================== --- . (nonexistent) +++ . (revision 33)
. Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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