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  • This comparison shows the changes necessary to convert path 
    /w11/tags/w11a_V0.7/rtl/make_viv
    from Rev 29 to Rev 33
    ↔ Reverse comparison
  •

Rev 29 → Rev 33

/generic_ghdl.mk
0,0 → 1,38
# $Id: generic_ghdl.mk 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-14 646 1.0 Initial version (cloned from make_ise)
#
GHDLIEEE = --ieee=synopsys
GHDLXLPATH = $(XTWV_PATH)/ghdl
#
% : %.vbom
vbomconv --ghdl_i $<
vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $<
#
# rules for _[o]sim to use 'virtual' [o]sim vbom's (derived from _ssim)
#
%_osim : %_ssim.vbom
vbomconv --ghdl_i $*_osim.vbom
vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_osim.vbom
#
%.dep_ghdl: %.vbom
vbomconv --dep_ghdl $< > $@
#
include $(RETROBASE)/rtl/make_ise/dontincdep.mk
#
.PHONY: ghdl_clean ghdl_tmp_clean
#
ghdl_clean: ghdl_tmp_clean
rm -f $(EXE_all)
rm -f $(EXE_all:%=%_[so]sim)
rm -f cext_*.o
#
ghdl_tmp_clean:
find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f
rm -f work-obj93.cf
#
/viv_default_basys3.mk
0,0 → 1,16
# $Id: viv_default_basys3.mk 637 2015-01-25 18:36:40Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-01-25 637 1.0 Initial version
#---
#
# Setup for Digilent Basys3
#
# setup default board and part
#
VIV_BOARD_SETUP = $(RETROBASE)/rtl/bplib/basys3/basys3_setup.tcl
#
/viv_tools_build.tcl
0,0 → 1,163
# $Id: viv_tools_build.tcl 649 2015-02-21 21:10:16Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-21 649 1.1 add 2014.4 specific setups
# 2015-02-14 646 1.0 Initial version
#
 
#
# --------------------------------------------------------------------
#
proc rvtb_trace_cmd {cmd} {
puts "# $cmd"
eval $cmd
return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_locate_setup_file {stem} {
set name "${stem}_setup.tcl"
if {[file readable $name]} {return $name}
set name "$../{stem}_setup.tcl"
if {[file readable $name]} {return $name}
return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_mv_file {src dst} {
if {[file readable $src]} {
exec mv $src $dst
} else {
puts "rvtb_mv_file-W: file '$src' not existing"
}
return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_cp_file {src dst} {
if {[file readable $src]} {
exec cp -p $src $dst
} else {
puts "rvtb_cp_file-W: file '$src' not existing"
}
return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_build_check {step} {
get_msg_config -rules
return ""
}
 
#
# --------------------------------------------------------------------
#
proc rvtb_default_build {stem step} {
# general setups
switch [version -short] {
"2014.4" {
# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
# set here to avoid messages during create_project
set_msg_config -suppress -id {Board 49-26}
}
}
 
# read setup
set setup_file [rvtb_locate_setup_file $stem]
if {$setup_file ne ""} {source -notrace $setup_file}
 
# Create project
rvtb_trace_cmd "create_project project_mflow ./project_mflow"
# Setup project properties
set obj [get_projects project_mflow]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" $::rvtb_part $obj
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "VHDL" $obj
# version dependent setups
switch [version -short] {
"2014.4" {
# suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
# repeated here because create_project apparently clears msg_config
set_msg_config -suppress -id {Board 49-26}
}
}
 
# Setup filesets
set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"]
eval $vbom_prj
update_compile_order -fileset sources_1
 
# some handy variables
set path_runs "project_mflow/project_mflow.runs"
set path_syn1 "${path_runs}/synth_1"
set path_imp1 "${path_runs}/impl_1"
 
# build: synthesize
rvtb_trace_cmd "launch_runs synth_1"
rvtb_trace_cmd "wait_on_run synth_1"
 
rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log"
rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt"
rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp"
 
if {$step eq "syn"} {return [rvtb_build_check $step]}
 
# build: implement
rvtb_trace_cmd "launch_runs impl_1"
rvtb_trace_cmd "wait_on_run impl_1"
 
rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log"
 
rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt"
rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt"
rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt"
rvtb_cp_file "$path_imp1/${stem}_clock_utilization_placed.rpt" \
"${stem}_pla_clk.rpt"
rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \
"${stem}_rou_tim.rpt"
rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \
"${stem}_pla_util.rpt"
rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt"
rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \
"${stem}_pla_cset.rpt"
rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt"
 
rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp"
rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp"
rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp"
 
# additional reports
rvtb_trace_cmd "open_run impl_1"
report_utilization -file "${stem}_rou_util.rpt"
report_utilization -hierarchical -file "${stem}_rou_util_h.rpt"
report_datasheet -file "${stem}_rou_ds.rpt"
 
if {$step eq "imp"} {return [rvtb_build_check $step]}
 
# build: bitstream
rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream"
rvtb_trace_cmd "wait_on_run impl_1"
 
rvtb_mv_file "$path_imp1/${stem}.bit" "."
rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log"
 
return [rvtb_build_check $step]
}
 
/viv_tools_model.tcl
0,0 → 1,38
# $Id: viv_tools_model.tcl 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-14 646 1.0 Initial version
#
 
#
# --------------------------------------------------------------------
#
proc rvtb_default_model {stem mode} {
 
switch $mode {
ssim {
open_checkpoint "${stem}_syn.dcp"
write_vhdl -mode funcsim -force "${stem}_ssim.vhd"
}
 
osim {
open_checkpoint "${stem}_opt.dcp"
write_vhdl -mode funcsim -force "${stem}_osim.vhd"
}
 
tsim {
open_checkpoint "${stem}_rou.dcp"
write_verilog -mode timesim -force -sdf_anno true "${stem}_tsim.v"
write_sdf -mode timesim -force "${stem}_tsim.sdf"
}
 
default {
error "-E: bad mode: $mode";
}
}
return "";
}
/viv_init.tcl
0,0 → 1,13
# $Id: viv_init.tcl 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-14 646 1.0 Initial version
# 2015-01-25 637 0.1 First draft
#
source -notrace "$::env(RETROBASE)/rtl/make_viv/viv_tools_build.tcl"
source -notrace "$::env(RETROBASE)/rtl/make_viv/viv_tools_config.tcl"
source -notrace "$::env(RETROBASE)/rtl/make_viv/viv_tools_model.tcl"
/viv_default_nexys4.mk
0,0 → 1,16
# $Id: viv_default_nexys4.mk 640 2015-02-01 09:56:53Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-01-25 639 1.0 Initial version
#---
#
# Setup for Digilent Nexys4
#
# setup default board and part
#
VIV_BOARD_SETUP = $(RETROBASE)/rtl/bplib/nexys4/nexys4_setup.tcl
#
/viv_default_build.tcl
0,0 → 1,12
# $Id: viv_default_build.tcl 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-14 646 1.0 Initial version
# 2015-01-25 637 0.1 First draft
#
 
rvtb_default_build [lindex $::argv 0] [lindex $::argv 1]
/viv_default_model.tcl
0,0 → 1,11
# $Id: viv_default_model.tcl 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-14 646 1.0 Initial version
#
 
rvtb_default_model [lindex $::argv 0] [lindex $::argv 1]
/viv_tools_config.tcl
0,0 → 1,29
# $Id: viv_tools_config.tcl 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-14 646 1.0 Initial version
#
 
#
# --------------------------------------------------------------------
#
proc rvtb_default_config {stem} {
# open and connect to hardware server
open_hw
connect_hw_server
 
# connect to target
open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0]
 
# setup bitfile
set_property PROGRAM.FILE "${stem}.bit" [lindex [get_hw_devices] 0]
 
# and configure FPGA
program_hw_devices [lindex [get_hw_devices] 0]
 
return "";
}
/generic_vivado.mk
0,0 → 1,142
# $Id: generic_vivado.mk 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-15 646 1.0 Initial version
# 2015-01-25 637 0.1 First draft
#---
#
# check that part is defined
#
ifndef VIV_BOARD_SETUP
$(error VIV_BOARD_SETUP is not defined)
endif
#
# ensure that default tools and flows are defined
#
ifndef VIV_INIT
VIV_INIT = $(RETROBASE)/rtl/make_viv/viv_init.tcl
endif
ifndef VIV_BUILD_FLOW
VIV_BUILD_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_build.tcl
endif
ifndef VIV_CONFIG_FLOW
VIV_CONFIG_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_config.tcl
endif
ifndef VIV_MODEL_FLOW
VIV_MODEL_FLOW = $(RETROBASE)/rtl/make_viv/viv_default_model.tcl
endif
#
# $@ first target
# $< first dependency
# $* stem in rule match
#
# when chaining, don't delete 'expensive' intermediate files:
.SECONDARY :
#
# Synthesize + Implement -> generate bit file
# input: %.vbom vbom project description
# output: %.bit
#
%.bit : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* bit
#
# Configure FPGA with vivado hardware server
# input: %.bit
# output: .PHONY
#
%.vconfig : %.bit
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_BOARD_SETUP} \
-source ${VIV_CONFIG_FLOW} \
-tclargs $*
#
# Partial Synthesize + Implement -> generate dcp for model generation
#
%_syn.dcp : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* syn
%_opt.dcp %_rou.dcp : %.vbom
rm -rf project_mflow
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_BOARD_SETUP} \
-source ${VIV_BUILD_FLOW} \
-tclargs $* imp
#
# Post-synthesis functional simulation model (Vhdl/Unisim)
# input: %_syn.dcp
# output: %_ssim.vhd
#
%_ssim.vhd : %_syn.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* ssim
#
# Post-optimization functional simulation model (Vhdl/Unisim)
# input: %_opt.dcp
# output: %_osim.vhd
#
%_osim.vhd : %_opt.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* osim
#
# Post-routing timing simulation model (Verilog/Simprim)
# input: %_rou.dcp
# output: %_tsim.v
# %_tsim.sdf
#
%_tsim.v %_tsim.sdf : %_rou.dcp
xtwv vivado -mode batch \
-source ${VIV_INIT} \
-source ${VIV_MODEL_FLOW} \
-tclargs $* tsim
#
# vivado project quick starter
#
.PHONY : vivado
vivado :
xtwv vivado -mode gui project_mflow/project_mflow.xpr
 
#
# generate dep_vsyn files from vbom
#
%.dep_vsyn: %.vbom
vbomconv --dep_vsyn $< > $@
 
#
# Cleanup
#
include $(RETROBASE)/rtl/make_viv/dontincdep.mk
#
.PHONY : viv_clean viv_tmp_clean
#
viv_clean: viv_tmp_clean
rm -f *.bit
rm -f *.dcp
rm -f *.jou
rm -f *.log
rm -f *.rpt
rm -f *_[so]sim.vhd
rm -f *_tsim.v
rm -f *_tsim.sdf
#
viv_tmp_clean:
rm -rf ./project_mflow
#
/dontincdep.mk
0,0 → 1,24
# $Id: dontincdep.mk 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2013-01-27 477 1.0 Initial version
#
# DONTINCDEP controls whether dependency files are included. Set it if
# any of the 'clean' type targets is involved
#
ifneq ($(findstring clean, $(MAKECMDGOALS)),)
DONTINCDEP = 1
endif
ifneq ($(findstring realclean, $(MAKECMDGOALS)),)
DONTINCDEP = 1
endif
ifneq ($(findstring distclean, $(MAKECMDGOALS)),)
DONTINCDEP = 1
endif
ifdef DONTINCDEP
$(info DONTINCDEP set, *.dep files not included)
endif
/viv_default_config.tcl
0,0 → 1,12
# $Id: viv_default_config.tcl 646 2015-02-15 12:04:55Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2015-02-14 646 1.0 Initial version
# 2015-01-25 637 0.1 First draft
#
 
rvtb_default_config [lindex $::argv 0]
/.
. Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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