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/w11/tags/w11a_V0.7/rtl/sys_gen/tst_fx2loop
- from Rev 29 to Rev 33
- ↔ Reverse comparison
Rev 29 → Rev 33
/tst_fx2loop_hiomap.vhd
0,0 → 1,194
-- $Id: tst_fx2loop_hiomap.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tst_fx2loop_hiomap - syn |
-- Description: default human I/O mapper |
-- |
-- Dependencies: - |
-- Test bench: - |
-- |
-- Target Devices: generic |
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage |
-- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout |
-- 2011-12-26 445 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- Usage of Switches, Buttons, LEDs: |
-- |
-- BTN(3) -- unused -- |
-- (2) -- unused -- |
-- (1) -- unused -- |
-- (0) reset state [!! decoded by top level design !!] |
-- |
-- SWI(7:5) select display |
-- (4) -- unused -- |
-- (3) throttle |
-- (2) tx2blast |
-- (1:0) mode 00 idle |
-- 01 rxblast |
-- 10 txblast |
-- 11 loop |
-- |
-- LED(7) MONI.fifo_ep4 |
-- (6) MONI.fifo_ep6 |
-- (5) MONI.fifo_ep8 |
-- (4) MONI.flag_ep4_empty |
-- (3) MONI.flag_ep4_almost |
-- (2) MONI.flag_ep6_full |
-- (1) MONI.flag_ep6_almost |
-- (0) rxsecnt > 0 (sequence error) |
-- |
-- DSP data as selected by SWI(7:5) |
-- 000 -> rxsecnt |
-- 001 -> -- unused -- (display ffff) |
-- 010 -> rxcnt.l |
-- 011 -> rxcnt.h |
-- 100 -> txcnt.l |
-- 101 -> txcnt.h |
-- 110 -> tx2cnt.l |
-- 111 -> tx2cnt.h |
-- |
-- DP(3) FX2_TXBUSY (shows tx back preasure) |
-- (2) FX2_MONI.slwr (shows tx activity) |
-- (1) FX2_RXHOLD (shows rx back preasure) |
-- (0) FX2_MONI.slrd (shows rx activity) |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.fx2lib.all; |
use work.tst_fx2looplib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity tst_fx2loop_hiomap is -- default human I/O mapper |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
HIO_CNTL : out hio_cntl_type; -- tester controls from hio |
HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio |
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio |
SWI : in slv8; -- switch settings |
BTN : in slv4; -- button settings |
LED : out slv8; -- led data |
DSP_DAT : out slv16; -- display data |
DSP_DP : out slv4 -- display decimal points |
); |
end tst_fx2loop_hiomap; |
|
architecture syn of tst_fx2loop_hiomap is |
|
type regs_type is record |
dspdat : slv16; -- display data |
dummy : slbit; -- <remove when 2nd signal added...> |
end record regs_type; |
|
constant regs_init : regs_type := ( |
(others=>'0'), -- dspdat |
'0' |
); |
|
signal R_REGS : regs_type := regs_init; -- state registers |
signal N_REGS : regs_type := regs_init; -- next value state regs |
|
begin |
|
proc_regs: process (CLK) |
begin |
|
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
|
end process proc_regs; |
|
proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN) |
|
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
|
variable icntl : hio_cntl_type := hio_cntl_init; |
variable iled : slv8 := (others=>'0'); |
variable idat : slv16 := (others=>'0'); |
variable idp : slv4 := (others=>'0'); |
|
begin |
|
r := R_REGS; |
n := R_REGS; |
|
icntl := hio_cntl_init; |
iled := (others=>'0'); |
idat := (others=>'0'); |
idp := (others=>'0'); |
|
-- setup tester controls |
|
icntl.mode := SWI(1 downto 0); |
icntl.tx2blast := SWI(2); |
icntl.throttle := SWI(3); |
|
-- setup leds |
iled(7) := FX2_MONI.fifo_ep4; |
iled(6) := FX2_MONI.fifo_ep6; |
iled(5) := FX2_MONI.fifo_ep8; |
iled(4) := FX2_MONI.flag_ep4_empty; |
iled(3) := FX2_MONI.flag_ep4_almost; |
iled(2) := FX2_MONI.flag_ep6_full; |
iled(1) := FX2_MONI.flag_ep6_almost; |
if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if; |
|
-- setup display data |
|
case SWI(7 downto 5) is |
when "000" => idat := HIO_STAT.rxsecnt; |
when "001" => idat := (others=>'1'); |
when "010" => idat := HIO_STAT.rxcnt(15 downto 0); |
when "011" => idat := HIO_STAT.rxcnt(31 downto 16); |
when "100" => idat := HIO_STAT.txcnt(15 downto 0); |
when "101" => idat := HIO_STAT.txcnt(31 downto 16); |
when "110" => idat := HIO_STAT.tx2cnt(15 downto 0); |
when "111" => idat := HIO_STAT.tx2cnt(31 downto 16); |
when others => null; |
end case; |
n.dspdat := idat; |
|
-- setup display decimal points |
|
idp(3) := HIO_STAT.txbusy; -- tx back preasure |
idp(2) := FX2_MONI.slwr; -- tx activity |
idp(1) := HIO_STAT.rxhold; -- rx back preasure |
idp(0) := FX2_MONI.slrd; -- rx activity |
|
N_REGS <= n; |
|
HIO_CNTL <= icntl; |
LED <= iled; |
DSP_DAT <= r.dspdat; |
DSP_DP <= idp; |
|
end process proc_next; |
|
end syn; |
/tst_fx2loop.vhd
0,0 → 1,267
-- $Id: tst_fx2loop.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: tst_fx2loop - syn |
-- Description: simple stand-alone tester for fx2lib components |
-- |
-- Dependencies: comlib/byte2word |
-- comlib/word2byte |
-- Test bench: - |
-- |
-- Target Devices: generic |
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2013-04-24 510 1.0.1 fix sensitivity list of proc_next |
-- 2012-01-15 453 1.0 Initial version |
-- 2011-12-26 445 0.5 First draft |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.comlib.all; |
use work.fx2lib.all; |
use work.tst_fx2looplib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity tst_fx2loop is -- tester for fx2lib components |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
CE_MSEC : in slbit; -- msec pulse |
HIO_CNTL : in hio_cntl_type; -- humanio controls |
HIO_STAT : out hio_stat_type; -- humanio status |
FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor |
RXDATA : in slv8; -- receiver data out |
RXVAL : in slbit; -- receiver data valid |
RXHOLD : out slbit; -- receiver data hold |
TXDATA : out slv8; -- transmit data in |
TXENA : out slbit; -- transmit data enable |
TXBUSY : in slbit; -- transmit busy |
TX2DATA : out slv8; -- transmit 2 data in |
TX2ENA : out slbit; -- transmit 2 data enable |
TX2BUSY : in slbit -- transmit 2 busy |
); |
end tst_fx2loop; |
|
architecture syn of tst_fx2loop is |
|
type regs_type is record |
rxdata : slv16; -- next rx word |
txdata : slv16; -- next tx word |
tx2data : slv16; -- next tx2 word |
rxsecnt : slv16; -- rx sequence error counter |
rxcnt : slv32; -- rx word counter |
txcnt : slv32; -- tx word counter |
tx2cnt : slv32; -- tx2 word counter |
rxthrottle : slbit; -- rx throttle flag |
end record regs_type; |
|
constant regs_init : regs_type := ( |
(others=>'0'), -- rxdata |
(others=>'0'), -- txdata |
(others=>'0'), -- tx2data |
(others=>'0'), -- rxsecnt |
(others=>'0'), -- rxcnt |
(others=>'0'), -- txcnt |
(others=>'0'), -- tx2cnt |
'0' -- rxthrottle |
); |
|
signal R_REGS : regs_type := regs_init; -- state registers |
signal N_REGS : regs_type := regs_init; -- next value state regs |
|
signal RXWDATA : slv16 := (others=>'0'); |
signal RXWVAL : slbit := '0'; |
signal RXWHOLD : slbit := '0'; |
signal RXODD : slbit := '0'; |
|
signal TXWDATA : slv16 := (others=>'0'); |
signal TXWENA : slbit := '0'; |
signal TXWBUSY : slbit := '0'; |
signal TXODD : slbit := '0'; |
signal TX2WDATA : slv16 := (others=>'0'); |
signal TX2WENA : slbit := '0'; |
signal TX2WBUSY : slbit := '0'; |
signal TX2ODD : slbit := '0'; |
|
signal RXHOLD_L : slbit := '0'; -- local copy of out port signal |
signal TXENA_L : slbit := '0'; -- local copy of out port signal |
signal TX2ENA_L : slbit := '0'; -- local copy of out port signal |
signal CNTL_RESET_L : slbit := '0'; -- local copy of out port signal |
|
begin |
|
CNTL_RESET_L <= '0'; -- so far unused |
|
RXB2W : byte2word |
port map ( |
CLK => CLK, |
RESET => CNTL_RESET_L, |
DI => RXDATA, |
ENA => RXVAL, |
BUSY => RXHOLD_L, |
DO => RXWDATA, |
VAL => RXWVAL, |
HOLD => RXWHOLD, |
ODD => RXODD |
); |
|
TX1W2B : word2byte |
port map ( |
CLK => CLK, |
RESET => CNTL_RESET_L, |
DI => TXWDATA, |
ENA => TXWENA, |
BUSY => TXWBUSY, |
DO => TXDATA, |
VAL => TXENA_L, |
HOLD => TXBUSY, |
ODD => TXODD |
); |
|
TX2W2B : word2byte |
port map ( |
CLK => CLK, |
RESET => CNTL_RESET_L, |
DI => TX2WDATA, |
ENA => TX2WENA, |
BUSY => TX2WBUSY, |
DO => TX2DATA, |
VAL => TX2ENA_L, |
HOLD => TX2BUSY, |
ODD => TX2ODD |
); |
|
proc_regs: process (CLK) |
begin |
|
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
|
end process proc_regs; |
|
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, FX2_MONI, |
RXWDATA, RXWVAL, TXWBUSY, TX2WBUSY, |
RXHOLD_L, TXBUSY, TX2BUSY) |
|
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
|
variable irxwhold : slbit := '1'; |
variable itxwena : slbit := '0'; |
variable itxwdata : slv16 := (others=>'0'); |
variable itx2wena : slbit := '0'; |
|
begin |
r := R_REGS; |
n := R_REGS; |
|
irxwhold := '1'; |
itxwena := '0'; |
itxwdata := RXWDATA; |
itx2wena := '0'; |
|
if HIO_CNTL.throttle = '1' then |
if CE_MSEC = '1' then |
n.rxthrottle := not r.rxthrottle; |
end if; |
else |
n.rxthrottle := '0'; |
end if; |
|
|
case HIO_CNTL.mode is |
when c_mode_idle => |
null; |
|
when c_mode_rxblast => |
if RXWVAL='1' and r.rxthrottle='0' then |
irxwhold := '0'; |
if RXWDATA /= r.rxdata then |
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1); |
end if; |
n.rxdata := slv(unsigned(RXWDATA) + 1); |
end if; |
|
when c_mode_txblast => |
itxwdata := r.txdata; |
if TXWBUSY = '0' then |
itxwena := '1'; |
n.txdata := slv(unsigned(r.txdata) + 1); |
end if; |
irxwhold := '0'; |
|
when c_mode_loop => |
itxwdata := RXWDATA; |
if RXWVAL='1' and r.rxthrottle='0' and TXWBUSY = '0' then |
irxwhold := '0'; |
itxwena := '1'; |
end if; |
|
when others => null; |
end case; |
|
if HIO_CNTL.tx2blast = '1' then |
if TX2WBUSY = '0' then |
itx2wena := '1'; |
n.tx2data := slv(unsigned(r.tx2data) + 1); |
end if; |
end if; |
|
if RXWVAL='1' and irxwhold='0' then |
n.rxcnt := slv(unsigned(r.rxcnt) + 1); |
end if; |
|
if itxwena = '1' then |
n.txcnt := slv(unsigned(r.txcnt) + 1); |
end if; |
|
if itx2wena = '1' then |
n.tx2cnt := slv(unsigned(r.tx2cnt) + 1); |
end if; |
|
N_REGS <= n; |
|
RXWHOLD <= irxwhold; |
TXWENA <= itxwena; |
TXWDATA <= itxwdata; |
TX2WENA <= itx2wena; |
TX2WDATA <= r.tx2data; |
|
HIO_STAT.rxhold <= RXHOLD_L; |
HIO_STAT.txbusy <= TXBUSY; |
HIO_STAT.tx2busy <= TX2BUSY; |
HIO_STAT.rxsecnt <= r.rxsecnt; |
HIO_STAT.rxcnt <= r.rxcnt; |
HIO_STAT.txcnt <= r.txcnt; |
HIO_STAT.tx2cnt <= r.tx2cnt; |
|
end process proc_next; |
|
RXHOLD <= RXHOLD_L; |
TXENA <= TXENA_L; |
TX2ENA <= TX2ENA_L; |
|
end syn; |
/nexys2/sys_tst_fx2loop_n2.vhd
0,0 → 1,316
-- $Id: sys_tst_fx2loop_n2.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: sys_tst_fx2loop_n2 - syn |
-- Description: test of Cypress EZ-USB FX2 controller |
-- |
-- Dependencies: vlib/xlib/dcm_sfs |
-- vlib/genlib/clkdivce |
-- bpgen/sn_humanio |
-- tst_fx2loop_hiomap |
-- tst_fx2loop |
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"] |
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"] |
-- bplib/nxcramlib/nx_cram_dummy |
-- |
-- Test bench: - |
-- |
-- Target Devices: generic |
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz |
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100 |
-- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100 |
-- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-01-25 638 1.1.1 retire fx2_2fifoctl_as |
-- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers |
-- 2011-12-26 445 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.xlib.all; |
use work.genlib.all; |
use work.bpgenlib.all; |
use work.tst_fx2looplib.all; |
use work.fx2lib.all; |
use work.nxcramlib.all; |
use work.sys_conf.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity sys_tst_fx2loop_n2 is -- top level |
-- implements nexys2_aif + fx2 pins |
port ( |
I_CLK50 : in slbit; -- 50 MHz board clock |
I_RXD : in slbit; -- receive data (board view) |
O_TXD : out slbit; -- transmit data (board view) |
I_SWI : in slv8; -- n2 switches |
I_BTN : in slv4; -- n2 buttons |
O_LED : out slv8; -- n2 leds |
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) |
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) |
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) |
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) |
O_MEM_WE_N : out slbit; -- cram: write enable (act.low) |
O_MEM_OE_N : out slbit; -- cram: output enable (act.low) |
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) |
O_MEM_CLK : out slbit; -- cram: clock |
O_MEM_CRE : out slbit; -- cram: command register enable |
I_MEM_WAIT : in slbit; -- cram: mem wait |
O_MEM_ADDR : out slv23; -- cram: address lines |
IO_MEM_DATA : inout slv16; -- cram: data lines |
O_FLA_CE_N : out slbit; -- flash ce.. (act.low) |
I_FX2_IFCLK : in slbit; -- fx2: interface clock |
O_FX2_FIFO : out slv2; -- fx2: fifo address |
I_FX2_FLAG : in slv4; -- fx2: fifo flags |
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) |
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) |
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) |
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) |
IO_FX2_DATA : inout slv8 -- fx2: data lines |
); |
end sys_tst_fx2loop_n2; |
|
architecture syn of sys_tst_fx2loop_n2 is |
|
signal CLK : slbit := '0'; |
signal RESET : slbit := '0'; |
|
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal SWI : slv8 := (others=>'0'); |
signal BTN : slv4 := (others=>'0'); |
signal LED : slv8 := (others=>'0'); |
signal DSP_DAT : slv16 := (others=>'0'); |
signal DSP_DP : slv4 := (others=>'0'); |
|
signal LED_MAP : slv8 := (others=>'0'); |
|
signal HIO_CNTL : hio_cntl_type := hio_cntl_init; |
signal HIO_STAT : hio_stat_type := hio_stat_init; |
|
signal FX2_RXDATA : slv8 := (others=>'0'); |
signal FX2_RXVAL : slbit := '0'; |
signal FX2_RXHOLD : slbit := '0'; |
signal FX2_RXAEMPTY : slbit := '0'; |
signal FX2_TXDATA : slv8 := (others=>'0'); |
signal FX2_TXENA : slbit := '0'; |
signal FX2_TXBUSY : slbit := '0'; |
signal FX2_TXAFULL : slbit := '0'; |
signal FX2_TX2DATA : slv8 := (others=>'0'); |
signal FX2_TX2ENA : slbit := '0'; |
signal FX2_TX2BUSY : slbit := '1'; |
signal FX2_TX2AFULL : slbit := '0'; |
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
DCM : dcm_sfs |
generic map ( |
CLKFX_DIVIDE => sys_conf_clkfx_divide, |
CLKFX_MULTIPLY => sys_conf_clkfx_multiply, |
CLKIN_PERIOD => 20.0) |
port map ( |
CLKIN => I_CLK50, |
CLKFX => CLK, |
LOCKED => open |
); |
|
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 7, -- good for up to 127 MHz ! |
USECDIV => sys_conf_clksys_mhz, |
MSECDIV => 1000) |
port map ( |
CLK => CLK, |
CE_USEC => CE_USEC, |
CE_MSEC => CE_MSEC |
); |
|
HIO : sn_humanio |
generic map ( |
DEBOUNCE => sys_conf_hio_debounce) |
port map ( |
CLK => CLK, |
RESET => '0', |
CE_MSEC => CE_MSEC, |
SWI => SWI, |
BTN => BTN, |
LED => LED, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP, |
I_SWI => I_SWI, |
I_BTN => I_BTN, |
O_LED => O_LED, |
O_ANO_N => O_ANO_N, |
O_SEG_N => O_SEG_N |
); |
|
RESET <= BTN(0); -- BTN(0) will reset tester !! |
|
HIOMAP : tst_fx2loop_hiomap |
port map ( |
CLK => CLK, |
RESET => RESET, |
HIO_CNTL => HIO_CNTL, |
HIO_STAT => HIO_STAT, |
FX2_MONI => FX2_MONI, |
SWI => SWI, |
BTN => BTN, |
LED => LED_MAP, |
DSP_DAT => DSP_DAT, |
DSP_DP => DSP_DP |
); |
|
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA, |
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL) |
begin |
|
if SWI(4) = '1' then |
LED(7) <= '0'; |
LED(6) <= '0'; |
LED(5) <= FX2_TX2BUSY; |
LED(4) <= FX2_TX2ENA; |
LED(3) <= FX2_TXBUSY; |
LED(2) <= FX2_TXENA; |
LED(1) <= FX2_RXHOLD; |
LED(0) <= FX2_RXVAL; |
else |
LED <= LED_MAP; |
end if; |
|
end process proc_led; |
|
|
TST : tst_fx2loop |
port map ( |
CLK => CLK, |
RESET => RESET, |
CE_MSEC => CE_MSEC, |
HIO_CNTL => HIO_CNTL, |
HIO_STAT => HIO_STAT, |
FX2_MONI => FX2_MONI, |
RXDATA => FX2_RXDATA, |
RXVAL => FX2_RXVAL, |
RXHOLD => FX2_RXHOLD, |
TXDATA => FX2_TXDATA, |
TXENA => FX2_TXENA, |
TXBUSY => FX2_TXBUSY, |
TX2DATA => FX2_TX2DATA, |
TX2ENA => FX2_TX2ENA, |
TX2BUSY => FX2_TX2BUSY |
); |
|
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate |
CNTL : fx2_2fifoctl_ic |
generic map ( |
RXFAWIDTH => 5, |
TXFAWIDTH => 5, |
PETOWIDTH => sys_conf_fx2_petowidth, |
CCWIDTH => sys_conf_fx2_ccwidth, |
RXAEMPTY_THRES => 1, |
TXAFULL_THRES => 1) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RXDATA => FX2_RXDATA, |
RXVAL => FX2_RXVAL, |
RXHOLD => FX2_RXHOLD, |
RXAEMPTY => FX2_RXAEMPTY, |
TXDATA => FX2_TXDATA, |
TXENA => FX2_TXENA, |
TXBUSY => FX2_TXBUSY, |
TXAFULL => FX2_TXAFULL, |
MONI => FX2_MONI, |
I_FX2_IFCLK => I_FX2_IFCLK, |
O_FX2_FIFO => O_FX2_FIFO, |
I_FX2_FLAG => I_FX2_FLAG, |
O_FX2_SLRD_N => O_FX2_SLRD_N, |
O_FX2_SLWR_N => O_FX2_SLWR_N, |
O_FX2_SLOE_N => O_FX2_SLOE_N, |
O_FX2_PKTEND_N => O_FX2_PKTEND_N, |
IO_FX2_DATA => IO_FX2_DATA |
); |
end generate FX2_CNTL_IC; |
|
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate |
CNTL : fx2_3fifoctl_ic |
generic map ( |
RXFAWIDTH => 5, |
TXFAWIDTH => 5, |
PETOWIDTH => sys_conf_fx2_petowidth, |
CCWIDTH => sys_conf_fx2_ccwidth, |
RXAEMPTY_THRES => 1, |
TXAFULL_THRES => 1, |
TX2AFULL_THRES => 1) |
port map ( |
CLK => CLK, |
RESET => RESET, |
RXDATA => FX2_RXDATA, |
RXVAL => FX2_RXVAL, |
RXHOLD => FX2_RXHOLD, |
RXAEMPTY => FX2_RXAEMPTY, |
TXDATA => FX2_TXDATA, |
TXENA => FX2_TXENA, |
TXBUSY => FX2_TXBUSY, |
TXAFULL => FX2_TXAFULL, |
TX2DATA => FX2_TX2DATA, |
TX2ENA => FX2_TX2ENA, |
TX2BUSY => FX2_TX2BUSY, |
TX2AFULL => FX2_TX2AFULL, |
MONI => FX2_MONI, |
I_FX2_IFCLK => I_FX2_IFCLK, |
O_FX2_FIFO => O_FX2_FIFO, |
I_FX2_FLAG => I_FX2_FLAG, |
O_FX2_SLRD_N => O_FX2_SLRD_N, |
O_FX2_SLWR_N => O_FX2_SLWR_N, |
O_FX2_SLOE_N => O_FX2_SLOE_N, |
O_FX2_PKTEND_N => O_FX2_PKTEND_N, |
IO_FX2_DATA => IO_FX2_DATA |
); |
end generate FX2_CNTL_IC3; |
|
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy |
port map ( |
O_MEM_CE_N => O_MEM_CE_N, |
O_MEM_BE_N => O_MEM_BE_N, |
O_MEM_WE_N => O_MEM_WE_N, |
O_MEM_OE_N => O_MEM_OE_N, |
O_MEM_ADV_N => O_MEM_ADV_N, |
O_MEM_CLK => O_MEM_CLK, |
O_MEM_CRE => O_MEM_CRE, |
I_MEM_WAIT => I_MEM_WAIT, |
O_MEM_ADDR => O_MEM_ADDR, |
IO_MEM_DATA => IO_MEM_DATA |
); |
|
O_FLA_CE_N <= '1'; -- keep Flash memory disabled |
|
O_TXD <= I_RXD; -- loop-back in serial port... |
|
end syn; |
|
/nexys2/sys_tst_fx2loop_n2.vbom
0,0 → 1,28
# this is the vbom for the 'generic' top level entity |
# to be referenced in the vbom's of the specific systems |
# ./ic/sys_tst_fx2loop_ic_n2 |
# ./ic3/sys_tst_fx2loop_ic3_n2 |
# |
# libs |
../../../vlib/slvtypes.vhd |
../../../vlib/xlib/xlib.vhd |
../../../vlib/genlib/genlib.vhd |
../../../bplib/bpgen/bpgenlib.vbom |
../tst_fx2looplib.vbom |
../../../bplib/fx2lib/fx2lib.vhd |
../../../bplib/nxcramlib/nxcramlib.vhd |
${sys_conf} |
# components |
[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom |
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/sn_humanio.vbom |
../tst_fx2loop_hiomap.vbom |
../tst_fx2loop.vbom |
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom |
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom |
../../../bplib/nxcramlib/nx_cram_dummy.vbom |
# design |
sys_tst_fx2loop_n2.vhd |
## no @ucf_cpp |
|
/nexys2/ic/sys_conf.vhd
0,0 → 1,58
-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: sys_conf |
-- Description: Definitions for sys_tst_fx2loop_ic_n2 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2012-01-15 453 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
|
package sys_conf is |
|
constant sys_conf_clkfx_divide : positive := 1; |
constant sys_conf_clkfx_multiply : positive := 2; |
|
constant sys_conf_fx2_type : string := "ic2"; |
|
-- dummy values defs for generic parameters of as controller |
constant sys_conf_fx2_rdpwldelay : positive := 1; |
constant sys_conf_fx2_rdpwhdelay : positive := 1; |
constant sys_conf_fx2_wrpwldelay : positive := 1; |
constant sys_conf_fx2_wrpwhdelay : positive := 1; |
constant sys_conf_fx2_flagdelay : positive := 1; |
|
-- pktend timer setting |
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation) |
constant sys_conf_fx2_petowidth : positive := 10; |
|
constant sys_conf_fx2_ccwidth : positive := 5; |
|
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers |
|
-- derived constants |
|
constant sys_conf_clksys : integer := |
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply; |
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; |
|
end package sys_conf; |
/nexys2/ic/Makefile
0,0 → 1,30
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2012-01-15 453 1.0 Initial version |
# |
# |
VBOM_all = $(wildcard *.vbom) |
BIT_all = $(VBOM_all:.vbom=.bit) |
# |
include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk |
FX2_FILE = nexys2_jtag_2fifo_ic.ihx |
# |
.PHONY : all clean |
# |
all : $(BIT_all) |
# |
clean : ise_clean |
rm -f $(VBOM_all:.vbom=.ucf) |
# |
#---- |
# |
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk |
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
include $(VBOM_all:.vbom=.dep_ghdl) |
endif |
# |
/nexys2/ic/sys_tst_fx2loop_ic_n2.mfset
0,0 → 1,63
# $Id: sys_tst_fx2loop_ic_n2.mfset 453 2012-01-15 17:51:18Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Mux is complete : default of case is discarded |
|
Unconnected output port 'LOCKED' of component 'dcm_sfs' |
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' |
|
Node <TST/R_REGS.tx2data_\d*> of sequential type is unconnected |
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected |
Node <HIO/HIO/DEB.DEB_BTN/R_REGS\..*_\d> of sequential type is unconnected |
Node <TST/TX2W2B/R_REGS.datl_\d*> of sequential type is unconnected |
Node <TST/TX2W2B/R_REGS.dath_\d*> of sequential type is unconnected |
|
Signal <FX2_TX2DATA> is assigned but never used |
|
Input <BTN> is never used |
Input <SWI<4>> is never used |
Input <FX2_MONI.pktend> is never used |
Input <FX2_MONI.slrd> is never used |
Input <FX2_MONI.slwr> is never used |
Input <I_MEM_WAIT> is never used |
|
Signal <TXODD> is assigned but never used |
Signal <TX2ODD> is assigned but never used |
Signal <RXODD> is assigned but never used |
|
# |
# ---------------------------------------------------------------------------- |
[tra] |
INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP |
The Offset constraint .*, is specified without a duration |
|
# |
# ---------------------------------------------------------------------------- |
[map] |
The signal <I_MEM_WAIT_IBUF> is incomplete |
The signal <I_BTN<1>_IBUF> is incomplete |
The signal <I_BTN<2>_IBUF> is incomplete |
The signal <I_BTN<3>_IBUF> is incomplete |
INFO:.* |
|
# |
# ---------------------------------------------------------------------------- |
[par] |
A clock IOB / clock component pair have been found that are not placed at |
The Offset constraint .*, is specified without a duration |
The signal I_MEM_WAIT_IBUF has no load |
The signal I_BTN<1>_IBUF has no load |
The signal I_BTN<2>_IBUF has no load |
The signal I_BTN<3>_IBUF has no load |
There are 4 loadless signals in this design |
|
# |
# ---------------------------------------------------------------------------- |
[bgn] |
Spartan-3 1200E and 1600E devices do not support bitstream |
To achieve optimal frequency synthesis performance .* consult |
The signal <I_MEM_WAIT_IBUF> is incomplete |
The signal <I_BTN<1>_IBUF> is incomplete |
The signal <I_BTN<2>_IBUF> is incomplete |
The signal <I_BTN<3>_IBUF> is incomplete |
/nexys2/ic/sys_tst_fx2loop_ic_n2.ucf_cpp
0,0 → 1,15
## $Id: sys_tst_fx2loop_ic_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $ |
## |
## Revision History: |
## Date Rev Version Comment |
## 2011-12-26 445 1.0 Initial version |
## |
|
NET "I_CLK50" TNM_NET = "I_CLK50"; |
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; |
OFFSET = IN 10 ns BEFORE "I_CLK50"; |
OFFSET = OUT 20 ns AFTER "I_CLK50"; |
|
#include "bplib/nexys2/nexys2_pins.ucf" |
#include "bplib/nexys2/nexys2_pins_fx2.ucf" |
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" |
/nexys2/ic/sys_tst_fx2loop_ic_n2.vbom
0,0 → 1,8
# conf |
sys_conf = sys_conf.vhd |
# libs |
# components |
# design |
../sys_tst_fx2loop_n2.vbom |
@ucf_cpp: sys_tst_fx2loop_ic_n2.ucf |
@top: sys_tst_fx2loop_n2 |
/nexys2/ic/.cvsignore
0,0 → 1,4
_impactbatch.log |
sys_tst_fx2loop_ic_n2.ucf |
*.dep_ucf_cpp |
*.svf |
nexys2/ic
Property changes :
Added: svn:ignore
## -0,0 +1,37 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_fx2loop_ic_n2.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys2/ic3/sys_conf.vhd
===================================================================
--- nexys2/ic3/sys_conf.vhd (nonexistent)
+++ nexys2/ic3/sys_conf.vhd (revision 33)
@@ -0,0 +1,58 @@
+-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
+--
+-- Copyright 2012- by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
+-- Revision History:
+-- Date Rev Version Comment
+-- 2012-01-15 453 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clkfx_divide : positive := 1;
+ constant sys_conf_clkfx_multiply : positive := 2;
+
+ constant sys_conf_fx2_type : string := "ic3";
+
+ -- dummy values defs for generic parameters of as controller
+ constant sys_conf_fx2_rdpwldelay : positive := 1;
+ constant sys_conf_fx2_rdpwhdelay : positive := 1;
+ constant sys_conf_fx2_wrpwldelay : positive := 1;
+ constant sys_conf_fx2_wrpwhdelay : positive := 1;
+ constant sys_conf_fx2_flagdelay : positive := 1;
+
+ -- pktend timer setting
+ -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
+ constant sys_conf_fx2_petowidth : positive := 10;
+
+ constant sys_conf_fx2_ccwidth : positive := 5;
+
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+
+ -- derived constants
+
+ constant sys_conf_clksys : integer :=
+ (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
+ constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+end package sys_conf;
Index: nexys2/ic3/Makefile
===================================================================
--- nexys2/ic3/Makefile (nonexistent)
+++ nexys2/ic3/Makefile (revision 33)
@@ -0,0 +1,30 @@
+# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2012-01-15 453 1.0 Initial version
+#
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk
+FX2_FILE = nexys2_jtag_3fifo_ic.ihx
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
+include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+endif
+#
Index: nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom
===================================================================
--- nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (nonexistent)
+++ nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (revision 33)
@@ -0,0 +1,8 @@
+# conf
+sys_conf = sys_conf.vhd
+# libs
+# components
+# design
+../sys_tst_fx2loop_n2.vbom
+@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf
+@top: sys_tst_fx2loop_n2
Index: nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset
===================================================================
--- nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (nonexistent)
+++ nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (revision 33)
@@ -0,0 +1,58 @@
+# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $
+#
+# ----------------------------------------------------------------------------
+[xst]
+INFO:.*Mux is complete : default of case is discarded
+
+Unconnected output port 'LOCKED' of component 'dcm_sfs'
+Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
+
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+
+Input is never used
+Input > is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+
+Signal is assigned but never used
+Signal is assigned but never used
+Signal is assigned but never used
+
+#
+# ----------------------------------------------------------------------------
+[tra]
+INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
+The Offset constraint .*, is specified without a duration
+
+#
+# ----------------------------------------------------------------------------
+[map]
+The signal is incomplete
+The signal _IBUF> is incomplete
+The signal _IBUF> is incomplete
+The signal _IBUF> is incomplete
+INFO:.*
+
+#
+# ----------------------------------------------------------------------------
+[par]
+A clock IOB / clock component pair have been found that are not placed at
+The Offset constraint .*, is specified without a duration
+The signal I_MEM_WAIT_IBUF has no load
+The signal I_BTN<1>_IBUF has no load
+The signal I_BTN<2>_IBUF has no load
+The signal I_BTN<3>_IBUF has no load
+There are 4 loadless signals in this design
+
+#
+# ----------------------------------------------------------------------------
+[bgn]
+Spartan-3 1200E and 1600E devices do not support bitstream
+To achieve optimal frequency synthesis performance .* consult
+The signal is incomplete
+The signal _IBUF> is incomplete
+The signal _IBUF> is incomplete
+The signal _IBUF> is incomplete
Index: nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp
===================================================================
--- nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (nonexistent)
+++ nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (revision 33)
@@ -0,0 +1,15 @@
+## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2011-12-26 445 1.0 Initial version
+##
+
+NET "I_CLK50" TNM_NET = "I_CLK50";
+TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK50";
+OFFSET = OUT 20 ns AFTER "I_CLK50";
+
+#include "bplib/nexys2/nexys2_pins.ucf"
+#include "bplib/nexys2/nexys2_pins_fx2.ucf"
+#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"
Index: nexys2/ic3/.cvsignore
===================================================================
--- nexys2/ic3/.cvsignore (nonexistent)
+++ nexys2/ic3/.cvsignore (revision 33)
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_fx2loop_ic3_n2.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys2/ic3
===================================================================
--- nexys2/ic3 (nonexistent)
+++ nexys2/ic3 (revision 33)
nexys2/ic3
Property changes :
Added: svn:ignore
## -0,0 +1,37 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_fx2loop_ic3_n2.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys2
===================================================================
--- nexys2 (nonexistent)
+++ nexys2 (revision 33)
nexys2
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: nexys3/sys_tst_fx2loop_n3.vhd
===================================================================
--- nexys3/sys_tst_fx2loop_n3.vhd (nonexistent)
+++ nexys3/sys_tst_fx2loop_n3.vhd (revision 33)
@@ -0,0 +1,330 @@
+-- $Id: sys_tst_fx2loop_n3.vhd 638 2015-01-25 22:01:38Z mueller $
+--
+-- Copyright 2012-2015 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name: sys_tst_fx2loop_n3 - syn
+-- Description: test of Cypress EZ-USB FX2 controller
+--
+-- Dependencies: vlib/xlib/s6_cmt_sfs
+-- vlib/genlib/clkdivce
+-- bpgen/sn_humanio
+-- tst_fx2loop_hiomap
+-- tst_fx2loop
+-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
+-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
+-- bplib/nxcramlib/nx_cram_dummy
+--
+-- Test bench: -
+--
+-- Target Devices: generic
+-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
+--
+-- Synthesized (xst):
+-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
+-- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150
+-- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175
+-- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100
+--
+-- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150
+-- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175
+-- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100
+--
+-- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100
+-- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100
+--
+-- Revision History:
+-- Date Rev Version Comment
+-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
+-- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk
+-- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.tst_fx2looplib.all;
+use work.fx2lib.all;
+use work.nxcramlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_fx2loop_n3 is -- top level
+ -- implements nexys3_aif + fx2 pins
+ port (
+ I_CLK100 : in slbit; -- 100 MHz clock
+ I_RXD : in slbit; -- receive data (board view)
+ O_TXD : out slbit; -- transmit data (board view)
+ I_SWI : in slv8; -- n3 switches
+ I_BTN : in slv5; -- n3 buttons
+ O_LED : out slv8; -- n3 leds
+ O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
+ O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
+ O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
+ O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
+ O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
+ O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
+ O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
+ O_MEM_CLK : out slbit; -- cram: clock
+ O_MEM_CRE : out slbit; -- cram: command register enable
+ I_MEM_WAIT : in slbit; -- cram: mem wait
+ O_MEM_ADDR : out slv23; -- cram: address lines
+ IO_MEM_DATA : inout slv16; -- cram: data lines
+ O_PPCM_CE_N : out slbit; -- ppcm: ...
+ O_PPCM_RST_N : out slbit; -- ppcm: ...
+ I_FX2_IFCLK : in slbit; -- fx2: interface clock
+ O_FX2_FIFO : out slv2; -- fx2: fifo address
+ I_FX2_FLAG : in slv4; -- fx2: fifo flags
+ O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
+ O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
+ O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
+ O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
+ IO_FX2_DATA : inout slv8 -- fx2: data lines
+ );
+end sys_tst_fx2loop_n3;
+
+architecture syn of sys_tst_fx2loop_n3 is
+
+ signal CLK : slbit := '0';
+ signal RESET : slbit := '0';
+
+ signal CE_USEC : slbit := '0';
+ signal CE_MSEC : slbit := '0';
+
+ signal SWI : slv8 := (others=>'0');
+ signal BTN : slv5 := (others=>'0');
+ signal LED : slv8 := (others=>'0');
+ signal DSP_DAT : slv16 := (others=>'0');
+ signal DSP_DP : slv4 := (others=>'0');
+
+ signal LED_MAP : slv8 := (others=>'0');
+
+ signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
+ signal HIO_STAT : hio_stat_type := hio_stat_init;
+
+ signal FX2_RXDATA : slv8 := (others=>'0');
+ signal FX2_RXVAL : slbit := '0';
+ signal FX2_RXHOLD : slbit := '0';
+ signal FX2_RXAEMPTY : slbit := '0';
+ signal FX2_TXDATA : slv8 := (others=>'0');
+ signal FX2_TXENA : slbit := '0';
+ signal FX2_TXBUSY : slbit := '0';
+ signal FX2_TXAFULL : slbit := '0';
+ signal FX2_TX2DATA : slv8 := (others=>'0');
+ signal FX2_TX2ENA : slbit := '0';
+ signal FX2_TX2BUSY : slbit := '1';
+ signal FX2_TX2AFULL : slbit := '0';
+ signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
+
+begin
+
+ assert (sys_conf_clksys mod 1000000) = 0
+ report "assert sys_conf_clksys on MHz grid"
+ severity failure;
+
+ GEN_CLKSYS : s6_cmt_sfs
+ generic map (
+ VCO_DIVIDE => sys_conf_clksys_vcodivide,
+ VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
+ OUT_DIVIDE => sys_conf_clksys_outdivide,
+ CLKIN_PERIOD => 10.0,
+ CLKIN_JITTER => 0.01,
+ STARTUP_WAIT => false,
+ GEN_TYPE => sys_conf_clksys_gentype)
+ port map (
+ CLKIN => I_CLK100,
+ CLKFX => CLK,
+ LOCKED => open
+ );
+
+ CLKDIV : clkdivce
+ generic map (
+ CDUWIDTH => 8, -- good for up to 255 MHz !
+ USECDIV => sys_conf_clksys_mhz,
+ MSECDIV => 1000)
+ port map (
+ CLK => CLK,
+ CE_USEC => CE_USEC,
+ CE_MSEC => CE_MSEC
+ );
+
+ HIO : sn_humanio
+ generic map (
+ BWIDTH => 5,
+ DEBOUNCE => sys_conf_hio_debounce)
+ port map (
+ CLK => CLK,
+ RESET => '0',
+ CE_MSEC => CE_MSEC,
+ SWI => SWI,
+ BTN => BTN,
+ LED => LED,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP,
+ I_SWI => I_SWI,
+ I_BTN => I_BTN,
+ O_LED => O_LED,
+ O_ANO_N => O_ANO_N,
+ O_SEG_N => O_SEG_N
+ );
+
+ RESET <= BTN(0); -- BTN(0) will reset tester !!
+
+ HIOMAP : tst_fx2loop_hiomap
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ FX2_MONI => FX2_MONI,
+ SWI => SWI,
+ BTN => BTN(3 downto 0),
+ LED => LED_MAP,
+ DSP_DAT => DSP_DAT,
+ DSP_DP => DSP_DP
+ );
+
+ proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
+ FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
+ begin
+
+ if SWI(4) = '1' then
+ LED(7) <= '0';
+ LED(6) <= '0';
+ LED(5) <= FX2_TX2BUSY;
+ LED(4) <= FX2_TX2ENA;
+ LED(3) <= FX2_TXBUSY;
+ LED(2) <= FX2_TXENA;
+ LED(1) <= FX2_RXHOLD;
+ LED(0) <= FX2_RXVAL;
+ else
+ LED <= LED_MAP;
+ end if;
+
+ end process proc_led;
+
+
+ TST : tst_fx2loop
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CE_MSEC => CE_MSEC,
+ HIO_CNTL => HIO_CNTL,
+ HIO_STAT => HIO_STAT,
+ FX2_MONI => FX2_MONI,
+ RXDATA => FX2_RXDATA,
+ RXVAL => FX2_RXVAL,
+ RXHOLD => FX2_RXHOLD,
+ TXDATA => FX2_TXDATA,
+ TXENA => FX2_TXENA,
+ TXBUSY => FX2_TXBUSY,
+ TX2DATA => FX2_TX2DATA,
+ TX2ENA => FX2_TX2ENA,
+ TX2BUSY => FX2_TX2BUSY
+ );
+
+ FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
+ CNTL : fx2_2fifoctl_ic
+ generic map (
+ RXFAWIDTH => 5,
+ TXFAWIDTH => 5,
+ PETOWIDTH => sys_conf_fx2_petowidth,
+ CCWIDTH => sys_conf_fx2_ccwidth,
+ RXAEMPTY_THRES => 1,
+ TXAFULL_THRES => 1)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ RXDATA => FX2_RXDATA,
+ RXVAL => FX2_RXVAL,
+ RXHOLD => FX2_RXHOLD,
+ RXAEMPTY => FX2_RXAEMPTY,
+ TXDATA => FX2_TXDATA,
+ TXENA => FX2_TXENA,
+ TXBUSY => FX2_TXBUSY,
+ TXAFULL => FX2_TXAFULL,
+ MONI => FX2_MONI,
+ I_FX2_IFCLK => I_FX2_IFCLK,
+ O_FX2_FIFO => O_FX2_FIFO,
+ I_FX2_FLAG => I_FX2_FLAG,
+ O_FX2_SLRD_N => O_FX2_SLRD_N,
+ O_FX2_SLWR_N => O_FX2_SLWR_N,
+ O_FX2_SLOE_N => O_FX2_SLOE_N,
+ O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+ IO_FX2_DATA => IO_FX2_DATA
+ );
+ end generate FX2_CNTL_IC;
+
+ FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
+ CNTL : fx2_3fifoctl_ic
+ generic map (
+ RXFAWIDTH => 5,
+ TXFAWIDTH => 5,
+ PETOWIDTH => sys_conf_fx2_petowidth,
+ CCWIDTH => sys_conf_fx2_ccwidth,
+ RXAEMPTY_THRES => 1,
+ TXAFULL_THRES => 1,
+ TX2AFULL_THRES => 1)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ RXDATA => FX2_RXDATA,
+ RXVAL => FX2_RXVAL,
+ RXHOLD => FX2_RXHOLD,
+ RXAEMPTY => FX2_RXAEMPTY,
+ TXDATA => FX2_TXDATA,
+ TXENA => FX2_TXENA,
+ TXBUSY => FX2_TXBUSY,
+ TXAFULL => FX2_TXAFULL,
+ TX2DATA => FX2_TX2DATA,
+ TX2ENA => FX2_TX2ENA,
+ TX2BUSY => FX2_TX2BUSY,
+ TX2AFULL => FX2_TX2AFULL,
+ MONI => FX2_MONI,
+ I_FX2_IFCLK => I_FX2_IFCLK,
+ O_FX2_FIFO => O_FX2_FIFO,
+ I_FX2_FLAG => I_FX2_FLAG,
+ O_FX2_SLRD_N => O_FX2_SLRD_N,
+ O_FX2_SLWR_N => O_FX2_SLWR_N,
+ O_FX2_SLOE_N => O_FX2_SLOE_N,
+ O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+ IO_FX2_DATA => IO_FX2_DATA
+ );
+ end generate FX2_CNTL_IC3;
+
+ SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
+ port map (
+ O_MEM_CE_N => O_MEM_CE_N,
+ O_MEM_BE_N => O_MEM_BE_N,
+ O_MEM_WE_N => O_MEM_WE_N,
+ O_MEM_OE_N => O_MEM_OE_N,
+ O_MEM_ADV_N => O_MEM_ADV_N,
+ O_MEM_CLK => O_MEM_CLK,
+ O_MEM_CRE => O_MEM_CRE,
+ I_MEM_WAIT => I_MEM_WAIT,
+ O_MEM_ADDR => O_MEM_ADDR,
+ IO_MEM_DATA => IO_MEM_DATA
+ );
+
+ O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
+ O_PPCM_RST_N <= '1'; --
+
+ O_TXD <= I_RXD; -- loop-back in serial port...
+
+end syn;
+
Index: nexys3/sys_tst_fx2loop_n3.vbom
===================================================================
--- nexys3/sys_tst_fx2loop_n3.vbom (nonexistent)
+++ nexys3/sys_tst_fx2loop_n3.vbom (revision 33)
@@ -0,0 +1,28 @@
+# this is the vbom for the 'generic' top level entity
+# to be referenced in the vbom's of the specific systems
+# ./ic/sys_tst_fx2loop_ic_n3
+# ./ic3/sys_tst_fx2loop_ic3_n3
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../tst_fx2looplib.vbom
+../../../bplib/fx2lib/fx2lib.vhd
+../../../bplib/nxcramlib/nxcramlib.vhd
+${sys_conf}
+# components
+[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
+[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/sn_humanio.vbom
+../tst_fx2loop_hiomap.vbom
+../tst_fx2loop.vbom
+../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
+../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+# design
+sys_tst_fx2loop_n3.vhd
+## no @ucf_cpp
+
Index: nexys3/ic/sys_conf.vhd
===================================================================
--- nexys3/ic/sys_conf.vhd (nonexistent)
+++ nexys3/ic/sys_conf.vhd (revision 33)
@@ -0,0 +1,63 @@
+-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
+--
+-- Copyright 2012-2013 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
+-- Revision History:
+-- Date Rev Version Comment
+-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
+-- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk
+-- 2012-04-09 461 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clksys_vcodivide : positive := 2;
+ constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
+ constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
+ constant sys_conf_clksys_gentype : string := "DCM";
+
+ constant sys_conf_fx2_type : string := "ic2";
+
+ -- dummy values defs for generic parameters of as controller
+ constant sys_conf_fx2_rdpwldelay : positive := 1;
+ constant sys_conf_fx2_rdpwhdelay : positive := 1;
+ constant sys_conf_fx2_wrpwldelay : positive := 1;
+ constant sys_conf_fx2_wrpwhdelay : positive := 1;
+ constant sys_conf_fx2_flagdelay : positive := 1;
+
+ -- pktend timer setting
+ -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
+ constant sys_conf_fx2_petowidth : positive := 10;
+
+ constant sys_conf_fx2_ccwidth : positive := 5;
+
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+
+ -- derived constants
+
+ constant sys_conf_clksys : integer :=
+ ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
+ sys_conf_clksys_outdivide;
+ constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+end package sys_conf;
Index: nexys3/ic/Makefile
===================================================================
--- nexys3/ic/Makefile (nonexistent)
+++ nexys3/ic/Makefile (revision 33)
@@ -0,0 +1,30 @@
+# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2012-04-09 461 1.0 Initial version
+#
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk
+FX2_FILE = nexys3_jtag_2fifo_ic.ihx
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
+include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+endif
+#
Index: nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp
===================================================================
--- nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp (nonexistent)
+++ nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp (revision 33)
@@ -0,0 +1,48 @@
+## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints
+## 2012-04-09 461 1.0 Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns AFTER "I_CLK100";
+
+## constrain pad->net clock delay
+NET CLK TNM = TNM_CLK;
+TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
+NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
+TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
+
+## constrain async pad->pad delays
+TIMEGRP TG_SLOW_INS = PADS(I_RXD);
+TIMEGRP TG_SLOW_OUTS = PADS(O_TXD);
+TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns;
+
+## FX2 controller specific constraints
+## constrain cdc path in fifos and reset
+TIMESPEC TS_CDC_FIFO =
+ FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*
+ *FIFO/R_REG?_rst?
+ *FIFO/R_REG?_rst?_s)
+ TO FFS(*FIFO/R_REG?_?addr_c*
+ *FIFO/R_REG?_rst?_c
+ *FIFO/R_REG?_rst?_sc)
+ 5 ns DATAPATHONLY;
+
+## constrain cdc path in monitor
+TIMESPEC TS_CDC_FX2MONI = FROM FFS
+ TO FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY;
+
+##
+## std board
+##
+#include "bplib/nexys3/nexys3_pins.ucf"
+##
+## FX2 interface
+##
+#include "bplib/nexys3/nexys3_pins_fx2.ucf"
+#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"
Index: nexys3/ic/.cvsignore
===================================================================
--- nexys3/ic/.cvsignore (nonexistent)
+++ nexys3/ic/.cvsignore (revision 33)
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_fx2loop_ic_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys3/ic/sys_tst_fx2loop_ic_n3.vbom
===================================================================
--- nexys3/ic/sys_tst_fx2loop_ic_n3.vbom (nonexistent)
+++ nexys3/ic/sys_tst_fx2loop_ic_n3.vbom (revision 33)
@@ -0,0 +1,8 @@
+# conf
+sys_conf = sys_conf.vhd
+# libs
+# components
+# design
+../sys_tst_fx2loop_n3.vbom
+@ucf_cpp: sys_tst_fx2loop_ic_n3.ucf
+@top: sys_tst_fx2loop_n3
Index: nexys3/ic
===================================================================
--- nexys3/ic (nonexistent)
+++ nexys3/ic (revision 33)
nexys3/ic
Property changes :
Added: svn:ignore
## -0,0 +1,37 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_fx2loop_ic_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys3/ic3/sys_conf.vhd
===================================================================
--- nexys3/ic3/sys_conf.vhd (nonexistent)
+++ nexys3/ic3/sys_conf.vhd (revision 33)
@@ -0,0 +1,63 @@
+-- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
+--
+-- Copyright 2012-2013 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: sys_conf
+-- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis)
+--
+-- Dependencies: -
+-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
+-- Revision History:
+-- Date Rev Version Comment
+-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
+-- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk
+-- 2012-04-09 461 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+ constant sys_conf_clksys_vcodivide : positive := 2;
+ constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
+ constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
+ constant sys_conf_clksys_gentype : string := "DCM";
+
+ constant sys_conf_fx2_type : string := "ic3";
+
+ -- dummy values defs for generic parameters of as controller
+ constant sys_conf_fx2_rdpwldelay : positive := 1;
+ constant sys_conf_fx2_rdpwhdelay : positive := 1;
+ constant sys_conf_fx2_wrpwldelay : positive := 1;
+ constant sys_conf_fx2_wrpwhdelay : positive := 1;
+ constant sys_conf_fx2_flagdelay : positive := 1;
+
+ -- pktend timer setting
+ -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
+ constant sys_conf_fx2_petowidth : positive := 10;
+
+ constant sys_conf_fx2_ccwidth : positive := 5;
+
+ constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
+
+ -- derived constants
+
+ constant sys_conf_clksys : integer :=
+ ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
+ sys_conf_clksys_outdivide;
+ constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+end package sys_conf;
Index: nexys3/ic3/Makefile
===================================================================
--- nexys3/ic3/Makefile (nonexistent)
+++ nexys3/ic3/Makefile (revision 33)
@@ -0,0 +1,30 @@
+# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2012-04-09 461 1.0 Initial version
+#
+#
+VBOM_all = $(wildcard *.vbom)
+BIT_all = $(VBOM_all:.vbom=.bit)
+#
+include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk
+FX2_FILE = nexys3_jtag_3fifo_ic.ihx
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+ rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
+include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+endif
+#
Index: nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom
===================================================================
--- nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (nonexistent)
+++ nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (revision 33)
@@ -0,0 +1,8 @@
+# conf
+sys_conf = sys_conf.vhd
+# libs
+# components
+# design
+../sys_tst_fx2loop_n3.vbom
+@ucf_cpp: sys_tst_fx2loop_ic3_n3.ucf
+@top: sys_tst_fx2loop_n3
Index: nexys3/ic3/.cvsignore
===================================================================
--- nexys3/ic3/.cvsignore (nonexistent)
+++ nexys3/ic3/.cvsignore (revision 33)
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_fx2loop_ic3_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp
===================================================================
--- nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (nonexistent)
+++ nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (revision 33)
@@ -0,0 +1,20 @@
+## $Id: sys_tst_fx2loop_ic3_n3.ucf_cpp 461 2012-04-09 21:17:54Z mueller $
+##
+## Revision History:
+## Date Rev Version Comment
+## 2012-04-09 461 1.0 Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET = IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns AFTER "I_CLK100";
+
+## std board
+##
+#include "bplib/nexys3/nexys3_pins.ucf"
+##
+## FX2 interface
+##
+#include "bplib/nexys3/nexys3_pins_fx2.ucf"
+#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"
Index: nexys3/ic3
===================================================================
--- nexys3/ic3 (nonexistent)
+++ nexys3/ic3 (revision 33)
nexys3/ic3
Property changes :
Added: svn:ignore
## -0,0 +1,37 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+_impactbatch.log
+sys_tst_fx2loop_ic3_n3.ucf
+*.dep_ucf_cpp
+*.svf
Index: nexys3
===================================================================
--- nexys3 (nonexistent)
+++ nexys3 (revision 33)
nexys3
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: tst_fx2looplib.vhd
===================================================================
--- tst_fx2looplib.vhd (nonexistent)
+++ tst_fx2looplib.vhd (revision 33)
@@ -0,0 +1,109 @@
+-- $Id: tst_fx2looplib.vhd 649 2015-02-21 21:10:16Z mueller $
+--
+-- Copyright 2011-2012 by Walter F.J. Mueller
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name: tst_fx2looplib
+-- Description: Definitions for tst_fx2loop records and helpers
+--
+-- Dependencies: -
+-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
+-- Revision History:
+-- Date Rev Version Comment
+-- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat
+-- 2011-12-26 445 1.0 Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.fx2lib.all;
+
+package tst_fx2looplib is
+
+ constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as
+ constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic
+ constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic
+
+ constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
+ constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
+ constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
+ constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
+
+ type hio_cntl_type is record -- humanio controls
+ mode : slv2; -- mode (idle,(tx|tx)blast,loop)
+ tx2blast : slbit; -- enable tx2 blast
+ throttle : slbit; -- enable 1 msec tx throttling
+ end record hio_cntl_type;
+
+ constant hio_cntl_init : hio_cntl_type := (
+ c_mode_idle, -- mode
+ '0','0' -- tx2blast,throttle
+ );
+
+ type hio_stat_type is record -- humanio status
+ rxhold : slbit; -- rx hold
+ txbusy : slbit; -- tx busy
+ tx2busy : slbit; -- tx2 busy
+ rxsecnt : slv16; -- rx sequence error counter
+ rxcnt : slv32; -- rx word counter
+ txcnt : slv32; -- tx word counter
+ tx2cnt : slv32; -- tx2 word counter
+ end record hio_stat_type;
+
+ constant hio_stat_init : hio_stat_type := (
+ '0','0','0', -- rxhold,txbusy,tx2busy
+ (others=>'0'), -- rxsecnt
+ (others=>'0'), -- rxcnt
+ (others=>'0'), -- txcnt
+ (others=>'0') -- tx2cnt
+ );
+
+-- -------------------------------------
+
+component tst_fx2loop is -- tester for serport components
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ CE_MSEC : in slbit; -- msec pulse
+ HIO_CNTL : in hio_cntl_type; -- humanio controls
+ HIO_STAT : out hio_stat_type; -- humanio status
+ FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
+ RXDATA : in slv8; -- receiver data out
+ RXVAL : in slbit; -- receiver data valid
+ RXHOLD : out slbit; -- receiver data hold
+ TXDATA : out slv8; -- transmit data in
+ TXENA : out slbit; -- transmit data enable
+ TXBUSY : in slbit; -- transmit busy
+ TX2DATA : out slv8; -- transmit 2 data in
+ TX2ENA : out slbit; -- transmit 2 data enable
+ TX2BUSY : in slbit -- transmit 2 busy
+ );
+end component;
+
+component tst_fx2loop_hiomap is -- default human I/O mapper
+ port (
+ CLK : in slbit; -- clock
+ RESET : in slbit; -- reset
+ HIO_CNTL : out hio_cntl_type; -- tester controls from hio
+ HIO_STAT : in hio_stat_type; -- tester status to display by hio
+ FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
+ SWI : in slv8; -- switch settings
+ BTN : in slv4; -- button settings
+ LED : out slv8; -- led data
+ DSP_DAT : out slv16; -- display data
+ DSP_DP : out slv4 -- display decimal points
+ );
+end component;
+
+end package tst_fx2looplib;
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 33)
@@ -0,0 +1,41 @@
+# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-11-08 602 1.3 rename realclean->distclean
+# 2013-01-05 470 1.2 fix LDLIBS (must come after objs)
+# 2012-02-26 458 1.1 add tst_fx2loop_si
+# 2011-12-26 445 1.0 Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+NGC_all = $(VBOM_all:.vbom=.ngc)
+#
+include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk
+#
+.PHONY : all clean distclean
+#
+all : tst_fx2loop tst_fx2loop_si
+#
+clean : ise_clean
+ rm -f tst_fx2loop
+ rm -f tst_fx2loop_si
+#
+distclean :
+ rm -f tst_fx2loop tst_fx2loop_si
+#
+CFLAGS = -Wall -O2 -g
+LDLIBS = -lusb-1.0
+#
+tst_fx2loop : tst_fx2loop.c
+ ${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS}
+tst_fx2loop_si : tst_fx2loop_si.c
+ ${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS}
+#
+#----
+#
+include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_xst)
+endif
+#
Index: tst_fx2loop.c
===================================================================
--- tst_fx2loop.c (nonexistent)
+++ tst_fx2loop.c (revision 33)
@@ -0,0 +1,1045 @@
+/* $Id: tst_fx2loop.c 530 2013-08-09 21:25:04Z mueller $ */
+/*
+ * Copyright 2011-2013 by Walter F.J. Mueller
+ *
+ * This program is free software; you may redistribute and/or modify it under
+ * the terms of the GNU General Public License as published by the Free
+ * Software Foundation, either version 2, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for complete details.
+ *
+ *
+ * Revision History:
+ * Date Rev Version Comment
+ * 2013-08-09 530 2.1.2 -read: write up to 9 nstead of 7 words
+ * 2012-04-09 461 2.1.1 fix loop back code: fix run-down, add pipe drain
+ * 2012-03-24 460 2.1 add message loop back code (preliminary)
+ * 2012-03-10 459 2.0 re-write for asynchronous libusb interface
+ * 2012-02-12 457 1.1 redo argument handling; add -stat and -rndm
+ * 2012-01-15 453 1.0.1 add -tx2blast; fix bug in loop read loop
+ * 2011-12-29 446 1.0 Initial version (only -read/write/loop)
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+static int nsigint = 0;
+static int endpoll = 0;
+static libusb_context* pUsbContext = 0;
+static libusb_device** pUsbDevList = 0;
+static int UsbDevCount = 0;
+static libusb_device_handle* pUsbDevHdl = 0;
+
+static struct pollfd pollfd_fds[16];
+static int pollfd_nfds = 0;
+
+struct dsc_queue {
+ int par_nfrm;
+ int par_nque;
+ double stat_nbuf;
+ double stat_nbyt;
+ double stat_npt;
+ uint16_t cval;
+};
+
+static struct dsc_queue dsc_rx;
+static struct dsc_queue dsc_tx1;
+static struct dsc_queue dsc_tx2;
+
+static int par_nwmsg = 0;
+static int par_nwrndm = 0;
+static int par_stat = 0;
+static int par_trace = 0;
+static int par_nsec = 0;
+
+static int cur_nwmsg = 0;
+static double stat_nmsg = 0.;
+
+static double t_start;
+static int nreq = 0;
+
+static char** argv;
+static int argc;
+static int argi;
+
+
+void usage(FILE* of);
+int get_pint(char* p);
+double get_double(char* p);
+int get_arg_pint(int min, int max, const char* text);
+
+void do_write(uint16_t* buf, int nw);
+void do_read(int ep);
+void do_run();
+void do_stat();
+void usb_claim();
+void usb_release();
+char* usb_strerror(int rc);
+void prt_time(void);
+double get_time(void);
+void bad_syscall_exit(const char* text, int rc);
+void bad_usbcall_exit(const char* text, int rc);
+void bad_transfer_exit(struct libusb_transfer *t, const char* text);
+
+void sigint_handler(int signum)
+{
+ printf("\n");
+ nsigint += 1;
+ if (nsigint > 3) {
+ fprintf(stderr, "tst_fx2loop-F: 3rd ^C, aborting\n");
+ exit(EXIT_FAILURE);
+ }
+ return;
+}
+
+int main(int main_argc, char *main_argv[])
+{
+ argc = main_argc;
+ argv = main_argv;
+ argi = 1;
+
+ int i;
+
+ /* setup ^C handler */
+ struct sigaction new_action;
+
+ new_action.sa_handler = sigint_handler;
+ sigemptyset (&new_action.sa_mask);
+ new_action.sa_flags = 0;
+ sigaction (SIGINT, &new_action, NULL);
+
+ /* capture -help case here */
+ for (i = 1; i < argc; i++) {
+ if (strcmp(argv[i], "-help") == 0) {
+ usage(stdout);
+ return EXIT_SUCCESS;
+ }
+ }
+
+ /* determine usb device path (first arg or from RETRO_FX2_VID/PID */
+ char devbuf[10];
+ char* path = 0;
+
+ if (argc > argi && argv[argi][0] != '-') {
+ path = argv[argi];
+ argi += 1;
+ } else {
+ char* env_vid = getenv("RETRO_FX2_VID");
+ char* env_pid = getenv("RETRO_FX2_PID");
+ if (env_vid && strlen(env_vid) == 4 &&
+ env_pid && strlen(env_pid) == 4) {
+ strncpy(devbuf , env_vid,4);
+ devbuf[4] = ':';
+ strncpy(devbuf+5, env_pid,4);
+ devbuf[9] = 0;
+ path = devbuf;
+ } else {
+ fprintf(stderr,
+ "tst_fx2loop-F: RETRO_FX2_VID/PID not or ill defined\n");
+ return EXIT_FAILURE;
+ }
+ }
+
+ /* init libusb, connect to device */
+ libusb_init(&pUsbContext);
+ libusb_set_debug(pUsbContext, 3);
+ UsbDevCount = libusb_get_device_list(pUsbContext, &pUsbDevList);
+
+ libusb_device* mydev = 0;
+
+ if (strlen(path)==8 && path[0]=='/' && path[4]=='/') {
+ char busnam[4];
+ char devnam[4];
+ strncpy(busnam, path+1, 3);
+ strncpy(devnam, path+5, 3);
+ busnam[3] = 0;
+ devnam[3] = 0;
+
+ char* endptr;
+ uint8_t busnum = strtol(busnam, &endptr, 10);
+ uint8_t devnum = strtol(devnam, &endptr, 10);
+
+ int idev;
+ for (idev=0; idev 0xffff) {
+ nw = 0;
+ break;
+ }
+ argi += 1;
+ buf[nw++] = (uint16_t)val;
+ }
+ if (nw == 0) {
+ fprintf(stderr, "tst_fx2loop-E: bad word list\n");
+ break;
+ }
+ do_write(buf, nw);
+
+ } else if (strcmp(argv[argi],"-read") == 0) {
+ argi += 1;
+ int ep = 6;
+ if (argi < argc) ep = get_pint(argv[argi++]);
+ if (ep != 6 && ep != 8) {
+ fprintf(stderr, "tst_fx2loop-F: bad read endpoint (must be 6 or 8)\n");
+ return EXIT_FAILURE;
+ }
+ do_read(ep);
+
+ } else if (strcmp(argv[argi],"-run") == 0) {
+ argi += 1;
+ if (argi < argc) par_nsec = get_pint(argv[argi++]);
+ if (par_nsec < 0) {
+ fprintf(stderr, "tst_fx2loop-E: bad args for -run\n");
+ break;
+ }
+ do_run();
+ do_stat();
+
+ } else {
+ fprintf(stderr, "tst_fx2loop-F: unknown option %s\n", argv[argi]);
+ usage(stderr);
+ return EXIT_FAILURE;
+ }
+ }
+
+ return EXIT_SUCCESS;
+}
+
+/*--------------------------------------------------------------------------*/
+void usage(FILE* of)
+{
+ fprintf(of, "Usage: tst_fx2loop [dev] [setup-opts...] [action-opts...]\n");
+ fprintf(of, " arguments:\n");
+ fprintf(of, " dev path usb device, either bus/dev or vend:prod\n");
+ fprintf(of, " default is $RETRO_FX2_VID:$RETRO_FX2_VID\n");
+ fprintf(of, " setup options:\n");
+ fprintf(of, " -nbrx nb buffer size (in 512B) for rxblast\n");
+ fprintf(of, " -nqrx nb number of buffers for rxblast\n");
+ fprintf(of, " -nbtx nb buffer size (in 512B) for txblast or loop\n");
+ fprintf(of, " -nqtx nb number of buffers for txblast or loop\n");
+ fprintf(of, " -nbtx2 nb buffer size (in 512B) for tx2blast\n");
+ fprintf(of, " -nqtx2 nb number of buffers for tx2blast\n");
+ fprintf(of, " -nwmsg nw number words for loop test\n");
+ fprintf(of, " -rndm use random length for loop test\n");
+ fprintf(of, " -stat print live stats\n");
+ fprintf(of, " -trace trace usb calls\n");
+ fprintf(of, " action options:\n");
+ fprintf(of, " -write w0 w1 ... write list of words to endpoint 4\n");
+ fprintf(of, " -read ep read from endpoint ep\n");
+ fprintf(of, " -run ns run tests for nw seconds\n");
+}
+
+/*--------------------------------------------------------------------------*/
+
+int get_pint(char* p)
+{
+ char *endptr;
+ long num = 0;
+
+ num = strtol(p, &endptr, 0);
+ if ((endptr && *endptr) || num < 0 || num > INT_MAX) {
+ fprintf(stderr, "tst_fx2loop-E: \"%s\" not a non-negative integer\n", p);
+ return -1;
+ }
+ return num;
+}
+
+/*--------------------------------------------------------------------------*/
+
+double get_double(char* p)
+{
+ char *endptr;
+ double num = 0.;
+
+ num = strtod(p, &endptr);
+ if ((endptr && *endptr) || num < 0.) {
+ fprintf(stderr, "tst_fx2loop-E: \"%s\" not a valid positive float\n", p);
+ return -1.;
+ }
+ return num;
+}
+
+/*--------------------------------------------------------------------------*/
+
+int get_arg_pint(int min, int max, const char* text)
+{
+ int tmp = -1;
+ if (argi < argc) tmp = get_pint(argv[argi++]);
+ if (tmp < min || tmp > max) {
+ fprintf(stderr, "tst_fx2loop-F: %s\n", text);
+ exit(EXIT_FAILURE);
+ }
+ return tmp;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void do_write(uint16_t* buf, int nw)
+{
+ int rc;
+ int i;
+ int ntrans;
+ int tout = 1000;
+ int ep = 4;
+
+ usb_claim();
+ rc = libusb_bulk_transfer(pUsbDevHdl, ep,
+ (unsigned char *)buf, nw*2, &ntrans, tout);
+ if (rc!=0 || ntrans != nw*2) {
+ fprintf(stderr, "tst_fx2loop-E: bulk write failed ntrans=%d rc=%d: %s \n",
+ ntrans, rc, usb_strerror(rc));
+ } else {
+ prt_time();
+ printf("write %4d word:", nw);
+ for (i = 0; i < nw; i++) printf(" %4.4x", buf[i]);
+ printf("\n");
+ }
+ usb_release();
+
+ return;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void do_read(int ep)
+{
+ int rc;
+ int i;
+ int ntrans;
+ uint16_t buf[4096];
+ int tout = 1000;
+ int nloop;
+
+ usb_claim();
+ for (nloop=0;;nloop++) {
+ rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80,
+ (unsigned char *)buf, 2*4096, &ntrans, tout);
+
+ if (ntrans==0 && rc) {
+ if (rc==LIBUSB_ERROR_TIMEOUT && ntrans==0 && nloop>0) break;
+ fprintf(stderr, "tst_fx2loop-E: bulk read failed ntrans=%d rc=%d: %s \n",
+ ntrans, rc, usb_strerror(rc));
+ break;
+ }
+ prt_time();
+ printf("read %4d word:", ntrans/2);
+ int nprt = ntrans/2;
+ if (nprt > 9) nprt = 9;
+ for (i = 0; i < nprt; i++) printf(" %4.4x", (uint16_t)buf[i]);
+ printf("\n");
+ if (nsigint>0) break;
+ }
+ usb_release();
+ return;
+}
+
+/*----------------------------------------------------------*/
+void pollfd_add(int fd, short events, void *user_data)
+{
+ if (pollfd_nfds >= 16) {
+ fprintf(stderr, "tst_fx2loop-F: pollfd list overflow\n");
+ exit(EXIT_FAILURE);
+ }
+ if (par_trace) {
+ prt_time();
+ printf("pollfd_add: fd=%3d evt=%4.4x\n", fd, events);
+ }
+ pollfd_fds[pollfd_nfds].fd = fd;
+ pollfd_fds[pollfd_nfds].events = events;
+ pollfd_fds[pollfd_nfds].revents = 0;
+ pollfd_nfds += 1;
+ return;
+}
+
+/*----------------------------------------------------------*/
+void pollfd_remove(int fd, void *user_data)
+{
+ int iw = 0;
+ int ir = 0;
+ if (par_trace) {
+ prt_time();
+ printf("pollfd_remove: fd=%3d\n", fd);
+ }
+ for (ir = 0; ir < pollfd_nfds; ir++) {
+ if (pollfd_fds[ir].fd != fd) {
+ pollfd_fds[iw].fd = pollfd_fds[ir].fd;
+ pollfd_fds[iw].events = pollfd_fds[ir].events;
+ pollfd_fds[iw].revents = pollfd_fds[ir].revents;
+ iw += 1;
+ }
+ }
+ pollfd_nfds = iw;
+ return;
+}
+
+/*----------------------------------------------------------*/
+void pollfd_init()
+{
+ const struct libusb_pollfd** plist = libusb_get_pollfds(pUsbContext);
+ const struct libusb_pollfd** p;
+
+ for (p = plist; *p !=0; p++) {
+ pollfd_add((*p)->fd, (*p)->events, NULL);
+ }
+
+ free(plist);
+
+ libusb_set_pollfd_notifiers(pUsbContext, pollfd_add, pollfd_remove,NULL);
+
+ return;
+}
+
+/*----------------------------------------------------------*/
+int keep_running()
+{
+ if (nsigint > 0) return 0;
+ if (par_nsec > 0 && (get_time()-t_start) > par_nsec) return 0;
+ return 1;
+
+}
+
+/* forward declaration needed... */
+void cb_rxblast(struct libusb_transfer *t);
+
+/*----------------------------------------------------------*/
+void que_write()
+{
+ int rc;
+ int i;
+ int nw = 512*dsc_rx.par_nfrm/2;
+ int length = 2*nw;
+ uint16_t* pdat;
+
+ struct libusb_transfer* t = libusb_alloc_transfer(0);
+
+ t->dev_handle = pUsbDevHdl;
+ t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
+ t->endpoint = 4;
+ t->type = LIBUSB_TRANSFER_TYPE_BULK;
+ t->timeout = 1000;
+ t->status = 0;
+ t->buffer = malloc(length);
+ t->length = length;
+ t->actual_length = 0;
+ t->callback = cb_rxblast;
+ t->user_data = 0;
+
+ pdat = (uint16_t*)(t->buffer);
+ for (i = 0; i < nw; i++) *pdat++ = dsc_rx.cval++;
+
+ rc = libusb_submit_transfer(t);
+ if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
+
+ nreq += 1;
+
+ if (par_trace) {
+ prt_time();
+ printf("que_write: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length);
+ }
+
+ return;
+}
+
+/*----------------------------------------------------------*/
+void que_read(int ep, int nb, libusb_transfer_cb_fn cb)
+{
+ int rc;
+ int length = 512*nb;
+
+ struct libusb_transfer* t = libusb_alloc_transfer(0);
+
+ t->dev_handle = pUsbDevHdl;
+ t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
+ t->endpoint = (unsigned char) (ep|0x80);
+ t->type = LIBUSB_TRANSFER_TYPE_BULK;
+ t->timeout = 1000;
+ t->status = 0;
+ t->buffer = malloc(length);
+ t->length = length;
+ t->actual_length = 0;
+ t->callback = cb;
+ t->user_data = 0;
+
+ rc = libusb_submit_transfer(t);
+ if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
+
+ nreq += 1;
+
+ if (par_trace) {
+ prt_time();
+ printf("que_read: ep=%1d l=%5d\n", t->endpoint&(~0x80), t->length);
+ }
+
+ return;
+}
+
+/*----------------------------------------------------------*/
+void send_msg()
+{
+ int rc;
+ int i;
+ int nw = par_nwmsg;
+ int length;
+ uint16_t* pdat;
+
+ if (par_nwrndm) nw = 1 + (random() % par_nwmsg);
+ length = 2 * nw;
+ cur_nwmsg = nw;
+
+ struct libusb_transfer* t = libusb_alloc_transfer(0);
+
+ t->dev_handle = pUsbDevHdl;
+ t->flags = LIBUSB_TRANSFER_FREE_TRANSFER | LIBUSB_TRANSFER_FREE_BUFFER;
+ t->endpoint = 4;
+ t->type = LIBUSB_TRANSFER_TYPE_BULK;
+ t->timeout = 1000;
+ t->status = 0;
+ t->buffer = malloc(length);
+ t->length = length;
+ t->actual_length = 0;
+ t->callback = cb_rxblast;
+ t->user_data = 0;
+
+ pdat = (uint16_t*)(t->buffer);
+ for (i = 0; i < nw-1; i++) *pdat++ = dsc_rx.cval++;
+ *pdat++ = 0xdead;
+
+ rc = libusb_submit_transfer(t);
+ if (rc) bad_usbcall_exit("libusb_submit_transfer()", rc);
+
+ nreq += 1;
+
+ if (par_trace) {
+ prt_time();
+ printf("send_msg: ep=%1d l=%5d", t->endpoint&(~0x80), t->length);
+ printf(" buf=%4.4x,..", ((uint16_t*)(t->buffer))[0]);
+ for (i = nw-2; i < nw; i++) {
+ printf(",%4.4x", ((uint16_t*)(t->buffer))[i]);
+ }
+ printf("\n");
+ }
+
+ return;
+}
+
+/*----------------------------------------------------------*/
+void cb_rxblast(struct libusb_transfer *t)
+{
+ nreq -= 1;
+
+ if (par_trace) {
+ prt_time();
+ printf("cb_rx : ep=%d l=%5d al=%5d\n",
+ t->endpoint&(~0x80), t->length, t->actual_length);
+ }
+
+ bad_transfer_exit(t, "cb_rxblast");
+ dsc_rx.stat_nbuf += 1;
+ dsc_rx.stat_nbyt += t->actual_length;
+
+ if (par_nwmsg==0 && keep_running()) que_write();
+
+ return;
+}
+
+/*----------------------------------------------------------*/
+void cb_txblast(struct libusb_transfer *t, int ep, libusb_transfer_cb_fn cb,
+ struct dsc_queue* pdsc)
+{
+ nreq -= 1;
+
+ if (par_trace) {
+ prt_time();
+ printf("cb_txx: ep=%d l=%5d al=%5d\n",
+ t->endpoint&(~0x80), t->length, t->actual_length);
+ }
+
+ bad_transfer_exit(t, "cb_txblast");
+ if (t->actual_length > 0) {
+ uint16_t* pdat = (uint16_t*)(t->buffer);
+ int nw = t->actual_length/2;
+ int i;
+ if (pdsc->stat_nbuf == 0) pdsc->cval = pdat[0];
+ for (i = 0; i < nw; i++) {
+ uint16_t dat = *pdat++;
+ if (pdsc->cval != dat) {
+ prt_time();
+ printf("FAIL: on ep=%d seen %4.4x expect %4.4x after %10.0f char\n",
+ ep&(~0x80), dat, pdsc->cval, pdsc->stat_nbyt+2*i);
+ pdsc->cval = dat;
+ }
+ pdsc->cval += 1;
+ }
+ }
+
+ pdsc->stat_nbuf += 1;
+ pdsc->stat_nbyt += t->actual_length;
+ if (t->actual_length < t->length) pdsc->stat_npt += 1;
+
+ if (keep_running()) que_read(ep, pdsc->par_nfrm, cb);
+}
+
+/*----------------------------------------------------------*/
+void cb_tx1blast(struct libusb_transfer *t)
+{
+ cb_txblast(t, 6, cb_tx1blast, &dsc_tx1);
+ return;
+}
+
+/*----------------------------------------------------------*/
+void cb_tx2blast(struct libusb_transfer *t)
+{
+ cb_txblast(t, 8, cb_tx2blast, &dsc_tx2);
+ return;
+}
+
+/*----------------------------------------------------------*/
+void cb_txloop(struct libusb_transfer *t)
+{
+ nreq -= 1;
+
+ if (par_trace) {
+ prt_time();
+ printf("cb_txl: ep=%d l=%5d al=%5d\n",
+ t->endpoint&(~0x80), t->length, t->actual_length);
+ }
+
+ bad_transfer_exit(t, "cb_txloop");
+ if (t->actual_length > 0) {
+ uint16_t* pdat = (uint16_t*)(t->buffer);
+ int nw = t->actual_length/2;
+ int i;
+
+ for (i = 0; i < nw; i++) {
+ uint16_t dat = *pdat++;
+
+ if (cur_nwmsg > 0) {
+ uint16_t dat_exp = (cur_nwmsg>1) ? dsc_tx1.cval++ : 0xdead;
+ if (dat_exp != dat) {
+ prt_time();
+ printf("FAIL: on ep=6 seen %4.4x expect %4.4x after %10.0f char\n",
+ dat, dat_exp, dsc_tx1.stat_nbyt+2*i);
+ if (cur_nwmsg>1) dsc_tx1.cval = dat + 1;
+ }
+ cur_nwmsg -= 1;
+ if (cur_nwmsg==0 && dat==0xdead) stat_nmsg += 1;
+ } else {
+ prt_time();
+ printf("FAIL: on ep=6 seen %4.4x unexpected after %10.0f char\n",
+ dat, dsc_tx1.stat_nbyt+2*i);
+ }
+ }
+ }
+
+ dsc_tx1.stat_nbuf += 1;
+ dsc_tx1.stat_nbyt += t->actual_length;
+ if (t->actual_length < t->length) dsc_tx1.stat_npt += 1;
+
+ if (cur_nwmsg==0) { /* end of message seen */
+ if (keep_running()) {
+ send_msg();
+ } else {
+ if (par_trace) { prt_time(); printf("set endpoll = 1\n"); }
+ endpoll = 1;
+ }
+ }
+
+ que_read(6, dsc_tx1.par_nfrm, cb_txloop);
+
+ return;
+}
+
+/*----------------------------------------------------------*/
+void tx_pipe_drain(int ep)
+{
+ unsigned char buf[16384];
+ int ntrans;
+ int rc = libusb_bulk_transfer(pUsbDevHdl, ep|0x80,
+ buf, sizeof(buf), &ntrans, 10);
+ if (rc == LIBUSB_ERROR_TIMEOUT) return;
+ if (rc) bad_usbcall_exit("pipe drain: libusb_bulk_transfer()", rc);
+
+ fprintf(stderr, "tst_fx2loop-I: pipe drain for ep=%d: ntrans=%d\n",
+ ep&(~0x80), ntrans);
+
+ return;
+}
+
+/*--------------------------------------------------------------------------*/
+void do_run()
+{
+ int rc;
+ int fd_timer = -1;
+ int i;
+
+ struct itimerspec tspec;
+ struct dsc_queue dsc_rx_last = dsc_rx;
+ struct dsc_queue dsc_tx1_last = dsc_tx1;
+ struct dsc_queue dsc_tx2_last = dsc_tx2;
+
+ if (par_trace) {
+ prt_time();
+ printf("rx:nf=%d,nq=%d; tx1:nf=%d,nq=%d; tx2:nf=%d,nq=%d\n",
+ dsc_rx.par_nfrm, dsc_rx.par_nque,
+ dsc_tx1.par_nfrm, dsc_tx2.par_nque,
+ dsc_tx2.par_nfrm, dsc_tx2.par_nque);
+ }
+
+ /* setup pollfd list */
+ fd_timer = timerfd_create(CLOCK_MONOTONIC, TFD_NONBLOCK);
+ if (fd_timer < 0) bad_syscall_exit("timerfd_create() failed", fd_timer);
+ tspec.it_interval.tv_sec = 1;
+ tspec.it_interval.tv_nsec = 0;
+ tspec.it_value.tv_sec = 1;
+ tspec.it_value.tv_nsec = 0;
+ rc = timerfd_settime(fd_timer, 0, &tspec, NULL);
+ if (rc<0) bad_syscall_exit("timerfd_settime() failed", rc);
+ pollfd_fds[0].fd = fd_timer;
+ pollfd_fds[0].events = POLLIN;
+ pollfd_fds[0].revents = 0;
+ pollfd_nfds = 1;
+
+ pollfd_init();
+
+ /* setup loop */
+ if (par_nwmsg > 0) {
+ dsc_rx.par_nfrm = 0;
+ dsc_rx.par_nque = 0;
+ if (dsc_tx1.par_nfrm == 0) dsc_tx1.par_nfrm = 1;
+ if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1;
+
+ tx_pipe_drain(6); /* drain tx1 */
+ for (i = 0; i < dsc_tx1.par_nque; i++) /* prime tx1 */
+ que_read(6, dsc_tx1.par_nfrm, cb_txloop);
+ send_msg();
+ }
+
+ /* setup rxblast */
+ if (dsc_rx.par_nfrm > 0) {
+ int i;
+ if (dsc_rx.par_nque == 0) dsc_rx.par_nque = 1;
+ for (i = 0; i < dsc_rx.par_nque; i++) que_write();
+ }
+
+ /* setup txblast */
+ if (par_nwmsg==0 && dsc_tx1.par_nfrm>0) {
+ int i;
+ if (dsc_tx1.par_nque == 0) dsc_tx1.par_nque = 1;
+ for (i = 0; i < dsc_tx1.par_nque; i++)
+ que_read(6, dsc_tx1.par_nfrm, cb_tx1blast);
+ }
+
+ /* setup tx2blast */
+ if (dsc_tx2.par_nfrm > 0) {
+ int i;
+ if (dsc_tx2.par_nque == 0) dsc_tx2.par_nque = 1;
+ for (i = 0; i < dsc_tx2.par_nque; i++)
+ que_read(8, dsc_tx2.par_nfrm, cb_tx2blast);
+ }
+
+ t_start = get_time();
+
+ while(nreq>0 && endpoll==0) {
+ uint64_t tbuf;
+ rc = poll(pollfd_fds, pollfd_nfds, 2000);
+ if (rc==-1 && errno==EINTR) continue;
+ if (rc < 0) bad_syscall_exit("poll() failed", rc);
+ if (rc == 0) fprintf(stderr, "tst_fx2loop-I: poll() timeout\n");
+
+ if (par_trace) {
+ int i;
+ prt_time();
+ printf("poll: rc=%d:", rc);
+ for (i = 0; i < pollfd_nfds; i++) {
+ printf(" %d,%2.2x", pollfd_fds[i].fd, pollfd_fds[i].revents);
+ }
+ printf("\n");
+ }
+
+ if (pollfd_fds[0].revents == POLLIN) {
+ errno = EBADMSG; /* to be reported on short read */
+ rc = read(fd_timer, &tbuf, sizeof(tbuf));
+ if (rc != sizeof(tbuf)) bad_syscall_exit("read(fd_timer,...) failed", rc);
+ if (par_stat) {
+ prt_time();
+ if (par_nwmsg>0 || dsc_rx.par_nque>0) {
+ double nbuf = dsc_rx.stat_nbuf - dsc_rx_last.stat_nbuf;
+ double nbyt = dsc_rx.stat_nbyt - dsc_rx_last.stat_nbyt;
+ printf("rx: %5.0f,%7.1f ", nbuf, nbyt/1000.);
+ }
+ if (dsc_tx1.par_nque > 0 ) {
+ double nbuf = dsc_tx1.stat_nbuf - dsc_tx1_last.stat_nbuf;
+ double nbyt = dsc_tx1.stat_nbyt - dsc_tx1_last.stat_nbyt;
+ printf("tx1: %5.0f,%7.1f ", nbuf, nbyt/1000.);
+ }
+ if (dsc_tx2.par_nque > 0 ) {
+ double nbuf = dsc_tx2.stat_nbuf - dsc_tx2_last.stat_nbuf;
+ double nbyt = dsc_tx2.stat_nbyt - dsc_tx2_last.stat_nbyt;
+ printf("tx2: %5.0f,%7.1f ", nbuf, nbyt/1000.);
+ }
+ printf("\n");
+ dsc_rx_last = dsc_rx;
+ dsc_tx1_last = dsc_tx1;
+ dsc_tx2_last = dsc_tx2;
+ }
+ } else {
+ struct timeval tv;
+ tv.tv_sec = 0;
+ tv.tv_usec = 0;
+ rc = libusb_handle_events_timeout(pUsbContext, &tv);
+ //setting the timeval pointer to NULL should work, but doesn't (in 1.0.6)
+ //rc = libusb_handle_events_timeout(pUsbContext, 0);
+ if (rc) bad_usbcall_exit("libusb_handle_events_timeout()", rc);
+ }
+ }
+
+ return;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void do_stat()
+{
+ printf("run statistics:\n");
+ printf("runtime : %13.3f\n", get_time()-t_start);
+ printf("nbuf_rx : %13.0f\n", dsc_rx.stat_nbuf);
+ printf("nbyt_rx : %13.0f\n", dsc_rx.stat_nbyt);
+ printf("nbuf_tx1 : %13.0f\n", dsc_tx1.stat_nbuf);
+ printf("nbyt_tx1 : %13.0f\n", dsc_tx1.stat_nbyt);
+ printf("npt_tx1 : %13.0f\n", dsc_tx1.stat_npt);
+ printf("nbuf_tx2 : %13.0f\n", dsc_tx2.stat_nbuf);
+ printf("nbyt_tx2 : %13.0f\n", dsc_tx2.stat_nbyt);
+ printf("npt_tx2 : %13.0f\n", dsc_tx2.stat_npt);
+ printf("nmsg : %13.0f\n", stat_nmsg);
+ return;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void usb_claim()
+{
+ int rc = libusb_claim_interface(pUsbDevHdl, 0);
+ if (rc) bad_usbcall_exit("libusb_claim_interface()", rc);
+ return;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void usb_release()
+{
+ int rc = libusb_release_interface(pUsbDevHdl, 0);
+ if (rc) bad_usbcall_exit("libusb_release_interface()", rc);
+ return;
+}
+
+/*--------------------------------------------------------------------------*/
+
+char* usb_strerror(int rc)
+{
+ switch(rc) {
+ case LIBUSB_SUCCESS:
+ return "";
+ case LIBUSB_ERROR_IO:
+ return "Input/output error";
+ case LIBUSB_ERROR_INVALID_PARAM:
+ return "Invalid parameter";
+ case LIBUSB_ERROR_ACCESS:
+ return "Access denied";
+ case LIBUSB_ERROR_NO_DEVICE:
+ return "No such device";
+ case LIBUSB_ERROR_NOT_FOUND:
+ return "Entity not found";
+ case LIBUSB_ERROR_BUSY:
+ return "Resource busy";
+ case LIBUSB_ERROR_TIMEOUT:
+ return "Operation timed out";
+ case LIBUSB_ERROR_OVERFLOW:
+ return "Overflow";
+ case LIBUSB_ERROR_PIPE:
+ return "Pipe error";
+ case LIBUSB_ERROR_INTERRUPTED:
+ return "System call interrupted";
+ case LIBUSB_ERROR_NO_MEM:
+ return "Insufficient memory";
+ case LIBUSB_ERROR_NOT_SUPPORTED:
+ return "Operation not supported";
+ case LIBUSB_ERROR_OTHER:
+ return "Other error";
+ default:
+ return "Unknown libusb error code";
+ }
+}
+
+/*--------------------------------------------------------------------------*/
+
+void prt_time(void)
+{
+ struct timeval tv;
+ struct timezone tz;
+ struct tm tmval;
+
+ gettimeofday(&tv, &tz);
+ localtime_r(&tv.tv_sec, &tmval);
+ printf("%02d:%02d:%02d.%06d: ", tmval.tm_hour, tmval.tm_min, tmval.tm_sec,
+ (int) tv.tv_usec);
+}
+
+/*--------------------------------------------------------------------------*/
+
+double get_time(void)
+{
+ struct timeval tv;
+ struct timezone tz;
+ gettimeofday(&tv, &tz);
+ return (double)tv.tv_sec + 1.e-6 * (double)tv.tv_usec;
+}
+
+/*--------------------------------------------------------------------------*/
+
+void bad_syscall_exit(const char* text, int rc)
+{
+ fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d errno=%d : %s\n",
+ text, rc, errno, strerror(errno));
+ exit(EXIT_FAILURE);
+}
+
+/*--------------------------------------------------------------------------*/
+
+void bad_usbcall_exit(const char* text, int rc)
+{
+ fprintf(stderr, "tst_fx2loop-F: %s failed with rc=%d: %s\n",
+ text, rc, usb_strerror(rc));
+ exit(EXIT_FAILURE);
+}
+
+/*--------------------------------------------------------------------------*/
+
+void bad_transfer_exit(struct libusb_transfer *t, const char* text)
+{
+ const char* etext = 0;
+
+ if (t->status == LIBUSB_TRANSFER_ERROR) etext = "ERROR";
+ if (t->status == LIBUSB_TRANSFER_STALL) etext = "STALL";
+ if (t->status == LIBUSB_TRANSFER_NO_DEVICE) etext = "NO_DEVICE";
+ if (t->status == LIBUSB_TRANSFER_OVERFLOW) etext = "OVERFLOW";
+
+ if (etext == 0) return;
+
+ fprintf(stderr, "tst_fx2loop-F: transfer failure in %s on ep=%d: %s\n",
+ text, (int)(t->endpoint&(~0x80)), etext);
+ exit(EXIT_FAILURE);
+}
+
Index: tst_fx2loop_hiomap.vbom
===================================================================
--- tst_fx2loop_hiomap.vbom (nonexistent)
+++ tst_fx2loop_hiomap.vbom (revision 33)
@@ -0,0 +1,7 @@
+# libs
+../../vlib/slvtypes.vhd
+../../bplib/fx2lib/fx2lib.vhd
+tst_fx2looplib.vbom
+# components
+# design
+tst_fx2loop_hiomap.vhd
Index: tst_fx2loop.vbom
===================================================================
--- tst_fx2loop.vbom (nonexistent)
+++ tst_fx2loop.vbom (revision 33)
@@ -0,0 +1,10 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/comlib/comlib.vhd
+../../bplib/fx2lib/fx2lib.vhd
+tst_fx2looplib.vhd
+# components
+../../vlib/comlib/byte2word.vbom
+../../vlib/comlib/word2byte.vbom
+# design
+tst_fx2loop.vhd
Index: tst_fx2looplib.vbom
===================================================================
--- tst_fx2looplib.vbom (nonexistent)
+++ tst_fx2looplib.vbom (revision 33)
@@ -0,0 +1,4 @@
+# libs
+../../vlib/slvtypes.vhd
+../../bplib/fx2lib/fx2lib.vhd
+tst_fx2looplib.vhd
Index: .cvsignore
===================================================================
--- .cvsignore (nonexistent)
+++ .cvsignore (revision 33)
@@ -0,0 +1,2 @@
+tst_fx2loop
+tst_fx2loop_si
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 33)
.
Property changes :
Added: svn:ignore
## -0,0 +1,35 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
+tst_fx2loop
+tst_fx2loop_si