Subversion Repositories w11

/nexys2/sys_conf.vhd

/nexys2/sys_w11a_n2.vhd

/nexys2/tb/sys_conf_sim.vhd

/nexys2/tb/Makefile

/nexys2/tb/tb_w11a_n2_ssim.vbom

/nexys2/tb/tb_w11a_n2.vbom

/nexys2/tb/tb_w11a_n2.vhd

/nexys2/tb/tbw.dat

/nexys2/tb/.cvsignore

/nexys2/tb/sys_w11a_n2.ucf_cpp

nexys2/tb/sys_w11a_n2.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: nexys2/tb =================================================================== --- nexys2/tb (nonexistent) +++ nexys2/tb (revision 33)

nexys2/tb Property changes : Added: svn:ignore ## -0,0 +1,41 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_n2 +tb_w11a_n2_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n2.ucf +*.dep_ucf_cpp Index: nexys2/sys_w11a_n2.vbom =================================================================== --- nexys2/sys_w11a_n2.vbom (nonexistent) +++ nexys2/sys_w11a_n2.vbom (revision 33) @@ -0,0 +1,32 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/fx2rlink/fx2rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom +[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +# design +sys_w11a_n2.vhd +@ucf_cpp: sys_w11a_n2.ucf Index: nexys2/Makefile =================================================================== --- nexys2/Makefile (nonexistent) +++ nexys2/Makefile (revision 33) @@ -0,0 +1,36 @@ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-04-20 509 1.2 add fx2 support +# 2011-08-13 405 1.1 use includes from rtl/make +# 2010-05-28 295 1.0 Initial version (derived from _s3 version) +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys2.mk +FX2_FILE = nexys2_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +sys_w11a_n2.mcs : sys_w11a_n2.bit + promgen -w -x xcf04s -p mcs -u 0 sys_w11a_n2 + mv sys_w11a_n2.prm sys_w11a_n2_prm.log + mv sys_w11a_n2.cfi sys_w11a_n2_cfi.log +# +#---- +# +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: nexys2/sys_w11a_n2.ucf_cpp =================================================================== --- nexys2/sys_w11a_n2.ucf_cpp (nonexistent) +++ nexys2/sys_w11a_n2.ucf_cpp (revision 33) @@ -0,0 +1,33 @@ +## $Id: sys_w11a_n2.ucf_cpp 540 2013-10-13 18:42:50Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-13 540 1.1 add pad->clk constraints +## 2013-04-20 509 1.1 add fx2 support +## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50 +## 2010-05-26 295 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## constrain pad->net clock delay +NET CLK TNM = TNM_CLK; +TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK50) TO TNM_CLK 10 ns; +NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK; +TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns; + +## std board +## +#include "bplib/nexys2/nexys2_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" +## +## Cypress FX2 +## +#include "bplib/nexys2/nexys2_pins_fx2.ucf" +#include "bplib/nexys2/nexys2_time_fx2_ic.ucf" Index: nexys2/.cvsignore =================================================================== --- nexys2/.cvsignore (nonexistent) +++ nexys2/.cvsignore (revision 33) @@ -0,0 +1,5 @@ +sys_w11a_n2.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: nexys2/sys_w11a_n2.mfset =================================================================== --- nexys2/sys_w11a_n2.mfset (nonexistent) +++ nexys2/sys_w11a_n2.mfset (revision 33) @@ -0,0 +1,148 @@ +# $Id: sys_w11a_n2.mfset 427 2011-11-19 21:04:11Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded +INFO:.*You can improve the performance of the multiplier + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Unconnected output port 'LOCKED' of component 'dcm_sfs' +Unconnected output port 'RL_MONI' of component 'rlink_base_serport' +Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport' +Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as' +Unconnected output port 'OFIFO_SIZE' of component 'rlink_base' +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen' + +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input > is never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used + +Signal > is assigned but never used +Signal > is assigned but never used +Signal is assigned but never used + +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +# +# ---------------------------------------------------------------------------- +[tra] +INFO:.*TNM.*used in period specification.*was traced into DCM_SP + +# +# ---------------------------------------------------------------------------- +[map] +The signal is incomplete +Logical network I_MEM_WAIT_IBUF has no load +There is a dangling output parity pin +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] +The signal I_MEM_WAIT_IBUF has no load +There are 1 loadless signals in this design +# +# ---------------------------------------------------------------------------- +[bgn] +Spartan-3 1200E and 1600E devices do not support bitstream +The signal is incomplete +There is a dangling output parity pin +INFO:.*To achieve optimal frequency synthesis performance \ No newline at end of file Index: nexys2 =================================================================== --- nexys2 (nonexistent) +++ nexys2 (revision 33)

nexys2 Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +sys_w11a_n2.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: nexys3/sys_conf.vhd =================================================================== --- nexys3/sys_conf.vhd (nonexistent) +++ nexys3/sys_conf.vhd (revision 33) @@ -0,0 +1,103 @@ +-- $Id: sys_conf.vhd 692 2015-06-21 11:53:24Z mueller $ +-- +-- Copyright 2011-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-06-21 692 1.4.1 use clksys=64 (no closure after rhrp fixes) +-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions +-- 2015-02-15 647 1.3 drop bram and minisys options +-- 2014-12-26 621 1.2.2 use 68 MHz, get occasional problems with 72 MHz +-- 2014-12-22 619 1.2.1 add _rbmon_awidth +-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect +-- 2013-10-05 537 1.1.1 use 72 MHz, no closure w/ ISE 14.x for 80 anymore +-- 2013-04-21 509 1.1 add fx2 settings +-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432) +-- 2011-11-20 430 1.0 Initial version (derived from _n2 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd): +-- div mul clksys read0 read1 write +-- 2 1 50.0 2 2 3 +-- 4 3 75.0 4 4 5 (also 70 MHz) +-- 5 4 80.0 5 5 5 +-- 20 17 85.0 5 5 6 +-- 10 9 90.0 6 6 6 (also 95 MHz) +-- 1 1 100.0 6 6 7 + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 25; + constant sys_conf_clksys_vcomultiply : positive := 16; -- dcm 64 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 64 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec + constant sys_conf_fx2_petowidth : positive := 10; + constant sys_conf_fx2_ccwidth : positive := 5; + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 4; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: nexys3/sys_w11a_n3.vhd =================================================================== --- nexys3/sys_w11a_n3.vhd (nonexistent) +++ nexys3/sys_w11a_n3.vhd (revision 33) @@ -0,0 +1,485 @@ +-- $Id: sys_w11a_n3.vhd 692 2015-06-21 11:53:24Z mueller $ +-- +-- Copyright 2011-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_n3 - syn +-- Description: w11a test design for nexys3 +-- +-- Dependencies: vlib/xlib/s6_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- bplib/fx2rlink/rlink_sp1c_fx2 +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- bplib/nxcramlib/nx_cram_memctl_as +-- bplib/fx2rlink/ioleds_sp1c_fx2 +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_sys_w11a_n3 +-- +-- Target Devices: generic +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes +-- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67% +-- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67% +-- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65% +-- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 +-- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon +-- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4 +-- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11 +-- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: +-- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 ! +-- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II +-- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 +-- 2015-04-24 668 1.8.3 added ibd_ibmon +-- 2015-04-11 666 1.8.2 rearrange XON handling +-- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2015-02-15 647 1.8 drop bram and minisys options +-- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address +-- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon +-- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT +-- 2014-08-15 583 1.6 rb_mreq addr now 16 bit +-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect +-- 2013-04-21 509 1.4 added fx2 (cuff) support +-- 2011-12-18 440 1.0.4 use rlink_sp1c +-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks) +-- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now +-- 2011-11-23 432 1.0.1 fixup PPCM handling +-- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2) +------------------------------------------------------------------------------ +-- +-- w11a test design for nexys3 +-- w11a + rlink + serport +-- +-- Usage of Nexys 3 Switches, Buttons, LEDs: +-- +-- SWI(7:6): no function (only connected to sn_humanio_rbus) +-- (5:4): select DSP +-- 00 abclkdiv & abclkdiv_f +-- 01 PC +-- 10 DISPREG +-- 11 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- (1): 1 enable XON +-- (0): 0 -> main board RS232 port +-- 1 -> Pmod B/top RS232 port +-- +-- LEDs if SWI(3) = 1 +-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DP(3:0) shows IO activity +-- if SWI(2)=0 (serport) +-- (3): not SER_MONI.txok (shows tx back preasure) +-- (2): SER_MONI.txact (shows tx activity) +-- (1): not SER_MONI.rxok (shows rx back preasure) +-- (0): SER_MONI.rxact (shows rx activity) +-- if SWI(2)=1 (fx2-usb) +-- (3): RB_SRES.busy (shows rbus back preasure) +-- (2): RLB_TXBUSY (shows tx back preasure) +-- (1): RLB_TXENA (shows tx activity) +-- (0): RLB_RXVAL (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.fx2lib.all; +use work.fx2rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.nxcramlib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_n3 is -- top level + -- implements nexys3_fusp_cuff_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- n3 switches + I_BTN : in slv5; -- n3 buttons + O_LED : out slv8; -- n3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16; -- cram: data lines + O_PPCM_CE_N : out slbit; -- ppcm: ... + O_PPCM_RST_N : out slbit; -- ppcm: ... + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit; -- fusp: rs232 tx + I_FX2_IFCLK : in slbit; -- fx2: interface clock + O_FX2_FIFO : out slv2; -- fx2: fifo address + I_FX2_FLAG : in slv4; -- fx2: fifo flags + O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) + O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) + O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) + O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) + IO_FX2_DATA : inout slv8 -- fx2: data lines + ); +end sys_w11a_n3; + +architecture syn of sys_w11a_n3 is + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal RLB_MONI : rlb_moni_type := rlb_moni_init; + signal SER_MONI : serport_moni_type := serport_moni_init; + signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MEM_ADDR_EXT : slv22 := (others=>'0'); + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s6_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce -- usec/msec clock divider ----------- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 ----------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + PETOWIDTH => sys_conf_fx2_petowidth, + CCWIDTH => sys_conf_fx2_ccwidth, + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ENAFX2 => SWI(2), + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + RLB_MONI => RLB_MONI, + SER_MONI => SER_MONI, + FX2_MONI => FX2_MONI, + I_FX2_IFCLK => I_FX2_IFCLK, + O_FX2_FIFO => O_FX2_FIFO, + I_FX2_FLAG => I_FX2_FLAG, + O_FX2_SLRD_N => O_FX2_SLRD_N, + O_FX2_SLWR_N => O_FX2_SLWR_N, + O_FX2_SLOE_N => O_FX2_SLOE_N, + O_FX2_PKTEND_N => O_FX2_PKTEND_N, + IO_FX2_DATA => IO_FX2_DATA + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) + + SRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled + O_PPCM_RST_N <= '1'; -- + + LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------ + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + RESET => GRESET, + ENAFX2 => SWI(2), + RB_SRES => RB_SRES, + RLB_MONI => RLB_MONI, + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 2) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- + generic map ( + BWIDTH => 5, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + +end syn; Index: nexys3/tb/sys_conf_sim.vhd =================================================================== --- nexys3/tb/sys_conf_sim.vhd (nonexistent) +++ nexys3/tb/sys_conf_sim.vhd (revision 33) @@ -0,0 +1,87 @@ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ +-- +-- Copyright 2011-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-14 658 1.5 add sys_conf_ibd_* definitions +-- 2015-02-15 647 1.4 drop bram and minisys options +-- 2014-12-22 619 1.3.1 add _rbmon_awidth +-- 2013-10-06 538 1.3 pll support, use clksys_vcodivide ect +-- 2013-04-21 509 1.2 add fx2 settings +-- 2011-11-25 432 1.0 Initial version (cloned from _n3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 25; + constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz + constant sys_conf_clksys_gentype : string := "DCM"; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec + constant sys_conf_fx2_petowidth : positive := 10; + constant sys_conf_fx2_ccwidth : positive := 5; + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable rbmon + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + +end package sys_conf; Index: nexys3/tb/Makefile =================================================================== --- nexys3/tb/Makefile (nonexistent) +++ nexys3/tb/Makefile (revision 33) @@ -0,0 +1,31 @@ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-11-25 432 1.0 Initial version +# +EXE_all = tb_w11a_n3 +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: nexys3/tb/tb_w11a_n3_ssim.vbom =================================================================== --- nexys3/tb/tb_w11a_n3_ssim.vbom (nonexistent) +++ nexys3/tb/tb_w11a_n3_ssim.vbom (revision 33) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_n3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys3_fusp_cuff_aif = sys_w11a_n3_ssim.vhd +tb_w11a_n3.vbom +@top:tb_w11a_n3 Index: nexys3/tb/tb_w11a_n3.vbom =================================================================== --- nexys3/tb/tb_w11a_n3.vbom (nonexistent) +++ nexys3/tb/tb_w11a_n3.vbom (revision 33) @@ -0,0 +1,7 @@ +# configure tb_nexys3_fusp with sys_w11a_n3 target; +# use vhdl configure file (tb_w11a_n3.vhd) to allow +# that all configurations will co-exist in work library +nexys3_fusp_cuff_aif = ../sys_w11a_n3.vbom +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom +tb_w11a_n3.vhd Index: nexys3/tb/tb_w11a_n3.vhd =================================================================== --- nexys3/tb/tb_w11a_n3.vhd (nonexistent) +++ nexys3/tb/tb_w11a_n3.vhd (revision 33) @@ -0,0 +1,41 @@ +-- $Id: tb_w11a_n3.vhd 509 2013-04-21 20:46:20Z mueller $ +-- +-- Copyright 2011-2013 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_n3 +-- Description: Configuration for tb_w11a_n3 for tb_nexys3_fusp_cuff +-- +-- Dependencies: sys_w11a_n3 +-- +-- To test: sys_w11a_n3 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-25 295 - -.-- - - -:-- +-- +-- Revision History: +-- Date Rev Version Comment +-- 2013-04-21 509 1.1 now based on tb_nexys3_fusp_cuff +-- 2011-11-25 432 1.0 Initial version (cloned from _n2) +------------------------------------------------------------------------------ + +configuration tb_w11a_n3 of tb_nexys3_fusp_cuff is + + for sim + for all : nexys3_fusp_cuff_aif + use entity work.sys_w11a_n3; + end for; + end for; + +end tb_w11a_n3; Index: nexys3/tb/tbw.dat =================================================================== --- nexys3/tb/tbw.dat (nonexistent) +++ nexys3/tb/tbw.dat (revision 33) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 432 2011-11-25 20:16:28Z mueller $ +# +[tb_w11a_n3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: nexys3/tb/sys_w11a_n3.ucf_cpp =================================================================== --- nexys3/tb/sys_w11a_n3.ucf_cpp (nonexistent) +++ nexys3/tb/sys_w11a_n3.ucf_cpp (revision 33) @@ -0,0 +1 @@ +link ../sys_w11a_n3.ucf_cpp \ No newline at end of file

nexys3/tb/sys_w11a_n3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: nexys3/tb/.cvsignore =================================================================== --- nexys3/tb/.cvsignore (nonexistent) +++ nexys3/tb/.cvsignore (revision 33) @@ -0,0 +1,8 @@ +tb_w11a_n3 +tb_w11a_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n3.ucf +*.dep_ucf_cpp Index: nexys3/tb =================================================================== --- nexys3/tb (nonexistent) +++ nexys3/tb (revision 33)

nexys3/tb Property changes : Added: svn:ignore ## -0,0 +1,41 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_n3 +tb_w11a_n3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n3.ucf +*.dep_ucf_cpp Index: nexys3/sys_w11a_n3.vbom =================================================================== --- nexys3/sys_w11a_n3.vbom (nonexistent) +++ nexys3/sys_w11a_n3.vbom (revision 33) @@ -0,0 +1,32 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/fx2lib/fx2lib.vhd +../../../bplib/fx2rlink/fx2rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../bplib/fx2rlink/rlink_sp1c_fx2.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +../../../bplib/fx2rlink/ioleds_sp1c_fx2.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +# design +sys_w11a_n3.vhd +@ucf_cpp: sys_w11a_n3.ucf Index: nexys3/Makefile =================================================================== --- nexys3/Makefile (nonexistent) +++ nexys3/Makefile (revision 33) @@ -0,0 +1,30 @@ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-04-20 509 1.2 add fx2 support +# 2011-11-20 430 1.0 Initial version (derived from _n2 version) +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys3.mk +FX2_FILE = nexys3_jtag_2fifo_ic.ihx +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: nexys3/sys_w11a_n3.ucf_cpp =================================================================== --- nexys3/sys_w11a_n3.ucf_cpp (nonexistent) +++ nexys3/sys_w11a_n3.ucf_cpp (revision 33) @@ -0,0 +1,39 @@ +## $Id: sys_w11a_n3.ucf_cpp 540 2013-10-13 18:42:50Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints +## 2013-04-21 509 1.1 add fx2 support +## 2011-11-20 430 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## constrain pad->net clock delay +NET CLK TNM = TNM_CLK; +TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns; +NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK; +TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns; + +## FX2 controller specific constraints +## constrain cdc path in fifos and reset +TIMESPEC TS_CDC_FIFO = + FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*) + TO FFS(*FIFO/R_REG?_?addr_c*) + 5 ns DATAPATHONLY; + +## std board +## +#include "bplib/nexys3/nexys3_pins.ucf" +## +## Pmod B0 - RS232 +## +#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" +## +## Cypress FX2 +## +#include "bplib/nexys3/nexys3_pins_fx2.ucf" +#include "bplib/nexys3/nexys3_time_fx2_ic.ucf" Index: nexys3/.cvsignore =================================================================== --- nexys3/.cvsignore (nonexistent) +++ nexys3/.cvsignore (revision 33) @@ -0,0 +1,5 @@ +sys_w11a_n3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: nexys3/sys_w11a_n3.mfset =================================================================== --- nexys3/sys_w11a_n3.mfset (nonexistent) +++ nexys3/sys_w11a_n3.mfset (revision 33) @@ -0,0 +1,35 @@ +# $Id: sys_w11a_n3.mfset 440 2011-12-18 20:08:09Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Case statement is complete. others clause is never selected +INFO:.*The small RAM <.*> will be implemented on LUTs + +sys_w11a_n3\..*Output port of the instance is unconnected +sys_w11a_n3\..*Output port of the instance is unconnected +sys_w11a_n3\..*Output port of the instance is unconnected +sys_w11a_n3\..*Output port of the instance is unconnected +# +# ---------------------------------------------------------------------------- +[tra] +INFO:.*TNM 'I_CLK100'.*was traced into DCM_SP +INFO:.*Setting CLKIN_PERIOD attribute associated with DCM instance +# +# ---------------------------------------------------------------------------- +[map] +WARNING:.*has the attribute CLK_FEEDBACK set to NONE +WARNING:.*The signal is incomplete +WARNING:.*to use input parity pin.*dangling output for parity pin +INFO:.* +# +# ---------------------------------------------------------------------------- +[par] +WARNING:.*has the attribute CLK_FEEDBACK set to NONE +WARNING:.*The signal I_MEM_WAIT_IBUF has no load +WARNING:.*There are 1 loadless signals in this design +# +# ---------------------------------------------------------------------------- +[bgn] +WARNING:.*The signal is incomplete +WARNING:.*to use input parity pin.*dangling output for parity pin +INFO:.*To achieve optimal frequency synthesis performance Index: nexys3 =================================================================== --- nexys3 (nonexistent) +++ nexys3 (revision 33)

nexys3 Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +sys_w11a_n3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: basys3/sys_conf.vhd =================================================================== --- basys3/sys_conf.vhd (nonexistent) +++ basys3/sys_conf.vhd (revision 33) @@ -0,0 +1,92 @@ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_b3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions +-- 2015-02-08 644 1.0 Initial version (derived from _n4 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 11; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: basys3/tb/sys_conf_sim.vhd =================================================================== --- basys3/tb/sys_conf_sim.vhd (nonexistent) +++ basys3/tb/sys_conf_sim.vhd (revision 33) @@ -0,0 +1,89 @@ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_b3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: viv 2014.4; ghdl 0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions +-- 2015-02-21 649 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz + constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_mawidth : positive := 4; + constant sys_conf_memctl_nblock : positive := 11; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs + constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs + + -- configure w11 cpu core -------------------------------------------------- + -- sys_conf_mem_losize is highest 64 byte MMU block number + -- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks + constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; Index: basys3/tb/tb_w11a_b3_ssim.vbom =================================================================== --- basys3/tb/tb_w11a_b3_ssim.vbom (nonexistent) +++ basys3/tb/tb_w11a_b3_ssim.vbom (revision 33) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_b3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +basys3_aif = sys_w11a_b3_ssim.vhd +tb_w11a_b3.vbom +@top:tb_w11a_b3 Index: basys3/tb/tb_w11a_b3.vhd =================================================================== --- basys3/tb/tb_w11a_b3.vhd (nonexistent) +++ basys3/tb/tb_w11a_b3.vhd (revision 33) @@ -0,0 +1,35 @@ +-- $Id: tb_w11a_b3.vhd 649 2015-02-21 21:10:16Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_b3 +-- Description: Configuration for tb_w11a_b3 for tb_basys3 +-- +-- Dependencies: sys_w11a_b3 +-- +-- To test: sys_w11a_b3 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-21 649 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_w11a_b3 of tb_basys3 is + + for sim + for all : basys3_aif + use entity work.sys_w11a_b3; + end for; + end for; + +end tb_w11a_b3; Index: basys3/tb/tbw.dat =================================================================== --- basys3/tb/tbw.dat (nonexistent) +++ basys3/tb/tbw.dat (revision 33) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 649 2015-02-21 21:10:16Z mueller $ +# +[tb_w11a_b3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: basys3/tb/tb_w11a_b3.vbom =================================================================== --- basys3/tb/tb_w11a_b3.vbom (nonexistent) +++ basys3/tb/tb_w11a_b3.vbom (revision 33) @@ -0,0 +1,7 @@ +# configure tb_basys3 with sys_w11a_b3 target; +# use vhdl configure file (tb_w11a_b3.vhd) to allow +# that all configurations will co-exist in work library +${basys3_aif := ../sys_w11a_b3.vbom} +sys_conf = sys_conf_sim.vhd +../../../../bplib/basys3/tb/tb_basys3.vbom +tb_w11a_b3.vhd Index: basys3/tb/Makefile =================================================================== --- basys3/tb/Makefile (nonexistent) +++ basys3/tb/Makefile (revision 33) @@ -0,0 +1,30 @@ +# $Id: Makefile 649 2015-02-21 21:10:16Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-21 649 1.0 Initial version +# +EXE_all = tb_w11a_b3 +# +include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: basys3/tb/.cvsignore =================================================================== --- basys3/tb/.cvsignore (nonexistent) +++ basys3/tb/.cvsignore (revision 33) @@ -0,0 +1,6 @@ +tb_w11a_b3 +tb_w11a_b3_[so]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_* Index: basys3/tb =================================================================== --- basys3/tb (nonexistent) +++ basys3/tb (revision 33)

basys3/tb Property changes : Added: svn:ignore ## -0,0 +1,39 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_b3 +tb_w11a_b3_[so]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +*.dep_* Index: basys3/sys_w11a_b3.vhd =================================================================== --- basys3/sys_w11a_b3.vhd (nonexistent) +++ basys3/sys_w11a_b3.vhd (revision 33) @@ -0,0 +1,386 @@ +-- $Id: sys_w11a_b3.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2015- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_b3 - syn +-- Description: w11a test design for basys3 +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2line_iob +-- vlib/rlink/rlink_sp1c +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- w11a/pdp11_bram_memctl +-- vlib/rlink/ioleds_sp1c +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_sys_w11a_b3 +-- +-- Target Devices: generic +-- Tool versions: viv 2014.4; ghdl 0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic +-- 2015-06-04 686 2014.4 xc7a35t-1 1919 4372 162 47.5 1408 +TM11 17% +-- 2015-05-14 680 2014.4 xc7a35t-1 1837 4304 162 47.5 1354 +RHRP 17% +-- 2015-02-21 649 2014.4 xc7a35t-1 1637 3767 146 47.5 1195 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 +-- 2015-04-11 666 1.1.1 rearrange XON handling +-- 2015-02-21 649 1.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2015-02-08 644 1.0 Initial version (derived from sys_w11a_n4) +------------------------------------------------------------------------------ +-- +-- w11a test design for basys3 +-- w11a + rlink + serport +-- +-- Usage of Basys 3 Switches, Buttons, LEDs +-- +-- SWI(15:6): no function (only connected to sn_humanio_rbus) +-- SWI(5:4): select DSP +-- 00 abclkdiv & abclkdiv_f +-- 01 PC +-- 10 DISPREG +-- 11 DR emulation +-- SWI(3): select LED display +-- 0 overall status +-- 1 DR emulation +-- SWI(2): unused-reserved (USB port select) +-- SWI(1): 1 enable XON +-- SWI(0): unused-reserved (serial port select) +-- +-- LEDs if SWI(3) = 1 +-- (15:0) DR emulation; shows R0 during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS depending on SWI(4) +-- DSP(3:0) shows DISPREG +-- DP(3:0) shows IO activity +-- (3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_b3 is -- top level + -- implements basys3_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv16; -- b3 switches + I_BTN : in slv5; -- b3 buttons + O_LED : out slv16; -- b3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8 -- 7 segment disp: segments (act.low) + ); +end sys_w11a_b3; + +architecture syn of sys_w11a_b3 is + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce -- usec/msec clock divider ----------- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + I_RXD => I_RXD, + O_TXD => O_TXD + ); + + RLINK : rlink_sp1c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => '0', + RTS_N => open, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + BRAM_CTL: pdp11_bram_memctl -- memory controller ----------------- + generic map ( + MAWIDTH => sys_conf_memctl_mawidth, + NBLOCK => sys_conf_memctl_nblock) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 2) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 2, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + +end syn; Index: basys3/sys_w11a_b3.vbom =================================================================== --- basys3/sys_w11a_b3.vbom (nonexistent) +++ basys3/sys_w11a_b3.vbom (revision 33) @@ -0,0 +1,30 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2line_iob.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../w11a/pdp11_bram_memctl.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +# design +sys_w11a_b3.vhd +@xdc:../../../bplib/basys3/basys3_pclk.xdc +@xdc:../../../bplib/basys3/basys3_pins.xdc Index: basys3/Makefile =================================================================== --- basys3/Makefile (nonexistent) +++ basys3/Makefile (revision 33) @@ -0,0 +1,25 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-08 644 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_basys3.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# Index: basys3/.cvsignore =================================================================== --- basys3/.cvsignore (nonexistent) +++ basys3/.cvsignore (revision 33) @@ -0,0 +1,7 @@ +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* Index: basys3 =================================================================== --- basys3 (nonexistent) +++ basys3 (revision 33)

basys3 Property changes : Added: svn:ignore ## -0,0 +1,40 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* Index: nexys4/sys_conf.vhd =================================================================== --- nexys4/sys_conf.vhd (nonexistent) +++ nexys4/sys_conf.vhd (revision 33) @@ -0,0 +1,101 @@ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n4 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions +-- 2015-02-07 643 1.1 drop bram and minisys options +-- 2013-09-22 534 1.0 Initial version (derived from _n3 version) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +-- valid system clock / delay combinations (see n2_cram_memctl_as.vhd): +-- div mul clksys read0 read1 write +-- 2 1 50.0 2 2 3 +-- 4 3 75.0 4 4 5 (also 70 MHz) +-- 5 4 80.0 5 5 5 +-- 20 17 85.0 5 5 6 +-- 10 9 90.0 6 6 6 (also 95 MHz) +-- 1 1 100.0 6 6 7 + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 5; + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 5; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + + constant sys_conf_ser2rri_cdinit : integer := + (sys_conf_clkser/sys_conf_ser2rri_defbaud)-1; + +end package sys_conf; Index: nexys4/tb/sys_conf_sim.vhd =================================================================== --- nexys4/tb/sys_conf_sim.vhd (nonexistent) +++ nexys4/tb/sys_conf_sim.vhd (revision 33) @@ -0,0 +1,89 @@ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_n4 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions +-- 2015-02-07 643 1.1 drop bram and minisys options +-- 2013-09-34 534 1.0 Initial version (cloned from _n3) +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure clocks -------------------------------------------------------- + constant sys_conf_clksys_vcodivide : positive := 1; + constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz + constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz + constant sys_conf_clksys_gentype : string := "MMCM"; + -- single clock design, clkser = clksys + constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; + constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; + constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; + constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure memory controller --------------------------------------------- + constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz + constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay; + constant sys_conf_memctl_writedelay : positive := 7; + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + + -- derived constants ======================================================= + constant sys_conf_clksys : integer := + ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / + sys_conf_clksys_outdivide; + constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; + + constant sys_conf_clkser : integer := + ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / + sys_conf_clkser_outdivide; + constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; + +end package sys_conf; Index: nexys4/tb/tb_w11a_n4.vhd =================================================================== --- nexys4/tb/tb_w11a_n4.vhd (nonexistent) +++ nexys4/tb/tb_w11a_n4.vhd (revision 33) @@ -0,0 +1,41 @@ +-- $Id: tb_w11a_n4.vhd 644 2015-02-08 22:56:54Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_n4 +-- Description: Configuration for tb_w11a_n4 for tb_nexys4_cram +-- +-- Dependencies: sys_w11a_n4 +-- +-- To test: sys_w11a_n4 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2011-11-25 295 - -.-- - - -:-- +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-02-06 643 1.1 use tb_nexys4_cram now +-- 2013-09-22 432 1.0 Initial version (cloned from _n3) +------------------------------------------------------------------------------ + +configuration tb_w11a_n4 of tb_nexys4_cram is + + for sim + for all : nexys4_cram_aif + use entity work.sys_w11a_n4; + end for; + end for; + +end tb_w11a_n4; Index: nexys4/tb/tb_w11a_n4.vbom =================================================================== --- nexys4/tb/tb_w11a_n4.vbom (nonexistent) +++ nexys4/tb/tb_w11a_n4.vbom (revision 33) @@ -0,0 +1,7 @@ +# configure tb_nexys4_cram with sys_w11a_n4 target; +# use vhdl configure file (tb_w11a_n4.vhd) to allow +# that all configurations will co-exist in work library +nexys4_cram_aif = ../sys_w11a_n4.vbom +sys_conf = sys_conf_sim.vhd +../../../../bplib/nexys4/tb/tb_nexys4_cram.vbom +tb_w11a_n4.vhd Index: nexys4/tb/tbw.dat =================================================================== --- nexys4/tb/tbw.dat (nonexistent) +++ nexys4/tb/tbw.dat (revision 33) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 535 2013-09-29 11:46:25Z mueller $ +# +[tb_w11a_n4] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: nexys4/tb/sys_w11a_n4.ucf_cpp =================================================================== --- nexys4/tb/sys_w11a_n4.ucf_cpp (nonexistent) +++ nexys4/tb/sys_w11a_n4.ucf_cpp (revision 33) @@ -0,0 +1 @@ +link ../sys_w11a_n4.ucf_cpp \ No newline at end of file

nexys4/tb/sys_w11a_n4.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: nexys4/tb/Makefile.ise =================================================================== --- nexys4/tb/Makefile.ise (nonexistent) +++ nexys4/tb/Makefile.ise (revision 33) @@ -0,0 +1,32 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-22 534 1.0 Initial version +# +EXE_all = tb_w11a_n4 +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: nexys4/tb/tb_w11a_n4_ssim.vbom =================================================================== --- nexys4/tb/tb_w11a_n4_ssim.vbom (nonexistent) +++ nexys4/tb/tb_w11a_n4_ssim.vbom (revision 33) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_n4.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +nexys4_cram_aif = sys_w11a_n4_ssim.vhd +tb_w11a_n4.vbom +@top:tb_w11a_n4 Index: nexys4/tb/.cvsignore =================================================================== --- nexys4/tb/.cvsignore (nonexistent) +++ nexys4/tb/.cvsignore (revision 33) @@ -0,0 +1,9 @@ +tb_w11a_n4 +tb_w11a_n4_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n4.ucf +*.dep_ucf_cpp +*.dep_* Index: nexys4/tb/Makefile =================================================================== --- nexys4/tb/Makefile (nonexistent) +++ nexys4/tb/Makefile (revision 33) @@ -0,0 +1,31 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-02-14 646 1.0 Initial version +# 2015-02-01 640 0.1 First draft +# +EXE_all = tb_w11a_n4 +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all all_ssim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +# +clean : viv_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +include $(RETROBASE)/rtl/make_viv/generic_ghdl.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: nexys4/tb =================================================================== --- nexys4/tb (nonexistent) +++ nexys4/tb (revision 33)

nexys4/tb Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_n4 +tb_w11a_n4_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_n4.ucf +*.dep_ucf_cpp +*.dep_* Index: nexys4/sys_w11a_n4.vhd =================================================================== --- nexys4/sys_w11a_n4.vhd (nonexistent) +++ nexys4/sys_w11a_n4.vhd (revision 33) @@ -0,0 +1,437 @@ +-- $Id: sys_w11a_n4.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2013-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_n4 - syn +-- Description: w11a test design for nexys4 +-- +-- Dependencies: vlib/xlib/s7_cmt_sfs +-- vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_4line_iob +-- vlib/rlink/rlink_sp1c +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- bplib/nxcramlib/nx_cram_memctl_as +-- bplib/fx2rlink/ioleds_sp1c +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_sys_w11a_n4 +-- +-- Target Devices: generic +-- Tool versions: ise 14.5-14.7; viv 2014.4; ghdl 0.29-0.31 +-- +-- Synthesized: +-- Date Rev viv Target flop lutl lutm bram slic MHz +-- 2015-06-04 686 2014.4 xc7a100t-1 2111 4541 162 7.5 1469 80 +TM11 +-- 2015-05-14 680 2014.4 xc7a100t-1 2030 4459 162 7.5 1427 80 +-- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80 +-- 2015-02-22 650 i 17.7 xc7a100t-1 1670 3564 124 1508 80 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; ; reset overhaul +-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 +-- 2015-04-11 666 1.4.2 rearrange XON handling +-- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2015-02-07 643 1.4 new DSP+LED layout, use pdp11_dr; drop bram and +-- minisys options; +-- 2015-02-01 641 1.3.1 separate I_BTNRST_N; autobaud on msb of display +-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio +-- 2014-12-24 620 1.2.1 relocate ibus window and hio rbus address +-- 2014-08-28 588 1.2 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit +-- 2013-09-28 535 1.0.1 use proper clock manager +-- 2013-09-22 543 1.0 Initial version (derived from sys_w11a_n3) +------------------------------------------------------------------------------ +-- +-- w11a test design for nexys4 +-- w11a + rlink + serport +-- +-- Usage of Nexys 4 Switches, Buttons, LEDs +-- +-- SWI(15:5): no function (only connected to sn_humanio_rbus) +-- (5): select DSP(7:4) display +-- 0 abclkdiv & abclkdiv_f +-- 1 PC +-- (4): select DSP(3:0) display +-- 0 DISPREG +-- 1 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation +-- (2): unused-reserved (USB port select) +-- (1): 1 enable XON +-- (0): unused-reserved (serial port select) +-- +-- LEDs if SWI(3) = 1 +-- (15:0) DR emulation; shows R0 during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DSP(7:4) shows abclkdiv & abclkdiv_f or PS, depending on SWI(5) +-- DSP(3:0) shows DISPREG or DR emulation, depending on SWI(4) +-- DP(3:0) shows IO activity +-- (3) not SER_MONI.txok (shows tx back preasure) +-- (2) SER_MONI.txact (shows tx activity) +-- (1) not SER_MONI.rxok (shows rx back preasure) +-- (0) SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.xlib.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.nxcramlib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_n4 is -- top level + -- implements nexys4_cram_aif + port ( + I_CLK100 : in slbit; -- 100 MHz clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + O_RTS_N : out slbit; -- rx rts (board view; act.low) + I_CTS_N : in slbit; -- tx cts (board view; act.low) + I_SWI : in slv16; -- n4 switches + I_BTN : in slv5; -- n4 buttons + I_BTNRST_N : in slbit; -- n4 reset button + O_LED : out slv16; -- n4 leds + O_RGBLED0 : out slv3; -- n4 rgb-led 0 + O_RGBLED1 : out slv3; -- n4 rgb-led 1 + O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) + O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- cram: write enable (act.low) + O_MEM_OE_N : out slbit; -- cram: output enable (act.low) + O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) + O_MEM_CLK : out slbit; -- cram: clock + O_MEM_CRE : out slbit; -- cram: command register enable + I_MEM_WAIT : in slbit; -- cram: mem wait + O_MEM_ADDR : out slv23; -- cram: address lines + IO_MEM_DATA : inout slv16 -- cram: data lines + ); +end sys_w11a_n4; + +architecture syn of sys_w11a_n4 is + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal MEM_ADDR_EXT : slv22 := (others=>'0'); + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + signal SWI : slv16 := (others=>'0'); + signal BTN : slv5 := (others=>'0'); + signal LED : slv16 := (others=>'0'); + signal DSP_DAT : slv32 := (others=>'0'); + signal DSP_DP : slv8 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + +begin + + assert (sys_conf_clksys mod 1000000) = 0 + report "assert sys_conf_clksys on MHz grid" + severity failure; + + GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- + generic map ( + VCO_DIVIDE => sys_conf_clksys_vcodivide, + VCO_MULTIPLY => sys_conf_clksys_vcomultiply, + OUT_DIVIDE => sys_conf_clksys_outdivide, + CLKIN_PERIOD => 10.0, + CLKIN_JITTER => 0.01, + STARTUP_WAIT => false, + GEN_TYPE => sys_conf_clksys_gentype) + port map ( + CLKIN => I_CLK100, + CLKFX => CLK, + LOCKED => open + ); + + CLKDIV : clkdivce -- usec/msec clock divider ----------- + generic map ( + CDUWIDTH => 7, + USECDIV => sys_conf_clksys_mhz, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- + port map ( + CLK => CLK, + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD => I_RXD, + O_TXD => O_TXD, + I_CTS_N => I_CTS_N, + O_RTS_N => O_RTS_N + ); + + RLINK : rlink_sp1c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 7, -- 128 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG + ); + + MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) + + CRAM_CTL: nx_cram_memctl_as -- memory controller ----------------- + generic map ( + READ0DELAY => sys_conf_memctl_read0delay, + READ1DELAY => sys_conf_memctl_read1delay, + WRITEDELAY => sys_conf_memctl_writedelay) + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR_EXT, + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADV_N => O_MEM_ADV_N, + O_MEM_CLK => O_MEM_CLK, + O_MEM_CRE => O_MEM_CRE, + I_MEM_WAIT => I_MEM_WAIT, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP(3 downto 0) + ); + DSP_DP(7 downto 4) <= "0010"; + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 3) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- + generic map ( + SWIDTH => 16, + BWIDTH => 5, + LWIDTH => 16, + DCWIDTH => 3, + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + + -- setup unused outputs in nexys4 + O_RGBLED0 <= (others=>'0'); + O_RGBLED1 <= (others=>not I_BTNRST_N); + +end syn; Index: nexys4/sys_w11a_n4.vbom =================================================================== --- nexys4/sys_w11a_n4.vbom (nonexistent) +++ nexys4/sys_w11a_n4.vbom (revision 33) @@ -0,0 +1,34 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/xlib/xlib.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/nxcramlib/nxcramlib.vhd +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +[xst,vsyn,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom +[ghdl]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_4line_iob.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../bplib/nxcramlib/nx_cram_memctl_as.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../ibus/ib_sres_or_2.vbom +# design +sys_w11a_n4.vhd +# constraints +@ucf_cpp: sys_w11a_n4.ucf +@xdc:../../../bplib/nexys4/nexys4_pclk.xdc +@xdc:../../../bplib/nexys4/nexys4_pins.xdc +@xdc:../../../bplib/nexys4/nexys4_pins_cram.xdc Index: nexys4/sys_w11a_n4.ucf_cpp =================================================================== --- nexys4/sys_w11a_n4.ucf_cpp (nonexistent) +++ nexys4/sys_w11a_n4.ucf_cpp (revision 33) @@ -0,0 +1,21 @@ +## $Id: sys_w11a_n4.ucf_cpp 643 2015-02-07 17:41:53Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2013-10-13 540 1.1 add pad->clk constraints +## 2013-09-22 534 1.0 Initial version +## + +NET "I_CLK100" TNM_NET = "I_CLK100"; +TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK100"; +OFFSET = OUT 20 ns AFTER "I_CLK100"; + +## constrain pad->net clock delay +NET CLK TNM = TNM_CLK; +TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns; + +## std board +## +#include "bplib/nexys4/nexys4_pins.ucf" +#include "bplib/nexys4/nexys4_pins_cram.ucf" Index: nexys4/Makefile.ise =================================================================== --- nexys4/Makefile.ise (nonexistent) +++ nexys4/Makefile.ise (revision 33) @@ -0,0 +1,29 @@ +# -*- makefile-gmake -*- +# $Id: Makefile.ise 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2013-09-22 534 1.0 Initial version (derived from _n3 version) +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_ise/xflow_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +#---- +# +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: nexys4/Makefile =================================================================== --- nexys4/Makefile (nonexistent) +++ nexys4/Makefile (revision 33) @@ -0,0 +1,25 @@ +# $Id: Makefile 646 2015-02-15 12:04:55Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2015-01-25 637 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_viv/viv_default_nexys4.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : viv_clean +# +#---- +# +include $(RETROBASE)/rtl/make_viv/generic_vivado.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_vsyn) +endif +# Index: nexys4/.cvsignore =================================================================== --- nexys4/.cvsignore (nonexistent) +++ nexys4/.cvsignore (revision 33) @@ -0,0 +1,12 @@ +sys_w11a_n4.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* Index: nexys4 =================================================================== --- nexys4 (nonexistent) +++ nexys4 (revision 33)

nexys4 Property changes : Added: svn:ignore ## -0,0 +1,45 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +sys_w11a_n4.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf +.Xil +project_mflow +*.jou +*.log +*.rpt +*.dcp +*.dep_* Index: s3board/sys_conf.vhd =================================================================== --- s3board/sys_conf.vhd (nonexistent) +++ s3board/sys_conf.vhd (revision 33) @@ -0,0 +1,64 @@ +-- $Id: sys_conf.vhd 683 2015-05-17 21:54:35Z mueller $ +-- +-- Copyright 2007-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_s3 (for synthesis) +-- +-- Dependencies: - +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions +-- 2014-12-22 619 1.1.2 add _rbmon_awidth +-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce +-- 2008-02-23 118 1.1 add memory config +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200 + constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + +end package sys_conf; Index: s3board/tb/sys_conf_sim.vhd =================================================================== --- s3board/tb/sys_conf_sim.vhd (nonexistent) +++ s3board/tb/sys_conf_sim.vhd (revision 33) @@ -0,0 +1,72 @@ +-- $Id: sys_conf_sim.vhd 683 2015-05-17 21:54:35Z mueller $ +-- +-- Copyright 2007-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Package Name: sys_conf +-- Description: Definitions for sys_w11a_s3 (for simulation) +-- +-- Dependencies: - +-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 +-- Revision History: +-- Date Rev Version Comment +-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions +-- 2014-12-22 619 1.1.2 add _rbmon_awidth +-- 2010-05-05 288 1.1.1 add sys_conf_hio_debounce +-- 2008-02-23 118 1.1 add memory config +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; + +use work.slvtypes.all; + +package sys_conf is + + -- configure rlink and hio interfaces -------------------------------------- + constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim + constant sys_conf_hio_debounce : boolean := false; -- no debouncers + + -- configure debug and monitoring units ------------------------------------ + constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable rbmon + constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable ibmon + + -- configure w11 cpu core -------------------------------------------------- + constant sys_conf_bram : integer := 0; -- no bram, use cache + constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) + constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte +--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) + +-- constant sys_conf_bram : integer := 1; -- bram only +-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) +-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte + + constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled + + -- configure w11 system devices -------------------------------------------- + -- configure character and communication devices + constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 + constant sys_conf_ibd_pc11 : boolean := true; -- PC11 + constant sys_conf_ibd_lp11 : boolean := true; -- LP11 + + -- configure mass storage devices + constant sys_conf_ibd_rk11 : boolean := true; -- RK11 + constant sys_conf_ibd_rl11 : boolean := true; -- RL11 + constant sys_conf_ibd_rhrp : boolean := true; -- RHRP + constant sys_conf_ibd_tm11 : boolean := true; -- TM11 + + -- configure other devices + constant sys_conf_ibd_iist : boolean := true; -- IIST + +end package sys_conf; + Index: s3board/tb/Makefile =================================================================== --- s3board/tb/Makefile (nonexistent) +++ s3board/tb/Makefile (revision 33) @@ -0,0 +1,34 @@ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.3 use includes from rtl/make +# 2010-05-26 295 1.2 rename tb_s3board_pdp11core -> tb_w11a_s3 +# 2007-11-26 98 1.1 add all_ssim and all_tsim targets +# 2007-09-23 84 1.0 Initial version +# +EXE_all = tb_w11a_s3 +# +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +# +.PHONY : all all_ssim all_tsim clean +# +all : $(EXE_all) +all_ssim : $(EXE_all:=_ssim) +all_tsim : $(EXE_all:=_tsim) +# +clean : ise_clean ghdl_clean +# +#----- +# +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +# +VBOM_all = $(wildcard *.vbom) +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +include $(wildcard *.o.dep_ghdl) +endif +# Index: s3board/tb/tb_w11a_s3_ssim.vbom =================================================================== --- s3board/tb/tb_w11a_s3_ssim.vbom (nonexistent) +++ s3board/tb/tb_w11a_s3_ssim.vbom (revision 33) @@ -0,0 +1,6 @@ +# configure for _*sim case +# Note: this tb uses sys_w11a_s3.vbom in local directory +# (not in .. as usual) to allow a tb specific configure !!! +s3board_fusp_aif = sys_w11a_s3_ssim.vhd +tb_w11a_s3.vbom +@top:tb_w11a_s3 Index: s3board/tb/tbw.dat =================================================================== --- s3board/tb/tbw.dat (nonexistent) +++ s3board/tb/tbw.dat (revision 33) @@ -0,0 +1,6 @@ +# $Id: tbw.dat 351 2010-12-30 21:50:54Z mueller $ +# +[tb_w11a_s3] +rlink_cext_fifo_rx = +rlink_cext_fifo_tx = +rlink_cext_conf = Index: s3board/tb/.cvsignore =================================================================== --- s3board/tb/.cvsignore (nonexistent) +++ s3board/tb/.cvsignore (revision 33) @@ -0,0 +1,8 @@ +tb_w11a_s3 +tb_w11a_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_s3.ucf +*.dep_ucf_cpp Index: s3board/tb/tb_w11a_s3.vhd =================================================================== --- s3board/tb/tb_w11a_s3.vhd (nonexistent) +++ s3board/tb/tb_w11a_s3.vhd (revision 33) @@ -0,0 +1,49 @@ +-- $Id: tb_w11a_s3.vhd 314 2010-07-09 17:38:41Z mueller $ +-- +-- Copyright 2007-2010 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: tb_w11a_s3 +-- Description: Configuration for tb_w11a_s3 for tb_s3board_fusp +-- +-- Dependencies: sys_w11a_s3 +-- +-- To test: sys_w11a_s3 +-- +-- Verified (with (#1) ../../tb/tb_rritba_pdp11core_stim.dat +-- (#2) ../../tb/tb_pdp11_core_stim.dat): +-- Date Rev Code ghdl ise Target Comment +-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#2) 91497s; 632m +-- 2007-11-23 97 _tsim 0.26 9.1 J30 xc3s1000 d:ok (#1) 3356s; 632m +-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#2) 2227s +-- 2007-11-23 97 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (#1) 82s +-- 2007-10-21 91 - 0.26 - - d:ok (#2) +-- 2007-10-19 90 - 0.26 - - d:ok (#2) +-- 2007-10-19 90 - 0.26 - - d:ok (#1) +-- +-- Revision History: +-- Date Rev Version Comment +-- 2010-05-26 295 1.1.2 rename tb_s3board_pdp11core -> tb_w11a_s3 +-- 2010-05-16 291 1.1.1 use now tb_s3board_fusp +-- 2010-05-02 287 1.1 use now tb_s3board_usp +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ + +configuration tb_w11a_s3 of tb_s3board_fusp is + + for sim + for all : s3board_fusp_aif + use entity work.sys_w11a_s3; + end for; + end for; + +end tb_w11a_s3; Index: s3board/tb/tb_w11a_s3.vbom =================================================================== --- s3board/tb/tb_w11a_s3.vbom (nonexistent) +++ s3board/tb/tb_w11a_s3.vbom (revision 33) @@ -0,0 +1,7 @@ +# configure tb_s3board_fusp with sys_w11a_s3 target; +# use vhdl configure file (tb_w11a_s3.vhd) to allow +# that all configurations will co-exist in work library +s3board_fusp_aif = ../sys_w11a_s3.vbom +sys_conf = sys_conf_sim.vhd +../../../../bplib/s3board/tb/tb_s3board_fusp.vbom +tb_w11a_s3.vhd Index: s3board/tb/sys_w11a_s3.ucf_cpp =================================================================== --- s3board/tb/sys_w11a_s3.ucf_cpp (nonexistent) +++ s3board/tb/sys_w11a_s3.ucf_cpp (revision 33) @@ -0,0 +1 @@ +link ../sys_w11a_s3.ucf_cpp \ No newline at end of file

s3board/tb/sys_w11a_s3.ucf_cpp Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property Index: s3board/tb =================================================================== --- s3board/tb (nonexistent) +++ s3board/tb (revision 33)

s3board/tb Property changes : Added: svn:ignore ## -0,0 +1,41 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +tb_w11a_s3 +tb_w11a_s3_[sft]sim +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +tmu_ofile +sys_w11a_s3.ucf +*.dep_ucf_cpp Index: s3board/sys_w11a_s3.vhd =================================================================== --- s3board/sys_w11a_s3.vhd (nonexistent) +++ s3board/sys_w11a_s3.vhd (revision 33) @@ -0,0 +1,468 @@ +-- $Id: sys_w11a_s3.vhd 686 2015-06-04 21:08:08Z mueller $ +-- +-- Copyright 2007-2015 by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sys_w11a_s3 - syn +-- Description: w11a test design for s3board +-- +-- Dependencies: vlib/genlib/clkdivce +-- bplib/bpgen/bp_rs232_2l4l_iob +-- vlib/rlink/rlink_sp1c +-- w11a/pdp11_sys70 +-- ibus/ibdr_maxisys +-- bplib/s3board/s3_sram_memctl +-- vlib/rlink/ioleds_sp1c +-- w11a/pdp11_hio70 +-- bplib/bpgen/sn_humanio_rbus +-- vlib/rbus/rb_sres_or_2 +-- +-- Test bench: tb/tb_sys_w11a_s3 +-- +-- Target Devices: generic +-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 +-- +-- Synthesized (xst): +-- Date Rev ise Target flop lutl lutm slic t peri +-- 2015-06-04 686 14.7 131013 xc3s1000-4 2158 6453 350 3975 OK: +TM11 51% +-- 2015-05-14 680 14.7 131013 xc3s1000-4 2087 6316 350 3928 OK: +RHRP 51% +-- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11 +-- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon +-- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4 +-- 2014-06-08 561 14.7 131013 xc3s1000-4 1374 4580 286 2776 OK: +RL11 +-- 2014-06-01 558 14.7 131013 xc3s1000-4 1301 4306 270 2614 OK: +-- 2011-12-21 442 13.1 O40d xc3s1000-4 1301 4307 270 2613 OK: LP+PC+DL+II +-- 2011-11-19 427 13.1 O40d xc3s1000-4 1322 4298 242 2616 OK: LP+PC+DL+II +-- 2010-12-30 351 12.1 M53d xc3s1000-4 1316 4291 242 2609 OK: LP+PC+DL+II +-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II +-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II +-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II +-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II +-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II +-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 1250 4097 224 2494 OK: LP+PC+DL+II +-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 1209 3986 224 2425 OK: LP+PC+DL+II +-- 2009-05-17 216 10.1.03 K39 xc3s1000-4 1039 3542 224 2116 m+p; TIME OK +-- 2009-05-09 213 10.1.03 K39 xc3s1000-4 1037 3500 224 2100 m+p; TIME OK +-- 2009-04-26 209 8.2.03 I34 xc3s1000-4 1099 3557 224 2264 m+p; TIME OK +-- 2008-12-13 176 8.2.03 I34 xc3s1000-4 1116 3672 224 2280 m+p; TIME OK +-- 2008-12-06 174 10.1.02 K37 xc3s1000-4 1038 3503 224 2100 m+p; TIME OK +-- 2008-12-06 174 8.2.03 I34 xc3s1000-4 1116 3682 224 2281 m+p; TIME OK +-- 2008-08-22 161 8.2.03 I34 xc3s1000-4 1118 3677 224 2288 m+p; TIME OK +-- 2008-08-22 161 10.1.02 K37 xc3s1000-4 1035 3488 224 2086 m+p; TIME OK +-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3344 224 2119 m+p; 21ns;BR-32 +-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3357 224 2128 m+p; 21ns;BR-16 +-- 2008-05-01 140 8.2.03 I34 xc3s1000-4 1057 3509 224 2220 m+p; TIME OK +-- 2008-05-01 140 9.2.04 J40 xc3s200-4 1009 3195 224 1918 m+p; T-OK;BR-16 +-- 2008-03-19 127 8.2.03 I34 xc3s1000-4 1077 3471 224 2207 m+p; TIME OK +-- 2008-03-02 122 8.2.03 I34 xc3s1000-4 1068 3448 224 2179 m+p; TIME OK +-- 2008-03-02 121 8.2.03 I34 xc3s1000-4 1064 3418 224 2148 m+p; TIME FAIL +-- 2008-02-24 119 8.2.03 I34 xc3s1000-4 1071 3372 224 2141 m+p; TIME OK +-- 2008-02-23 118 8.2.03 I34 xc3s1000-4 1035 3301 182 1996 m+p; TIME OK +-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK +-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8 +-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK +-- Note: till 2010-10-24 lutm included 'route-thru', after only logic +-- +-- Revision History: +-- Date Rev Version Comment +-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul +-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form +-- 2015-04-11 666 1.7.1 rearrange XON handling +-- 2015-02-21 649 1.7 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) +-- 2014-12-24 620 1.6.2 relocate ibus window and hio rbus address +-- 2014-12-22 619 1.6.1 add rbus monitor rbd_rbmon +-- 2014-08-28 588 1.6 use new rlink v4 iface and 4 bit STAT +-- 2014-08-15 583 1.5 rb_mreq addr now 16 bit +-- 2011-12-21 442 1.4.4 use rlink_sp1c; hio led usage now a for n2/n3 +-- 2011-11-19 427 1.4.3 now numeric_std clean +-- 2011-07-09 391 1.4.2 use now bp_rs232_2l4l_iob +-- 2011-07-08 390 1.4.1 use now sn_humanio +-- 2010-12-30 351 1.4 ported to rbv3 +-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50 +-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM; +-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...) +-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS; +-- remove pdp11_ibdr_rri +-- 2010-06-13 305 1.6.1 add CP_ADDR, wire up pdp11_core_rri->pdp11_core +-- 2010-06-11 303 1.6 use IB_MREQ.racc instead of RRI_REQ +-- 2010-06-03 300 1.5.6 use default FAWIDTH for rri_core_serport +-- 2010-05-28 295 1.5.5 rename sys_pdp11core -> sys_w11a_s3 +-- 2010-05-21 292 1.5.4 rename _PM1_ -> _FUSP_ +-- 2010-05-16 291 1.5.3 rename memctl_s3sram->s3_sram_memctl +-- 2010-05-05 288 1.5.2 add sys_conf_hio_debounce +-- 2010-05-02 287 1.5.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM +-- drop RP_IINT from interfaces; drop RTSFLUSH generic +-- add pm1 rs232 (usp) support +-- 2010-05-01 285 1.5 port to rri V2 interface, use rri_core_serport +-- 2010-04-17 278 1.4.5 rename sram_dummy -> s3_sram_dummy +-- 2010-04-10 275 1.4.4 use s3_humanio; invert DP(1,3) +-- 2009-07-12 233 1.4.3 adapt to ibdr_(mini|maxi)sys interface changes +-- 2009-06-01 221 1.4.2 support ibdr_maxisys as well as _minisys +-- 2009-05-10 214 1.4.1 use pdp11_tmu_sb instead of pdp11_tmu +-- 2008-08-22 161 1.4.0 use iblib, ibdlib; renames +-- 2008-05-03 143 1.3.6 rename _cpursta->_cpurust +-- 2008-05-01 142 1.3.5 reassign LED(cpugo,halt,rust) and DISP(dispreg) +-- 2008-04-19 137 1.3.4 add DM_STAT_(DP|VM|CO|SY) signals, add pdp11_tmu +-- 2008-04-18 136 1.3.3 add RESET for ibdr_minisys +-- 2008-04-13 135 1.3.2 add _mem70 also for _bram configs +-- 2008-02-23 118 1.3.1 add _mem70 +-- 2008-02-17 117 1.3 use ext. memory interface of _core; +-- use _cache + memctl or _bram (configurable) +-- 2008-01-20 113 1.2.1 finalize AP_LAM handling (0=cpu,1=dl11;4=rk05) +-- 2008-01-20 112 1.2 rename clkgen->clkdivce; use ibdr_minisys, BRESET +-- add _ib_mux2 +-- 2008-01-06 111 1.1 use now iob_reg_*; remove rricp_pdp11core hack +-- instanciate all parts directly +-- 2007-12-23 105 1.0.4 add rritb_cpmon_sb +-- 2007-12-16 101 1.0.3 use _N for active low; set IOB attribute to RI/RO +-- 2007-12-09 100 1.0.2 add sram memory signals, dummy handle them +-- 2007-10-19 90 1.0.1 init RI_RXD,RO_TXD=1 to avoid startup glitch +-- 2007-09-23 84 1.0 Initial version +------------------------------------------------------------------------------ +-- +-- w11a test design for s3board +-- w11a + rlink + serport +-- +-- Usage of S3BOARD Switches, Buttons, LEDs: +-- +-- SWI(7:6): no function (only connected to sn_humanio_rbus) +-- (5:4): select DSP +-- 00 abclkdiv & abclkdiv_f +-- 01 PC +-- 10 DISPREG +-- 11 DR emulation +-- (3): select LED display +-- 0 overall status +-- 1 DR emulation +-- (2) 0 -> int/ext RS242 port for rlink +-- 1 -> use USB interface for rlink +-- (1): 1 enable XON +-- (0): 0 -> main board RS232 port +-- 1 -> Pmod B/top RS232 port +-- +-- LEDs if SWI(3) = 1 +-- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70 +-- +-- LEDs if SWI(3) = 0 +-- (7) MEM_ACT_W +-- (6) MEM_ACT_R +-- (5) cmdbusy (all rlink access, mostly rdma) +-- (4:0) if cpugo=1 show cpu mode activity +-- (4) kernel mode, pri>0 +-- (3) kernel mode, pri=0 +-- (2) kernel mode, wait +-- (1) supervisor mode +-- (0) user mode +-- if cpugo=0 shows cpurust +-- (4) '1' +-- (3:0) cpurust code +-- +-- DP(3): not SER_MONI.txok (shows tx back preasure) +-- DP(2): SER_MONI.txact (shows tx activity) +-- DP(1): not SER_MONI.rxok (shows rx back preasure) +-- DP(0): SER_MONI.rxact (shows rx activity) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.slvtypes.all; +use work.genlib.all; +use work.serportlib.all; +use work.rblib.all; +use work.rlinklib.all; +use work.bpgenlib.all; +use work.bpgenrbuslib.all; +use work.s3boardlib.all; +use work.iblib.all; +use work.ibdlib.all; +use work.pdp11.all; +use work.sys_conf.all; + +-- ---------------------------------------------------------------------------- + +entity sys_w11a_s3 is -- top level + -- implements s3board_fusp_aif + port ( + I_CLK50 : in slbit; -- 50 MHz board clock + I_RXD : in slbit; -- receive data (board view) + O_TXD : out slbit; -- transmit data (board view) + I_SWI : in slv8; -- s3 switches + I_BTN : in slv4; -- s3 buttons + O_LED : out slv8; -- s3 leds + O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) + O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) + O_MEM_CE_N : out slv2; -- sram: chip enables (act.low) + O_MEM_BE_N : out slv4; -- sram: byte enables (act.low) + O_MEM_WE_N : out slbit; -- sram: write enable (act.low) + O_MEM_OE_N : out slbit; -- sram: output enable (act.low) + O_MEM_ADDR : out slv18; -- sram: address lines + IO_MEM_DATA : inout slv32; -- sram: data lines + O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n + I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n + I_FUSP_RXD : in slbit; -- fusp: rs232 rx + O_FUSP_TXD : out slbit -- fusp: rs232 tx + ); +end sys_w11a_s3; + +architecture syn of sys_w11a_s3 is + + signal CLK : slbit := '0'; + + signal RESET : slbit := '0'; + signal CE_USEC : slbit := '0'; + signal CE_MSEC : slbit := '0'; + + signal RXD : slbit := '1'; + signal TXD : slbit := '0'; + signal RTS_N : slbit := '0'; + signal CTS_N : slbit := '0'; + + signal RB_MREQ : rb_mreq_type := rb_mreq_init; + signal RB_SRES : rb_sres_type := rb_sres_init; + signal RB_SRES_CPU : rb_sres_type := rb_sres_init; + signal RB_SRES_HIO : rb_sres_type := rb_sres_init; + + signal RB_LAM : slv16 := (others=>'0'); + signal RB_STAT : slv4 := (others=>'0'); + + signal SER_MONI : serport_moni_type := serport_moni_init; + + signal SWI : slv8 := (others=>'0'); + signal BTN : slv4 := (others=>'0'); + signal LED : slv8 := (others=>'0'); + signal DSP_DAT : slv16 := (others=>'0'); + signal DSP_DP : slv4 := (others=>'0'); + + signal GRESET : slbit := '0'; -- general reset (from rbus) + signal CRESET : slbit := '0'; -- cpu reset (from cp) + signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) + signal ITIMER : slbit := '0'; + + signal EI_PRI : slv3 := (others=>'0'); + signal EI_VECT : slv9_2 := (others=>'0'); + signal EI_ACKM : slbit := '0'; + + signal CP_STAT : cp_stat_type := cp_stat_init; + signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init; + + signal MEM_REQ : slbit := '0'; + signal MEM_WE : slbit := '0'; + signal MEM_BUSY : slbit := '0'; + signal MEM_ACK_R : slbit := '0'; + signal MEM_ACT_R : slbit := '0'; + signal MEM_ACT_W : slbit := '0'; + signal MEM_ADDR : slv20 := (others=>'0'); + signal MEM_BE : slv4 := (others=>'0'); + signal MEM_DI : slv32 := (others=>'0'); + signal MEM_DO : slv32 := (others=>'0'); + + signal IB_MREQ : ib_mreq_type := ib_mreq_init; + signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; + + signal DISPREG : slv16 := (others=>'0'); + signal STATLEDS : slv8 := (others=>'0'); + signal ABCLKDIV : slv16 := (others=>'0'); + + constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx + constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0004: 1111 1110 1111 00xx + +begin + + CLK <= I_CLK50; -- use 50MHz as system clock + + CLKDIV : clkdivce -- usec/msec clock divider ----------- + generic map ( + CDUWIDTH => 6, + USECDIV => 50, + MSECDIV => 1000) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC + ); + + IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- + port map ( + CLK => CLK, + RESET => '0', + SEL => SWI(0), + RXD => RXD, + TXD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + I_RXD0 => I_RXD, + O_TXD0 => O_TXD, + I_RXD1 => I_FUSP_RXD, + O_TXD1 => O_FUSP_TXD, + I_CTS1_N => I_FUSP_CTS_N, + O_RTS1_N => O_FUSP_RTS_N + ); + + RLINK : rlink_sp1c -- rlink for serport ----------------- + generic map ( + BTOWIDTH => 6, -- 64 cycles access timeout + RTAWIDTH => 12, + SYSID => (others=>'0'), + IFAWIDTH => 5, -- 32 word input fifo + OFAWIDTH => 5, -- 32 word output fifo + ENAPIN_RLMON => sbcntl_sbf_rlmon, + ENAPIN_RBMON => sbcntl_sbf_rbmon, + CDWIDTH => 13, + CDINIT => sys_conf_ser2rri_cdinit, + RBMON_AWIDTH => sys_conf_rbmon_awidth, + RBMON_RBADDR => rbaddr_rbmon) + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + CE_INT => CE_MSEC, + RESET => RESET, + ENAXON => SWI(1), + ESCFILL => '0', + RXSD => RXD, + TXSD => TXD, + CTS_N => CTS_N, + RTS_N => RTS_N, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + RB_LAM => RB_LAM, + RB_STAT => RB_STAT, + RL_MONI => open, + SER_MONI => SER_MONI + ); + + SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_CPU, + RB_STAT => RB_STAT, + RB_LAM_CPU => RB_LAM(0), + GRESET => GRESET, + CRESET => CRESET, + BRESET => BRESET, + CP_STAT => CP_STAT, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + EI_ACKM => EI_ACKM, + ITIMER => ITIMER, + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + MEM_REQ => MEM_REQ, + MEM_WE => MEM_WE, + MEM_BUSY => MEM_BUSY, + MEM_ACK_R => MEM_ACK_R, + MEM_ADDR => MEM_ADDR, + MEM_BE => MEM_BE, + MEM_DI => MEM_DI, + MEM_DO => MEM_DO, + DM_STAT_DP => DM_STAT_DP + ); + + IBDR_SYS : ibdr_maxisys -- IO system ------------------------- + port map ( + CLK => CLK, + CE_USEC => CE_USEC, + CE_MSEC => CE_MSEC, + RESET => GRESET, + BRESET => BRESET, + ITIMER => ITIMER, + CPUSUSP => CP_STAT.cpususp, + RB_LAM => RB_LAM(15 downto 1), + IB_MREQ => IB_MREQ, + IB_SRES => IB_SRES_IBDR, + EI_ACKM => EI_ACKM, + EI_PRI => EI_PRI, + EI_VECT => EI_VECT, + DISPREG => DISPREG); + + SRAM_CTL: s3_sram_memctl -- memory controller ----------------- + port map ( + CLK => CLK, + RESET => GRESET, + REQ => MEM_REQ, + WE => MEM_WE, + BUSY => MEM_BUSY, + ACK_R => MEM_ACK_R, + ACK_W => open, + ACT_R => MEM_ACT_R, + ACT_W => MEM_ACT_W, + ADDR => MEM_ADDR(17 downto 0), + BE => MEM_BE, + DI => MEM_DI, + DO => MEM_DO, + O_MEM_CE_N => O_MEM_CE_N, + O_MEM_BE_N => O_MEM_BE_N, + O_MEM_WE_N => O_MEM_WE_N, + O_MEM_OE_N => O_MEM_OE_N, + O_MEM_ADDR => O_MEM_ADDR, + IO_MEM_DATA => IO_MEM_DATA + ); + + LED_IO : ioleds_sp1c -- hio leds from serport ------------- + port map ( + SER_MONI => SER_MONI, + IOLEDS => DSP_DP + ); + + ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; + + HIO70 : pdp11_hio70 -- hio from sys70 -------------------- + generic map ( + LWIDTH => LED'length, + DCWIDTH => 2) + port map ( + SEL_LED => SWI(3), + SEL_DSP => SWI(5 downto 4), + MEM_ACT_R => MEM_ACT_R, + MEM_ACT_W => MEM_ACT_W, + CP_STAT => CP_STAT, + DM_STAT_DP => DM_STAT_DP, + ABCLKDIV => ABCLKDIV, + DISPREG => DISPREG, + LED => LED, + DSP_DAT => DSP_DAT + ); + + HIO : sn_humanio_rbus -- hio manager ----------------------- + generic map ( + DEBOUNCE => sys_conf_hio_debounce, + RB_ADDR => rbaddr_hio) + port map ( + CLK => CLK, + RESET => RESET, + CE_MSEC => CE_MSEC, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES_HIO, + SWI => SWI, + BTN => BTN, + LED => LED, + DSP_DAT => DSP_DAT, + DSP_DP => DSP_DP, + I_SWI => I_SWI, + I_BTN => I_BTN, + O_LED => O_LED, + O_ANO_N => O_ANO_N, + O_SEG_N => O_SEG_N + ); + + RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- + port map ( + RB_SRES_1 => RB_SRES_CPU, + RB_SRES_2 => RB_SRES_HIO, + RB_SRES_OR => RB_SRES + ); + +end syn; Index: s3board/sys_w11a_s3.vbom =================================================================== --- s3board/sys_w11a_s3.vbom (nonexistent) +++ s3board/sys_w11a_s3.vbom (revision 33) @@ -0,0 +1,27 @@ +# libs +../../../vlib/slvtypes.vhd +../../../vlib/genlib/genlib.vhd +../../../vlib/serport/serportlib.vbom +../../../vlib/rbus/rblib.vhd +../../../vlib/rlink/rlinklib.vbom +../../../bplib/bpgen/bpgenlib.vbom +../../../bplib/bpgen/bpgenrbuslib.vbom +../../../bplib/s3board/s3boardlib.vbom +../../../ibus/iblib.vhd +../../../ibus/ibdlib.vhd +../../../w11a/pdp11.vhd +sys_conf = sys_conf.vhd +# components +../../../vlib/genlib/clkdivce.vbom +../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom +../../../vlib/rlink/rlink_sp1c.vbom +../../../w11a/pdp11_sys70.vbom +../../../ibus/ibdr_maxisys.vbom +../../../bplib/s3board/s3_sram_memctl.vbom +../../../vlib/rlink/ioleds_sp1c.vbom +../../../w11a/pdp11_hio70.vbom +../../../bplib/bpgen/sn_humanio_rbus.vbom +../../../vlib/rbus/rb_sres_or_2.vbom +# design +sys_w11a_s3.vhd +@ucf_cpp: sys_w11a_s3.ucf Index: s3board/Makefile =================================================================== --- s3board/Makefile (nonexistent) +++ s3board/Makefile (revision 33) @@ -0,0 +1,39 @@ +# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ +# +# Revision History: +# Date Rev Version Comment +# 2011-08-13 405 1.2 use includes from rtl/make +# 2010-05-28 295 1.1.4 rename sys_pdp11core -> sys_w11a_s3 +# 2010-04-24 282 1.1.3 use %.impact rule, all=BIT_all now +# 2009-11-20 251 1.1.2 add .mcs rule +# 2009-07-26 236 1.1.1 add program: rule +# 2007-11-26 98 1.1 include $(RETROBASE)/vlib/Makefile.(ghdl|xflow) +# 2007-07-08 65 1.0 Initial version +# +VBOM_all = $(wildcard *.vbom) +BIT_all = $(VBOM_all:.vbom=.bit) +# +include $(RETROBASE)/rtl/make_ise/xflow_default_s3board.mk +# +.PHONY : all clean +# +all : $(BIT_all) +# +clean : ise_clean + rm -f $(VBOM_all:.vbom=.ucf) +# +sys_w11a_s3.mcs : sys_w11a_s3.bit + promgen -w -x xcf04s -p mcs -u 0 sys_w11a_s3 + mv sys_w11a_s3.prm sys_w11a_s3_prm.log + mv sys_w11a_s3.cfi sys_w11a_s3_cfi.log +# +#---- +# +include $(RETROBASE)/rtl/make_ise/generic_xflow.mk +include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk +# +ifndef DONTINCDEP +include $(VBOM_all:.vbom=.dep_xst) +include $(VBOM_all:.vbom=.dep_ghdl) +endif +# Index: s3board/.cvsignore =================================================================== --- s3board/.cvsignore (nonexistent) +++ s3board/.cvsignore (revision 33) @@ -0,0 +1,5 @@ +sys_w11a_s3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: s3board/sys_w11a_s3.mfset =================================================================== --- s3board/sys_w11a_s3.mfset (nonexistent) +++ s3board/sys_w11a_s3.mfset (revision 33) @@ -0,0 +1,120 @@ +# $Id: sys_w11a_s3.mfset 442 2011-12-23 10:03:28Z mueller $ +# +# ---------------------------------------------------------------------------- +[xst] +INFO:.*Mux is complete : default of case is discarded + +Node of sequential type is unconnected +Node of sequential type is unconnected +Node of sequential type is unconnected + +Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' +Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen' +Unconnected output port 'ACK_W' of component 's3_sram_memctl' + +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input is never used +Input > is never used +Input > is never used +Input is never used +Input > is never used +Input is never used +Input is never used +Input > is never used +Input is never used +Input > is never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used + +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal is assigned but never used +Signal > is assigned but never used + +Signal > is assigned but never used + +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent +FF/Latch in Unit is equivalent + +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 +FF/Latch has a constant value of 0 + +# +# ---------------------------------------------------------------------------- +[tra] + +# +# ---------------------------------------------------------------------------- +[map] +There is a dangling output parity pin +INFO:.* + +# +# ---------------------------------------------------------------------------- +[par] + +# +# ---------------------------------------------------------------------------- +[bgn] +There is a dangling output parity pin Index: s3board/sys_w11a_s3.ucf_cpp =================================================================== --- s3board/sys_w11a_s3.ucf_cpp (nonexistent) +++ s3board/sys_w11a_s3.ucf_cpp (revision 33) @@ -0,0 +1,22 @@ +## $Id: sys_w11a_s3.ucf_cpp 336 2010-11-06 18:28:27Z mueller $ +## +## Revision History: +## Date Rev Version Comment +## 2010-11-06 336 2.0.1 rename input pin CLK -> I_CLK50 +## 2010-05-02 287 2.0 added defs for pm1 rs232 +## 2007-12-16 101 1.1 converted to ucf_cpp, factor out std pins +## 2007-12-09 100 1.0 Initial version +## + +NET "I_CLK50" TNM_NET = "I_CLK50"; +TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %; +OFFSET = IN 10 ns BEFORE "I_CLK50"; +OFFSET = OUT 20 ns AFTER "I_CLK50"; + +## std board +## +#include "bplib/s3board/s3board_pins.ucf" +## +## Pmod1-RS232 on A2 connector +## +#include "bplib/s3board/s3board_a2_pm1_rs232.ucf" Index: s3board =================================================================== --- s3board (nonexistent) +++ s3board (revision 33)

s3board Property changes : Added: svn:ignore ## -0,0 +1,38 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +sys_w11a_s3.ucf +*.dep_ucf_cpp +log_* +_impact* +*.svf Index: tb/.cvsignore =================================================================== --- tb/.cvsignore (nonexistent) +++ tb/.cvsignore (revision 33) @@ -0,0 +1,14 @@ +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +to_ptp +to_lda +tmu_ofile +*.dsk +*.log +*.log.gz +*.lst +*.lda +lpt.dat +ptp.dat +*.LOG Index: tb =================================================================== --- tb (nonexistent) +++ tb (revision 33)

tb Property changes : Added: svn:ignore ## -0,0 +1,47 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +rlink_cext_fifo_rx +rlink_cext_fifo_tx +rlink_cext_conf +to_ptp +to_lda +tmu_ofile +*.dsk +*.log +*.log.gz +*.lst +*.lda +lpt.dat +ptp.dat +*.LOG Index: . =================================================================== --- . (nonexistent) +++ . (revision 33)

. Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log