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- from Rev 30 to Rev 33
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Rev 30 → Rev 33
/rbd_rbmon.vhd
0,0 → 1,461
-- $Id: rbd_rbmon.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rbd_rbmon - syn |
-- Description: rbus dev: rbus monitor |
-- |
-- Dependencies: memlib/ram_1swsr_wfirst_gen |
-- |
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo |
-- |
-- Target Devices: generic |
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2014-12-22 619 14.7 131013 xc6slx16-2 114 209 - 72 s 5.6 |
-- 2014-12-21 593 14.7 131013 xc6slx16-2 99 207 - 77 s 7.0 |
-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue |
-- 2014-12-22 619 5.0 reorganized, supports now 16 bit addresses |
-- 2014-09-13 593 4.1 change default address -> ffe8 |
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit (but only 8 bit recorded) |
-- 2011-11-19 427 1.0.3 now numeric_std clean |
-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles |
-- 2010-12-31 352 1.0.1 simplify irb_ack logic |
-- 2010-12-27 349 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- Addr Bits Name r/w/f Function |
-- 000 cntl r/w/f Control register |
-- 02 wena r/w/- wrap enable |
-- 01 stop r/w/f writing 1 stops moni |
-- 00 start r/w/f writing 1 starts moni and clears addr |
-- 001 stat r/w/- Status register |
-- 15:13 bsize r/-/- buffer size (AWIDTH-9) |
-- 00 wrap r/-/- line address wrapped (cleared on go) |
-- 010 hilim r/w/- upper address limit, inclusive (def: 0xfffb) |
-- 011 lolim r/w/- lower address limit, inclusive (def: 0x0000) |
-- 100 addr r/w/- Address register |
-- *:02 laddr r/w/- line address |
-- 01:00 waddr r/w/- word address |
-- 101 data r/w/- Data register |
-- |
-- data format: |
-- word 3 15 : burst (2nd re/we in a aval sequence) |
-- 14 : tout (busy in last re-we cycle) |
-- 13 : nak (no ack in last non-busy cycle) |
-- 12 : ack (ack seen) |
-- 11 : busy (busy seen) |
-- 10 : err (err seen) |
-- 09 : we (write cycle) |
-- 08 : init (init cycle) |
-- 07:00 : delay to prev (msb's) |
-- word 2 15:10 : delay to prev (lsb's) |
-- 09:00 : number of busy cycles |
-- word 1 : data |
-- word 0 : addr |
-- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.memlib.all; |
use work.rblib.all; |
|
-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates |
-- to control the instantiation. ghdl checks even for not instantiated |
-- entities the validity of generics, that's why natural needed here .... |
|
entity rbd_rbmon is -- rbus dev: rbus monitor |
generic ( |
RB_ADDR : slv16 := slv(to_unsigned(16#ffe8#,16)); |
AWIDTH : natural := 9); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor) |
); |
end entity rbd_rbmon; |
|
|
architecture syn of rbd_rbmon is |
|
constant rbaddr_cntl : slv3 := "000"; -- cntl address offset |
constant rbaddr_stat : slv3 := "001"; -- stat address offset |
constant rbaddr_hilim : slv3 := "010"; -- hilim address offset |
constant rbaddr_lolim : slv3 := "011"; -- lolim address offset |
constant rbaddr_addr : slv3 := "100"; -- addr address offset |
constant rbaddr_data : slv3 := "101"; -- data address offset |
|
constant cntl_rbf_wena : integer := 2; |
constant cntl_rbf_stop : integer := 1; |
constant cntl_rbf_start : integer := 0; |
subtype stat_rbf_bsize is integer range 15 downto 13; |
constant stat_rbf_wrap : integer := 0; |
subtype addr_rbf_laddr is integer range 2+AWIDTH-1 downto 2; |
subtype addr_rbf_waddr is integer range 1 downto 0; |
|
constant dat3_rbf_burst : integer := 15; |
constant dat3_rbf_tout : integer := 14; |
constant dat3_rbf_nak : integer := 13; |
constant dat3_rbf_ack : integer := 12; |
constant dat3_rbf_busy : integer := 11; |
constant dat3_rbf_err : integer := 10; |
constant dat3_rbf_we : integer := 9; |
constant dat3_rbf_init : integer := 8; |
subtype dat3_rbf_ndlymsb is integer range 7 downto 0; |
subtype dat2_rbf_ndlylsb is integer range 15 downto 10; |
subtype dat2_rbf_nbusy is integer range 9 downto 0; |
|
type regs_type is record -- state registers |
rbsel : slbit; -- rbus select |
wena : slbit; -- wena flag (wrap enable) |
go : slbit; -- go flag |
hilim : slv16; -- upper address limit |
lolim : slv16; -- lower address limit |
wrap : slbit; -- laddr wrap flag |
laddr : slv(AWIDTH-1 downto 0); -- line address |
waddr : slv2; -- word address |
rbtake_1 : slbit; -- rb capture active in last cycle |
rbaddr : slv16; -- rbus trace: addr |
rbinit : slbit; -- rbus trace: init |
rbwe : slbit; -- rbus trace: we |
rback : slbit; -- rbus trace: ack seen |
rbbusy : slbit; -- rbus trace: busy seen |
rberr : slbit; -- rbus trace: err seen |
rbnak : slbit; -- rbus trace: nak detected |
rbtout : slbit; -- rbus trace: tout detected |
rbburst : slbit; -- rbus trace: burst detected |
rbdata : slv16; -- rbus trace: data |
rbnbusy : slv10; -- rbus number of busy cycles |
rbndly : slv14; -- rbus delay to prev. access |
end record regs_type; |
|
constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0'); |
constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1'); |
|
constant regs_init : regs_type := ( |
'0', -- rbsel |
'0','0', -- wena,go |
x"fffb", -- hilim (def: fffb) |
x"0000", -- lolim (def: 0000) |
'0', -- wrap |
laddrzero, -- laddr |
"00", -- waddr |
'0', -- rbtake_1 |
(others=>'0'), -- rbaddr |
'0','0','0','0','0', -- rbinit,rbwe,rback,rbbusy,rberr |
'0','0','0', -- rbnak,rbtout,rbburst |
(others=>'0'), -- rbdata |
(others=>'0'), -- rbnbusy |
(others=>'0') -- rbndly |
); |
|
constant rbnbusylast : slv10 := (others=>'1'); |
constant rbndlylast : slv14 := (others=>'1'); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
signal BRAM_EN : slbit := '0'; |
signal BRAM_WE : slbit := '0'; |
signal BRAM0_DI : slv32 := (others=>'0'); |
signal BRAM1_DI : slv32 := (others=>'0'); |
signal BRAM0_DO : slv32 := (others=>'0'); |
signal BRAM1_DO : slv32 := (others=>'0'); |
|
begin |
|
assert AWIDTH>=9 and AWIDTH<=14 |
report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH" |
severity failure; |
|
BRAM1 : ram_1swsr_wfirst_gen |
generic map ( |
AWIDTH => AWIDTH, |
DWIDTH => 32) |
port map ( |
CLK => CLK, |
EN => BRAM_EN, |
WE => BRAM_WE, |
ADDR => R_REGS.laddr, |
DI => BRAM1_DI, |
DO => BRAM1_DO |
); |
|
BRAM0 : ram_1swsr_wfirst_gen |
generic map ( |
AWIDTH => AWIDTH, |
DWIDTH => 32) |
port map ( |
CLK => CLK, |
EN => BRAM_EN, |
WE => BRAM_WE, |
ADDR => R_REGS.laddr, |
DI => BRAM0_DI, |
DO => BRAM0_DO |
); |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, RB_MREQ, RB_SRES_SUM, BRAM0_DO, BRAM1_DO) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable irb_ack : slbit := '0'; |
variable irb_busy : slbit := '0'; |
variable irb_err : slbit := '0'; |
variable irb_dout : slv16 := (others=>'0'); |
variable irbena : slbit := '0'; |
variable ibramen : slbit := '0'; -- BRAM enable |
variable ibramwe : slbit := '0'; -- BRAN we |
variable rbtake : slbit := '0'; |
variable laddr_inc : slbit := '0'; |
variable idat0 : slv16 := (others=>'0'); |
variable idat1 : slv16 := (others=>'0'); |
variable idat2 : slv16 := (others=>'0'); |
variable idat3 : slv16 := (others=>'0'); |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
irb_ack := '0'; |
irb_busy := '0'; |
irb_err := '0'; |
irb_dout := (others=>'0'); |
|
irbena := RB_MREQ.re or RB_MREQ.we; |
|
ibramen := '0'; |
ibramwe := '0'; |
|
laddr_inc := '0'; |
|
-- rbus address decoder |
n.rbsel := '0'; |
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then |
n.rbsel := '1'; |
ibramen := '1'; |
end if; |
|
-- rbus transactions |
if r.rbsel = '1' then |
|
irb_ack := irbena; -- ack all accesses |
|
case RB_MREQ.addr(2 downto 0) is |
|
when rbaddr_cntl => -- cntl ------------------ |
if RB_MREQ.we = '1' then |
n.wena := RB_MREQ.din(cntl_rbf_wena); |
if RB_MREQ.din(cntl_rbf_start) = '1' then |
n.go := '1'; |
n.wrap := '0'; |
n.laddr := laddrzero; |
n.waddr := "00"; |
end if; |
if RB_MREQ.din(cntl_rbf_stop) = '1' then |
n.go := '0'; |
end if; |
end if; |
|
when rbaddr_stat => null; -- stat ------------------ |
|
when rbaddr_hilim => -- hilim ----------------- |
if RB_MREQ.we = '1' then |
n.hilim := RB_MREQ.din; |
end if; |
|
when rbaddr_lolim => -- lolim ----------------- |
if RB_MREQ.we = '1' then |
n.lolim := RB_MREQ.din; |
end if; |
|
when rbaddr_addr => -- addr ------------------ |
if RB_MREQ.we = '1' then |
n.go := '0'; |
n.wrap := '0'; |
n.laddr := RB_MREQ.din(addr_rbf_laddr); |
n.waddr := RB_MREQ.din(addr_rbf_waddr); |
end if; |
|
when rbaddr_data => -- data ------------------ |
if r.go='1' or RB_MREQ.we='1' then |
irb_err := '1'; |
end if; |
if RB_MREQ.re = '1' then |
n.waddr := slv(unsigned(r.waddr) + 1); |
if r.waddr = "11" then |
laddr_inc := '1'; |
end if; |
end if; |
|
when others => -- <> -------------------- |
irb_err := '1'; |
|
end case; |
end if; |
|
-- rbus output driver |
if r.rbsel = '1' then |
case RB_MREQ.addr(2 downto 0) is |
when rbaddr_cntl => -- cntl ------------------ |
irb_dout(cntl_rbf_wena) := r.wena; |
irb_dout(cntl_rbf_start) := r.go; |
when rbaddr_stat => -- stat ------------------ |
irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-9,3)); |
irb_dout(stat_rbf_wrap) := r.wrap; |
when rbaddr_hilim => -- hilim ----------------- |
irb_dout := r.hilim; |
when rbaddr_lolim => -- lolim ----------------- |
irb_dout := r.lolim; |
when rbaddr_addr => -- addr ------------------ |
irb_dout(addr_rbf_laddr) := r.laddr; |
irb_dout(addr_rbf_waddr) := r.waddr; |
when rbaddr_data => -- data ------------------ |
case r.waddr is |
when "11" => irb_dout := BRAM1_DO(31 downto 16); |
when "10" => irb_dout := BRAM1_DO(15 downto 0); |
when "01" => irb_dout := BRAM0_DO(31 downto 16); |
when "00" => irb_dout := BRAM0_DO(15 downto 0); |
when others => null; |
end case; |
when others => null; |
end case; |
end if; |
|
-- rbus monitor |
-- a rbus transaction are captured if the address is in alim window |
-- and the access is not refering to rbd_rbmon itself |
|
rbtake := '0'; |
if RB_MREQ.aval='1' and irbena='1' then -- aval and (re or we) |
if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window |
unsigned(RB_MREQ.addr)<=unsigned(r.hilim) and |
r.rbsel='0' then -- and not self |
rbtake := '1'; |
end if; |
end if; |
if RB_MREQ.init = '1' then -- also take init's |
rbtake := '1'; |
end if; |
|
if rbtake = '1' then -- if capture active |
n.rbaddr := RB_MREQ.addr; -- keep track of some state |
n.rbinit := RB_MREQ.init; |
n.rbwe := RB_MREQ.we; |
if RB_MREQ.init='1' or RB_MREQ.we='1' then -- for write/init of din |
n.rbdata := RB_MREQ.din; |
else -- for read of dout |
n.rbdata := RB_SRES_SUM.dout; |
end if; |
|
if r.rbtake_1 = '0' then -- if initial cycle of a transaction |
n.rback := RB_SRES_SUM.ack; |
n.rbbusy := RB_SRES_SUM.busy; |
n.rberr := RB_SRES_SUM.err; |
n.rbnbusy := (others=>'0'); |
else -- if non-initial cycles |
if RB_SRES_SUM.err = '1' then -- keep track of err flags |
n.rberr := '1'; |
end if; |
if r.rbnbusy /= rbnbusylast then -- and count |
n.rbnbusy := slv(unsigned(r.rbnbusy) + 1); |
end if; |
end if; |
n.rbnak := not RB_SRES_SUM.ack; |
n.rbtout := RB_SRES_SUM.busy; |
|
else -- if capture not active |
if r.go='1' and r.rbtake_1='1' then -- active and transaction just ended |
ibramen := '1'; |
ibramwe := '1'; |
laddr_inc := '1'; |
n.rbburst := '1'; -- assume burst |
end if; |
if r.rbtake_1 = '1' then -- rbus transaction just ended |
n.rbndly := (others=>'0'); -- clear delay counter |
else -- just idle |
if r.rbndly /= rbndlylast then -- count cycles |
n.rbndly := slv(unsigned(r.rbndly) + 1); |
end if; |
end if; |
end if; |
|
if RB_MREQ.aval = '0' then -- if aval gone |
n.rbburst := '0'; -- clear burst flag |
end if; |
|
if laddr_inc = '1' then |
n.laddr := slv(unsigned(r.laddr) + 1); |
if r.go='1' and r.laddr=laddrlast then |
if r.wena = '1' then |
n.wrap := '1'; |
else |
n.go := '0'; |
end if; |
end if; |
end if; |
|
idat3 := (others=>'0'); |
idat3(dat3_rbf_burst) := r.rbburst; |
idat3(dat3_rbf_tout) := r.rbtout; |
idat3(dat3_rbf_nak) := r.rbnak; |
idat3(dat3_rbf_ack) := r.rback; |
idat3(dat3_rbf_busy) := r.rbbusy; |
idat3(dat3_rbf_err) := r.rberr; |
idat3(dat3_rbf_we) := r.rbwe; |
idat3(dat3_rbf_init) := r.rbinit; |
idat3(dat3_rbf_ndlymsb):= r.rbndly(13 downto 6); |
idat2(dat2_rbf_ndlylsb):= r.rbndly( 5 downto 0); |
idat2(dat2_rbf_nbusy) := r.rbnbusy; |
idat1 := r.rbdata; |
idat0 := r.rbaddr; |
|
n.rbtake_1 := rbtake; |
|
N_REGS <= n; |
|
BRAM_EN <= ibramen; |
BRAM_WE <= ibramwe; |
|
BRAM1_DI <= idat3 & idat2; |
BRAM0_DI <= idat1 & idat0; |
|
RB_SRES.dout <= irb_dout; |
RB_SRES.ack <= irb_ack; |
RB_SRES.err <= irb_err; |
RB_SRES.busy <= irb_busy; |
|
end process proc_next; |
|
end syn; |
/rbdlib.vhd
0,0 → 1,116
-- $Id: rbdlib.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: rbdlib |
-- Description: Definitions for rbus devices |
-- |
-- Dependencies: - |
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-09-13 593 4.0 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit |
-- 2011-11-19 427 1.2.1 now numeric_std clean |
-- 2010-12-29 351 1.2 new address layout; add rbd_timer |
-- 2010-12-27 349 1.1 now correct defs for _rbmon and _eyemon |
-- 2010-12-04 343 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- two devices have standard addresses |
-- rbd_rbmon x"ffe8" |
-- rbd_tester x"ffe0" |
-- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
|
package rbdlib is |
|
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/8: 1111 1111 1110 1xxx |
constant rbaddr_tester : slv16 := x"ffe0"; -- ffe0/8: 1111 1111 1110 0xxx |
|
component rbd_tester is -- rbus dev: rbus tester |
-- complete rbus_aif interface |
generic ( |
RB_ADDR : slv16 := rbaddr_tester); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
RB_LAM : out slv16; -- rbus: look at me |
RB_STAT : out slv4 -- rbus: status flags |
); |
end component; |
|
component rbd_rbmon is -- rbus dev: rbus monitor |
generic ( |
RB_ADDR : slv16 := rbaddr_rbmon; |
AWIDTH : natural := 9); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor) |
); |
end component; |
|
component rbd_eyemon is -- rbus dev: eye monitor for serport's |
generic ( |
RB_ADDR : slv16 := (others=>'0'); |
RDIV : slv8 := (others=>'0')); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
RXSD : in slbit; -- rx: serial data |
RXACT : in slbit -- rx: active (start seen) |
); |
end component; |
|
component rbd_bram is -- rbus dev: bram test target |
-- incomplete rbus_aif interface |
generic ( |
RB_ADDR : slv16 := (others=>'0')); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type -- rbus: response |
); |
end component; |
|
component rbd_timer is -- rbus dev: usec precision timer |
generic ( |
RB_ADDR : slv16 := (others=>'0')); |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
DONE : out slbit; -- mark last timer cycle |
BUSY : out slbit -- timer running |
); |
end component; |
|
end package rbdlib; |
/rb_sres_or_2.vbom
0,0 → 1,7
# libs |
../slvtypes.vhd |
rblib.vhd |
# components |
[sim]rb_sres_or_mon.vbom |
# design |
rb_sres_or_2.vhd |
/rb_sres_or_3.vbom
0,0 → 1,7
# libs |
../slvtypes.vhd |
rblib.vhd |
# components |
[sim]rb_sres_or_mon.vbom |
# design |
rb_sres_or_3.vhd |
/rb_sres_or_4.vbom
0,0 → 1,7
# libs |
../slvtypes.vhd |
rblib.vhd |
# components |
[sim]rb_sres_or_mon.vbom |
# design |
rb_sres_or_4.vhd |
/rbd_eyemon.vbom
0,0 → 1,9
# libs |
../slvtypes.vhd |
../memlib/memlib.vhd |
rblib.vhd |
# components |
[sim]../memlib/ram_2swsr_wfirst_gen.vbom |
[xst,vsyn]../memlib/ram_2swsr_wfirst_gen_unisim.vbom |
# design |
rbd_eyemon.vhd |
/rb_sel.vhd
0,0 → 1,70
-- $Id: rb_sel.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rb_sel - syn |
-- Description: rbus: address select logic |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.29-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit |
-- 2010-12-26 349 1.0 Initial version (cloned from ibus/ib_sel) |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity rb_sel is -- rbus address select logic |
generic ( |
RB_ADDR : slv16; -- rbus address base |
SAWIDTH : natural := 0); -- device subaddress space width |
port ( |
CLK : in slbit; -- clock |
RB_MREQ : in rb_mreq_type; -- ibus request |
SEL : out slbit -- select state bit |
); |
end rb_sel; |
|
architecture syn of rb_sel is |
signal R_SEL : slbit := '0'; |
begin |
|
assert SAWIDTH<=15 -- at most 32k word devices |
report "assert(SAWIDTH<=15)" severity failure; |
|
proc_regs: process (CLK) |
variable isel : slbit := '0'; |
begin |
if rising_edge(CLK) then |
isel := '0'; |
if RB_MREQ.aval='1' and |
RB_MREQ.addr(15 downto SAWIDTH)=RB_ADDR(15 downto SAWIDTH) then |
isel := '1'; |
end if; |
R_SEL <= isel; |
end if; |
end process proc_regs; |
|
SEL <= R_SEL; |
|
end syn; |
/rb_sres_or_mon.vhd
0,0 → 1,111
-- $Id: rb_sres_or_mon.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rb_sres_or_mon - sim |
-- Description: rbus result or monitor |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Tool versions: ghdl 0.29-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-12-23 347 3.0 rename rritb_sres_or_mon->rb_sres_or_mon |
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches) |
-- 2010-06-26 309 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity rb_sres_or_mon is -- rbus result or monitor |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4 |
); |
end rb_sres_or_mon; |
|
architecture sim of rb_sres_or_mon is |
|
begin |
|
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, RB_SRES_4) |
constant dzero : slv16 := (others=>'0'); |
variable oline : line; |
variable nack : integer := 0; |
variable nbusy : integer := 0; |
variable nerr : integer := 0; |
variable ndout : integer := 0; |
begin |
|
nack := 0; |
nbusy := 0; |
nerr := 0; |
ndout := 0; |
|
if RB_SRES_1.ack /= '0' then nack := nack + 1; end if; |
if RB_SRES_2.ack /= '0' then nack := nack + 1; end if; |
if RB_SRES_3.ack /= '0' then nack := nack + 1; end if; |
if RB_SRES_4.ack /= '0' then nack := nack + 1; end if; |
|
if RB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if; |
if RB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if; |
if RB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if; |
if RB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if; |
|
if RB_SRES_1.err /= '0' then nerr := nerr + 1; end if; |
if RB_SRES_2.err /= '0' then nerr := nerr + 1; end if; |
if RB_SRES_3.err /= '0' then nerr := nerr + 1; end if; |
if RB_SRES_4.err /= '0' then nerr := nerr + 1; end if; |
|
if RB_SRES_1.dout /= dzero then ndout := ndout + 1; end if; |
if RB_SRES_2.dout /= dzero then ndout := ndout + 1; end if; |
if RB_SRES_3.dout /= dzero then ndout := ndout + 1; end if; |
if RB_SRES_4.dout /= dzero then ndout := ndout + 1; end if; |
|
if now > 0 ns and (nack>1 or nbusy>1 or nerr>1 or ndout>1) then |
write(oline, now, right, 12); |
if nack > 1 then |
write(oline, string'(" #ack=")); |
write(oline, nack); |
end if; |
if nbusy > 1 then |
write(oline, string'(" #busy=")); |
write(oline, nbusy); |
end if; |
if nerr > 1 then |
write(oline, string'(" #err=")); |
write(oline, nerr); |
end if; |
if ndout > 1 then |
write(oline, string'(" #dout=")); |
write(oline, ndout); |
end if; |
write(oline, string'(" FAIL in ")); |
write(oline, rb_sres_or_mon'path_name); |
writeline(output, oline); |
end if; |
|
end process proc_comb; |
|
end sim; |
/rb_sres_or_2.vhd
0,0 → 1,75
-- $Id: rb_sres_or_2.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rb_sres_or_2 - syn |
-- Description: rbus result or, 2 input |
-- |
-- Dependencies: rb_sres_or_mon [sim only] |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: ise 8.114.7; viv 2014.4; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon |
-- 2010-06-26 309 1.1 add rritb_sres_or_mon |
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_ |
-- 2008-01-20 113 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity rb_sres_or_2 is -- rbus result or, 2 input |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 |
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output |
); |
end rb_sres_or_2; |
|
architecture syn of rb_sres_or_2 is |
|
begin |
|
proc_comb : process (RB_SRES_1, RB_SRES_2) |
begin |
|
RB_SRES_OR.ack <= RB_SRES_1.ack or |
RB_SRES_2.ack; |
RB_SRES_OR.busy <= RB_SRES_1.busy or |
RB_SRES_2.busy; |
RB_SRES_OR.err <= RB_SRES_1.err or |
RB_SRES_2.err; |
RB_SRES_OR.dout <= RB_SRES_1.dout or |
RB_SRES_2.dout; |
|
end process proc_comb; |
|
-- synthesis translate_off |
ORMON : rb_sres_or_mon |
port map ( |
RB_SRES_1 => RB_SRES_1, |
RB_SRES_2 => RB_SRES_2, |
RB_SRES_3 => rb_sres_init, |
RB_SRES_4 => rb_sres_init |
); |
-- synthesis translate_on |
|
end syn; |
/rb_sres_or_3.vhd
0,0 → 1,80
-- $Id: rb_sres_or_3.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rb_sres_or_3 - syn |
-- Description: rbus result or, 3 input |
-- |
-- Dependencies: rb_sres_or_mon [sim only] |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon |
-- 2010-06-26 309 1.1 add rritb_sres_or_mon |
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_ |
-- 2008-01-20 113 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity rb_sres_or_3 is -- rbus result or, 3 input |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output |
); |
end rb_sres_or_3; |
|
architecture syn of rb_sres_or_3 is |
|
begin |
|
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3) |
begin |
|
RB_SRES_OR.ack <= RB_SRES_1.ack or |
RB_SRES_2.ack or |
RB_SRES_3.ack; |
RB_SRES_OR.busy <= RB_SRES_1.busy or |
RB_SRES_2.busy or |
RB_SRES_3.busy; |
RB_SRES_OR.err <= RB_SRES_1.err or |
RB_SRES_2.err or |
RB_SRES_3.err; |
RB_SRES_OR.dout <= RB_SRES_1.dout or |
RB_SRES_2.dout or |
RB_SRES_3.dout; |
|
end process proc_comb; |
|
-- synthesis translate_off |
ORMON : rb_sres_or_mon |
port map ( |
RB_SRES_1 => RB_SRES_1, |
RB_SRES_2 => RB_SRES_2, |
RB_SRES_3 => RB_SRES_3, |
RB_SRES_4 => rb_sres_init |
); |
-- synthesis translate_on |
|
end syn; |
/rb_sres_or_4.vhd
0,0 → 1,85
-- $Id: rb_sres_or_4.vhd 649 2015-02-21 21:10:16Z mueller $ |
-- |
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rb_sres_or_4 - syn |
-- Description: rbus result or, 4 input |
-- |
-- Dependencies: rb_sres_or_mon [sim only] |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: xst 8.114.7; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon |
-- 2010-06-26 309 1.1 add rritb_sres_or_mon |
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_ |
-- 2008-01-20 113 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
|
-- ---------------------------------------------------------------------------- |
|
entity rb_sres_or_4 is -- rbus result or, 4 input |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 |
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output |
); |
end rb_sres_or_4; |
|
architecture syn of rb_sres_or_4 is |
|
begin |
|
proc_comb : process (RB_SRES_1, RB_SRES_2, RB_SRES_3, RB_SRES_4) |
begin |
|
RB_SRES_OR.ack <= RB_SRES_1.ack or |
RB_SRES_2.ack or |
RB_SRES_3.ack or |
RB_SRES_4.ack; |
RB_SRES_OR.busy <= RB_SRES_1.busy or |
RB_SRES_2.busy or |
RB_SRES_3.busy or |
RB_SRES_4.busy; |
RB_SRES_OR.err <= RB_SRES_1.err or |
RB_SRES_2.err or |
RB_SRES_3.err or |
RB_SRES_4.err; |
RB_SRES_OR.dout <= RB_SRES_1.dout or |
RB_SRES_2.dout or |
RB_SRES_3.dout or |
RB_SRES_4.dout; |
|
end process proc_comb; |
|
-- synthesis translate_off |
ORMON : rb_sres_or_mon |
port map ( |
RB_SRES_1 => RB_SRES_1, |
RB_SRES_2 => RB_SRES_2, |
RB_SRES_3 => RB_SRES_3, |
RB_SRES_4 => RB_SRES_4 |
); |
-- synthesis translate_on |
|
end syn; |
/rbd_rbmon.vbom
0,0 → 1,9
# libs |
../slvtypes.vhd |
../memlib/memlib.vhd |
rblib.vhd |
# components |
[sim]../memlib/ram_1swsr_wfirst_gen.vbom |
[xst,vsyn]../memlib/ram_1swsr_wfirst_gen_unisim.vbom |
# design |
rbd_rbmon.vhd |
/rbd_bram.vbom
0,0 → 1,9
# libs |
../slvtypes.vhd |
../memlib/memlib.vhd |
rblib.vhd |
# components |
[sim]../memlib/ram_1swsr_wfirst_gen.vbom |
[xst,vsyn]../memlib/ram_1swsr_wfirst_gen_unisim.vbom |
# design |
rbd_bram.vhd |
/rblib.vhd
0,0 → 1,196
-- $Id: rblib.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- |
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Package Name: rblib |
-- Description: Definitions for rbus interface and bus entities |
-- |
-- Dependencies: - |
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-09-14 593 4.0 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit |
-- 2011-12-23 444 3.1 CLK_CYCLE now integer |
-- 2011-08-13 405 3.0.3 add in direction for FADDR,SEL ports |
-- 2010-12-26 349 3.0.2 add rb_sel |
-- 2010-12-22 346 3.0.1 add rb_mon and rb_mon_sb; |
-- 2010-12-04 343 3.0 extracted from rrilib and rritblib; |
-- rbus V3 interface: use aval,re,we |
-- ... rrilib history removed ... |
-- 2007-09-09 81 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
|
package rblib is |
|
type rb_mreq_type is record -- rbus - master request |
aval : slbit; -- address valid |
re : slbit; -- read enable |
we : slbit; -- write enable |
init : slbit; -- init |
addr : slv16; -- address |
din : slv16; -- data (input to slave) |
end record rb_mreq_type; |
|
constant rb_mreq_init : rb_mreq_type := |
('0','0','0','0', -- aval, re, we, init |
(others=>'0'), -- addr |
(others=>'0')); -- din |
|
type rb_sres_type is record -- rbus - slave response |
ack : slbit; -- acknowledge |
busy : slbit; -- busy |
err : slbit; -- error |
dout : slv16; -- data (output from slave) |
end record rb_sres_type; |
|
constant rb_sres_init : rb_sres_type := |
('0','0','0', -- ack, busy, err |
(others=>'0')); -- dout |
|
component rb_sel is -- rbus address select logic |
generic ( |
RB_ADDR : slv16; -- rbus address base |
SAWIDTH : natural := 0); -- device subaddress space width |
port ( |
CLK : in slbit; -- clock |
RB_MREQ : in rb_mreq_type; -- rbus request |
SEL : out slbit -- select state bit |
); |
end component; |
|
component rb_sres_or_2 is -- rbus result or, 2 input |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 |
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output |
); |
end component; |
component rb_sres_or_3 is -- rbus result or, 3 input |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output |
); |
end component; |
component rb_sres_or_4 is -- rbus result or, 4 input |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_4 : in rb_sres_type := rb_sres_init; -- rb_sres input 4 |
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output |
); |
end component; |
|
component rbus_aif is -- rbus, abstract interface |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit := '0'; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
RB_LAM : out slv16; -- rbus: look at me |
RB_STAT : out slv4 -- rbus: status flags |
); |
end component; |
|
component rb_wreg_rw_3 is -- rbus: wide register r/w 3 bit select |
generic ( |
DWIDTH : positive := 16); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
FADDR : in slv3; -- field address |
SEL : in slbit; -- select |
DATA : out slv(DWIDTH-1 downto 0); -- data |
RB_MREQ : in rb_mreq_type; -- rbus request |
RB_SRES : out rb_sres_type -- rbus response |
); |
end component; |
|
component rb_wreg_w_3 is -- rbus: wide register w-o 3 bit select |
generic ( |
DWIDTH : positive := 16); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
FADDR : in slv3; -- field address |
SEL : in slbit; -- select |
DATA : out slv(DWIDTH-1 downto 0); -- data |
RB_MREQ : in rb_mreq_type; -- rbus request |
RB_SRES : out rb_sres_type -- rbus response |
); |
end component; |
|
component rb_wreg_r_3 is -- rbus: wide register r-o 3 bit select |
generic ( |
DWIDTH : positive := 16); |
port ( |
FADDR : in slv3; -- field address |
SEL : in slbit; -- select |
DATA : in slv(DWIDTH-1 downto 0); -- data |
RB_SRES : out rb_sres_type -- rbus response |
); |
end component; |
|
-- |
-- components for use in test benches (not synthesizable) |
-- |
|
component rb_sres_or_mon is -- rbus result or monitor |
port ( |
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1 |
RB_SRES_2 : in rb_sres_type; -- rb_sres input 2 |
RB_SRES_3 : in rb_sres_type := rb_sres_init; -- rb_sres input 3 |
RB_SRES_4 : in rb_sres_type := rb_sres_init -- rb_sres input 4 |
); |
end component; |
|
-- simbus sb_cntl field usage for rbus |
constant sbcntl_sbf_rbmon : integer := 13; |
|
component rb_mon is -- rbus monitor |
generic ( |
DBASE : positive := 2); -- base for writing data values |
port ( |
CLK : in slbit; -- clock |
CLK_CYCLE : in integer := 0; -- clock cycle number |
ENA : in slbit := '1'; -- enable monitor output |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv4 -- rbus: status flags |
); |
end component; |
|
component rb_mon_sb is -- simbus wrapper for rbus monitor |
generic ( |
DBASE : positive := 2; -- base for writing data values |
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv4 -- rbus: status flags |
); |
end component; |
|
end package rblib; |
/Makefile
0,0 → 1,32
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD |
# 2011-08-13 405 1.1 use includes from rtl/make |
# 2007-12-09 100 1.0.1 drop ISE_p definition |
# 2007-07-06 64 1.0 Initial version |
# |
VBOM_all = $(wildcard *.vbom) |
NGC_all = $(VBOM_all:.vbom=.ngc) |
# |
# reference board for test synthesis is Spartan-6 based Nexys3 |
ifndef XTW_BOARD |
XTW_BOARD=nexys3 |
endif |
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk |
# |
.PHONY : all clean |
# |
all : $(NGC_all) |
# |
clean : ise_clean |
# |
#---- |
# |
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
endif |
# |
/rb_mon_sb.vhd
0,0 → 1,88
-- $Id: rb_mon_sb.vhd 589 2014-08-30 12:43:16Z mueller $ |
-- |
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rb_mon_sb - sim |
-- Description: simbus wrapper for rbus monitor (for tb's) |
-- |
-- Dependencies: simbus |
-- simlib/simclkcnt |
-- rb_mon |
-- Test bench: - |
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-08-28 588 4.0 use new rlink v4 iface and 4 bit STAT |
-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global |
-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb |
-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon |
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT signal from interfaces |
-- use sbcntl_sbf_cpmon def |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2007-12-23 105 1.2 added AP_LAM display |
-- 2007-11-24 98 1.1 added RP_IINT support |
-- 2007-08-27 76 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.simbus.all; |
use work.rblib.all; |
|
entity rb_mon_sb is -- simbus wrapper for rbus monitor |
generic ( |
DBASE : positive := 2; -- base for writing data values |
ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable |
port ( |
CLK : in slbit; -- clock |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv4 -- rbus: status flags |
); |
end rb_mon_sb; |
|
|
architecture sim of rb_mon_sb is |
|
signal ENA : slbit := '0'; |
signal CLK_CYCLE : integer := 0; |
|
begin |
|
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high |
report "assert(ENAPIN in SB_CNTL'range)" severity failure; |
|
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE); |
|
ENA <= to_x01(SB_CNTL(ENAPIN)); |
|
RBMON : rb_mon |
generic map ( |
DBASE => DBASE) |
port map ( |
CLK => CLK, |
CLK_CYCLE => CLK_CYCLE, |
ENA => ENA, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES, |
RB_LAM => RB_LAM, |
RB_STAT => RB_STAT |
); |
|
end sim; |
/rbd_timer.vhd
0,0 → 1,154
-- $Id: rbd_timer.vhd 593 2014-09-14 22:21:33Z mueller $ |
-- |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rbd_timer - syn |
-- Description: rbus dev: usec precision timer |
-- |
-- Dependencies: - |
-- |
-- Test bench: - |
-- |
-- Target Devices: generic |
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-12-29 351 12.1 M53d xc3s1000-4 19 63 - 34 s 7.6 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit |
-- 2011-11-19 427 1.0.1 now numeric_std clean |
-- 2010-12-29 351 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- rbus registers: |
-- |
-- Addr Bits Name r/w/f Function |
-- 0 time r/w/- Timer register |
-- w: if > 0 timer is running |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.rblib.all; |
|
entity rbd_timer is -- rbus dev: usec precision timer |
generic ( |
RB_ADDR : slv16 := (others=>'0')); |
port ( |
CLK : in slbit; -- clock |
CE_USEC : in slbit; -- usec pulse |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
DONE : out slbit; -- 1 cycle pulse when expired |
BUSY : out slbit -- timer running |
); |
end entity rbd_timer; |
|
|
architecture syn of rbd_timer is |
|
type regs_type is record -- state registers |
rbsel : slbit; -- rbus select |
timer : slv16; -- timer value |
timer_act : slbit; -- timer active flag |
timer_end : slbit; -- timer done flag |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- rbsel |
(others=>'0'), -- timer |
'0','0' -- timer_act,timer_end |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
begin |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, CE_USEC, RB_MREQ) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable irb_ack : slbit := '0'; |
variable irb_dout : slv16 := (others=>'0'); |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
irb_ack := '0'; |
irb_dout := (others=>'0'); |
|
-- rbus address decoder |
n.rbsel := '0'; |
if RB_MREQ.aval='1' and RB_MREQ.addr=RB_ADDR then |
n.rbsel := '1'; |
end if; |
|
-- rbus transactions |
if r.rbsel = '1' then |
irb_ack := RB_MREQ.re or RB_MREQ.we; |
|
if RB_MREQ.we = '1' then |
n.timer := RB_MREQ.din; |
n.timer_act := '1'; |
end if; |
if RB_MREQ.re = '1' then |
irb_dout := r.timer; |
end if; |
end if; |
|
-- timer logic |
-- count down when active and 'on-the-usec' |
n.timer_end := '0'; -- ensure end is 1 cycle pulse |
if CE_USEC = '1' then -- if at usec |
if r.timer_act = '1' then -- if timer active |
if unsigned(r.timer) = 0 then -- if timer at end |
n.timer_act := '0'; -- mark unactive |
n.timer_end := '1'; -- send end marker |
else -- else: timer not at end |
n.timer := slv(unsigned(r.timer) - 1); -- decrement |
end if; |
end if; |
end if; |
|
N_REGS <= n; |
|
RB_SRES.dout <= irb_dout; |
RB_SRES.ack <= irb_ack; |
RB_SRES.err <= '0'; |
RB_SRES.busy <= '0'; |
|
DONE <= r.timer_end; |
BUSY <= r.timer_act; |
|
end process proc_next; |
|
end syn; |
/rbd_bram.vhd
0,0 → 1,224
-- $Id: rbd_bram.vhd 593 2014-09-14 22:21:33Z mueller $ |
-- |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rbd_bram - syn |
-- Description: rbus dev: rbus bram test target |
-- |
-- Dependencies: memlib/ram_1swsr_wfirst_gen |
-- |
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo |
-- |
-- Target Devices: generic |
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2010-12-26 349 12.1 M53d xc3s1000-4 23 61 - 34 s 6.3 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-09-13 593 4.1 no default rbus addess anymore, def=0 |
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit |
-- 2011-11-19 427 1.0.3 now numeric_std clean |
-- 2010-12-31 352 1.0.2 simplify irb_ack logic |
-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x |
-- 2010-12-26 349 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- rbus registers: |
-- |
-- Addr Bits Name r/w/f Function |
-- 0 cntl r/w/- Control register |
-- 15:10 nbusy r/w/- busy cycles |
-- 9:00 addr r/w/- bram address (will auto-increment) |
-- 1 15:00 data r/w/- Data register (read/write to bram via addr) |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.memlib.all; |
use work.rblib.all; |
|
entity rbd_bram is -- rbus dev: rbus bram test target |
-- complete rrirp_aif interface |
generic ( |
RB_ADDR : slv16 := (others=>'0')); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type -- rbus: response |
); |
end entity rbd_bram; |
|
|
architecture syn of rbd_bram is |
|
constant rbaddr_cntl : slv1 := "0"; -- cntl address offset |
constant rbaddr_data : slv1 := "1"; -- data address offset |
|
subtype cntl_rbf_nbusy is integer range 15 downto 10; |
subtype cntl_rbf_addr is integer range 9 downto 0; |
|
type regs_type is record -- state registers |
rbsel : slbit; -- rbus select |
addr : slv10; -- addr register |
nbusy : slv6; -- nbusy setting |
cntbusy : slv6; -- busy timer |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0', -- rbsel |
(others=>'0'), -- addr |
(others=>'0'), -- nbusy |
(others=>'0') -- cntbusy |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
signal BRAM_EN : slbit := '0'; |
signal BRAM_WE : slbit := '0'; |
signal BRAM_DO : slv16 := (others=>'0'); |
|
begin |
|
BRAM : ram_1swsr_wfirst_gen |
generic map ( |
AWIDTH => 10, |
DWIDTH => 16) |
port map ( |
CLK => CLK, |
EN => BRAM_EN, |
WE => BRAM_WE, |
ADDR => R_REGS.addr, |
DI => RB_MREQ.din, |
DO => BRAM_DO |
); |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, RB_MREQ, BRAM_DO) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable irb_ack : slbit := '0'; |
variable irb_busy : slbit := '0'; |
variable irb_dout : slv16 := (others=>'0'); |
variable irbena : slbit := '0'; |
variable isbusy : slbit := '0'; |
variable ibramen : slbit := '0'; |
variable ibramwe : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
irb_ack := '0'; |
irb_busy := '0'; |
irb_dout := (others=>'0'); |
|
irbena := RB_MREQ.re or RB_MREQ.we; |
|
isbusy := '0'; |
if unsigned(r.cntbusy) /= 0 then |
isbusy := '1'; |
end if; |
|
ibramen := '0'; |
ibramwe := '0'; |
|
-- rbus address decoder |
n.rbsel := '0'; |
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 1)=RB_ADDR(15 downto 1) then |
|
n.rbsel := '1'; |
ibramen := '1'; |
|
if irbena = '0' then -- addr valid and selected, but no req |
n.cntbusy := r.nbusy; -- preset busy timer |
end if; |
|
end if; |
|
-- rbus transactions |
if r.rbsel = '1' then |
|
if irbena = '1' then -- if request active |
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0 |
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer |
end if; |
end if; |
|
irb_ack := irbena; -- ack all accesses |
|
case RB_MREQ.addr(0 downto 0) is |
|
when rbaddr_cntl => |
if RB_MREQ.we = '1' then |
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy); |
n.addr := RB_MREQ.din(cntl_rbf_addr); |
end if; |
|
when rbaddr_data => |
irb_busy := irbena and isbusy; |
if isbusy = '0' then |
if RB_MREQ.we = '1' then |
ibramwe := '1'; |
end if; |
if irbena = '1' then |
n.addr := slv(unsigned(r.addr) + 1); |
end if; |
end if; |
|
when others => null; |
end case; |
end if; |
|
-- rbus output driver |
if r.rbsel = '1' then |
case RB_MREQ.addr(0 downto 0) is |
when rbaddr_cntl => |
irb_dout(cntl_rbf_nbusy) := r.nbusy; |
irb_dout(cntl_rbf_addr) := r.addr; |
when rbaddr_data => |
irb_dout := BRAM_DO; |
when others => null; |
end case; |
end if; |
|
N_REGS <= n; |
|
BRAM_EN <= ibramen; |
BRAM_WE <= ibramwe; |
|
RB_SRES.dout <= irb_dout; |
RB_SRES.ack <= irb_ack; |
RB_SRES.err <= '0'; |
RB_SRES.busy <= irb_busy; |
|
end process proc_next; |
|
end syn; |
/rb_mon.vhd
0,0 → 1,267
-- $Id: rb_mon.vhd 599 2014-10-25 13:43:56Z mueller $ |
-- |
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rb_mon - sim |
-- Description: rbus monitor (for tb's) |
-- |
-- Dependencies: - |
-- Test bench: - |
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-10-25 599 4.1.1 use writeoptint() |
-- 2014-09-03 591 4.1 add burst counter; add state checker |
-- 2014-08-30 589 4.0 use hex for addr; 4 bit STAT; monitor ACK=0 |
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit |
-- 2011-12-23 444 3.1 CLK_CYCLE now integer |
-- 2011-11-19 427 3.0.1 now numeric_std clean |
-- 2010-12-22 346 3.0 renamed rritb_rbmon -> rb_mon |
-- 2010-06-05 301 2.1.1 renamed _rpmon -> _rbmon |
-- 2010-06-03 299 2.1 new init encoding (WE=0/1 int/ext) |
-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM |
-- drop RP_IINT signal from interfaces |
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface |
-- 2008-03-24 129 1.2.1 CLK_CYCLE now 31 bits |
-- 2007-12-23 105 1.2 added AP_LAM display |
-- 2007-11-24 98 1.1 added RP_IINT support |
-- 2007-08-27 76 1.0 Initial version |
------------------------------------------------------------------------------ |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use ieee.std_logic_textio.all; |
use std.textio.all; |
|
use work.slvtypes.all; |
use work.simlib.all; |
use work.rblib.all; |
|
entity rb_mon is -- rbus monitor (for tb's) |
generic ( |
DBASE : positive := 2); -- base for writing data values |
port ( |
CLK : in slbit; -- clock |
CLK_CYCLE : in integer := 0; -- clock cycle number |
ENA : in slbit := '1'; -- enable monitor output |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : in rb_sres_type; -- rbus: response |
RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me |
RB_STAT : in slv4 -- rbus: status flags |
); |
end rb_mon; |
|
|
architecture sim of rb_mon is |
|
begin |
|
proc_moni: process |
variable oline : line; |
variable nhold : integer := 0; |
variable nburst : integer := 0; |
variable data : slv16 := (others=>'0'); |
variable tag : string(1 to 8) := (others=>' '); |
variable err : slbit := '0'; |
variable r_sel : slbit := '0'; |
|
procedure write_data(L: inout line; |
tag: in string; |
data: in slv16; |
nhold: in integer := 0; |
nburst: in integer := 0; |
cond: in boolean := false; |
ctxt: in string := " ") is |
begin |
writetimestamp(L, CLK_CYCLE, tag); |
writehex(L, RB_MREQ.addr, right, 4); |
write(L, string'(" ")); |
writegen(L, data, right, 0, DBASE); |
write(L, string'(" ")); |
write(L, RB_STAT, right, 4); |
writeoptint(L, " hold=", nhold, 2); |
writeoptint(L, " b=", nburst, 2); |
if cond then |
write(L, ctxt); |
end if; |
writeline(output, L); |
end procedure write_data; |
|
begin |
|
loop |
|
if ENA = '0' then -- if disabled |
wait until ENA='1'; -- stall process till enabled |
end if; |
|
wait until rising_edge(CLK); -- check at end of clock cycle |
|
if RB_MREQ.aval='1' and r_sel='0' then |
nburst := 0; |
end if; |
|
if RB_MREQ.re='1' or RB_MREQ.we='1' then |
if RB_SRES.err = '1' then |
err := '1'; |
end if; |
if RB_SRES.busy = '1' then |
nhold := nhold + 1; |
else |
data := (others=>'0'); |
tag := ": ???? "; |
if RB_MREQ.re = '1' then |
data := RB_SRES.dout; |
tag := ": rbre "; |
end if; |
if RB_MREQ.we = '1' then |
data := RB_MREQ.din; |
tag := ": rbwe "; |
end if; |
|
if RB_SRES.ack = '1' then |
write_data(oline, tag, data, nhold, nburst, err='1', " ERR='1'"); |
else |
write_data(oline, tag, data, nhold, nburst, true, " ACK='0'"); |
end if; |
nburst := nburst + 1; |
nhold := 0; |
end if; |
|
else |
if nhold > 0 then |
write_data(oline, tag, data, nhold, nburst, true, " TIMEOUT"); |
end if; |
nhold := 0; |
err := '0'; |
end if; |
|
if RB_MREQ.init = '1' then -- init |
write_data(oline, ": rbini ", RB_MREQ.din); |
end if; |
|
if unsigned(RB_LAM) /= 0 then |
write_data(oline, ": rblam ", RB_LAM, 0, 0, true, " RB_LAM active"); |
end if; |
|
r_sel := RB_MREQ.aval; |
|
end loop; |
end process proc_moni; |
|
proc_check: process (CLK) |
variable r_sel : slbit := '0'; |
variable r_addr : slv16 := (others=>'0'); |
variable idump : boolean := false; |
variable oline : line; |
begin |
|
if rising_edge(CLK) then |
idump := false; |
|
-- check that addr doesn't change after 1st aval cycle |
if r_sel='1' and RB_MREQ.addr /= r_addr then |
writetimestamp(oline, CLK_CYCLE, |
": FAIL rb_mon: addr changed after aval; initial addr="); |
writehex(oline, r_addr, right, 4); |
writeline(output, oline); |
idump := true; |
end if; |
|
-- check that we,re don't come together in core select time |
-- (aval and r_sel) and not at all outside |
if RB_MREQ.aval='1' and r_sel='1' then |
if RB_MREQ.we='1' and RB_MREQ.re='1' then |
writetimestamp(oline, CLK_CYCLE, |
": FAIL rb_mon: we and re both active"); |
writeline(output, oline); |
idump := true; |
end if; |
if RB_MREQ.init='1' then |
writetimestamp(oline, CLK_CYCLE, |
": FAIL rb_mon: init seen inside select"); |
writeline(output, oline); |
idump := true; |
end if; |
else |
if RB_MREQ.we='1' or RB_MREQ.re='1' then |
writetimestamp(oline, CLK_CYCLE, |
": FAIL rb_mon: no select and we,re seen"); |
writeline(output, oline); |
idump := true; |
end if; |
end if; |
|
-- check that init not seen when aval or select is active |
if RB_MREQ.aval='1' or r_sel='1' then |
if RB_MREQ.init='1' then |
writetimestamp(oline, CLK_CYCLE, |
": FAIL rb_mon: init seen inside aval or select"); |
writeline(output, oline); |
idump := true; |
end if; |
end if; |
|
-- check that SRES isn't touched unless aval or select is active |
if RB_MREQ.aval='0' and r_sel='0' then |
if RB_SRES.dout/=x"0000" or RB_SRES.busy='1' or |
RB_SRES.ack='1' or RB_SRES.err='1' then |
writetimestamp(oline, CLK_CYCLE, |
": FAIL rb_mon: SRES driven outside aval or select"); |
writeline(output, oline); |
idump := true; |
end if; |
end if; |
|
-- dump rbus state in case of any error seen above |
if idump then |
write(oline, string'(" FAIL: MREQ aval=")); |
write(oline, RB_MREQ.aval, right, 1); |
write(oline, string'(" re=")); |
write(oline, RB_MREQ.re , right, 1); |
write(oline, string'(" we=")); |
write(oline, RB_MREQ.we , right, 1); |
write(oline, string'(" init=")); |
write(oline, RB_MREQ.init, right, 1); |
write(oline, string'(" sel=")); |
write(oline, r_sel , right, 1); |
write(oline, string'(" addr=")); |
writehex(oline, RB_MREQ.addr, right, 4); |
write(oline, string'(" din=")); |
writehex(oline, RB_MREQ.din, right, 4); |
writeline(output, oline); |
|
write(oline, string'(" FAIL: SRES ack=")); |
write(oline, RB_SRES.ack , right, 1); |
write(oline, string'(" busy=")); |
write(oline, RB_SRES.busy, right, 1); |
write(oline, string'(" err=")); |
write(oline, RB_SRES.err , right, 1); |
write(oline, string'(" dout=")); |
writehex(oline, RB_SRES.dout, right, 4); |
writeline(output, oline); |
end if; |
|
-- keep track of select state and latch current addr |
if RB_MREQ.aval='1' and r_sel='0' then -- if 1st cycle of aval |
r_addr := RB_MREQ.addr; -- latch addr |
end if; |
-- select simply aval if last cycle (assume all addr are valid) |
r_sel := RB_MREQ.aval; |
end if; |
|
end process proc_check; |
|
end sim; |
/rbd_eyemon.vhd
0,0 → 1,362
-- $Id: rbd_eyemon.vhd 593 2014-09-14 22:21:33Z mueller $ |
-- |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rbd_eyemon - syn |
-- Description: rbus dev: eye monitor for serport's |
-- |
-- Dependencies: memlib/ram_2swsr_wfirst_gen |
-- |
-- Test bench: - |
-- |
-- Target Devices: generic |
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2011-04-02 374 12.1 M53d xc3s1000-4 46 154 - 109 s 8.7 |
-- 2010-12-27 349 12.1 M53d xc3s1000-4 45 147 - 106 s 8.9 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-09-13 593 4.1 no default rbus addess anymore, def=0 |
-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit |
-- 2011-11-19 427 1.0.3 now numeric_std clean |
-- 2011-04-02 375 1.0.2 handle back-to-back chars properly (in sim..) |
-- 2010-12-31 352 1.0.1 simplify irb_ack logic |
-- 2010-12-27 349 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- rbus registers: |
-- |
-- Addr Bits Name r/w/f Function |
-- 00 cntl r/w/- Control register |
-- 03 ena01 r/w/- track 0->1 rxsd transitions |
-- 02 ena10 r/w/- track 1->0 rxsd transitions |
-- 01 clr r/-/f w: writing a 1 starts memory clear |
-- r: 1 indicates clr in progress (512 cyc) |
-- 00 go r/w/- enables monitor |
-- 01 7:00 rdiv r/w/- Sample rate divider |
-- 10 addr r/w/- Address register |
-- 9:01 laddr r/w/ line address |
-- 00 waddr r/w/ word address |
-- 11 15:00 data r/-/- Data register |
-- |
-- data format: |
-- word 1 counter msb's |
-- word 0 counter lsb's |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.memlib.all; |
use work.rblib.all; |
|
entity rbd_eyemon is -- rbus dev: eye monitor for serport's |
generic ( |
RB_ADDR : slv16 := (others=>'0'); |
RDIV : slv8 := (others=>'0')); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
RXSD : in slbit; -- rx: serial data |
RXACT : in slbit -- rx: active (start seen) |
); |
end entity rbd_eyemon; |
|
|
architecture syn of rbd_eyemon is |
|
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset |
constant rbaddr_rdiv : slv2 := "01"; -- rdiv address offset |
constant rbaddr_addr : slv2 := "10"; -- addr address offset |
constant rbaddr_data : slv2 := "11"; -- data address offset |
|
constant cntl_rbf_ena01 : integer := 3; |
constant cntl_rbf_ena10 : integer := 2; |
constant cntl_rbf_clr : integer := 1; |
constant cntl_rbf_go : integer := 0; |
subtype addr_rbf_laddr is integer range 9 downto 1; |
constant addr_rbf_waddr : integer := 0; |
|
type state_type is ( |
s_idle, -- s_idle: wait for char or clr |
s_char, -- s_char: processing a char |
s_clr -- s_clr: clear memory |
); |
|
type regs_type is record -- state registers |
state : state_type; -- state |
rbsel : slbit; -- rbus select |
go : slbit; -- go flag |
clr : slbit; -- clear pending |
ena10 : slbit; -- enable 1->0 |
ena01 : slbit; -- enable 0->1 |
rdiv : slv8; -- rate divider |
laddr : slv9; -- line address |
waddr : slbit; -- word address |
laddr_1 : slv9; -- line address last cycle |
rxsd_1 : slbit; -- rxsd last cycle |
memwe : slbit; -- write bram (clr or inc) |
memclr : slbit; -- write zero into bram |
rdivcnt : slv8; -- rate divider counter |
end record regs_type; |
|
constant regs_init : regs_type := ( |
s_idle, -- state |
'0', -- rbsel |
'0', -- go (default is off) |
'0','0','0', -- clr,ena01,ena10 |
(others=>'0'), -- rdiv |
(others=>'0'), -- laddr |
'0', -- waddr |
(others=>'0'), -- laddr_1 |
'0','0','0', -- rxsd_1,memwe,memclr |
(others=>'0') -- rdivcnt |
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
signal BRAM_ENA : slbit := '0'; |
signal BRAM_DIA : slv32 := (others=>'0'); |
signal BRAM_DIB : slv32 := (others=>'0'); |
signal BRAM_DOA : slv32 := (others=>'0'); |
|
begin |
|
BRAM_DIA <= (others=>'0'); -- always 0, no writes on this port |
|
BRAM : ram_2swsr_wfirst_gen |
generic map ( |
AWIDTH => 9, |
DWIDTH => 32) |
port map ( |
CLKA => CLK, |
CLKB => CLK, |
ENA => BRAM_ENA, |
ENB => R_REGS.memwe, |
WEA => '0', |
WEB => R_REGS.memwe, |
ADDRA => R_REGS.laddr, |
ADDRB => R_REGS.laddr_1, |
DIA => BRAM_DIA, |
DIB => BRAM_DIB, |
DOA => BRAM_DOA, |
DOB => open |
); |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, RB_MREQ, RXSD, RXACT, BRAM_DOA) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable irb_ack : slbit := '0'; |
variable irb_busy : slbit := '0'; |
variable irb_err : slbit := '0'; |
variable irb_dout : slv16 := (others=>'0'); |
variable irbena : slbit := '0'; |
variable ibramen : slbit := '0'; |
variable ibramdi : slv32 := (others=>'0'); |
variable laddr_we : slbit := '0'; |
variable laddr_clr : slbit := '0'; |
variable laddr_inc : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
irb_ack := '0'; |
irb_busy := '0'; |
irb_err := '0'; |
irb_dout := (others=>'0'); |
|
irbena := RB_MREQ.re or RB_MREQ.we; |
|
ibramen := '0'; |
|
laddr_we := '0'; |
laddr_clr := '0'; |
laddr_inc := '0'; |
|
-- rbus address decoder |
n.rbsel := '0'; |
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then |
n.rbsel := '1'; |
ibramen := '1'; |
end if; |
|
-- rbus transactions |
if r.rbsel = '1' then |
|
irb_ack := irbena; -- ack all accesses |
|
case RB_MREQ.addr(1 downto 0) is |
|
when rbaddr_cntl => |
if RB_MREQ.we = '1' then |
n.ena01 := RB_MREQ.din(cntl_rbf_ena01); |
n.ena10 := RB_MREQ.din(cntl_rbf_ena10); |
if RB_MREQ.din(cntl_rbf_clr) = '1' then |
n.clr := '1'; |
end if; |
n.go := RB_MREQ.din(cntl_rbf_go); |
end if; |
|
when rbaddr_rdiv => |
if RB_MREQ.we = '1' then |
n.rdiv := RB_MREQ.din(n.rdiv'range); |
end if; |
|
when rbaddr_addr => |
if RB_MREQ.we = '1' then |
laddr_we := '1'; |
n.waddr := RB_MREQ.din(addr_rbf_waddr); |
end if; |
|
when rbaddr_data => |
if RB_MREQ.we='1' then |
irb_err := '1'; |
end if; |
if RB_MREQ.re = '1' then |
if r.go='0' and r.clr='0' and r.state=s_idle then |
n.waddr := not r.waddr; |
if r.waddr = '1' then |
laddr_inc := '1'; |
end if; |
else |
irb_err := '1'; |
end if; |
end if; |
|
when others => null; |
end case; |
end if; |
|
-- rbus output driver |
if r.rbsel = '1' then |
case RB_MREQ.addr(1 downto 0) is |
when rbaddr_cntl => |
irb_dout(cntl_rbf_ena01) := r.ena01; |
irb_dout(cntl_rbf_ena10) := r.ena10; |
irb_dout(cntl_rbf_clr) := r.clr; |
irb_dout(cntl_rbf_go) := r.go; |
when rbaddr_rdiv => |
irb_dout(r.rdiv'range) := r.rdiv; |
when rbaddr_addr => |
irb_dout(addr_rbf_laddr) := r.laddr; |
irb_dout(addr_rbf_waddr) := r.waddr; |
when rbaddr_data => |
case r.waddr is |
when '1' => irb_dout := BRAM_DOA(31 downto 16); |
when '0' => irb_dout := BRAM_DOA(15 downto 0); |
when others => null; |
end case; |
when others => null; |
end case; |
end if; |
|
-- eye monitor |
n.memwe := '0'; |
n.memclr := '0'; |
|
case r.state is |
when s_idle => -- s_idle: wait for char or clr ------ |
if r.clr = '1' then |
laddr_clr := '1'; |
n.state := s_clr; |
elsif r.go = '1' and RXSD='0' then |
laddr_clr := '1'; |
n.rdivcnt := r.rdiv; |
n.state := s_char; |
end if; |
|
when s_char => -- s_char: processing a char --------- |
if RXACT = '0' then -- uart went unactive |
if RXSD = '1' then -- line idle -> to s_idle |
n.state := s_idle; |
else -- already next start bit seen |
laddr_clr := '1'; -- clear and restart |
n.rdivcnt := r.rdiv; -- happens only in simulation... |
end if; |
else |
if (r.ena01='1' and r.rxsd_1='0' and RXSD='1') or |
(r.ena10='1' and r.rxsd_1='1' and RXSD='0') then |
n.memwe := '1'; |
ibramen := '1'; |
end if; |
end if; |
if unsigned(r.rdiv)=0 or unsigned(r.rdivcnt)=0 then |
n.rdivcnt := r.rdiv; |
if unsigned(r.laddr) /= (2**r.laddr'length)-1 then |
laddr_inc := '1'; |
end if; |
else |
n.rdivcnt := slv(unsigned(r.rdivcnt) - 1); |
end if; |
|
when s_clr => -- s_clr: clear memory --------------- |
laddr_inc := '1'; |
n.memwe := '1'; |
n.memclr := '1'; |
if unsigned(r.laddr) = (2**r.laddr'length)-1 then |
n.clr := '0'; |
n.state := s_idle; |
end if; |
|
when others => null; |
end case; |
|
if laddr_we = '1' then |
n.laddr := RB_MREQ.din(addr_rbf_laddr); |
elsif laddr_clr = '1' then |
n.laddr := (others=>'0'); |
elsif laddr_inc = '1' then |
n.laddr := slv(unsigned(r.laddr) + 1); |
end if; |
|
n.laddr_1 := r.laddr; |
n.rxsd_1 := RXSD; |
|
ibramdi := (others=>'0'); |
if r.memclr = '0' then |
ibramdi := slv(unsigned(BRAM_DOA) + 1); |
end if; |
|
N_REGS <= n; |
|
BRAM_ENA <= ibramen; |
BRAM_DIB <= ibramdi; |
|
RB_SRES.dout <= irb_dout; |
RB_SRES.ack <= irb_ack; |
RB_SRES.err <= irb_err; |
RB_SRES.busy <= irb_busy; |
|
end process proc_next; |
|
end syn; |
/rb_sel.vbom
0,0 → 1,6
# libs |
../slvtypes.vhd |
rblib.vhd |
# components |
# design |
rb_sel.vhd |
/rbd_tester.vhd
0,0 → 1,367
-- $Id: rbd_tester.vhd 593 2014-09-14 22:21:33Z mueller $ |
-- |
-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
-- Software Foundation, either version 2, or at your option any later version. |
-- |
-- This program is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
-- for complete details. |
-- |
------------------------------------------------------------------------------ |
-- Module Name: rbd_tester - syn |
-- Description: rbus dev: rbus tester |
-- |
-- Dependencies: memlib/fifo_1c_dram_raw |
-- |
-- Test bench: rlink/tb/tb_rlink (used as test target) |
-- |
-- Target Devices: generic |
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
-- 2014-08-31 590 14.7 131013 xc6slx16-2 74 162 16 73 s 5.8 ver 4.1 |
-- 2010-12-12 344 12.1 M53d xc3s1000-4 78 204 32 133 s 8.0 |
-- 2010-12-04 343 12.1 M53d xc3s1000-4 75 214 32 136 s 9.3 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2014-09-05 591 4.1 use new iface with 8 regs |
-- 2014-08-30 589 4.0 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit |
-- 2011-11-19 427 1.0.4 now numeric_std clean |
-- 2010-12-31 352 1.0.3 simplify irb_ack logic |
-- 2010-12-29 351 1.0.2 default addr 111101xx->111100xx |
-- 2010-12-12 344 1.0.1 send 0101.. on busy or err; fix init and busy logic |
-- 2010-12-04 343 1.0 Initial version |
------------------------------------------------------------------------------ |
-- |
-- rbus registers: |
-- |
-- Addr Bits Name r/w/f Function |
-- 000 cntl r/w/- Control register |
-- 15 wchk r/w/- write check seen (cleared on data write) |
-- 09:00 nbusy r/w/- busy cycles (for data,dinc,fifo,lnak) |
-- 001 03:00 stat r/w/- status send to RB_STAT |
-- 010 attn -/w/f Attn register: ping RB_LAM lines |
-- 011 09:00 ncyc r/-/- return cycle length of last access |
-- 100 data r/w/- Data register (plain read/write) |
-- 101 dinc r/w/- Data register (autoinc and write check) |
-- 110 fifo r/w/- Fifo interface register |
-- 111 lnak r/w/- delayed ack deassert |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
use work.slvtypes.all; |
use work.memlib.all; |
use work.rblib.all; |
|
entity rbd_tester is -- rbus dev: rbus tester |
-- complete rrirp_aif interface |
generic ( |
RB_ADDR : slv16 := slv(to_unsigned(16#ffe0#,16))); |
port ( |
CLK : in slbit; -- clock |
RESET : in slbit; -- reset |
RB_MREQ : in rb_mreq_type; -- rbus: request |
RB_SRES : out rb_sres_type; -- rbus: response |
RB_LAM : out slv16; -- rbus: look at me |
RB_STAT : out slv4 -- rbus: status flags |
); |
end entity rbd_tester; |
|
|
architecture syn of rbd_tester is |
|
constant awidth : positive := 4; -- fifo address width |
|
constant rbaddr_cntl : slv3 := "000"; -- cntl address offset |
constant rbaddr_stat : slv3 := "001"; -- stat address offset |
constant rbaddr_attn : slv3 := "010"; -- attn address offset |
constant rbaddr_ncyc : slv3 := "011"; -- ncyc address offset |
constant rbaddr_data : slv3 := "100"; -- data address offset |
constant rbaddr_dinc : slv3 := "101"; -- dinc address offset |
constant rbaddr_fifo : slv3 := "110"; -- fifo address offset |
constant rbaddr_lnak : slv3 := "111"; -- lnak address offset |
|
constant cntl_rbf_wchk : integer := 15; |
subtype cntl_rbf_nbusy is integer range 9 downto 0; |
|
constant init_rbf_cntl : integer := 0; |
constant init_rbf_data : integer := 1; |
constant init_rbf_fifo : integer := 2; |
|
type regs_type is record -- state registers |
rbsel : slbit; -- rbus select |
wchk : slbit; -- write check flag |
stat : slv4; -- stat setting |
nbusy : slv10; -- nbusy setting |
data : slv16; -- data register |
act_1 : slbit; -- rbsel and (re or we) in last cycle |
ncyc : slv10; -- cycle length of last access |
cntbusy : slv10; -- busy timer |
cntcyc : slv10; -- cycle length counter |
end record regs_type; |
|
constant regs_init : regs_type := ( |
'0','0', -- rbsel, wchk |
(others=>'0'), -- stat |
(others=>'0'), -- nbusy |
(others=>'0'), -- data |
'0', -- act_1 |
(others=>'0'), -- ncyc |
(others=>'0'), -- cntbusy |
(others=>'0') -- cntcyc |
); |
|
constant cntcyc_max : slv(regs_init.cntcyc'range) := (others=>'1'); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
|
signal FIFO_RESET : slbit := '0'; |
signal FIFO_RE : slbit := '0'; |
signal FIFO_WE : slbit := '0'; |
signal FIFO_EMPTY : slbit := '0'; |
signal FIFO_FULL : slbit := '0'; |
signal FIFO_SIZE : slv(awidth-1 downto 0) := (others=>'0'); |
signal FIFO_DO : slv16 := (others=>'0'); |
|
begin |
|
FIFO : fifo_1c_dram_raw |
generic map ( |
AWIDTH => awidth, |
DWIDTH => 16) |
port map ( |
CLK => CLK, |
RESET => FIFO_RESET, |
RE => FIFO_RE, |
WE => FIFO_WE, |
DI => RB_MREQ.din, |
DO => FIFO_DO, |
SIZE => FIFO_SIZE, |
EMPTY => FIFO_EMPTY, |
FULL => FIFO_FULL |
); |
|
proc_regs: process (CLK) |
begin |
if rising_edge(CLK) then |
if RESET = '1' then |
R_REGS <= regs_init; |
else |
R_REGS <= N_REGS; |
end if; |
end if; |
end process proc_regs; |
|
proc_next : process (R_REGS, RB_MREQ, FIFO_EMPTY, FIFO_FULL, FIFO_DO) |
variable r : regs_type := regs_init; |
variable n : regs_type := regs_init; |
variable irb_ack : slbit := '0'; |
variable irb_busy : slbit := '0'; |
variable irb_err : slbit := '0'; |
variable irb_dout : slv16 := (others=>'0'); |
variable irbena : slbit := '0'; |
variable irblam : slv16 := (others=>'0'); |
variable ififo_re : slbit := '0'; |
variable ififo_we : slbit := '0'; |
variable ififo_reset : slbit := '0'; |
variable isbusy : slbit := '0'; |
begin |
|
r := R_REGS; |
n := R_REGS; |
|
irb_ack := '0'; |
irb_busy := '0'; |
irb_err := '0'; |
irb_dout := (others=>'0'); |
irblam := (others=>'0'); |
|
irbena := RB_MREQ.re or RB_MREQ.we; |
|
ififo_re := '0'; |
ififo_we := '0'; |
ififo_reset := '0'; |
|
isbusy := '0'; |
if unsigned(r.cntbusy) /= 0 then |
isbusy := '1'; |
end if; |
|
-- rbus address decoder |
n.rbsel := '0'; |
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then |
|
n.rbsel := '1'; |
|
if irbena = '0' then -- addr valid and selected, but no req |
n.cntbusy := r.nbusy; -- preset busy timer |
n.cntcyc := (others=>'0'); -- clear cycle length counter |
end if; |
|
end if; |
|
-- rbus transactions |
if r.rbsel = '1' then |
|
if irbena = '1' then -- if request active |
if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0 |
n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer |
end if; |
if r.cntcyc /= cntcyc_max then -- if cycle counter < max |
n.cntcyc := slv(unsigned(r.cntcyc) + 1); -- increment cycle counter |
end if; |
end if; |
|
irb_ack := irbena; -- ack all (some rejects later) |
|
case RB_MREQ.addr(2 downto 0) is |
|
when rbaddr_cntl => |
if RB_MREQ.we='1' then |
n.wchk := RB_MREQ.din(cntl_rbf_wchk); |
n.nbusy := RB_MREQ.din(cntl_rbf_nbusy); |
end if; |
|
when rbaddr_stat => |
if RB_MREQ.we='1' then |
n.stat := RB_MREQ.din(r.stat'range); |
end if; |
|
when rbaddr_attn => |
if RB_MREQ.we = '1' then -- on we |
irblam := RB_MREQ.din; -- ping lam lines |
elsif RB_MREQ.re = '1' then -- on re |
irb_err := '1'; -- reject |
end if; |
|
when rbaddr_ncyc => |
if RB_MREQ.we = '1' then -- on we |
irb_err := '1'; -- reject |
end if; |
|
when rbaddr_data => |
irb_busy := irbena and isbusy; |
if RB_MREQ.we='1' and isbusy='0' then |
n.wchk := '0'; |
n.data := RB_MREQ.din; |
end if; |
|
when rbaddr_dinc => |
irb_busy := irbena and isbusy; |
if RB_MREQ.we = '1' then |
if r.data /= RB_MREQ.din then |
n.wchk := '1'; |
end if; |
end if; |
if (RB_MREQ.re='1' or RB_MREQ.we='1') and isbusy='0' then |
n.data := slv(unsigned(r.data) + 1); |
end if; |
|
when rbaddr_fifo => |
irb_busy := irbena and isbusy; |
if RB_MREQ.re='1' and isbusy='0' then |
if FIFO_EMPTY = '1' then |
irb_err := '1'; |
else |
ififo_re := '1'; |
end if; |
end if; |
if RB_MREQ.we='1' and isbusy='0' then |
if FIFO_FULL = '1' then |
irb_err := '1'; |
else |
ififo_we := '1'; |
end if; |
end if; |
|
when rbaddr_lnak => |
irb_ack := '0'; -- nak it |
if isbusy = '1' then -- or do a delayed nak |
irb_ack := irbena; |
irb_busy := irbena; |
end if; |
|
when others => null; |
end case; |
end if; |
|
-- rbus output driver |
-- send a '0101...' pattern when selected and busy or err |
-- send data only when busy=0 and err=0 |
-- this extra logic allows to debug rlink state machine |
if r.rbsel = '1' then |
irb_dout := "0101010101010101"; -- drive this pattern when selected |
if RB_MREQ.re='1' and irb_busy='0' and irb_err='0' then |
case RB_MREQ.addr(2 downto 0) is |
when rbaddr_cntl => |
irb_dout := (others=>'0'); |
irb_dout(cntl_rbf_wchk) := r.wchk; |
irb_dout(cntl_rbf_nbusy) := r.nbusy; |
when rbaddr_stat => |
irb_dout := (others=>'0'); |
irb_dout(r.stat'range) := r.stat; |
when rbaddr_attn => null; |
when rbaddr_ncyc => |
irb_dout := (others=>'0'); |
irb_dout(r.cntcyc'range) := r.ncyc; |
when rbaddr_data | rbaddr_dinc => |
irb_dout := r.data; |
when rbaddr_fifo => |
if FIFO_EMPTY = '0' then |
irb_dout := FIFO_DO; |
end if; |
when rbaddr_lnak => null; |
when others => null; |
end case; |
end if; |
end if; |
|
-- init transactions |
if RB_MREQ.init='1' and RB_MREQ.addr=RB_ADDR then |
if RB_MREQ.din(init_rbf_cntl) = '1' then |
n.wchk := '0'; |
n.stat := (others=>'0'); |
n.nbusy := (others=>'0'); |
end if; |
if RB_MREQ.din(init_rbf_data) = '1' then |
n.data := (others=>'0'); |
end if; |
if RB_MREQ.din(init_rbf_fifo) = '1' then |
ififo_reset := '1'; |
end if; |
end if; |
|
-- other transactions |
if irbena='0' and r.act_1='1' then |
n.ncyc := r.cntcyc; |
end if; |
n.act_1 := irbena; |
|
N_REGS <= n; |
|
FIFO_RE <= ififo_re; |
FIFO_WE <= ififo_we; |
FIFO_RESET <= ififo_reset; |
|
RB_SRES.dout <= irb_dout; |
RB_SRES.ack <= irb_ack; |
RB_SRES.err <= irb_err; |
RB_SRES.busy <= irb_busy; |
|
RB_LAM <= irblam; |
RB_STAT <= r.stat; |
|
end process proc_next; |
|
end syn; |
/rb_mon_sb.vbom
0,0 → 1,10
# libs |
../slvtypes.vhd |
../simlib/simlib.vhd |
../simlib/simbus.vhd |
rblib.vhd |
# components |
../simlib/simclkcnt.vbom |
rb_mon.vbom |
# design |
rb_mon_sb.vhd |
/rbd_timer.vbom
0,0 → 1,6
# libs |
../slvtypes.vhd |
rblib.vhd |
# components |
# design |
rbd_timer.vhd |
/rbd_tester.vbom
0,0 → 1,8
# libs |
../slvtypes.vhd |
../memlib/memlib.vhd |
rblib.vhd |
# components |
../memlib/fifo_1c_dram_raw.vbom |
# design |
rbd_tester.vhd |
/rb_sres_or_mon.vbom
0,0 → 1,5
# libs |
../slvtypes.vhd |
rblib.vhd |
# design |
rb_sres_or_mon.vhd |
/rb_mon.vbom
0,0 → 1,7
# libs |
../slvtypes.vhd |
../simlib/simlib.vhd |
rblib.vhd |
# components |
# design |
rb_mon.vhd |
.
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log