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    /w11/tags/w11a_V0.7/tools/fx2
    from Rev 29 to Rev 33
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  •

Rev 29 → Rev 33

/src/Makefile
0,0 → 1,196
# $Id: Makefile 638 2015-01-25 22:01:38Z mueller $
#
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
#
# - original copyright and licence disclaimer --------------------------------
# - Copyright 2007 Kolja Waschk, ixo.de
# - This code is part of usbjtag. usbjtag is free software;
#-----------------------------------------------------------------------------
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#-----------------------------------------------------------------------------
#
# Makefile for FX2 Firmware on Digilent Nexys2, Nexys3, and Atlys boards
#
# Revision History:
# Date Rev Version Comment
# 2015-01-25 638 2.1 retire _as versions (old async interface)
# 2014-11-16 604 2.0 add sdcc 3.x migration
# 2012-04-09 461 1.5.1 fixed nexys3_jtag_3fifo_ic.ihx rule,used _2fifo code
# 2012-02-11 457 1.5 re-organize VID/PID and descriptor handling
# 2012-01-02 448 1.4 add support for sync fifo w/ int. clock (_ic)
# 2011-12-29 446 1.3 add nexys3 support
# 2011-07-23 397 1.2 add usb_fifo_init.c
# 2011-07-17 395 1.1 reorganized to support multiple target/fifo configs
# 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)
#-----------------------------------------------------------------------------
#
# handle USB VID/PID
# - normaly given via the environment variables (as 4 digit hex number)
# RETRO_FX2_VID
# RETRO_FX2_PID
#
# - in the retro11 project the default is:
# VID: 16c0 (VOTI)
# PID: 03ef (VOTI free for internal lab use 1007)
#
# !! Important Note on Usage of this USB VID/PID !!
# This VID/PID is owned by VOTI, a small dutch company. Usage is granted
# for 'internal lab use only' by VOTI under the conditions:
# - the gadgets in which you use those PIDs do not leave your desk
# - you won't complain to VOTI if you get in trouble with duplicate PIDs
# (for instance because someone else did not follow the previous rule).
# See also http://www.voti.nl/pids/pidfaq.html
#
# Define default VID/PID -----------------------------------------------
#
ifndef RETRO_FX2_VID
RETRO_FX2_VID = 16c0
endif
ifndef RETRO_FX2_PID
RETRO_FX2_PID = 03ef
endif
#
DEFVIDPID=-DUSE_VID=0x${RETRO_FX2_VID} -DUSE_PID=0x${RETRO_FX2_PID}
#
# defs for sdcc 2.9 to 3.x transition handling -------------------------
#
include sdccdefs.mk
#
# compiler and assembler flags -----------------------------------------
#
LIBDIR=lib
LIB=libfx2.lib
 
CFLAGS+=-mmcs51 --no-xinit-opt -I${LIBDIR}
CFLAGS+=${CC29COMPOPT}
 
ASFLAGS+=-plosgff
 
LDFLAGS=--code-loc 0x0000 --code-size 0x1800
LDFLAGS+=--xram-loc 0x1800 --xram-size 0x0800
LDFLAGS+=-Wl '-b USBDESCSEG = 0xE100'
LDFLAGS+=-L ${LIBDIR}
#
# compile rules
#
%.rel : %.a51
$(AS) $(ASFLAGS) $<
 
%.rel : %.c
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@
#
# link rule
#
%.ihx :
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $+
#
# primary target rules
#
ALLIHX =nexys2_jtag.ihx
ALLIHX +=nexys2_jtag_2fifo_ic.ihx
ALLIHX +=nexys2_jtag_3fifo_ic.ihx
ALLIHX +=nexys3_jtag.ihx
ALLIHX +=nexys3_jtag_2fifo_ic.ihx
ALLIHX +=nexys3_jtag_3fifo_ic.ihx
 
.PHONY: all install
 
all: $(ALLIHX)
 
install: $(ALLIHX)
cp -p $(ALLIHX) ../bin
#
# rules to create USB descriptor sources
#
CPPA51=cpp -P -x assembler-with-cpp
 
dscr_nexys2_jtag.a51 : dscr_gen.A51
$(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 $< > $@
dscr_nexys2_jtag_2fifo_ic.a51 : dscr_gen.A51
$(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_2FIFO -DUSE_IC $< > $@
dscr_nexys2_jtag_3fifo_ic.a51 : dscr_gen.A51
$(CPPA51) $(DEFVIDPID) -DUSE_NEXYS2 -DUSE_3FIFO -DUSE_IC $< > $@
 
dscr_nexys3_jtag.a51 : dscr_gen.A51
$(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 $< > $@
dscr_nexys3_jtag_2fifo_ic.a51 : dscr_gen.A51
$(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_2FIFO -DUSE_IC $< > $@
dscr_nexys3_jtag_3fifo_ic.a51 : dscr_gen.A51
$(CPPA51) $(DEFVIDPID) -DUSE_NEXYS3 -DUSE_3FIFO -DUSE_IC $< > $@
#
# rules to create usb_fifo_init variants
#
usb_fifo_init_jtag.rel : usb_fifo_init.c
$(CC) -c $(CFLAGS) $< -o $@
#
usb_fifo_init_jtag_2fifo_ic.rel : usb_fifo_init.c
$(CC) -c $(CFLAGS) -DUSE_2FIFO -DUSE_IC30 $< -o $@
usb_fifo_init_jtag_3fifo_ic.rel : usb_fifo_init.c
$(CC) -c $(CFLAGS) -DUSE_3FIFO -DUSE_IC30 $< -o $@
#
COM_REL=vectors.rel main.rel eeprom.rel startup.rel
#
I0_REL=usb_fifo_init_jtag.rel
#
IIC2_REL=usb_fifo_init_jtag_2fifo_ic.rel
IIC3_REL=usb_fifo_init_jtag_3fifo_ic.rel
#
N2_REL=hw_nexys2.rel
N3_REL=hw_nexys3.rel
#
LIB_REL=$(LIBDIR)/$(LIB)
#
# rules to compile all code
#
$(LIBDIR)/$(LIB) :
make -C $(LIBDIR) $(MAKELIBOPT)
 
eeprom.rel : eeprom.c eeprom.h
main.rel : main.c hardware.h eeprom.h
 
$(N2_REL) : hw_nexys2.c hardware.h
$(N3_REL) : hw_nexys3.c hardware.h
 
#
# rules to build Nexys2 firmware images
#
nexys2_jtag.ihx : $(COM_REL) dscr_nexys2_jtag.rel \
$(N2_REL) $(I0_REL) $(LIB_REL)
#
nexys2_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_2fifo_ic.rel \
$(N2_REL) $(IIC2_REL) $(LIB_REL)
nexys2_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys2_jtag_3fifo_ic.rel \
$(N2_REL) $(IIC3_REL) $(LIB_REL)
#
# rules to build Nexys3 firmware images
#
nexys3_jtag.ihx : $(COM_REL) dscr_nexys3_jtag.rel \
$(N3_REL) $(I0_REL) $(LIB_REL)
#
nexys3_jtag_2fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_2fifo_ic.rel \
$(N3_REL) $(IIC2_REL) $(LIB_REL)
nexys3_jtag_3fifo_ic.ihx : $(COM_REL) dscr_nexys3_jtag_3fifo_ic.rel \
$(N3_REL) $(IIC3_REL) $(LIB_REL)
#
# cleanup phony's
#
.PHONY : clean distclean
 
clean :
make -C ${LIBDIR} clean
rm -f *.lst *.asm *.lib *.sym *.rel *.mem *.map *.rst *.lnk *.lk
rm -f dscr_*.a51
 
distclean : clean
rm -f *.ihx
 
 
/src/sdccdefs.mk
0,0 → 1,31
# $Id: sdccdefs.mk 604 2014-11-16 22:33:09Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2014-11-16 604 1.0 Initial version
#---
#
# sdcc 2.9 to 3.x transition handling ----------------------------------
# default is sdcc 3.x; if SDCC29 is specified sdcc 2.9 is used
#
 
CC=sdcc
 
ifdef SDCC29
MAKELIBOPT=SDCC29=1
AS=asx8051
CC29COMPOPT=
else
MAKELIBOPT=
AS=sdas8051
CC29COMPOPT+=-DSDCC3XCOMPAT=1
CC29COMPOPT+=-Dat=__at
CC29COMPOPT+=-Dsfr=__sfr
CC29COMPOPT+=-Dsbit=__sbit
CC29COMPOPT+=-Dbit=__bit
CC29COMPOPT+=-Dxdata=__xdata
CC29COMPOPT+=-D_asm=__asm
CC29COMPOPT+=-D_endasm=__endasm
CC29COMPOPT+=-D_naked=__naked
CC29COMPOPT+=-Dinterrupt=__interrupt
endif
/src/main.c
0,0 → 1,380
/* $Id: main.c 606 2014-11-24 07:08:51Z mueller $ */
/*
* Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
* Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
*
* - original copyright and licence disclaimer --------------------------------
* - Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter
* - Copyright (C) 2005..2007 Kolja Waschk, ixo.de
* - This code is part of usbjtag. usbjtag is free software;
*-----------------------------------------------------------------------------
*
* This program is free software; you may redistribute and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2, or at your option any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for complete details.
*
*-----------------------------------------------------------------------------
*
* EZ-USB FX2 controller main program
*
* Revision History:
*
* Date Rev Version Comment
* 2013-01-05 472 1.1.1 BUGFIX: explicitly set FIFOPINPOLAR=0
* 2011-07-23 397 1.1 factor out usb_fifo_init() code
* 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)
*
*-----------------------------------------------------------------------------
*/
 
#include "isr.h"
#include "timer.h"
#include "delay.h"
#include "fx2regs.h"
#include "fx2utils.h"
#include "usb_common.h"
#include "usb_descriptors.h"
#include "usb_requests.h"
 
#include "syncdelay.h"
 
#include "eeprom.h"
#include "hardware.h"
 
//-----------------------------------------------------------------------------
// Define USE_MOD256_OUTBUFFER:
// Saves about 256 bytes in code size, improves speed a little.
// A further optimization could be not to use an extra output buffer at
// all, but to write directly into EP1INBUF. Not implemented yet. When
// downloading large amounts of data _to_ the target, there is no output
// and thus the output buffer isn't used at all and doesn't slow down things.
 
#define USE_MOD256_OUTBUFFER 1
 
//-----------------------------------------------------------------------------
// Global data
 
typedef bit BOOL;
#define FALSE 0
#define TRUE 1
static BOOL Running;
static BOOL WriteOnly;
 
static BYTE ClockBytes;
static WORD Pending;
 
#ifdef USE_MOD256_OUTBUFFER
static BYTE FirstDataInOutBuffer;
static BYTE FirstFreeInOutBuffer;
#else
static WORD FirstDataInOutBuffer;
static WORD FirstFreeInOutBuffer;
#endif
 
#ifdef USE_MOD256_OUTBUFFER
/* Size of output buffer must be exactly 256 */
#define OUTBUFFER_LEN 0x100
/* Output buffer must begin at some address with lower 8 bits all zero */
xdata at 0xE000 BYTE OutBuffer[OUTBUFFER_LEN];
#else
#define OUTBUFFER_LEN 0x200
static xdata BYTE OutBuffer[OUTBUFFER_LEN];
#endif
 
//-----------------------------------------------------------------------------
 
void usb_jtag_init(void) // Called once at startup
{
WORD tmp;
 
Running = FALSE;
ClockBytes = 0;
Pending = 0;
WriteOnly = TRUE;
FirstDataInOutBuffer = 0;
FirstFreeInOutBuffer = 0;
 
ProgIO_Init();
 
ProgIO_Enable();
 
// Make Timer2 reload at 100 Hz to trigger Keepalive packets
 
tmp = 65536 - ( 48000000 / 12 / 100 );
RCAP2H = tmp >> 8;
RCAP2L = tmp & 0xFF;
CKCON = 0; // Default Clock
T2CON = 0x04; // Auto-reload mode using internal clock, no baud clock.
 
// Enable Autopointer
 
EXTACC = 1; // Enable
APTR1FZ = 1; // Don't freeze
APTR2FZ = 1; // Don't freeze
}
 
void OutputByte(BYTE d)
{
#ifdef USE_MOD256_OUTBUFFER
OutBuffer[FirstFreeInOutBuffer] = d;
FirstFreeInOutBuffer = ( FirstFreeInOutBuffer + 1 ) & 0xFF;
#else
OutBuffer[FirstFreeInOutBuffer++] = d;
if(FirstFreeInOutBuffer >= OUTBUFFER_LEN) FirstFreeInOutBuffer = 0;
#endif
Pending++;
}
 
//-----------------------------------------------------------------------------
// usb_jtag_activity does most of the work. It now happens to behave just like
// the combination of FT245BM and Altera-programmed EPM7064 CPLD in Altera's
// USB-Blaster. The CPLD knows two major modes: Bit banging mode and Byte
// shift mode. It starts in Bit banging mode. While bytes are received
// from the host on EP2OUT, each byte B of them is processed as follows:
//
// Please note: nCE, nCS, LED pins and DATAOUT actually aren't supported here.
// Support for these would be required for AS/PS mode and isn't too complicated,
// but I haven't had the time yet.
//
// Bit banging mode:
//
// 1. Remember bit 6 (0x40) in B as the "Read bit".
//
// 2. If bit 7 (0x40) is set, switch to Byte shift mode for the coming
// X bytes ( X := B & 0x3F ), and don't do anything else now.
//
// 3. Otherwise, set the JTAG signals as follows:
// TCK/DCLK high if bit 0 was set (0x01), otherwise low
// TMS/nCONFIG high if bit 1 was set (0x02), otherwise low
// nCE high if bit 2 was set (0x04), otherwise low
// nCS high if bit 3 was set (0x08), otherwise low
// TDI/ASDI/DATA0 high if bit 4 was set (0x10), otherwise low
// Output Enable/LED active if bit 5 was set (0x20), otherwise low
//
// 4. If "Read bit" (0x40) was set, record the state of TDO(CONF_DONE) and
// DATAOUT(nSTATUS) pins and put it as a byte ((DATAOUT<<1)|TDO) in the
// output FIFO _to_ the host (the code here reads TDO only and assumes
// DATAOUT=1)
//
// Byte shift mode:
//
// 1. Load shift register with byte from host
//
// 2. Do 8 times (i.e. for each bit of the byte; implemented in shift.a51)
// 2a) if nCS=1, set carry bit from TDO, else set carry bit from DATAOUT
// 2b) Rotate shift register through carry bit
// 2c) TDI := Carry bit
// 2d) Raise TCK, then lower TCK.
//
// 3. If "Read bit" was set when switching into byte shift mode,
// record the shift register content and put it into the FIFO
// _to_ the host.
//
// Some more (minor) things to consider to emulate the FT245BM:
//
// a) The FT245BM seems to transmit just packets of no more than 64 bytes
// (which perfectly matches the USB spec). Each packet starts with
// two non-data bytes (I use 0x31,0x60 here). A USB sniffer on Windows
// might show a number of packets to you as if it was a large transfer
// because of the way that Windows understands it: it _is_ a large
// transfer until terminated with an USB packet smaller than 64 byte.
//
// b) The Windows driver expects to get some data packets (with at least
// the two leading bytes 0x31,0x60) immediately after "resetting" the
// FT chip and then in regular intervals. Otherwise a blue screen may
// appear... In the code below, I make sure that every 10ms there is
// some packet.
//
// c) Vendor specific commands to configure the FT245 are mostly ignored
// in my code. Only those for reading the EEPROM are processed. See
// DR_GetStatus and DR_VendorCmd below for my implementation.
//
// All other TD_ and DR_ functions remain as provided with CY3681.
//
//-----------------------------------------------------------------------------
 
void usb_jtag_activity(void) // Called repeatedly while the device is idle
{
if(!Running) return;
 
ProgIO_Poll();
if(!(EP1INCS & bmEPBUSY)) {
if(Pending > 0) {
BYTE o, n;
 
AUTOPTRH2 = MSB( EP1INBUF );
AUTOPTRL2 = LSB( EP1INBUF );
XAUTODAT2 = 0x31;
XAUTODAT2 = 0x60;
if(Pending > 0x3E) { n = 0x3E; Pending -= n; }
else { n = Pending; Pending = 0; };
o = n;
 
#ifdef USE_MOD256_OUTBUFFER
APTR1H = MSB( OutBuffer );
APTR1L = FirstDataInOutBuffer;
while(n--) {
XAUTODAT2 = XAUTODAT1;
APTR1H = MSB( OutBuffer ); // Stay within 256-Byte-Buffer
}
FirstDataInOutBuffer = APTR1L;
#else
APTR1H = MSB( &(OutBuffer[FirstDataInOutBuffer]) );
APTR1L = LSB( &(OutBuffer[FirstDataInOutBuffer]) );
while(n--) {
XAUTODAT2 = XAUTODAT1;
 
if(++FirstDataInOutBuffer >= OUTBUFFER_LEN) {
FirstDataInOutBuffer = 0;
APTR1H = MSB( OutBuffer );
APTR1L = LSB( OutBuffer );
}
}
#endif
SYNCDELAY;
EP1INBC = 2 + o;
TF2 = 1; // Make sure there will be a short transfer soon
} else if(TF2) {
EP1INBUF[0] = 0x31;
EP1INBUF[1] = 0x60;
SYNCDELAY;
EP1INBC = 2;
TF2 = 0;
}
}
 
if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F)) {
//BYTE i, n = EP2BCL; // bugfix by Sune Mai (Oct 2008,
// https://sourceforge.net/projects/urjtag/forums/forum/682993/topic/2312452)
WORD i, n = EP2BCL|EP2BCH<<8;
 
APTR1H = MSB( EP2FIFOBUF );
APTR1L = LSB( EP2FIFOBUF );
 
for(i=0;i<n;) {
if(ClockBytes > 0) {
//BYTE m; // bugfix by Sune Mai, see above
WORD m;
 
m = n-i;
if(ClockBytes < m) m = ClockBytes;
ClockBytes -= m;
i += m;
 
/* Shift out 8 bits from d */
if(WriteOnly) { /* Shift out 8 bits from d */
while(m--) ProgIO_ShiftOut(XAUTODAT1);
} else { /* Shift in 8 bits at the other end */
while(m--) OutputByte(ProgIO_ShiftInOut(XAUTODAT1));
}
} else {
BYTE d = XAUTODAT1;
WriteOnly = (d & bmBIT6) ? FALSE : TRUE;
 
if(d & bmBIT7) {
/* Prepare byte transfer, do nothing else yet */
 
ClockBytes = d & 0x3F;
} else {
if(WriteOnly)
ProgIO_Set_State(d);
else
OutputByte(ProgIO_Set_Get_State(d));
}
i++;
}
}
 
SYNCDELAY;
EP2BCL = 0x80; // Re-arm endpoint 2
};
}
 
//-----------------------------------------------------------------------------
// Handler for Vendor Requests (
//-----------------------------------------------------------------------------
 
unsigned char app_vendor_cmd(void)
{
// OUT requests. Pretend we handle them all...
 
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_OUT) {
if(bRequest == RQ_GET_STATUS) {
Running = 1;
}
return 1;
}
 
// IN requests.
 
if(bRequest == 0x90) {
BYTE addr = (wIndexL<<1) & 0x7F;
EP0BUF[0] = eeprom[addr];
EP0BUF[1] = eeprom[addr+1];
} else {
// dummy data
EP0BUF[0] = 0x36;
EP0BUF[1] = 0x83;
}
 
EP0BCH = 0;
EP0BCL = (wLengthL<2) ? wLengthL : 2; // Arm endpoint with # bytes to transfer
 
return 1;
}
 
//-----------------------------------------------------------------------------
 
static void main_loop(void)
{
while(1) {
if(usb_setup_packet_avail()) usb_handle_setup_packet();
usb_jtag_activity();
}
}
 
//-----------------------------------------------------------------------------
 
extern void usb_fifo_init(void);
 
void main(void)
{
EA = 0; // disable all interrupts
// Digilent nexys3 and atlys boards change FIFOPINPOLAR such that
// EE and FF are active high. In nexys2 boards they are active low
// All config regs should be set (even when power on defaults are
// use, but this one especially....
 
// no SYNCHDELAY here because a subroutine call follows, slow enough
// !! if more regs will be touched here add SYNCHDELAYs !!
 
FIFOPINPOLAR = 0;
 
usb_jtag_init();
usb_fifo_init();
eeprom_init();
setup_autovectors ();
usb_install_handlers ();
 
 
EA = 1; // enable interrupts
 
fx2_renumerate(); // simulates disconnect / reconnect
 
main_loop();
}
 
 
 
 
/src/lib/syncdelay.h
0,0 → 1,74
/* -*- c++ -*- */
/* $Id: syncdelay.h 604 2014-11-16 22:33:09Z mueller $ */
/*
* Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
* Code was forked from USRP2 firmware (GNU Radio Project), version 3.0.2
*
* - original copyright and licence disclaimers -------------------------------
* Copyright 2003 Free Software Foundation, Inc.
* This code is part of usbjtag.
*-----------------------------------------------------------------------------
*
* This program is free software; you may redistribute and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2, or at your option any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for complete details.
*
*-----------------------------------------------------------------------------
*
* Synchronization delay for FX2 access to specific registers
*
* Revision History:
*
* Date Rev Version Comment
* 2014-11-16 604 1.1 BUGFIX: handle triple nop properly
* 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)
*/
 
#ifndef _SYNCDELAY_H_
#define _SYNCDELAY_H_
 
/*
* Magic delay required between access to certain xdata registers (TRM page 15-106).
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
* NOP is a single cycle....
*
* From TRM page 15-105:
*
* Under certain conditions, some read and write access to the FX2 registers must
* be separated by a "synchronization delay". The delay is necessary only under the
* following conditions:
*
* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
* of the registers listed below.
*
* - between a write to one of the registers listed below and a read from any register
* in the 0xE600 - 0xE6FF range.
*
* Registers which require a synchronization delay:
*
* FIFORESET FIFOPINPOLAR
* INPKTEND EPxBCH:L
* EPxFIFOPFH:L EPxAUTOINLENH:L
* EPxFIFOCFG EPxGPIFFLGSEL
* PINFLAGSAB PINFLAGSCD
* EPxFIFOIE EPxFIFOIRQ
* GPIFIE GPIFIRQ
* UDMACRCH:L GPIFADRH:L
* GPIFTRIG EPxGPIFTRIG
* OUTPKTEND REVCTL
* GPIFTCB3 GPIFTCB2
* GPIFTCB1 GPIFTCB0
*/
 
/*
* FIXME ensure that the peep hole optimizer isn't screwing us
*/
#define SYNCDELAY NOP; NOP; NOP
#define NOP _asm nop; _endasm
 
#endif /* _SYNCDELAY_H_ */
/src/lib/fx2regs.h
0,0 → 1,733
/* -*- c++ -*- */
/* $Id: fx2regs.h 604 2014-11-16 22:33:09Z mueller $ */
/*-----------------------------------------------------------------------------
* FX2 register definitions
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
/*
// original Cypress disclaimer
//-----------------------------------------------------------------------------
// File: FX2regs.h
// Contents: EZ-USB FX2 register declarations and bit mask definitions.
//
// $Archive: /USB/Target/Inc/fx2regs.h $
// $Date: 2006-09-13 14:30:04 -0700 (Wed, 13 Sep 2006) $
// $Revision: 3534 $
//
// Copyright (c) 2000 Cypress Semiconductor, All rights reserved
//-----------------------------------------------------------------------------
*/
 
/*
* Revision History in retro projects
*
* Date Rev Version Comment
* 2014-11-16 604 1.1 add sdcc 3.x migration support
* 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)
*
*-----------------------------------------------------------------------------
*/
 
#ifndef FX2REGS_H /* Header Sentry */
#define FX2REGS_H
 
#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h
 
/*
//-----------------------------------------------------------------------------
// FX2 Related Register Assignments
//-----------------------------------------------------------------------------
 
// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
// address allocation by using "#define ALLOCATE_EXTERN".
// When using "#define ALLOCATE_EXTERN", you get (for instance):
// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
// Such lines are created from FX2.h by using the preprocessor.
// Incidently, these lines will not generate any space in the resulting hex
// file; they just bind the symbols to the addresses for compilation.
// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
// i.e. fw.c or a stand-alone C source file.
// Without "#define ALLOCATE_EXTERN", you just get the external reference:
// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
// This uses the concatenation operator "##" to insert a comment "//"
// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
*/
 
/*
* Note on sdcc 3.x compatibility:
* Only the _AT_ macro is touched in the original Cypress sources.
* all other keyword mappings are done via pre-processor defines.
*/
 
#ifdef ALLOCATE_EXTERN
#define EXTERN
#ifdef SDCC3XCOMPAT
#define _AT_(a) __at a
#else
#define _AT_(a) at a
#endif
#else
#define EXTERN extern
#define _AT_ ;/ ## /
#endif
 
typedef unsigned char BYTE;
typedef unsigned short WORD;
 
EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
 
// General Configuration
 
EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
 
// Endpoint Configuration
 
EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
 
// Interrupts
 
EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
 
// Input/Output
 
EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
 
#define EXTAUTODAT1 XAUTODAT1
#define EXTAUTODAT2 XAUTODAT2
 
// USB Control
 
EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
 
// Endpoints
 
EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
 
// GPIF
 
EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
 
EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
 
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
 
// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
 
// UDMA
 
EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
 
 
// Debug/Test
 
EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
 
// Endpoint Buffers
 
EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
 
#undef EXTERN
#undef _AT_
 
/*-----------------------------------------------------------------------------
Special Function Registers (SFRs)
The byte registers and bits defined in the following list are based
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
If you modify the register definitions below, please regenerate the file
"ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/
 
sfr at 0x80 IOA;
sfr at 0x81 SP;
sfr at 0x82 DPL;
sfr at 0x83 DPH;
sfr at 0x84 DPL1;
sfr at 0x85 DPH1;
sfr at 0x86 DPS;
/* DPS */
sbit at 0x86+0 SEL;
sfr at 0x87 PCON; /* PCON */
//sbit IDLE = 0x87+0;
//sbit STOP = 0x87+1;
//sbit GF0 = 0x87+2;
//sbit GF1 = 0x87+3;
//sbit SMOD0 = 0x87+7;
sfr at 0x88 TCON;
/* TCON */
sbit at 0x88+0 IT0;
sbit at 0x88+1 IE0;
sbit at 0x88+2 IT1;
sbit at 0x88+3 IE1;
sbit at 0x88+4 TR0;
sbit at 0x88+5 TF0;
sbit at 0x88+6 TR1;
sbit at 0x88+7 TF1;
sfr at 0x89 TMOD;
/* TMOD */
//sbit M00 = 0x89+0;
//sbit M10 = 0x89+1;
//sbit CT0 = 0x89+2;
//sbit GATE0 = 0x89+3;
//sbit M01 = 0x89+4;
//sbit M11 = 0x89+5;
//sbit CT1 = 0x89+6;
//sbit GATE1 = 0x89+7;
sfr at 0x8A TL0;
sfr at 0x8B TL1;
sfr at 0x8C TH0;
sfr at 0x8D TH1;
sfr at 0x8E CKCON;
/* CKCON */
//sbit MD0 = 0x89+0;
//sbit MD1 = 0x89+1;
//sbit MD2 = 0x89+2;
//sbit T0M = 0x89+3;
//sbit T1M = 0x89+4;
//sbit T2M = 0x89+5;
// sfr at 0x8F SPC_FNC; // Was WRS in Reg320
/* CKCON */
//sbit WRS = 0x8F+0;
sfr at 0x90 IOB;
sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
/* EXIF */
//sbit USBINT = 0x91+4;
//sbit I2CINT = 0x91+5;
//sbit IE4 = 0x91+6;
//sbit IE5 = 0x91+7;
sfr at 0x92 MPAGE;
sfr at 0x98 SCON0;
/* SCON0 */
sbit at 0x98+0 RI;
sbit at 0x98+1 TI;
sbit at 0x98+2 RB8;
sbit at 0x98+3 TB8;
sbit at 0x98+4 REN;
sbit at 0x98+5 SM2;
sbit at 0x98+6 SM1;
sbit at 0x98+7 SM0;
sfr at 0x99 SBUF0;
 
sfr at 0x9A APTR1H;
sfr at 0x9B APTR1L;
sfr at 0x9C AUTODAT1;
sfr at 0x9D AUTOPTRH2;
sfr at 0x9E AUTOPTRL2;
sfr at 0x9F AUTODAT2;
sfr at 0xA0 IOC;
sfr at 0xA1 INT2CLR;
sfr at 0xA2 INT4CLR;
 
#define AUTOPTRH1 APTR1H
#define AUTOPTRL1 APTR1L
 
sfr at 0xA8 IE;
/* IE */
sbit at 0xA8+0 EX0;
sbit at 0xA8+1 ET0;
sbit at 0xA8+2 EX1;
sbit at 0xA8+3 ET1;
sbit at 0xA8+4 ES0;
sbit at 0xA8+5 ET2;
sbit at 0xA8+6 ES1;
sbit at 0xA8+7 EA;
 
sfr at 0xAA EP2468STAT;
/* EP2468STAT */
//sbit EP2E = 0xAA+0;
//sbit EP2F = 0xAA+1;
//sbit EP4E = 0xAA+2;
//sbit EP4F = 0xAA+3;
//sbit EP6E = 0xAA+4;
//sbit EP6F = 0xAA+5;
//sbit EP8E = 0xAA+6;
//sbit EP8F = 0xAA+7;
 
sfr at 0xAB EP24FIFOFLGS;
sfr at 0xAC EP68FIFOFLGS;
sfr at 0xAF AUTOPTRSETUP;
/* AUTOPTRSETUP */
sbit at 0xAF+0 EXTACC;
sbit at 0xAF+1 APTR1FZ;
sbit at 0xAF+2 APTR2FZ;
 
sfr at 0xB0 IOD;
sfr at 0xB1 IOE;
sfr at 0xB2 OEA;
sfr at 0xB3 OEB;
sfr at 0xB4 OEC;
sfr at 0xB5 OED;
sfr at 0xB6 OEE;
 
sfr at 0xB8 IP;
/* IP */
sbit at 0xB8+0 PX0;
sbit at 0xB8+1 PT0;
sbit at 0xB8+2 PX1;
sbit at 0xB8+3 PT1;
sbit at 0xB8+4 PS0;
sbit at 0xB8+5 PT2;
sbit at 0xB8+6 PS1;
 
sfr at 0xBA EP01STAT;
sfr at 0xBB GPIFTRIG;
sfr at 0xBD GPIFSGLDATH;
sfr at 0xBE GPIFSGLDATLX;
sfr at 0xBF GPIFSGLDATLNOX;
 
sfr at 0xC0 SCON1;
/* SCON1 */
sbit at 0xC0+0 RI1;
sbit at 0xC0+1 TI1;
sbit at 0xC0+2 RB81;
sbit at 0xC0+3 TB81;
sbit at 0xC0+4 REN1;
sbit at 0xC0+5 SM21;
sbit at 0xC0+6 SM11;
sbit at 0xC0+7 SM01;
sfr at 0xC1 SBUF1;
sfr at 0xC8 T2CON;
/* T2CON */
sbit at 0xC8+0 CP_RL2;
sbit at 0xC8+1 C_T2;
sbit at 0xC8+2 TR2;
sbit at 0xC8+3 EXEN2;
sbit at 0xC8+4 TCLK;
sbit at 0xC8+5 RCLK;
sbit at 0xC8+6 EXF2;
sbit at 0xC8+7 TF2;
sfr at 0xCA RCAP2L;
sfr at 0xCB RCAP2H;
sfr at 0xCC TL2;
sfr at 0xCD TH2;
sfr at 0xD0 PSW;
/* PSW */
sbit at 0xD0+0 P;
sbit at 0xD0+1 FL;
sbit at 0xD0+2 OV;
sbit at 0xD0+3 RS0;
sbit at 0xD0+4 RS1;
sbit at 0xD0+5 F0;
sbit at 0xD0+6 AC;
sbit at 0xD0+7 CY;
sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
/* EICON */
sbit at 0xD8+3 INT6;
sbit at 0xD8+4 RESI;
sbit at 0xD8+5 ERESI;
sbit at 0xD8+7 SMOD1;
sfr at 0xE0 ACC;
sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
/* EIE */
sbit at 0xE8+0 EIUSB;
sbit at 0xE8+1 EI2C;
sbit at 0xE8+2 EIEX4;
sbit at 0xE8+3 EIEX5;
sbit at 0xE8+4 EIEX6;
sfr at 0xF0 B;
sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
/* EIP */
sbit at 0xF8+0 PUSB;
sbit at 0xF8+1 PI2C;
sbit at 0xF8+2 EIPX4;
sbit at 0xF8+3 EIPX5;
sbit at 0xF8+4 EIPX6;
 
/*-----------------------------------------------------------------------------
Bit Masks
-----------------------------------------------------------------------------*/
 
#define bmBIT0 1
#define bmBIT1 2
#define bmBIT2 4
#define bmBIT3 8
#define bmBIT4 16
#define bmBIT5 32
#define bmBIT6 64
#define bmBIT7 128
 
/* CPU Control & Status Register (CPUCS) */
#define bmPRTCSTB bmBIT5
#define bmCLKSPD (bmBIT4 | bmBIT3)
#define bmCLKSPD1 bmBIT4
#define bmCLKSPD0 bmBIT3
#define bmCLKINV bmBIT2
#define bmCLKOE bmBIT1
#define bm8051RES bmBIT0
/* Port Alternate Configuration Registers */
/* Port A (PORTACFG) */
#define bmFLAGD bmBIT7
#define bmINT1 bmBIT1
#define bmINT0 bmBIT0
/* Port C (PORTCCFG) */
#define bmGPIFA7 bmBIT7
#define bmGPIFA6 bmBIT6
#define bmGPIFA5 bmBIT5
#define bmGPIFA4 bmBIT4
#define bmGPIFA3 bmBIT3
#define bmGPIFA2 bmBIT2
#define bmGPIFA1 bmBIT1
#define bmGPIFA0 bmBIT0
/* Port E (PORTECFG) */
#define bmGPIFA8 bmBIT7
#define bmT2EX bmBIT6
#define bmINT6 bmBIT5
#define bmRXD1OUT bmBIT4
#define bmRXD0OUT bmBIT3
#define bmT2OUT bmBIT2
#define bmT1OUT bmBIT1
#define bmT0OUT bmBIT0
 
/* I2C Control & Status Register (I2CS) */
#define bmSTART bmBIT7
#define bmSTOP bmBIT6
#define bmLASTRD bmBIT5
#define bmID (bmBIT4 | bmBIT3)
#define bmBERR bmBIT2
#define bmACK bmBIT1
#define bmDONE bmBIT0
/* I2C Control Register (I2CTL) */
#define bmSTOPIE bmBIT1
#define bm400KHZ bmBIT0
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
#define bmIV4 bmBIT6
#define bmIV3 bmBIT5
#define bmIV2 bmBIT4
#define bmIV1 bmBIT3
#define bmIV0 bmBIT2
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
#define bmEP0ACK bmBIT6
#define bmHSGRANT bmBIT5
#define bmURES bmBIT4
#define bmSUSP bmBIT3
#define bmSUTOK bmBIT2
#define bmSOF bmBIT1
#define bmSUDAV bmBIT0
/* Breakpoint register (BREAKPT) */
#define bmBREAK bmBIT3
#define bmBPPULSE bmBIT2
#define bmBPEN bmBIT1
/* Interrupt 2 & 4 Setup (INTSETUP) */
#define bmAV2EN bmBIT3
#define bmINT4IN bmBIT1
#define bmAV4EN bmBIT0
/* USB Control & Status Register (USBCS) */
#define bmHSM bmBIT7
#define bmDISCON bmBIT3
#define bmNOSYNSOF bmBIT2
#define bmRENUM bmBIT1
#define bmSIGRESUME bmBIT0
/* Wakeup Control and Status Register (WAKEUPCS) */
#define bmWU2 bmBIT7
#define bmWU bmBIT6
#define bmWU2POL bmBIT5
#define bmWUPOL bmBIT4
#define bmDPEN bmBIT2
#define bmWU2EN bmBIT1
#define bmWUEN bmBIT0
/* End Point 0 Control & Status Register (EP0CS) */
#define bmHSNAK bmBIT7
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
#define bmEPBUSY bmBIT1
#define bmEPSTALL bmBIT0
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
#define bmEPFULL bmBIT3
#define bmEPEMPTY bmBIT2
/* Endpoint Status (EP2468STAT) SFR bits */
#define bmEP8FULL bmBIT7
#define bmEP8EMPTY bmBIT6
#define bmEP6FULL bmBIT5
#define bmEP6EMPTY bmBIT4
#define bmEP4FULL bmBIT3
#define bmEP4EMPTY bmBIT2
#define bmEP2FULL bmBIT1
#define bmEP2EMPTY bmBIT0
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
#define bmSDPAUTO bmBIT0
/* Endpoint Data Toggle Control (TOGCTL) */
#define bmQUERYTOGGLE bmBIT7
#define bmSETTOGGLE bmBIT6
#define bmRESETTOGGLE bmBIT5
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
#define bmEP8IBN bmBIT5
#define bmEP6IBN bmBIT4
#define bmEP4IBN bmBIT3
#define bmEP2IBN bmBIT2
#define bmEP1IBN bmBIT1
#define bmEP0IBN bmBIT0
 
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
#define bmEP8PING bmBIT7
#define bmEP6PING bmBIT6
#define bmEP4PING bmBIT5
#define bmEP2PING bmBIT4
#define bmEP1PING bmBIT3
#define bmEP0PING bmBIT2
#define bmIBN bmBIT0
 
/* Interface Configuration bits (IFCONFIG) */
#define bmIFCLKSRC bmBIT7 // set == INTERNAL
#define bm3048MHZ bmBIT6 // set == 48 MHz
#define bmIFCLKOE bmBIT5
#define bmIFCLKPOL bmBIT4
#define bmASYNC bmBIT3
#define bmGSTATE bmBIT2
#define bmIFCFG1 bmBIT1
#define bmIFCFG0 bmBIT0
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
#define bmIFGPIF bmIFCFG1
 
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
#define bmINFM bmBIT6
#define bmOEP bmBIT5
#define bmAUTOOUT bmBIT4
#define bmAUTOIN bmBIT3
#define bmZEROLENIN bmBIT2
// must be zero bmBIT1
#define bmWORDWIDE bmBIT0
 
/*
* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
*/
#define bmNOAUTOARM bmBIT1 // these don't match the docs
#define bmSKIPCOMMIT bmBIT0 // these don't match the docs
 
#define bmDYN_OUT bmBIT1 // these do...
#define bmENH_PKT bmBIT0
 
 
/* Fifo Reset bits (FIFORESET) */
#define bmNAKALL bmBIT7
 
/* Endpoint Configuration (EPxCFG) */
#define bmVALID bmBIT7
#define bmIN bmBIT6
#define bmTYPE1 bmBIT5
#define bmTYPE0 bmBIT4
#define bmISOCHRONOUS bmTYPE0
#define bmBULK bmTYPE1
#define bmINTERRUPT (bmTYPE1 | bmTYPE0)
#define bm1KBUF bmBIT3
#define bmBUF1 bmBIT1
#define bmBUF0 bmBIT0
#define bmQUADBUF 0
#define bmINVALIDBUF bmBUF0
#define bmDOUBLEBUF bmBUF1
#define bmTRIPLEBUF (bmBUF1 | bmBUF0)
 
/* OUTPKTEND */
#define bmSKIP bmBIT7 // low 4 bits specify which end point
 
/* GPIFTRIG defs */
#define bmGPIF_IDLE bmBIT7 // status bit
 
#define bmGPIF_EP2_START 0
#define bmGPIF_EP4_START 1
#define bmGPIF_EP6_START 2
#define bmGPIF_EP8_START 3
#define bmGPIF_READ bmBIT2
#define bmGPIF_WRITE 0
 
/* EXIF bits */
#define bmEXIF_USBINT bmBIT4
#define bmEXIF_I2CINT bmBIT5
#define bmEXIF_IE4 bmBIT6
#define bmEXIF_IE5 bmBIT7
 
 
#endif /* FX2REGS_H */
/src/lib/Makefile
0,0 → 1,58
# $Id: Makefile 604 2014-11-16 22:33:09Z mueller $
 
#
# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
#
# - original copyright and licence disclaimer --------------------------------
# - Copyright 2007 Kolja Waschk, ixo.de
# - This code is part of usbjtag. usbjtag is free software;
#-----------------------------------------------------------------------------
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#-----------------------------------------------------------------------------
 
 
#-----------------------------------------------------------------------------
# Makefile for FX2 library code
#
# Revision History in retro projects
#
# Date Rev Version Comment
# 2014-11-16 604 1.1 add sdcc 3.x migration support
# 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204)
#
#-----------------------------------------------------------------------------
 
#
# defs for sdcc 2.9 to 3.x transition handling -------------------------
#
include ../sdccdefs.mk
 
CFLAGS+=-mmcs51 --no-xinit-opt -I.
CFLAGS+=${CC29COMPOPT}
 
CPPFLAGS+=
OBJS=delay.rel fx2utils.rel i2c.rel isr.rel timer.rel usb_common.rel
AR=sdcclib
 
(%.rel) : %.c
$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $*.rel
$(AR) -a $@ $*.rel
rm $*.rel
 
libfx2.lib: libfx2.lib($(OBJS))
 
clean:
rm -f *.lst *.asm *.lib *.sym *.rel *.lib
 
 
 
 
/src/lib/delay.c
0,0 → 1,75
/* -*- c++ -*- */
/* $Id: delay.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Delay routines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
/*
* Delay approximately 1 microsecond (including overhead in udelay).
*/
static void
udelay1 (void) _naked
{
_asm ; lcall that got us here took 4 bus cycles
ret ; 4 bus cycles
_endasm;
}
 
/*
* delay for approximately usecs microseconds
*/
void
udelay (unsigned char usecs)
{
do {
udelay1 ();
} while (--usecs != 0);
}
 
 
/*
* Delay approximately 1 millisecond.
* We're running at 48 MHz, so we need 48,000 clock cycles.
*
* Note however, that each bus cycle takes 4 clock cycles (not obvious,
* but explains the factor of 4 problem below).
*/
static void
mdelay1 (void) _naked
{
_asm
mov dptr,#(-1200 & 0xffff)
002$:
inc dptr ; 3 bus cycles
mov a, dpl ; 2 bus cycles
orl a, dph ; 2 bus cycles
jnz 002$ ; 3 bus cycles
 
ret
_endasm;
}
 
void
mdelay (unsigned int msecs)
{
do {
mdelay1 ();
} while (--msecs != 0);
}
 
/src/lib/usb_common.c
0,0 → 1,372
/* -*- c++ -*- */
/* $Id: usb_common.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Common USB code for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "usb_common.h"
#include "fx2regs.h"
#include "syncdelay.h"
#include "fx2utils.h"
#include "isr.h"
#include "usb_descriptors.h"
#include "usb_requests.h"
 
extern xdata char str0[];
extern xdata char str1[];
extern xdata char str2[];
extern xdata char str3[];
extern xdata char str4[];
extern xdata char str5[];
 
volatile bit _usb_got_SUDAV;
 
unsigned char _usb_config = 0;
unsigned char _usb_alt_setting = 0; // FIXME really 1/interface
 
xdata unsigned char *current_device_descr;
xdata unsigned char *current_devqual_descr;
xdata unsigned char *current_config_descr;
xdata unsigned char *other_config_descr;
 
static void
setup_descriptors (void)
{
if (USBCS & bmHSM){ // high speed mode
current_device_descr = high_speed_device_descr;
current_devqual_descr = high_speed_devqual_descr;
current_config_descr = high_speed_config_descr;
other_config_descr = full_speed_config_descr;
}
else {
current_device_descr = full_speed_device_descr;
current_devqual_descr = full_speed_devqual_descr;
current_config_descr = full_speed_config_descr;
other_config_descr = high_speed_config_descr;
}
 
// whack the type fields
// FIXME, may not be required.
// current_config_descr[1] = DT_CONFIG;
// other_config_descr[1] = DT_OTHER_SPEED;
}
 
static void
isr_SUDAV (void) interrupt
{
clear_usb_irq ();
_usb_got_SUDAV = 1;
}
 
static void
isr_USBRESET (void) interrupt
{
clear_usb_irq ();
setup_descriptors ();
}
 
static void
isr_HIGHSPEED (void) interrupt
{
clear_usb_irq ();
setup_descriptors ();
}
 
void
usb_install_handlers (void)
{
setup_descriptors (); // ensure that they're set before use
 
hook_uv (UV_SUDAV, (unsigned short) isr_SUDAV);
hook_uv (UV_USBRESET, (unsigned short) isr_USBRESET);
hook_uv (UV_HIGHSPEED, (unsigned short) isr_HIGHSPEED);
 
USBIE = bmSUDAV | bmURES | bmHSGRANT;
}
 
// On the FX2 the only plausible endpoints are 0, 1, 2, 4, 6, 8
// This doesn't check to see that they're enabled
 
unsigned char
plausible_endpoint (unsigned char ep)
{
ep &= ~0x80; // ignore direction bit
 
if (ep > 8)
return 0;
 
if (ep == 1)
return 1;
 
return (ep & 0x1) == 0; // must be even
}
 
// return pointer to control and status register for endpoint.
// only called with plausible_endpoints
 
xdata volatile unsigned char *
epcs (unsigned char ep)
{
if (ep == 0x01) // ep1 has different in and out CS regs
return EP1OUTCS;
 
if (ep == 0x81)
return EP1INCS;
 
ep &= ~0x80; // ignore direction bit
 
if (ep == 0x00) // ep0
return EP0CS;
 
return EP2CS + (ep >> 1); // 2, 4, 6, 8 are consecutive
}
 
void
usb_handle_setup_packet (void)
{
_usb_got_SUDAV = 0;
 
// handle the standard requests...
 
switch (bRequestType & bmRT_TYPE_MASK){
 
case bmRT_TYPE_CLASS:
case bmRT_TYPE_RESERVED:
fx2_stall_ep0 (); // we don't handle these. indicate error
break;
case bmRT_TYPE_VENDOR:
// call the application code.
// If it handles the command it returns non-zero
 
if (!app_vendor_cmd ())
fx2_stall_ep0 ();
break;
 
case bmRT_TYPE_STD:
// these are the standard requests...
 
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_IN){
 
////////////////////////////////////
// handle the IN requests
////////////////////////////////////
 
switch (bRequest){
 
case RQ_GET_CONFIG:
EP0BUF[0] = _usb_config; // FIXME app should handle
EP0BCH = 0;
EP0BCL = 1;
break;
// --------------------------------
 
case RQ_GET_INTERFACE:
EP0BUF[0] = _usb_alt_setting; // FIXME app should handle
EP0BCH = 0;
EP0BCL = 1;
break;
 
// --------------------------------
 
case RQ_GET_DESCR:
switch (wValueH){
 
case DT_DEVICE:
SUDPTRH = MSB (current_device_descr);
SUDPTRL = LSB (current_device_descr);
break;
case DT_DEVQUAL:
SUDPTRH = MSB (current_devqual_descr);
SUDPTRL = LSB (current_devqual_descr);
break;
 
case DT_CONFIG:
if (0 && wValueL != 1) // FIXME only a single configuration
fx2_stall_ep0 ();
else {
SUDPTRH = MSB (current_config_descr);
SUDPTRL = LSB (current_config_descr);
}
break;
 
case DT_OTHER_SPEED:
if (0 && wValueL != 1) // FIXME only a single configuration
fx2_stall_ep0 ();
else {
SUDPTRH = MSB (other_config_descr);
SUDPTRL = LSB (other_config_descr);
}
break;
 
case DT_STRING:
if (wValueL >= nstring_descriptors)
fx2_stall_ep0 ();
else {
xdata char *p = string_descriptors[wValueL];
SUDPTRH = MSB (p);
SUDPTRL = LSB (p);
}
break;
 
default:
fx2_stall_ep0 (); // invalid request
break;
}
break;
// --------------------------------
 
case RQ_GET_STATUS:
switch (bRequestType & bmRT_RECIP_MASK){
case bmRT_RECIP_DEVICE:
EP0BUF[0] = 0;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
 
case bmRT_RECIP_INTERFACE:
EP0BUF[0] = 0;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
 
case bmRT_RECIP_ENDPOINT:
if (plausible_endpoint (wIndexL)){
EP0BUF[0] = *epcs (wIndexL) & bmEPSTALL;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
}
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SYNCH_FRAME: // not implemented
default:
fx2_stall_ep0 ();
break;
}
}
 
else {
 
////////////////////////////////////
// handle the OUT requests
////////////////////////////////////
 
switch (bRequest){
 
case RQ_SET_CONFIG:
_usb_config = wValueL; // FIXME app should handle
break;
 
case RQ_SET_INTERFACE:
_usb_alt_setting = wValueL; // FIXME app should handle
break;
 
// --------------------------------
 
case RQ_CLEAR_FEATURE:
switch (bRequestType & bmRT_RECIP_MASK){
 
case bmRT_RECIP_DEVICE:
switch (wValueL){
case FS_DEV_REMOTE_WAKEUP:
default:
fx2_stall_ep0 ();
}
break;
 
case bmRT_RECIP_ENDPOINT:
if (wValueL == FS_ENDPOINT_HALT && plausible_endpoint (wIndexL)){
*epcs (wIndexL) &= ~bmEPSTALL;
fx2_reset_data_toggle (wIndexL);
}
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SET_FEATURE:
switch (bRequestType & bmRT_RECIP_MASK){
 
case bmRT_RECIP_DEVICE:
switch (wValueL){
case FS_TEST_MODE:
// hardware handles this after we complete SETUP phase handshake
break;
 
case FS_DEV_REMOTE_WAKEUP:
default:
fx2_stall_ep0 ();
break;
}
}
break;
 
case bmRT_RECIP_ENDPOINT:
switch (wValueL){
case FS_ENDPOINT_HALT:
if (plausible_endpoint (wIndexL))
*epcs (wIndexL) |= bmEPSTALL;
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SET_ADDRESS: // handled by fx2 hardware
case RQ_SET_DESCR: // not implemented
default:
fx2_stall_ep0 ();
}
 
}
break;
 
} // bmRT_TYPE_MASK
 
// ack handshake phase of device request
EP0CS |= bmHSNAK;
}
/src/lib/isr.h
0,0 → 1,171
/* -*- c++ -*- */
/* $Id: isr.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Interrupt handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _ISR_H_
#define _ISR_H_
 
/*
* ----------------------------------------------------------------
* routines for managing interrupt services routines
* ----------------------------------------------------------------
*/
 
/*
* The FX2 has three discrete sets of interrupt vectors.
* The first set is the standard 8051 vector (13 8-byte entries).
* The second set is USB interrupt autovector (32 4-byte entries).
* The third set is the FIFO/GPIF autovector (14 4-byte entries).
*
* Since all the code we're running in the FX2 is ram based, we
* forego the typical "initialize the interrupt vectors at link time"
* strategy, in favor of calls at run time that install the correct
* pointers to functions.
*/
 
/*
* Standard Vector numbers
*/
 
#define SV_INT_0 0x03
#define SV_TIMER_0 0x0b
#define SV_INT_1 0x13
#define SV_TIMER_1 0x1b
#define SV_SERIAL_0 0x23
#define SV_TIMER_2 0x2b
#define SV_RESUME 0x33
#define SV_SERIAL_1 0x3b
#define SV_INT_2 0x43 // (INT_2) points at USB autovector
#define SV_I2C 0x4b
#define SV_INT_4 0x53 // (INT_4) points at FIFO/GPIF autovector
#define SV_INT_5 0x5b
#define SV_INT_6 0x63
 
#define SV_MIN SV_INT_0
#define SV_MAX SV_INT_6
 
/*
* USB Auto Vector numbers
*/
 
#define UV_SUDAV 0x00
#define UV_SOF 0x04
#define UV_SUTOK 0x08
#define UV_SUSPEND 0x0c
#define UV_USBRESET 0x10
#define UV_HIGHSPEED 0x14
#define UV_EP0ACK 0x18
#define UV_SPARE_1C 0x1c
#define UV_EP0IN 0x20
#define UV_EP0OUT 0x24
#define UV_EP1IN 0x28
#define UV_EP1OUT 0x2c
#define UV_EP2 0x30
#define UV_EP4 0x34
#define UV_EP6 0x38
#define UV_EP8 0x3c
#define UV_IBN 0x40
#define UV_SPARE_44 0x44
#define UV_EP0PINGNAK 0x48
#define UV_EP1PINGNAK 0x4c
#define UV_EP2PINGNAK 0x50
#define UV_EP4PINGNAK 0x54
#define UV_EP6PINGNAK 0x58
#define UV_EP8PINGNAK 0x5c
#define UV_ERRLIMIT 0x60
#define UV_SPARE_64 0x64
#define UV_SPARE_68 0x68
#define UV_SPARE_6C 0x6c
#define UV_EP2ISOERR 0x70
#define UV_EP4ISOERR 0x74
#define UV_EP6ISOERR 0x78
#define UV_EP8ISOERR 0x7c
 
#define UV_MIN UV_SUDAV
#define UV_MAX UV_EP8ISOERR
 
/*
* FIFO/GPIF Auto Vector numbers
*/
 
#define FGV_EP2PF 0x80
#define FGV_EP4PF 0x84
#define FGV_EP6PF 0x88
#define FGV_EP8PF 0x8c
#define FGV_EP2EF 0x90
#define FGV_EP4EF 0x94
#define FGV_EP6EF 0x98
#define FGV_EP8EF 0x9c
#define FGV_EP2FF 0xa0
#define FGV_EP4FF 0xa4
#define FGV_EP6FF 0xa8
#define FGV_EP8FF 0xac
#define FGV_GPIFDONE 0xb0
#define FGV_GPIFWF 0xb4
 
#define FGV_MIN FGV_EP2PF
#define FGV_MAX FGV_GPIFWF
 
 
/*
* Hook standard interrupt vector.
*
* vector_number is from the SV_<foo> list above.
* addr is the address of the interrupt service routine.
*/
void hook_sv (unsigned char vector_number, unsigned short addr);
 
/*
* Hook usb interrupt vector.
*
* vector_number is from the UV_<foo> list above.
* addr is the address of the interrupt service routine.
*/
void hook_uv (unsigned char vector_number, unsigned short addr);
 
/*
* Hook fifo/gpif interrupt vector.
*
* vector_number is from the FGV_<foo> list above.
* addr is the address of the interrupt service routine.
*/
void hook_fgv (unsigned char vector_number, unsigned short addr);
 
/*
* One time call to enable autovectoring for both USB and FIFO/GPIF
*/
void setup_autovectors (void);
 
 
/*
* Must be called in each usb interrupt handler
*/
#define clear_usb_irq() \
EXIF &= ~bmEXIF_USBINT; \
INT2CLR = 0
 
/*
* Must be calledin each fifo/gpif interrupt handler
*/
#define clear_fifo_gpif_irq() \
EXIF &= ~bmEXIF_IE4; \
INT4CLR = 0
 
#endif /* _ISR_H_ */
/src/lib/delay.h
0,0 → 1,37
/* -*- c++ -*- */
/* $Id: delay.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Delay routines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _DELAY_H_
#define _DELAY_H_
 
/*
* delay for approximately usecs microseconds
* Note limit of 255 usecs.
*/
void udelay (unsigned char usecs);
 
/*
* delay for approximately msecs milliseconds
*/
void mdelay (unsigned short msecs);
 
 
#endif /* _DELAY_H_ */
/src/lib/usb_common.h
0,0 → 1,51
/* -*- c++ -*- */
/* $Id: usb_common.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Common USB code for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _USB_COMMON_H_
#define _USB_COMMON_H_
 
#define bRequestType SETUPDAT[0]
#define bRequest SETUPDAT[1]
#define wValueL SETUPDAT[2]
#define wValueH SETUPDAT[3]
#define wIndexL SETUPDAT[4]
#define wIndexH SETUPDAT[5]
#define wLengthL SETUPDAT[6]
#define wLengthH SETUPDAT[7]
 
#define MSB(x) (((unsigned short) x) >> 8)
#define LSB(x) (((unsigned short) x) & 0xff)
 
extern volatile bit _usb_got_SUDAV;
 
// Provided by user application to report device status.
// returns non-zero if it handled the command.
unsigned char app_get_status (void);
// Provided by user application to handle VENDOR commands.
// returns non-zero if it handled the command.
unsigned char app_vendor_cmd (void);
 
void usb_install_handlers (void);
void usb_handle_setup_packet (void);
 
#define usb_setup_packet_avail() _usb_got_SUDAV
 
#endif /* _USB_COMMON_H_ */
/src/lib/i2c.c
0,0 → 1,122
/* -*- c++ -*- */
/* $Id: i2c.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* I2C read/write functions for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "i2c.h"
#include "fx2regs.h"
#include <string.h>
 
 
// issue a stop bus cycle and wait for completion
 
 
// returns non-zero if successful, else 0
unsigned char
i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len)
{
volatile unsigned char junk;
if (len == 0) // reading zero bytes always works
return 1;
while (I2CS & bmSTOP) // wait for stop to clear
;
 
I2CS = bmSTART;
I2DAT = (addr << 1) | 1; // write address and direction (1's the read bit)
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
 
if (len == 1)
I2CS |= bmLASTRD;
 
junk = I2DAT; // trigger the first read cycle
 
while (--len != 0){
while ((I2CS & bmDONE) == 0)
;
 
if (I2CS & bmBERR)
goto fail;
 
if (len == 1)
I2CS |= bmLASTRD;
*buf++ = I2DAT; // get data, trigger another read
}
 
// wait for final byte
while ((I2CS & bmDONE) == 0)
;
if (I2CS & bmBERR)
goto fail;
 
I2CS |= bmSTOP;
*buf = I2DAT;
 
return 1;
 
fail:
I2CS |= bmSTOP;
return 0;
}
 
 
 
// returns non-zero if successful, else 0
unsigned char
i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len)
{
while (I2CS & bmSTOP) // wait for stop to clear
;
 
I2CS = bmSTART;
I2DAT = (addr << 1) | 0; // write address and direction (0's the write bit)
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
 
while (len > 0){
I2DAT = *buf++;
len--;
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
}
 
I2CS |= bmSTOP;
return 1;
 
fail:
I2CS |= bmSTOP;
return 0;
}
/src/lib/usb_descriptors.h
0,0 → 1,39
/* -*- c++ -*- */
/* $Id: usb_descriptors.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* USB descriptor references
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
extern xdata const char high_speed_device_descr[];
extern xdata const char high_speed_devqual_descr[];
extern xdata const char high_speed_config_descr[];
 
extern xdata const char full_speed_device_descr[];
extern xdata const char full_speed_devqual_descr[];
extern xdata const char full_speed_config_descr[];
 
extern xdata unsigned char nstring_descriptors;
extern xdata char * xdata string_descriptors[];
 
/*
* We patch these locations with info read from the usrp config eeprom
*/
extern xdata char usb_desc_hw_rev_binary_patch_location_0[];
extern xdata char usb_desc_hw_rev_binary_patch_location_1[];
extern xdata char usb_desc_hw_rev_ascii_patch_location_0[];
extern xdata char usb_desc_serial_number_ascii[];
/src/lib/timer.c
0,0 → 1,48
/* -*- c++ -*- */
/* $Id: timer.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Timer handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "timer.h"
#include "fx2regs.h"
#include "isr.h"
 
/*
* Arrange to have isr_tick_handler called at 100 Hz.
*
* The cpu clock is running at 48e6. The input to the timer
* is 48e6 / 12 = 4e6.
*
* We arrange to have the timer overflow every 40000 clocks == 100 Hz
*/
 
#define RELOAD_VALUE ((unsigned short) -40000)
 
void
hook_timer_tick (unsigned short isr_tick_handler)
{
ET2 = 0; // disable timer 2 interrupts
hook_sv (SV_TIMER_2, isr_tick_handler);
RCAP2H = RELOAD_VALUE >> 8; // setup the auto reload value
RCAP2L = RELOAD_VALUE & 0xFF;
 
T2CON = 0x04; // interrupt on overflow; reload; run
ET2 = 1; // enable timer 2 interrupts
}
/src/lib/fx2utils.c
0,0 → 1,53
/* -*- c++ -*- */
/* $Id: fx2utils.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* FX2 specific subroutines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "fx2utils.h"
#include "fx2regs.h"
#include "delay.h"
 
void
fx2_stall_ep0 (void)
{
EP0CS |= bmEPSTALL;
}
 
void
fx2_reset_data_toggle (unsigned char ep)
{
TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f));
TOGCTL |= bmRESETTOGGLE;
}
 
void
fx2_renumerate (void)
{
USBCS |= bmDISCON | bmRENUM;
 
// mdelay (1500); // FIXME why 1.5 seconds?
mdelay (250); // FIXME why 1.5 seconds?
USBIRQ = 0xff; // clear any pending USB irqs...
EPIRQ = 0xff; // they're from before the renumeration
 
EXIF &= ~bmEXIF_USBINT;
 
USBCS &= ~bmDISCON; // reconnect USB
}
/src/lib/i2c.h
0,0 → 1,31
/* -*- c++ -*- */
/* $Id: i2c.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* I2C read/write functions for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _I2C_H_
#define _I2C_H_
 
// returns non-zero if successful, else 0
unsigned char i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len);
 
// returns non-zero if successful, else 0
unsigned char i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len);
 
#endif /* _I2C_H_ */
/src/lib/timer.h
0,0 → 1,34
/* -*- c++ -*- */
/* $Id: timer.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Timer handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _TIMER_H_
#define _TIMER_H_
 
/*
* Arrange to have isr_tick_handler called at 100 Hz
*/
void hook_timer_tick (unsigned short isr_tick_handler);
 
#define clear_timer_irq() \
TF2 = 0 /* clear overflow flag */
 
 
#endif /* _TIMER_H_ */
/src/lib/fx2utils.h
0,0 → 1,31
/* -*- c++ -*- */
/* $Id: fx2utils.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* FX2 specific subroutines
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#ifndef _FX2UTILS_H_
#define _FX2UTILS_H_
 
void fx2_stall_ep0 (void);
void fx2_reset_data_toggle (unsigned char ep);
void fx2_renumerate (void);
 
 
 
#endif /* _FX2UTILS_H_ */
/src/lib/usb_requests.h
0,0 → 1,87
/* -*- c++ -*- */
/* $Id: usb_requests.h 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* USB request definitions
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
// Standard USB requests.
// These are contained in end point 0 setup packets
 
 
#ifndef _USB_REQUESTS_H_
#define _USB_REQUESTS_H_
 
// format of bmRequestType byte
 
#define bmRT_DIR_MASK (0x1 << 7)
#define bmRT_DIR_IN (1 << 7)
#define bmRT_DIR_OUT (0 << 7)
 
#define bmRT_TYPE_MASK (0x3 << 5)
#define bmRT_TYPE_STD (0 << 5)
#define bmRT_TYPE_CLASS (1 << 5)
#define bmRT_TYPE_VENDOR (2 << 5)
#define bmRT_TYPE_RESERVED (3 << 5)
 
#define bmRT_RECIP_MASK (0x1f << 0)
#define bmRT_RECIP_DEVICE (0 << 0)
#define bmRT_RECIP_INTERFACE (1 << 0)
#define bmRT_RECIP_ENDPOINT (2 << 0)
#define bmRT_RECIP_OTHER (3 << 0)
 
 
// standard request codes (bRequest)
 
#define RQ_GET_STATUS 0
#define RQ_CLEAR_FEATURE 1
#define RQ_RESERVED_2 2
#define RQ_SET_FEATURE 3
#define RQ_RESERVED_4 4
#define RQ_SET_ADDRESS 5
#define RQ_GET_DESCR 6
#define RQ_SET_DESCR 7
#define RQ_GET_CONFIG 8
#define RQ_SET_CONFIG 9
#define RQ_GET_INTERFACE 10
#define RQ_SET_INTERFACE 11
#define RQ_SYNCH_FRAME 12
 
// standard descriptor types
 
#define DT_DEVICE 1
#define DT_CONFIG 2
#define DT_STRING 3
#define DT_INTERFACE 4
#define DT_ENDPOINT 5
#define DT_DEVQUAL 6
#define DT_OTHER_SPEED 7
#define DT_INTERFACE_POWER 8
 
// standard feature selectors
 
#define FS_ENDPOINT_HALT 0 // recip: endpoint
#define FS_DEV_REMOTE_WAKEUP 1 // recip: device
#define FS_TEST_MODE 2 // recip: device
 
// Get Status device attributes
 
#define bmGSDA_SELF_POWERED 0x01
#define bmGSDA_REM_WAKEUP 0x02
 
 
#endif /* _USB_REQUESTS_H_ */
/src/lib/.cvsignore
0,0 → 1,10
*.asm
*.ihx
*.lnk
*.lst
*.map
*.mem
*.rel
*.rst
*.sym
libfx2.lib
/src/lib/isr.c
0,0 → 1,169
/* -*- c++ -*- */
/* $Id: isr.c 395 2011-07-17 22:02:55Z mueller $ */
/*-----------------------------------------------------------------------------
* Interrupt handling for FX2
*-----------------------------------------------------------------------------
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
* Copyright 2003 Free Software Foundation, Inc.
*-----------------------------------------------------------------------------
* This code is part of usbjtag. usbjtag is free software; you can redistribute
* it and/or modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the License,
* or (at your option) any later version. usbjtag is distributed in the hope
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details. You should have received a
* copy of the GNU General Public License along with this program in the file
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
* St, Fifth Floor, Boston, MA 02110-1301 USA
*-----------------------------------------------------------------------------
*/
 
#include "isr.h"
#include "fx2regs.h"
#include "syncdelay.h"
 
extern xdata unsigned char _standard_interrupt_vector[];
extern xdata unsigned char _usb_autovector[];
extern xdata unsigned char _fifo_gpif_autovector[];
 
#define LJMP_OPCODE 0x02
 
/*
* Hook standard interrupt vector.
*
* vector_number is from the SV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_sv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
if (vector_number < SV_MIN || vector_number > SV_MAX)
return;
 
if ((vector_number & 0x0f) != 0x03 && (vector_number & 0x0f) != 0x0b)
return;
 
t = EA;
EA = 0;
_standard_interrupt_vector[vector_number] = LJMP_OPCODE;
_standard_interrupt_vector[vector_number + 1] = addr >> 8;
_standard_interrupt_vector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* Hook usb interrupt vector.
*
* vector_number is from the UV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_uv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
#if UV_MIN>0
if (vector_number < UV_MIN) return;
#endif
if (vector_number > UV_MAX)
return;
 
if ((vector_number & 0x3) != 0)
return;
 
t = EA;
EA = 0;
_usb_autovector[vector_number] = LJMP_OPCODE;
_usb_autovector[vector_number + 1] = addr >> 8;
_usb_autovector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* Hook fifo/gpif interrupt vector.
*
* vector_number is from the FGV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_fgv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
if (vector_number < FGV_MIN || vector_number > FGV_MAX)
return;
 
if ((vector_number & 0x3) != 0)
return;
 
t = EA;
EA = 0;
_fifo_gpif_autovector[vector_number] = LJMP_OPCODE;
_fifo_gpif_autovector[vector_number + 1] = addr >> 8;
_fifo_gpif_autovector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* One time call to enable autovectoring for both USB and FIFO/GPIF.
*
* This disables all USB and FIFO/GPIF interrupts and clears
* any pending interrupts too. It leaves the master USB and FIFO/GPIF
* interrupts enabled.
*/
void
setup_autovectors (void)
{
// disable master usb and fifo/gpif interrupt enables
EIUSB = 0;
EIEX4 = 0;
 
hook_sv (SV_INT_2, (unsigned short) _usb_autovector);
hook_sv (SV_INT_4, (unsigned short) _fifo_gpif_autovector);
 
// disable all fifo interrupt enables
SYNCDELAY;
EP2FIFOIE = 0; SYNCDELAY;
EP4FIFOIE = 0; SYNCDELAY;
EP6FIFOIE = 0; SYNCDELAY;
EP8FIFOIE = 0; SYNCDELAY;
 
// clear all pending fifo irqs
EP2FIFOIRQ = 0xff; SYNCDELAY;
EP4FIFOIRQ = 0xff; SYNCDELAY;
EP6FIFOIRQ = 0xff; SYNCDELAY;
EP8FIFOIRQ = 0xff; SYNCDELAY;
 
IBNIE = 0;
IBNIRQ = 0xff;
NAKIE = 0;
NAKIRQ = 0xff;
USBIE = 0;
USBIRQ = 0xff;
EPIE = 0;
EPIRQ = 0xff;
SYNCDELAY; GPIFIE = 0;
SYNCDELAY; GPIFIRQ = 0xff;
USBERRIE = 0;
USBERRIRQ = 0xff;
CLRERRCNT = 0;
INTSETUP = bmAV2EN | bmAV4EN | bmINT4IN;
 
// clear master irq's for usb and fifo/gpif
EXIF &= ~bmEXIF_USBINT;
EXIF &= ~bmEXIF_IE4;
// enable master usb and fifo/gpif interrrupts
EIUSB = 1;
EIEX4 = 1;
}
/src/lib
src/lib Property changes : Added: svn:ignore ## -0,0 +1,43 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +libfx2.lib Index: src/dscr_gen.A51 =================================================================== --- src/dscr_gen.A51 (nonexistent) +++ src/dscr_gen.A51 (revision 33) @@ -0,0 +1,454 @@ +;;; -*- asm -*- +;;; $Id: dscr_gen.A51 605 2014-11-18 22:34:44Z mueller $ +;;; +;;; Copyright 2011-2014 by Walter F.J. Mueller +;;; Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 +;;; +;;;- original copyright and licence disclaimer --------------------------------- +;;;- Copyright 2005..2007 Kolja Waschk, ixo.de +;;;- Code based on USRP2 firmware (GNU Radio Project), version 3.0.2, +;;;- Copyright 2003 Free Software Foundation, Inc. +;;;- This code is part of usbjtag. usbjtag is free software; +;;;- --------------------------------------------------------------------------- +;;; +;;; This program is free software; you may redistribute and/or modify it under +;;; the terms of the GNU General Public License as published by the Free +;;; Software Foundation, either version 2, or at your option any later version. +;;; +;;; This program is distributed in the hope that it will be useful, but +;;; WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +;;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +;;; for complete details. +;;; +;;;----------------------------------------------------------------------------- +;;; USB Descriptor, common source for jtag + 0, 2, or 3 hardware fifo interface +;;; +;;; Use C preprocessor to create an assembler source for the configurations: +;;; +;;; Endpoint Usage Comment +;;; EP1 IN jtag always defined +;;; EP2 OUT jtag always defined +;;; EP4 OUT data defined if USE_2FIFO or USE_3FIFO +;;; EP6 IN data defined if USE_2FIFO or USE_3FIFO +;;; EP8 IN data defined if USE_3FIFO +;;; +;;; Available preprocessor options +;;; +;;; USE_VID USB Vendor ID +;;; USE_PID USB Product ID +;;; +;;; USE_2FIFO if given EP4 OUT and EP6 IN created +;;; USE_3FIFO if given EP4 OUT, EP6 IN and EP8 IN created +;;; USE_DID=0xhhhh for product version (default 0x0004) +;;; USE_MAXPOWER=nnn for USB max current (in units of 2 mA; default 250) +;;; +;;; USE_NEXYS2 prefix 'nexys2_' in iProduct string +;;; USE_NEXYS3 prefix 'nexys3_' in iProduct string +;;; USE_AS suffix '_as' in iProduct string +;;; USE_IC suffix '_ic' in iProduct string +;;; +;;; Usage +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 > ... +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 -DUSE_2FIFO > ... +;;; cpp -P -x assembler-with-cpp dscr_gen.A51 -DUSE_3FIFO > ... +;;; +;;; +;;; Revision History: +;;; +;;; Date Rev Version Comment +;;; 2014-11-18 605 2.2 BUGFIX: correct string 0 descriptor +;;; 2012-02-11 457 2.1 iVendor string now reflects firmware file name; +;;; iSerial string now 00000000; +;;; VID/PID now via USE_VID/USE_PID defines +;;; 2011-07-24 398 2.0 Convert all *.a51 to one common source +;;; 2011-07-17 395 1.1 Use USB 2.0; New string values; use 512 byte for +;;; all high speed endpoints +;;; 2011-07-17 395 1.0 Initial version (derived from dscr_jtag.a51) +;;;----------------------------------------------------------------------------- + +#ifndef USE_DID +#define USE_DID 0x0004 +#endif + +#ifndef USE_MAXPOWER +#define USE_MAXPOWER 250 +#endif + +#ifdef USE_3FIFO +#define NUM_EPS 5 +#elif USE_2FIFO +#define NUM_EPS 4 +#else +#define NUM_EPS 2 +#endif + + .module usb_descriptors + + VID = USE_VID ; Vendor ID + PID = USE_PID ; Product ID + VERSION = USE_DID ; Version + + USB_VER = 0x0200 ; Support USB version 2.00 + USB_ATTR = 0x80 ; Bus powered, no remote wakeup + FTD_ATTR = 0x001C ; Set USB version, use version string, enable suspend PD + MAX_POWER = USE_MAXPOWER + + DSCR_DEVICE = 1 ; Descriptor type: Device + DSCR_CONFIG = 2 ; Descriptor type: Configuration + DSCR_STRING = 3 ; Descriptor type: String + DSCR_INTRFC = 4 ; Descriptor type: Interface + DSCR_ENDPNT = 5 ; Descriptor type: Endpoint + DSCR_DEVQUAL = 6 ; Descriptor type: Device Qualifier + + DSCR_DEVICE_LEN = 18 + DSCR_CONFIG_LEN = 9 + DSCR_INTRFC_LEN = 9 + DSCR_ENDPNT_LEN = 7 + DSCR_DEVQUAL_LEN = 10 + + ET_CONTROL = 0 ; Endpoint type: Control + ET_ISO = 1 ; Endpoint type: Isochronous + ET_BULK = 2 ; Endpoint type: Bulk + ET_INT = 3 ; Endpoint type: Interrupt + +;;; -------------------------------------------------------- +;;; external ram data +;;;-------------------------------------------------------- + + .area USBDESCSEG (XDATA) + + .even ; descriptors must be 2-byte aligned for SUDPTR{H,L} to work + + ;; The .even directive isn't really honored by the linker. Bummer! + ;; (There's no way to specify an alignment requirement for a given area, + ;; hence when they're concatenated together, even doesn't work.) + ;; + ;; We work around this by telling the linker to put USBDESCSEG + ;; at absolute address 0xE100 (see LDFLAGS in Makefile). + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at high speed (480Mbps) +;;; ---------------------------------------------------------------- + +_high_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE +_dscr_usbver:: + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 +_dscr_vidpidver:: + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice +_dscr_strorder:: + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + + .even +_high_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB (MSB) + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 12Mbps) + .db 0 ; bReserved + + .even +_high_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_high_speed_config_descr_end - _high_speed_config_descr) + .db >(_high_speed_config_descr_end - _high_speed_config_descr) + .db 1 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration +_dscr_attrpow:: + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 2 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db NUM_EPS ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor (jtag response) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (EP 1 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) !! use only 64 byte + .db >512 ; wMaxPacketSize (MSB) !! use only 64 byte + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor (jtag request) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (EP 2 OUT) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) !! use only 64 byte + .db >512 ; wMaxPacketSize (MSB) !! use only 64 byte + .db 0 ; bInterval (iso only) + +#if defined(USE_2FIFO) || defined(USE_3FIFO) + + ;; endpoint descriptor (RXFIFO HOST->FPGA) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x04 ; bEndpointAddress (EP 4 OUT) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor (TXFIFO FPGA->HOST) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x86 ; bEndpointAddress (EP 6 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +#endif + +#if defined(USE_3FIFO) + + ;; endpoint descriptor (extra FIFO FPGA->HOST) + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x88 ; bEndpointAddress (EP 8 IN) + .db ET_BULK ; bmAttributes + .db <512 ; wMaxPacketSize (LSB) + .db >512 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +#endif + +_high_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; descriptors used when operating at full speed (12Mbps) +;;; no data fifo endpoints defined, if we are in full speed mode this will be no +;;; fun anyway. Shouldn't happen anyway, unless stone age USB hubs interfere... +;;; ---------------------------------------------------------------- + + .even +_full_speed_device_descr:: + .db DSCR_DEVICE_LEN + .db DSCR_DEVICE + .db USB_VER ; Specification version (MSB) + .db 0x00 ; device class (vendor specific) + .db 0x00 ; device subclass (vendor specific) + .db 0x00 ; device protocol (vendor specific) + .db 64 ; bMaxPacketSize0 for endpoint 0 + .db VID ; idVendor + .db PID ; idProduct + .db VERSION ; bcdDevice + .db SI_VENDOR ; iManufacturer (string index) + .db SI_PRODUCT ; iProduct (string index) + .db SI_SERIAL ; iSerial number (string index) + .db 1 ; bNumConfigurations + +;;; describes the other speed (480Mbps) + .even +_full_speed_devqual_descr:: + .db DSCR_DEVQUAL_LEN + .db DSCR_DEVQUAL + .db USB_VER ; bcdUSB + .db 0xFF ; bDeviceClass + .db 0xFF ; bDeviceSubClass + .db 0xFF ; bDeviceProtocol + .db 64 ; bMaxPacketSize0 + .db 1 ; bNumConfigurations (one config at 480Mbps) + .db 0 ; bReserved + + .even +_full_speed_config_descr:: + .db DSCR_CONFIG_LEN + .db DSCR_CONFIG + .db <(_full_speed_config_descr_end - _full_speed_config_descr) + .db >(_full_speed_config_descr_end - _full_speed_config_descr) + .db 1 ; bNumInterfaces + .db 1 ; bConfigurationValue + .db 0 ; iConfiguration + .db USB_ATTR ; bmAttributes + .db MAX_POWER ; bMaxPower [Unit: 2 mA] + + ;; interface descriptor + + .db DSCR_INTRFC_LEN + .db DSCR_INTRFC + .db 0 ; bInterfaceNumber (zero based) + .db 0 ; bAlternateSetting + .db 2 ; bNumEndpoints + .db 0xFF ; bInterfaceClass (vendor specific) + .db 0xFF ; bInterfaceSubClass (vendor specific) + .db 0xFF ; bInterfaceProtocol (vendor specific) + .db SI_PRODUCT ; iInterface (description) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x81 ; bEndpointAddress (EP 1 IN) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + + ;; endpoint descriptor + + .db DSCR_ENDPNT_LEN + .db DSCR_ENDPNT + .db 0x02 ; bEndpointAddress (EP 2 OUT) + .db ET_BULK ; bmAttributes + .db <64 ; wMaxPacketSize (LSB) + .db >64 ; wMaxPacketSize (MSB) + .db 0 ; bInterval (iso only) + +_full_speed_config_descr_end: + +;;; ---------------------------------------------------------------- +;;; string descriptors +;;; ---------------------------------------------------------------- + +_nstring_descriptors:: + .db (_string_descriptors_end - _string_descriptors) / 2 + +_string_descriptors:: + .db str0 + .db str1 + .db str2 + .db str3 +_string_descriptors_end: + + SI_NONE = 0 + ;; str0 contains the language ID's. + .even +_str0:: +str0: .db str0_end - str0 + .db DSCR_STRING + .db <0x0409 ; magic code for US English (LSB) + .db >0x0409 ; magic code for US English (MSB) +str0_end: + + SI_VENDOR = 1 + .even +_str1:: +str1: .db str1_end - str1 + .db DSCR_STRING + .db 'w, 0 ; 16-bit unicode + .db 'w, 0 + .db 'w, 0 + .db '., 0 + .db 'r, 0 + .db 'e, 0 + .db 't, 0 + .db 'r, 0 + .db 'o, 0 + .db '1, 0 + .db '1, 0 + .db '., 0 + .db 'd, 0 + .db 'e, 0 +str1_end: + + SI_PRODUCT = 2 + .even +_str2:: +str2: .db str2_end - str2 + .db DSCR_STRING +#if defined(USE_NEXYS2) + .db 'n, 0 + .db 'e, 0 + .db 'x, 0 + .db 'y, 0 + .db 's, 0 + .db '2, 0 + .db '_, 0 +#endif +#if defined(USE_NEXYS3) + .db 'n, 0 + .db 'e, 0 + .db 'x, 0 + .db 'y, 0 + .db 's, 0 + .db '3, 0 + .db '_, 0 +#endif + .db 'j, 0 + .db 't, 0 + .db 'a, 0 + .db 'g, 0 +#if defined(USE_2FIFO) + .db '_, 0 + .db '2, 0 + .db 'f, 0 + .db 'i, 0 + .db 'f, 0 + .db 'o, 0 +#endif +#if defined(USE_3FIFO) + .db '_, 0 + .db '3, 0 + .db 'f, 0 + .db 'i, 0 + .db 'f, 0 + .db 'o, 0 +#endif +#if defined(USE_AS) + .db '_, 0 + .db 'a, 0 + .db 's, 0 +#endif +#if defined(USE_IC) + .db '_, 0 + .db 'i, 0 + .db 'c, 0 +#endif +str2_end: + + SI_SERIAL = 3 + .even +_str3:: +str3: .db str3_end - str3 + .db DSCR_STRING + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 + .db '0, 0 +str3_end: Index: src/README.txt =================================================================== --- src/README.txt (nonexistent) +++ src/README.txt (revision 33) @@ -0,0 +1,79 @@ +# $Id: README.txt 604 2014-11-16 22:33:09Z mueller $ +# + +The FX2 software is based on the Sourceforge project ixo-jtag + + http://sourceforge.net/projects/ixo-jtag/ + +The usb_jtag sub project was checked out on 2011-07-17 (Rev 204) from +Sourceforge and take as the basis for the further developement. +The original README.txt is preserved under README_iso_jtag.txt. +Only the hw_nexys.c branch is kept on the import. + +Change log: + +2014-11-16 (Rev 604) + - ported to sdcc 3.3 + - all prior development was done with sdcc 2.x, latest sdcc 2.9 was bundled + with Ubuntu 12.04 LTS. + - now switching to sdcc 3.3 as bundled with Ubuntu 14.04 LTS. + - mayor changes: + 1. assembler now named sdas8051 (was asx8051) + 2. all special reserved keywords start now with a double underscore + at --> __at + bit --> __bit + interrupt --> __interrupt + sbit --> __sbit + sfr --> __sfr + xdata --> __xdata + _asm --> __asm + _endasm --> __endasm + _naked --> __naked + - in general sources stayed untouched in the sdcc 2.9 form, all keyword + mappings are done with the preprocessor and defs like "-Dat=__at" + + - make usage now + - default is now sdcc 3.x, in this case simply use + + make clean && make + + - on systems with sdcc 2.x use + + make clean && make SDCC29=1 + + - detected and fixed BUG inherted from ixo-jtag and GNU Radio in SYNCDELAY + The macro SYNCDELAY (defined in lib/syncdelay.h) inserts 'nop' needed + to resolve some timing issues in the FX2. The old implementation was + + #define SYNCDELAY _asm nop; nop; nop; _endasm + #define NOP _asm nop; _endasm + + This inserts into the assembler output a single line + nop; nop; nop; + Since ';' is the comment delimiter for the assember the 2nd and 3rd nop + are simply ignored. + + This wrong implementation was changed to + #define SYNCDELAY NOP; NOP; NOP + That created three lines in the assembler output + nop; + nop; + nop; + and generated the three desired nops in the binary. + + !! This was definitively broken from the very beginning. !! + !! The code ran alway. Reason is mosu likely that the SYNCDELAY !! + !! macros were only used in the setup phase and never is a !! + !! really time critical context. !! + +2011-07-17 (Rev 395) + - Makefile: reorganized to support multiple target/fifo configs + - renames: + dscr.a51->dscr_jtag.a51 + hw_nexys.c->hw_nexys2.c + usbjtag.c->main.c + - dscr_jtag.a51 + - Use USB 2.0; New string values + - use 512 byte for all high speed endpoints + - dscr_jtag_2fifo.a51 + - dscr with EP4 as HOST->FPGA and EP6 as FPGA->HOST hardware fifo Index: src/.cvsignore =================================================================== --- src/.cvsignore (nonexistent) +++ src/.cvsignore (revision 33) @@ -0,0 +1,11 @@ +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +*.lk +dscr_*.a51 Index: src/README_iso_jtag.txt =================================================================== --- src/README_iso_jtag.txt (nonexistent) +++ src/README_iso_jtag.txt (revision 33) @@ -0,0 +1,123 @@ +$Id: README_iso_jtag.txt 525 2013-07-06 12:19:39Z mueller $ + +usb_jtag using Cypress FX2 chip +=============================== + +== General information == + +The code in this directory is for Cypress FX2 (e.g. CY7C68013A) and can be +compiled with the SDCC compiler (I tried version 2.6 as shipped with Ubuntu +6.10). Once I had a version that could be compiled with Keil tools (until early +2007), but switched to SDCC because I usually develop on a Linux host. + +No logic beside the FX2 itself and only a few external components are required +for a basic JTAG adapter. I don't have detailed schematics available; my test +setup consists of a FX2 on a custom board where it's directly connected to a +Cyclone FPGA. + + ____________ + | | + | Cypress | + USB__| EZ-USB FX2 |__JTAG(TDI,TDO,TCK,TMS) + | CY7C68013A | + |____________| + __|__________ + | | + | 24 MHz XTAL | + |_____________| + + +Similar boards are available from fpga4fun.com - the boards named "Saxo-L" and +"Xylo-EM" are pre-wired for use with an adapted version of my code, while +"Saxo" and "Xylo" can be used after soldering 4 extra wires: + + http://www.fpga4fun.com/board_Xylo.html + +There's a discussion thread in the fpga4fun forum about this firmware: + + http://www.fpga4fun.com/forum/viewtopic.php?t=483 + + +== Use with Nexys 1 / 2 Boards == + +Through a contribution by Sune Mai, this code can be used with the Digilent +Nexys / Nexys2 boards. + + http://www.digilentinc.com/nexys/ + http://www.digilentinc.com/nexys2/ + +The hardware-specific code file is hw_nexys.c, just change the line +"HARDWARE=hw_basic" to "HARDWARE=hw_nexys" in the file "Makefile" to use it. + +Also, you may use the "nexys2prog" script by Andy Ross, available from the +same place this code is available from: + + http://ixo-jtag.sourceforge.net/ + + +== Adapting the code to your hardware == + +As is, the code assumes the following pin assignment: + + Port C.0: TDI + Port C.1: TDO + Port C.2: TCK + Port C.3: TMS + +Other assignments are possible. If you have your signals connected to +bit-addressable I/O pins (port A,B,C or D), I suggest you make a copy of +hw_basic.c and adapt the definitions and ProgIO_Init() in it to your needs. +The file hw_saxo_l is even simpler to adapt if you want only JTAG and no AS/PS +mode. If your signals are not on bit-addressable I/Os (that is, you're using +port E), you could base your adaptation on the slower hw_xpcu_i.c. You may +specify the name of your adapted hardware-specific file when "make"ing, e.g.: + + make HARDWARE=hw_saxo_l + + +The USB identification data (vendor/product ID, strings, ...) can be modified +in dscr.a51. The firmware emulates the 128 byte EEPROM that usually holds +configuration data for the FT245 and which can be read from the host; its +content (including checksum) is computed from the data in dscr.a51 as well. + +The WAKEUP pin should be high for the re-numeration to work reliably (thanks +Jean/fpga4fun!). + + +== Using it with Xilinx JTAG cable == + +There is code to support running in the "Xilinx Platform Cable USB". If you +select HARDWARE=hw_xpcu_i or hw_xpcu_x at the top of the Makefile, a firmware +for the XPCU will be built. I've tested this only with unmodified CPLD version +18 (0x12) on a Spartan-3E starter kit, as it was programmed by my WebPack 8.2i. +The code needs optimization; yet it is merely a proof of concept. +Compile for the XPCU with e.g. "make HARDWARE=hw_xpcu_x". + + hw_xpcu_i: Access "internal" chain (the XPCU CPLD, IC3, itself) + hw_xpcu_x: Access "external" chain (the Spartan 3E, PROM, etc.) + + +== History == + +Changes since previous release 2008-07-05: + - Imported to SourceForge, please see the project page: + http://ixo-jtag.sourceforge.net/ + +Changes since previous release on 2007-02-15: + - Jean Nicolle contributed hw_saxo_l.c for the FX2 boards from fpga4fun.com + - fx2/Makefile fixed to build correct libfx2.lib even under Windows. + +Changes since previous release on 2007-01-28: + - Initial suppport for running on Xilinx XPCU. + - New FX2 code, based on USRP2 from the GNU Radio Project; + - Firmware can now be compiled using SDCC 2.6. No more Keil support. + - EEPROM content is automatically computed from dscr.a51, including checksum. + +Changes since initial release on 2006-04-23: + - added this readme.txt + - reorganized my project folder: diff now created from Subversion repository + - stripped *.dist extension from eeprom.c and dscr.a51 + - added unique proper product and vendor ID (thanks to Antti Lukats!) + - fixed checksum in eeprom.c + - added comments about AS/PS mode pins in usbjtag.c + Index: src/usb_fifo_init.c =================================================================== --- src/usb_fifo_init.c (nonexistent) +++ src/usb_fifo_init.c (revision 33) @@ -0,0 +1,210 @@ +/* $Id: usb_fifo_init.c 450 2012-01-05 23:21:41Z mueller $ */ +/* + * Copyright 2011-2012 by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * The data fifo treatment is partially inspired by work of Marco Oster + * done at ZITI, Heidelberg in 2010. + * + * - original copyright and licence disclaimer (of usb_jtag_init) ------------- + * - Code that turns a Cypress FX2 USB Controller into an USB JTAG adapter + * - Copyright (C) 2005..2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + *----------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + *----------------------------------------------------------------------------- + * + * USB FIFO setup + * + * Revision History: + * + * Date Rev Version Comment + * 2012-01-04 450 1.5 new FLAGS layout (D=8-FF,C=4-EF,B=6-FF,A=indexed) + * 2012-01-02 448 1.4 add support for sync fifo w/ int. clock (_ic) + * 2011-07-24 398 1.1 support 0,2, or 3 data FIFO's + * 2011-07-23 397 1.0 Initial version, factored out from usb_jtag_init() + * + *----------------------------------------------------------------------------- + */ + +#include "fx2regs.h" +#include "syncdelay.h" + +//----------------------------------------------------------------------------- + +void usb_fifo_init(void) // Called once at startup +{ + // set the CPU clock to 48MHz, enable USB clock output to FPGA + // Note: CLKOUT not connected on nexys2, nexys3 and atlys... + CPUCS = bmCLKOE | bmCLKSPD1; + + // setup FIFO mode + // bmIFCLKSRC clock source: 0 external clock; 1 internal clock + // bm3048MHZ clock frequency: 0 30 MHz; 1 48 MHz + // bmIFCLKOE IFCLK pin output enable: 0 tri-state; 1 drive + // bmIFCLKPOL clock polarity: 0 rising edge active; 1 falling edge active + // bmASYNC fifo mode: 0 synchrounous; 1 asynchronous + // IFCFG interface mode: bmIFCFGMASK=11->slave fifo + +#if defined(USE_IC30) + // Use internal 30 MHz, enable output, slave sync FIFO, slave FIFO mode + IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmIFCFGMASK; +#else + // Use internal 30 MHz, enable output, slave async FIFO, slave FIFO mode + IFCONFIG = bmIFCLKSRC | bmIFCLKOE | bmASYNC | bmIFCFGMASK; +#endif + + // Setup PA7 as FLAGD + PORTACFG = 0x80; SYNCDELAY; // 1000 0000: FLAGD=1, SLCS=0 + + // setup usage of FLAG pins + // goal is to support EP4(out) and EP6/EP8(in) synchronous slave fifos + // for synchronous operation usage of empty/full and almost empty/full + // flags is needed, the later are realized with the programmable flags. + // the three empty/full flags are setup as fixed flags, while the three + // almost (or programmable) flags are channeled over one indexed flag pin. + // FLAGA = indexed, PF (the default) + // FLAGB = EP6 FF + // FLAGC = EP4 EF + // FLAGD = EP8 FF + + PINFLAGSAB = 0xE0; SYNCDELAY; // 1110 0000: B EP6 FF, A indexed + PINFLAGSCD = 0xF9; SYNCDELAY; // 1111 1001: D EP8 FF, C EP4 EF + + // define endpoint configuration + + FIFORESET = 0x80; SYNCDELAY; // From now on, NAK all + REVCTL = 3; SYNCDELAY; // Allow FW access to FIFO buffer + + // FIFOs used for JTAG emulation + // EP1 IN + // EP2 OUT + + EP1OUTCFG = 0x00; SYNCDELAY; // EP1 OUT: inactive + EP1INCFG = 0xA0; SYNCDELAY; // EP1 IN: active, bulk + + EP2FIFOCFG = 0x00; SYNCDELAY; // EP2 slave: 0, not used as slave + FIFORESET = 0x02; SYNCDELAY; // EP2 reset (0x02! see comment below) + EP2CFG = 0xA2; SYNCDELAY; // EP2: 1010 0010: VAL,OUT,BULK,DOUBLE + + // TMR (Rev *D) page 117: auto in/out initialization sequence + // Auto IN transfers + // 1. setup EPxCFG + // 2. reset the FIFO + // 3. set EPxFIFOCFG.3 = 1 + // 4. set EPxAUTOINLENH:L + // Auto OUT transfers + // 1. setup EPxCFG + // 2. reset the FIFO + // 3. arm OUT buffers by writing OUTPKTEND N times w/ skip=1 (N=buf depth) + // 4. set EPxFIFOCFG.4 = 1 + + // 2 FIFOs used for DATA transfer: + // EP4 OUT DOUBLE + // EP6 IN QUAD + +#if defined(USE_2FIFO) || defined(USE_3FIFO) + EP4CFG = 0xA2; SYNCDELAY; // EP4: 1010 0010: VAL,OUT,BULK,DOUBLE +#if defined(USE_3FIFO) + EP6CFG = 0xE2; SYNCDELAY; // EP6: 1110 0010: VAL,IN,BULK,DOUBLE + EP8CFG = 0xE2; SYNCDELAY; // EP8: 1110 0010: VAL,IN,BULK,DOUBLE +#else + EP6CFG = 0xE0; SYNCDELAY; // EP6: 1110 0000: VAL,IN,BULK,QUAD + EP8CFG = 0x02; SYNCDELAY; // EP8: disabled +#endif + + // Note: the description of the FIFORESET in the TMR, Rev *D (2011) is + // wrong. The TMR asks to write 0x80,0x82,0x84,0x86,0x88,0x00, e.g + // on page 117, also in other contexts. + // This doesn't work, FIFO's are in fact not reset ! + // The proper sequence is 0x80,0x02,0x04,0x06,0x08,0x00, as for + // example stated in http://www.cypress.com/?id=4&rID=32093 + FIFORESET = 0x04; SYNCDELAY; // EP4 reset + FIFORESET = 0x06; SYNCDELAY; // EP6 reset + FIFORESET = 0x08; SYNCDELAY; // EP8 reset + FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour + + // !! really needed here, before buffers are armed !! + REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer + + // EP4 OUT setup --------------------------------------------------- + OUTPKTEND = 0x84; SYNCDELAY; // arm all EP4 buffers + OUTPKTEND = 0x84; SYNCDELAY; + // !! hardware only arms endpoint when AUTOOUT 0->1 transition seen + // !! --> clean AUTOOUT to handle for example back-to-back firmware loads + EP4FIFOCFG = 0x00; SYNCDELAY; // EP4: force AUTOOUT 0->1 transition + EP4FIFOCFG = 0x10; SYNCDELAY; // EP4: 0001 0000: AUTOOUT, BYTE + // setup programmable fifo threshold as 'almost empty' at 3 bytes to go + // --> keep active low logic for prgrammable flags + // --> set flag 1 when fill >= threshold (DECIS=1) + // --> almost empty thus at fill<4, effective threshold thus 3 !! + EP4FIFOPFH = 0x80; SYNCDELAY; // 0000 0000: DECIS=1, PFC8=0 + EP4FIFOPFL = 0x04; SYNCDELAY; // PFC = 4 = 0 0000 0100 + + // EP6 IN setup --------------------------------------------------- + EP6FIFOCFG = 0x0C; SYNCDELAY; // EP6: 0000 1100: AUTOIN, ZEROLEN, BYTE + EP6AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers + EP6AUTOINLENL = 0x00; SYNCDELAY; + + // setup programmable fifo threshold as 'almost full' at 3 bytes to go + // --> keep active low logic for prgrammable flags + // --> set flag 1 when fill <= threshold (DECIS=0) + // --> use full buffer fill + // --> for dual buffered: (PKSTAT=0, PKTS=1) [in case 3 fifo's used] + // --> for quad buffered: (PKSTAT=0, PKTS=3) [in case 2 fifo's used] + // --> effective threshold thus 3 in both bases +#if defined(USE_3FIFO) + EP6FIFOPFH = 0x09; SYNCDELAY; // 0000 1001: DECIS=0, PK=0:1, PFC8=1 +#else + EP6FIFOPFH = 0x19; SYNCDELAY; // 0001 1001: DECIS=0, PK=0:3, PFC8=1 +#endif + EP6FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100 + +#if defined(USE_3FIFO) + // EP8 IN setup --------------------------------------------------- + EP8FIFOCFG = 0x0C; SYNCDELAY; // EP8: 0000 1100: AUTOIN, ZEROLEN, BYTE + EP8AUTOINLENH = 0x02; SYNCDELAY; // 512 byte buffers + EP8AUTOINLENL = 0x00; SYNCDELAY; + // setup programmable fifo threshold as 'almost full' at 4 bytes to go + // like for EP6 above + EP8FIFOPFH = 0x41; SYNCDELAY; // 0100 0001: DECIS=0, PKSTAT=1, PFC8=1 + EP8FIFOPFL = 0xfc; SYNCDELAY; // PFC = 508 = 1 1111 1100 + +#else + // EP8 setup + EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave +#endif + +#else + // no FIFOs used for DATA transfer + // EP4,6,8 inactive + EP4CFG = 0x02; SYNCDELAY; // EP4: disabled + EP6CFG = 0x02; SYNCDELAY; // EP6: disabled + EP8CFG = 0x02; SYNCDELAY; // EP8: disabled + + FIFORESET = 0x04; SYNCDELAY; // EP4 reset + FIFORESET = 0x06; SYNCDELAY; // EP6 reset + FIFORESET = 0x08; SYNCDELAY; // EP8 reset + FIFORESET = 0x00; SYNCDELAY; // Restore normal behaviour + + EP4FIFOCFG = 0x00; SYNCDELAY; // EP4 slave: 0, not used as slave + EP6FIFOCFG = 0x00; SYNCDELAY; // EP6 slave: 0, not used as slave + EP8FIFOCFG = 0x00; SYNCDELAY; // EP8 slave: 0, not used as slave + + REVCTL = 0; SYNCDELAY; // Reset FW access to FIFO buffer +#endif + + // the EP2 endpoint does not come up armed. It is used with double buffering + // so write dummy byte counts twice. + SYNCDELAY; // + EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT + EP2BCL = 0x80; SYNCDELAY; // arm EP2OUT +} Index: src/hardware.h =================================================================== --- src/hardware.h (nonexistent) +++ src/hardware.h (revision 33) @@ -0,0 +1,35 @@ +/* $Id: hardware.h 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _HARDWARE_H +#define _HARDWARE_H 1 + +extern void ProgIO_Init(void); +extern void ProgIO_Poll(void); +extern void ProgIO_Enable(void); +extern void ProgIO_Disable(void); +extern void ProgIO_Deinit(void); + +extern void ProgIO_Set_State(unsigned char d); +extern unsigned char ProgIO_Set_Get_State(unsigned char d); +extern void ProgIO_ShiftOut(unsigned char x); +extern unsigned char ProgIO_ShiftInOut(unsigned char x); + +#endif /* _HARDWARE_H */ + Index: src/hw_nexys2.c =================================================================== --- src/hw_nexys2.c (nonexistent) +++ src/hw_nexys2.c (revision 33) @@ -0,0 +1,284 @@ +/* $Id: hw_nexys2.c 447 2011-12-31 19:41:32Z mueller $ */ +/* + * Copyright 2011- by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * + * - original copyright and licence disclaimer -------------------------------- + * - Copyright (C) 2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + * - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2) + * - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling + * - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50 + * ---------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * ---------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + * + * Revision History: + * + * Date Rev Version Comment + * 2011-12-30 447 1.2.1 move JTAG pin OE intoProgIO_Set_State() + * 2011-12-29 446 1.2 clean-out all code not relevant for nexys2 + * 2011-07-23 397 1.1 move IFCONFIG and CPUCS init to usb_fifo_init + * 2011-07-17 394 1.0 Initial version (from ixo-jtag/usb_jtag Rev 204) + * + *----------------------------------------------------------------------------- + */ + +#include +#include "hardware.h" +#include "delay.h" + +//----------------------------------------------------------------------------- + +/* JTAG TCK, AS/PS DCLK */ + +sbit at 0xB4 TCK; /* Port D.4 */ +#define bmTCKOE bmBIT4 +#define SetTCK(x) do{TCK=(x);}while(0) + +/* JTAG TDI, AS ASDI, PS DATA0 */ + +sbit at 0xB2 TDI; /* Port D.2 */ +#define bmTDIOE bmBIT2 +#define SetTDI(x) do{TDI=(x);}while(0) + +/* JTAG TMS, AS/PS nCONFIG */ + +sbit at 0xB3 TMS; /* Port D.3 */ +#define bmTMSOE bmBIT3 +#define SetTMS(x) do{TMS=(x);}while(0) + +/* JTAG TDO, AS/PS CONF_DONE */ + +sbit at 0xB0 TDO; /* Port D.0 */ +#define bmTDOOE bmBIT0 +#define GetTDO(x) TDO + +/* USB Power-On (Nexys2 specific !!) */ + +sbit at 0xB7 USBPOW; /* Port D.7 */ +#define bmUSBPOWOE bmBIT7 +#define SetUSBPOW(x) do{USBPOW=(x);}while(0) + +//----------------------------------------------------------------------------- + +#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE) +#define bmPROGINOE (bmTDOOE) + +//----------------------------------------------------------------------------- + +void ProgIO_Poll(void) {} +void ProgIO_Enable(void) {} +// These aren't called anywhere in usbjtag.c so far, might come... +void ProgIO_Disable(void) {} +void ProgIO_Deinit(void) {} + + +void ProgIO_Init(void) +{ + /* The following code depends on your actual circuit design. + Make required changes _before_ you try the code! */ + + // power on the onboard FPGA: + // output enable and set to 1 the Nexys2 USB-Power-enable signal + SetUSBPOW(1); + OED=bmUSBPOWOE; + // Note: JTAG signal output enables are in ProgIO_Set_State() below. + + mdelay(500); // wait for supply to come up +} + +void ProgIO_Set_State(unsigned char d) +{ + /* Set state of output pins: + * + * d.0 => TCK + * d.1 => TMS + * d.4 => TDI + */ + + // JTAG signal output enables done at first request: + // this allows to use the JTAG connector with another JTAG cable + // alternatively. + OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable + + SetTCK((d & bmBIT0) ? 1 : 0); + SetTMS((d & bmBIT1) ? 1 : 0); + SetTDI((d & bmBIT4) ? 1 : 0); +} + +//----------------------------------------------------------------------------- +// dummied AS/PS code +#define GetASDO(x) 1 + +unsigned char ProgIO_Set_Get_State(unsigned char d) +{ + /* Set state of output pins (s.a.) + * then read state of input pins: + * + * TDO => d.0 + * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE) + */ + + ProgIO_Set_State(d); + return (GetASDO()<<1)|GetTDO(); +} + +//----------------------------------------------------------------------------- + +void ProgIO_ShiftOut(unsigned char c) +{ + /* Shift out byte C: + * + * 8x { + * Output least significant bit on TDI + * Raise TCK + * Shift c right + * Lower TCK + * } + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + ;; Bit0 + RRC A + MOV _TDI,C + SETB _TCK + ;; Bit1 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit2 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit3 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit4 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit5 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit6 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit7 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + ret + _endasm; +} + +/* +;; For ShiftInOut, the timing is a little more +;; critical because we have to read _TDO/shift/set _TDI +;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz +;; is just like 50% at 6 Mhz, and that's still acceptable +*/ + +unsigned char ProgIO_ShiftInOut(unsigned char c) +{ + /* Shift out byte C, shift in from TDO: + * + * 8x { + * Read carry from TDO + * Output least significant bit on TDI + * Raise TCK + * Shift c right, append carry (TDO) at left + * Lower TCK + * } + * Return c. + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + + ;; Bit0 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit1 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit2 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit3 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit4 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit5 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit6 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit7 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + + MOV DPL,A + ret + _endasm; + + /* return value in DPL */ + + return c; +} + Index: src/startup.a51 =================================================================== --- src/startup.a51 (nonexistent) +++ src/startup.a51 (revision 33) @@ -0,0 +1,79 @@ +;;; -*- asm -*- +;;; $Id: startup.a51 395 2011-07-17 22:02:55Z mueller $ +;;; +;;;----------------------------------------------------------------------------- +;;; Startup code +;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; The default external memory initialization provided by sdcc is not +;;; appropriate to the FX2. This is derived from the sdcc code, but uses +;;; the FX2 specific _MPAGE sfr. + + + ;; .area XISEG (XDATA) ; the initialized external data area + ;; .area XINIT (CODE) ; the code space consts to init XISEG + .area XSEG (XDATA) ; zero initialized xdata + .area USBDESCSEG (XDATA) ; usb descriptors + + + .area CSEG (CODE) + + ;; sfr that sets upper address byte of MOVX using @r0 or @r1 + _MPAGE = 0x0092 + +__sdcc_external_startup:: + ;; This system is now compiled with the --no-xinit-opt + ;; which means that any initialized XDATA is handled + ;; inline by code in the GSINIT segs emitted for each file. + ;; + ;; We zero XSEG and all of the internal ram to ensure + ;; a known good state for uninitialized variables. + +; _mcs51_genRAMCLEAR() start + mov r0,#l_XSEG + mov a,r0 + orl a,#(l_XSEG >> 8) + jz 00002$ + mov r1,#((l_XSEG + 255) >> 8) + mov dptr,#s_XSEG + clr a + +00001$: movx @dptr,a + inc dptr + djnz r0,00001$ + djnz r1,00001$ + + ;; We're about to clear internal memory. This will overwrite + ;; the stack which contains our return address. + ;; Pop our return address into DPH, DPL +00002$: pop dph + pop dpl + + ;; R0 and A contain 0. This loop will execute 256 times. + ;; + ;; FWIW the first iteration writes direct address 0x00, + ;; which is the location of r0. We get lucky, we're + ;; writing the correct value (0) + +00003$: mov @r0,a + djnz r0,00003$ + + push dpl ; restore our return address + push dph + + mov dpl,#0 ; indicate that data init is still required + ret Index: src/eeprom.c =================================================================== --- src/eeprom.c (nonexistent) +++ src/eeprom.c (revision 33) @@ -0,0 +1,78 @@ +/* $Id: eeprom.c 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#include "eeprom.h" +#include "usb_descriptors.h" + +xdata unsigned char eeprom[128]; + +extern xdata char dscr_vidpidver[6]; +extern xdata char dscr_attrpow[2]; +extern xdata char dscr_usbver[2]; +extern xdata char dscr_strorder[4]; +extern xdata char str1[]; +extern xdata char str2[]; +extern xdata char str3[]; + +static unsigned char ee_ptr; +static unsigned short ee_cksum; + +void eeprom_append(unsigned char nb) +{ + unsigned char pree_ptr = ee_ptr & ~1; + if(pree_ptr != ee_ptr) + { + ee_cksum = ee_cksum ^((unsigned short)nb << 8); + ee_cksum = ee_cksum ^ eeprom[pree_ptr]; + ee_cksum = (ee_cksum << 1) | (ee_cksum >> 15); + }; + eeprom[ee_ptr++] = nb; +} + +void eeprom_init(void) +{ + char j,sofs; + ee_ptr = 0; + ee_cksum = 0xAAAA; + + eeprom_append(0x00); + eeprom_append(0x00); + for(j=0;j<6;j++) eeprom_append(dscr_vidpidver[j]); + for(j=0;j<2;j++) eeprom_append(dscr_attrpow[j]); + eeprom_append(0x1C); + eeprom_append(0x00); + for(j=0;j<2;j++) eeprom_append(dscr_usbver[j]); + sofs = 0x80 + ee_ptr + 6; + eeprom_append(sofs); + eeprom_append(str1[0]); + sofs += str1[0]; + eeprom_append(sofs); + eeprom_append(str2[0]); + sofs += str2[0]; + eeprom_append(sofs); + eeprom_append(str3[0]); + for(j=0;j>8)&0xFF; +} + Index: src/hw_nexys3.c =================================================================== --- src/hw_nexys3.c (nonexistent) +++ src/hw_nexys3.c (revision 33) @@ -0,0 +1,274 @@ +/* $Id: hw_nexys3.c 447 2011-12-31 19:41:32Z mueller $ */ +/* + * Copyright 2011- by Walter F.J. Mueller + * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17 + * + * - original copyright and licence disclaimer -------------------------------- + * - Copyright (C) 2007 Kolja Waschk, ixo.de + * - This code is part of usbjtag. usbjtag is free software; + * - This code was copied from hw_basic.c and adapted for the Digilent Nexys(2) + * - boards by Sune Mai (Oct 2008) with minor cleanups by Hauke Daempfling + * - (May 2010). See http://www.fpga4fun.com/forum/viewtopic.php?t=483&start=50 + * ---------------------------------------------------------------------------- + * + * This program is free software; you may redistribute and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation, either version 2, or at your option any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for complete details. + * + * ---------------------------------------------------------------------------- + * Hardware-dependent code for usb_jtag + * + * Revision History: + * + * Date Rev Version Comment + * 2011-12-30 447 1.0.1 move JTAG pin OE intoProgIO_Set_State() + * 2011-12-29 446 1.0 Initial version (adapt&cleanup from hw_nexys2.c) + * + *----------------------------------------------------------------------------- + */ + +#include +#include "hardware.h" +#include "delay.h" + +//----------------------------------------------------------------------------- + +/* JTAG TCK, AS/PS DCLK */ + +sbit at 0xB4 TCK; /* Port D.4 */ +#define bmTCKOE bmBIT4 +#define SetTCK(x) do{TCK=(x);}while(0) + +/* JTAG TDI, AS ASDI, PS DATA0 */ + +sbit at 0xB2 TDI; /* Port D.2 */ +#define bmTDIOE bmBIT2 +#define SetTDI(x) do{TDI=(x);}while(0) + +/* JTAG TMS, AS/PS nCONFIG */ + +sbit at 0xB3 TMS; /* Port D.3 */ +#define bmTMSOE bmBIT3 +#define SetTMS(x) do{TMS=(x);}while(0) + +/* JTAG TDO, AS/PS CONF_DONE */ + +sbit at 0xB0 TDO; /* Port D.0 */ +#define bmTDOOE bmBIT0 +#define GetTDO(x) TDO + +//----------------------------------------------------------------------------- + +#define bmPROGOUTOE (bmTCKOE|bmTDIOE|bmTMSOE) +#define bmPROGINOE (bmTDOOE) + +//----------------------------------------------------------------------------- + +void ProgIO_Poll(void) {} +void ProgIO_Enable(void) {} +// These aren't called anywhere in usbjtag.c so far, might come... +void ProgIO_Disable(void) {} +void ProgIO_Deinit(void) {} + + +void ProgIO_Init(void) +{ + /* The following code depends on your actual circuit design. + Make required changes _before_ you try the code! */ + + // Note: JTAG signal output enables are in ProgIO_Set_State() below. + + mdelay(500); // wait for supply to come up + +} + +void ProgIO_Set_State(unsigned char d) +{ + /* Set state of output pins: + * + * d.0 => TCK + * d.1 => TMS + * d.4 => TDI + */ + + // JTAG signal output enables done at first request: + // this allows to use the JTAG connector with another JTAG cable + // alternatively. + OED=(OED&~bmPROGINOE) | bmPROGOUTOE; // Output enable + + SetTCK((d & bmBIT0) ? 1 : 0); + SetTMS((d & bmBIT1) ? 1 : 0); + SetTDI((d & bmBIT4) ? 1 : 0); +} + +//----------------------------------------------------------------------------- +// dummied AS/PS code +#define GetASDO(x) 1 + +unsigned char ProgIO_Set_Get_State(unsigned char d) +{ + /* Set state of output pins (s.a.) + * then read state of input pins: + * + * TDO => d.0 + * DATAOUT => d.1 (only #ifdef HAVE_AS_MODE) + */ + + ProgIO_Set_State(d); + return (GetASDO()<<1)|GetTDO(); +} + +//----------------------------------------------------------------------------- + +void ProgIO_ShiftOut(unsigned char c) +{ + /* Shift out byte C: + * + * 8x { + * Output least significant bit on TDI + * Raise TCK + * Shift c right + * Lower TCK + * } + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + ;; Bit0 + RRC A + MOV _TDI,C + SETB _TCK + ;; Bit1 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit2 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit3 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit4 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit5 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit6 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + ;; Bit7 + RRC A + CLR _TCK + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + ret + _endasm; +} + +/* +;; For ShiftInOut, the timing is a little more +;; critical because we have to read _TDO/shift/set _TDI +;; when _TCK is low. But 20% duty cycle at 48/4/5 MHz +;; is just like 50% at 6 Mhz, and that's still acceptable +*/ + +unsigned char ProgIO_ShiftInOut(unsigned char c) +{ + /* Shift out byte C, shift in from TDO: + * + * 8x { + * Read carry from TDO + * Output least significant bit on TDI + * Raise TCK + * Shift c right, append carry (TDO) at left + * Lower TCK + * } + * Return c. + */ + + (void)c; /* argument passed in DPL */ + + _asm + MOV A,DPL + + ;; Bit0 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit1 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit2 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit3 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit4 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit5 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit6 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + CLR _TCK + ;; Bit7 + MOV C,_TDO + RRC A + MOV _TDI,C + SETB _TCK + NOP + CLR _TCK + + MOV DPL,A + ret + _endasm; + + /* return value in DPL */ + + return c; +} + + Index: src/vectors.a51 =================================================================== --- src/vectors.a51 (nonexistent) +++ src/vectors.a51 (revision 33) @@ -0,0 +1,177 @@ +;;; -*- asm -*- +;;; $Id: vectors.a51 395 2011-07-17 22:02:55Z mueller $ +;;; +;;;----------------------------------------------------------------------------- +;;; Interrupt vectors +;;;----------------------------------------------------------------------------- +;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2, +;;; Copyright 2003 Free Software Foundation, Inc. +;;;----------------------------------------------------------------------------- +;;; This code is part of usbjtag. usbjtag is free software; you can redistribute +;;; it and/or modify it under the terms of the GNU General Public License as +;;; published by the Free Software Foundation; either version 2 of the License, +;;; or (at your option) any later version. usbjtag is distributed in the hope +;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;;; GNU General Public License for more details. You should have received a +;;; copy of the GNU General Public License along with this program in the file +;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin +;;; St, Fifth Floor, Boston, MA 02110-1301 USA +;;;----------------------------------------------------------------------------- + +;;; N.B. This object module must come first in the list of modules + + .module vectors + +;;; ---------------------------------------------------------------- +;;; standard FX2 interrupt vectors +;;; ---------------------------------------------------------------- + + .area CSEG (CODE) + .area GSINIT (CODE) + .area CSEG (CODE) +__standard_interrupt_vector:: +__reset_vector:: + ljmp s_GSINIT + + ;; 13 8-byte entries. We point them all at __isr_nop + ljmp __isr_nop ; 3 bytes + .ds 5 ; + 5 = 8 bytes for vector slot + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + ljmp __isr_nop + .ds 5 + +__isr_nop:: + reti + +;;; ---------------------------------------------------------------- +;;; the FIFO/GPIF autovector. 14 4-byte entries. +;;; must start on a 128 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0080 + +__fifo_gpif_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + + +;;; ---------------------------------------------------------------- +;;; the USB autovector. 32 4-byte entries. +;;; must start on a 256 byte boundary. +;;; ---------------------------------------------------------------- + + . = __reset_vector + 0x0100 + +__usb_autovector:: + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop + ljmp __isr_nop + nop Index: src/eeprom.h =================================================================== --- src/eeprom.h (nonexistent) +++ src/eeprom.h (revision 33) @@ -0,0 +1,27 @@ +/* $Id: eeprom.h 395 2011-07-17 22:02:55Z mueller $ */ +/*----------------------------------------------------------------------------- + * FTDI EEPROM emulation + *----------------------------------------------------------------------------- + * Copyright (C) 2007 Kolja Waschk, ixo.de + *----------------------------------------------------------------------------- + * This code is part of usbjtag. usbjtag is free software; you can redistribute + * it and/or modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. usbjtag is distributed in the hope + * that it will be useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. You should have received a + * copy of the GNU General Public License along with this program in the file + * COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin + * St, Fifth Floor, Boston, MA 02110-1301 USA + *----------------------------------------------------------------------------- + */ + +#ifndef _EEPROM_H +#define _EEPROM_H 1 + +extern xdata unsigned char eeprom[128]; +extern void eeprom_init(void); + +#endif /* _EEPROM_H */ + Index: src =================================================================== --- src (nonexistent) +++ src (revision 33)
src Property changes : Added: svn:ignore ## -0,0 +1,44 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log +*.asm +*.ihx +*.lnk +*.lst +*.map +*.mem +*.rel +*.rst +*.sym +*.lk +dscr_*.a51 Index: bin/nexys2_jtag.ihx =================================================================== --- bin/nexys2_jtag.ihx (nonexistent) +++ bin/nexys2_jtag.ihx (revision 33) @@ -0,0 +1,141 @@ +:06000000020E2302006B5A +:03000B0002006B85 +:0300130002006B7D +:03001B0002006B75 +:0300230002006B6D +:03002B0002006B65 +:0300330002006B5D +:03003B0002006B55 +:0300430002006B4D +:03004B0002006B45 +:0300530002006B3D +:03005B0002006B35 +:0300630002006B2D +:01006B003262 +:2000800002006B0002006B0002006B0002006B0002006B0002006B0002006B0002006B00F8 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bin/nexys2_jtag_3fifo_ic.ihx =================================================================== --- bin/nexys2_jtag_3fifo_ic.ihx (nonexistent) +++ bin/nexys2_jtag_3fifo_ic.ihx (revision 33) @@ -0,0 +1,146 @@ +:06000000020E9802006BE5 +:03000B0002006B85 +:0300130002006B7D +:03001B0002006B75 +:0300230002006B6D +:03002B0002006B65 +:0300330002006B5D +:03003B0002006B55 +:0300430002006B4D +:03004B0002006B45 +:0300530002006B3D +:03005B0002006B35 +:0300630002006B2D +:01006B003262 +:2000800002006B0002006B0002006B0002006B0002006B0002006B0002006B0002006B00F8 +:1800A00002006B0002006B0002006B0002006B0002006B0002006B00BA +:2001000002006B0002006B0002006B0002006B0002006B0002006B0002006B0002006B0077 +:2001200002006B0002006B0002006B0002006B0002006B0002006B0002006B0002006B0057 +:2001400002006B0002006B0002006B0002006B0002006B0002006B0002006B0002006B0037 +:2001600002006B0002006B0002006B0002006B0002006B0002006B0002006B0002006B0017 +:030E9E00020EA49D +:030EB700020EA187 +:030EA1000203F455 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+:200DBB00758253120C9B00000090E650E4F000000090E652E4F000000090E654E4F0000041 +:200DDB000090E656E4F000000090E65174FFF000000090E65374FFF000000090E65574FFC4 +:200DFB00F000000090E65774FFF000000090E658E4F090E65974FFF090E65AE4F090E65B6F +:200E1B0074FFF090E65CE4F090E65D74FFF090E65EE4F090E65F74FFF000000090E660E4DE +:200E3B00F000000090E66174FFF090E662E4F090E66374FFF090E665E4F090E668740BF089 +:130E5B00AF9174EF5FF591AF9174BF5FF591D2E8D2EA220C +:200E6E0022AF82120E6EDFFB2290FB50A3E582458370F922AE82AF83120E771EBEFF011F5B +:050E8E00EE4F70F4229C +:0D0E9F007581211205D6E5826003020E9CCC +:00000001FF Index: bin =================================================================== --- bin (nonexistent) +++ bin (revision 33)
bin Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: sys/README.txt =================================================================== --- sys/README.txt (nonexistent) +++ sys/README.txt (revision 33) @@ -0,0 +1,30 @@ +# $Id: README.txt 604 2014-11-16 22:33:09Z mueller $ + +This directory contains udev rules which ensure that the Cypress FX2 on + - Digilent Nexys2 + - Digilent Nexys3 + - Digilent Atlys + +is read/write accessible for user land processes, either in + - original power on state (thus Digilent VID/PID) + - after custom firmware is loaded (thus VOTI VID/PID) + +!! The rules assume that eligible user accounts are in group plugdev. +!! Check with the 'groups' command whether your account is in group plugdev, +!! in not, add this group to your accounts groups list. + +To setup udev rules do + + sudo cp -a 99-retro-usb-permissions.rules /etc/udev/rules.d/ + sudo chown root:root /etc/udev/rules.d/99-retro-usb-permissions.rules + dir /etc/udev/rules.d/ + + sudo udevadm control --reload-rules + +to verify whether usb device was really put into group 'plugdev' + + lsusb + --> look for bus/dev of interest + + find /dev/bus/usb -type c | sort| xargs ls -l + --> check whether bus/dev of interest is in group plugdev Index: sys/99-retro-usb-permissions.rules =================================================================== --- sys/99-retro-usb-permissions.rules (nonexistent) +++ sys/99-retro-usb-permissions.rules (revision 33) @@ -0,0 +1,26 @@ +# $Id: 99-retro-usb-permissions.rules 467 2013-01-02 19:49:05Z mueller $ +# +# udev rules to make some USB adaptors writable to group plugdev +# +# copy into /etc/udev/rules.d +# +ACTION!="add", GOTO="special_usb_rules_end" +SUBSYSTEM!="usb", GOTO="special_usb_rules_end" +# +# Cypress FX2 based systems ------------------------------------------ +# - Digilent Nexys2 +ATTR{idVendor}=="1443", ATTR{idProduct}=="0005", MODE="660", GROUP="plugdev" +# - Digilent Nexys3 and Atlys +ATTR{idVendor}=="1443", ATTR{idProduct}=="0007", MODE="660", GROUP="plugdev" +# +# - Cypress - EZ-USB FX2 USB 2.0 default +ATTR{idVendor}=="04b4", ATTR{idProduct}=="8613", MODE="660", GROUP="plugdev" +# +# - ixo.de - USB-JTAG-IF (used by ixo_jtag firmware) +ATTR{idVendor}=="16c0", ATTR{idProduct}=="06ad", MODE="660", GROUP="plugdev" +# - VOTI - free for internal lab use 1007 (used by retro11 firmware; primary) +ATTR{idVendor}=="16c0", ATTR{idProduct}=="03ef", MODE="660", GROUP="plugdev" +# - VOTI - free for internal lab use 1008 (used by retro11 firmware; alternate) +ATTR{idVendor}=="16c0", ATTR{idProduct}=="03f0", MODE="660", GROUP="plugdev" +# +LABEL="special_usb_rules_end" Index: sys =================================================================== --- sys (nonexistent) +++ sys (revision 33)
sys Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log Index: . =================================================================== --- . (nonexistent) +++ . (revision 33)
. Property changes : Added: svn:ignore ## -0,0 +1,33 ## +*.dep_ghdl +*.dep_isim +*.dep_xst +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +isim +isim.log +isim.wdb +fuse.log +*_[sft]sim.vhd +*_tsim.sdf +*_xst.log +*_tra.log +*_twr.log +*_map.log +*_par.log +*_tsi.log +*_pad.log +*_bgn.log +*_svn.log +*_sum.log +*_[dsft]sim.log

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