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/rhrp/test_rhrp_func_reg.tcl
0,0 → 1,160
# $Id: test_rhrp_func_reg.tcl 692 2015-06-21 11:53:24Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-06-20 692 1.0.1 de-configure all drives at begin |
# 2015-03-29 660 1.0 Initial version |
# |
# Test functions - register level |
# A: |
|
# ---------------------------------------------------------------------------- |
rlc log "test_rhrp_func_reg: test functions - register level -----------------" |
rlc log " setup: unit 0:RP06(mol), 1:RM05(mol,wrl), 2: RP07(mol=0), 3: off" |
package require ibd_rhrp |
ibd_rhrp::setup |
|
rlc set statmask $rw11::STAT_DEFMASK |
rlc set statvalue 0 |
|
# de-configure all drives (and clear errros and reset vv) |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] |
|
# configure drives |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol wrl] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RM05 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP07 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] |
|
# setup system: select unit 0; clr errors (cs1.tre and func=dclr); clear ATs |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \ |
-rma rpa.ds -edata [regbld ibd_rhrp::DS dpr mol dry] |
|
# -- Section A -- function basics -------------------------------------------- |
rlc log " A -- function basics ----------------------------------------------" |
rlc log " A1: test cs1 func basics ----------------------------------" |
rlc log " A1.1a: func noop; check no as ----------------------" |
|
set dsmsk [regbld ibd_rhrp::DS ata dpr] |
|
$cpu cp -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_NOOP] \ |
-rma rpa.as -edata 0x0 \ |
-rma rpa.ds -edata [regbld ibd_rhrp::DS dpr] $dsmsk |
|
rlc log " A2.1a: test invalid function (037) -----------------" |
|
$cpu cp -wma rpa.cs1 [ibd_rhrp::cs1_func 037] |
|
rlc log " A2.1b: check as,er1.ilf,ds.ata; clear as; recheck --" |
|
$cpu cp -rma rpa.as -edata [regbld ibd_rhrp::AS u0] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 ilf] \ |
-rma rpa.ds -edata [regbld ibd_rhrp::DS ata dpr] $dsmsk \ |
-wma rpa.as [regbld ibd_rhrp::AS u0] \ |
-rma rpa.as -edata 0x0 \ |
-rma rpa.ds -edata [regbld ibd_rhrp::DS dpr] $dsmsk |
|
rlc log " A2.2a: func dclr; check no as and er1 clear --------" |
|
$cpu cp -wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-rma rpa.as -edata 0x0 \ |
-rma rpa.er1 -edata 0x0 |
|
# -- Section B -- state functions -------------------------------------------- |
rlc log " B -- state functions ----------------------------------------------" |
|
# -- Section C -- seek functions --------------------------------------------- |
rlc log " C -- seek functions -----------------------------------------------" |
|
# -- Section D -- transfer functions ----------------------------------------- |
rlc log " D -- transfer functions -------------------------------------------" |
rlc log " D1: test func read sequence -------------------------------" |
rlc log " D1.1: issue func with ie=0 ---------------------------" |
|
# discard pending attn to be on save side |
rlc wtlam 0. |
rlc exec -attn |
|
set attnmsk [expr {1<<$ibd_rhrp::ANUM}] |
|
set ba 0x1000 |
set wc [expr {0xffff & (-256)}] |
set da [regbld ibd_rhrp::DA {ta 2} {sa 1}] |
set dc 0x0003 |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-wma rpa.ba $ba \ |
-wma rpa.bae 0x0 \ |
-wma rpa.wc $wc \ |
-wma rpa.da $da \ |
-wma rpa.dc $dc \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_READ] |
|
rlc log " D1.2: loc status check: cs1.rdy=0, ds.dry=0 ----------" |
|
$cpu cp -rma rpa.cs1 -edata 0 [regbld ibd_rhrp::CS1 rdy] \ |
-rma rpa.ds -edata 0 [regbld ibd_rhrp::DS dry] |
|
rlc log " D1.3: rem status check: attn + state -----------------" |
|
rlc exec -attn -edata $attnmsk |
|
# check rdy=0 ie=0 func=read |
set cs1val [regbld ibd_rhrp::CS1 [list func $ibd_rhrp::FUNC_READ]] |
set cs1msk [regbld ibd_rhrp::CS1 rdy ie {func -1}] |
# expect ds mol=1 dpr=1 dry=0 |
set dsval [regbld ibd_rhrp::DS mol dpr] |
|
$cpu cp -wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_CUNIT] \ |
-ribr rpa.cs1 -edata $cs1val $cs1msk \ |
-ribr rpa.ba -edata $ba \ |
-ribr rpa.bae -edata 0x0 \ |
-ribr rpa.wc -edata $wc \ |
-ribr rpa.da -edata $da \ |
-ribr rpa.dc -edata $dc \ |
-ribr rpa.ds -edata $dsval |
|
rlc log " D1.4: rem send response ------------------------------" |
|
set ba [expr {0xffff & (-$wc)}] |
set da [regbld ibd_rhrp::DA {ta 2} {sa 2}] |
|
$cpu cp -wibr rpa.ba $ba \ |
-wibr rpa.wc 0x0 \ |
-wibr rpa.da $da \ |
-wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_DONE] |
|
rlc log " D1.5: loc check: cs1.rdy=1, ds.dry=1 -----------------" |
|
# expect cs1 sc=0 tre=0 dva=1 rdy=1 ie=0 func=read go=0 |
set cs1val [regbld ibd_rhrp::CS1 dva rdy [list func $ibd_rhrp::FUNC_READ]] |
# expect ds ata=0 mol=1 dpr=1 dry=1 |
set dsval [regbld ibd_rhrp::DS mol dpr dry] |
|
$cpu cp -rma rpa.cs1 -edata $cs1val \ |
-rma rpa.ba -edata $ba \ |
-rma rpa.wc -edata 0x0 \ |
-rma rpa.da -edata $da \ |
-rma rpa.ds -edata $dsval |
/rhrp/test_rhrp_int.tcl
0,0 → 1,501
# $Id: test_rhrp_int.tcl 692 2015-06-21 11:53:24Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-06-20 692 1.1.1 de-configure all drives at begin |
# 2015-05-04 674 1.1 w11a start/stop/suspend overhaul |
# 2015-03-29 667 1.0 Initial version |
# |
# Test interrupt response |
# A: |
|
# ---------------------------------------------------------------------------- |
rlc log "test_rhrp_int: test interrupt response ------------------------------" |
rlc log " setup: unit 0:RP06(mol), 1:RM05(mol,wrl), 2: RP07(mol=0), 3: off" |
package require ibd_rhrp |
ibd_rhrp::setup |
|
rlc set statmask $rw11::STAT_DEFMASK |
rlc set statvalue 0 |
|
# de-configure all drives (and clear errros and reset vv) |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] |
|
# configure drives |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1} mol wrl] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RM05 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP07 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] |
|
# clear errors: cs1.tre=1 via unit 0 |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \ |
-rma rpa.ds -edata [regbld ibd_rhrp::DS dpr mol dry] |
|
# load test code |
$cpu ldasm -lst lst -sym sym { |
.include |lib/defs_cpu.mac| |
.include |lib/defs_rp.mac| |
; |
.include |lib/vec_cpucatch.mac| |
; |
. = 000254 ; setup RHRP interrupt vector |
v..rp: .word vh.rp |
.word cp.pr7 |
; |
. = 1000 ; data area |
stack: |
ibuf: .blkw 4. ; input buffer |
rint: .word 0 ; reinterrupt |
; |
icnt: .word 0 ; interrupt count |
pcnt: .word 0 ; poll count |
obuf: .blkw 6. ; output buffer |
fbuf: .blkw 5. ; final buffer |
; |
. = 2000 ; code area |
start: spl 7 ; lock out interrupts |
clr icnt ; clear counters |
clr pcnt |
; |
mov #obuf,r0 ; clear obuf |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
clr r5 ; r5 used to time int delay |
; |
mov #ibuf,r0 ; setup regs from ibuf |
mov (r0)+,@#rp.cs2 ; cs2 |
mov (r0)+,@#rp.da ; da |
mov (r0)+,@#rp.dc ; dc |
mov (r0)+,@#rp.cs1 ; cs1 |
spl 0 ; allow interrupts |
; |
inc r5 ; time int delay, up to 10 instructions |
inc r5 |
inc r5 |
inc r5 |
inc r5 |
inc r5 |
inc r5 |
inc r5 |
inc r5 |
inc r5 |
; |
poll: inc pcnt ; count polls |
tstb @#rp.cs1 ; check cs1 rdy |
bpl poll ; if rdy=0 keep polling |
tst icnt ; did we have an interrupt ? |
bne 1$ ; |
; |
mov #obuf,r0 ; store regs in obuf |
mov @#rp.cs1,(r0)+ ; cs1 |
mov @#rp.cs2,(r0)+ ; cs2 |
mov @#rp.er1,(r0)+ ; er1 |
mov @#rp.ds,(r0)+ ; ds |
mov @#rp.as,(r0)+ ; as |
; |
1$: tst rint ; re-interrupt wanted ? |
bne 2$ ; |
mov #377,@#rp.as ; if not, cancel all attentions |
clr rint |
; |
2$: bit #rp.erp,@#rp.ds ; ds.erp = 1 ? any controller errors ? |
beq 3$ |
mov #<rp.fcl+rp.go>,@#rp.cs1 ; than do drive clear |
; |
3$: bit #rp.tre,@#rp.cs1 ; cs1.tre = 1 ? any transfer errors ? |
beq 4$ |
mov #rp.tre,@#rp.cs1 ; if yes, clear them with tre=1 write |
; |
4$: mov #fbuf,r0 ; store final regs in fbuf |
mov @#rp.cs1,(r0)+ ; cs1 |
mov @#rp.cs2,(r0)+ ; cs2 |
mov @#rp.er1,(r0)+ ; er1 |
mov @#rp.ds,(r0)+ ; ds |
mov @#rp.as,(r0)+ ; as |
|
halt ; halt if done |
stop: |
; |
clr pcnt ; clear pcnt again |
mov #obuf,r0 ; clear obuf again |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
clr (r0)+ |
; |
mov #rp.ie,@#rp.cs1 ; re-enable interrupt |
br poll |
|
; RHRP interrupt handler |
vh.rp: mov #obuf,r0 ; store regs in obuf |
mov @#rp.cs1,(r0)+ ; cs1 |
mov @#rp.cs2,(r0)+ ; cs2 |
mov @#rp.er1,(r0)+ ; er1 |
mov @#rp.ds,(r0)+ ; ds |
mov @#rp.as,r1 ; |
mov r1,(r0)+ ; as |
mov r5,(r0)+ ; int delay |
; |
1$: tst icnt ; test first interrupt |
beq 2$ ; if yes quit |
mov r1,@#rp.as ; if not, clear as |
2$: inc icnt ; count interrupts |
rti ; and return |
} |
|
##puts $lst |
|
# define tmpproc for readback checks |
proc tmpproc_dotest {cpu symName opts} { |
upvar 1 $symName sym |
|
set tout 10.; # FIXME_code: parameter ?? |
|
# setup defs hash, first defaults, than write over concrete run values |
array set defs { i.cs2 0 \ |
i.da 0 \ |
i.dc 0 \ |
i.cs1 0 \ |
i.idly 0 \ |
o.cs1 0 \ |
o.cs2 0 \ |
o.er1 0 \ |
o.ds 0 \ |
o.as 0 \ |
o.itim 10 \ |
o.icnt 0 \ |
o.pcnt 1 \ |
or.cs1 0 \ |
or.cs2 0 \ |
or.er1 0 \ |
or.ds 0 \ |
or.as 0 \ |
or.icnt 0 \ |
or.pcnt 1 \ |
do.rint 0 \ |
do.lam 0 |
} |
array set defs $opts |
|
# build ibuf |
set ibuf [list $defs(i.cs2) $defs(i.da) $defs(i.dc) $defs(i.cs1) \ |
$defs(do.rint)] |
|
# setup idly, write ibuf, setup stack, and start cpu at start: |
$cpu cp -wibr rpa.cs1 [regbld ibd_rhrp::RCS1 \ |
[list val $defs(i.idly)] \ |
[list func $ibd_rhrp::RFUNC_WIDLY] ] \ |
-wal $sym(ibuf) \ |
-bwm $ibuf \ |
-wsp $sym(stack) \ |
-stapc $sym(start) |
|
# here do minimal lam handling (harvest + send DONE) |
if {$defs(do.lam)} { |
rlc wtlam $tout apat |
$cpu cp -attn \ |
-wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_DONE] |
} |
|
$cpu wtcpu -reset $tout |
|
# determine regs after cleanup |
set cs1msk [rutil::com16 [regbld ibd_rhrp::CS1 {func -1}]] |
set fcs2 [expr {$defs(o.cs2) & 0x00ff}]; # cs1.tre clears upper byte ! |
set fer1 0 |
if {!$defs(do.rint)} { # no reinterrupt, ata clear by cpu |
set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 sc tre {func -1}] }] |
set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS ata erp] }] |
set fas 0 |
} else { # reinterrupt, ata still pending |
set fcs1 [expr {$defs(o.cs1) & ~[regbld ibd_rhrp::CS1 tre {func -1}] }] |
set fds [expr {$defs(o.ds) & ~[regbld ibd_rhrp::DS erp] }] |
set fas $defs(o.as) |
} |
$cpu cp -rpc -edata $sym(stop) \ |
-rsp -edata $sym(stack) \ |
-wal $sym(icnt) \ |
-rmi -edata $defs(o.icnt) \ |
-rmi \ |
-rmi -edata $defs(o.cs1) \ |
-rmi -edata $defs(o.cs2) \ |
-rmi -edata $defs(o.er1) \ |
-rmi -edata $defs(o.ds) \ |
-rmi -edata $defs(o.as) \ |
-rmi -edata $defs(o.itim) \ |
-rmi -edata $fcs1 $cs1msk \ |
-rmi -edata $fcs2 \ |
-rmi -edata $fer1 \ |
-rmi -edata $fds \ |
-rmi -edata $fas |
|
if {!$defs(do.rint)} return ""; |
|
$cpu cp -start |
|
$cpu wtcpu -reset $tout |
|
# determine regs after cleanup |
set fcs1 [expr {$defs(or.cs1) & ~[regbld ibd_rhrp::CS1 sc] }] |
set fcs2 $defs(or.cs2) |
set fer1 0 |
set fds [expr {$defs(or.ds) & ~[regbld ibd_rhrp::DS ata] }] |
set fas 0 |
|
$cpu cp -rpc -edata $sym(stop) \ |
-rsp -edata $sym(stack) \ |
-wal $sym(icnt) \ |
-rmi -edata $defs(or.icnt) \ |
-rmi \ |
-rmi -edata $defs(or.cs1) \ |
-rmi -edata $defs(or.cs2) \ |
-rmi -edata $defs(or.er1) \ |
-rmi -edata $defs(or.ds) \ |
-rmi -edata $defs(or.as) \ |
-rmi \ |
-rmi -edata $fcs1 \ |
-rmi -edata $fcs2 \ |
-rmi -edata $fer1 \ |
-rmi -edata $fds \ |
-rmi -edata $fas |
|
return "" |
} |
|
# discard pending attn to be on save side |
rlc wtlam 0. |
rlc exec -attn |
|
# -- Section A --------------------------------------------------------------- |
rlc log " A -- function basics ----------------------------------------------" |
rlc log " A1: test rdy and ie logic ---------------------------------" |
rlc log " A1.1 set cs1.ie=1 alone -> no interrupt ------------" |
|
# Note: no interrupt, so ie stays on ! |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie] \ |
o.icnt 0 \ |
o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS mol dpr dry] \ |
o.as 0 \ |
o.itim 0 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A1.2 set cs1.ie=1 with rdy=1 -> software interrupt -" |
|
# Note: interrupt, so ie switched off again ! |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 rdy ie] \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 dva rdy] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS mol dpr dry] \ |
o.as 0 \ |
o.itim 1 |
] |
|
tmpproc_dotest $cpu sym $opts |
|
rlc log " A2: test state functions: iff no, as yes ------------------" |
rlc log " A2.1 noop function ---------------------------------" |
|
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie go] \ |
o.cs1 [regbld ibd_rhrp::CS1 ie dva rdy] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS mol dpr dry] \ |
o.as 0 \ |
o.itim 0 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A2.2 pack acknowledge function (sets ds.vv=1) ------" |
|
set rbcs1func [list func $ibd_rhrp::FUNC_PACK] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func ie go] \ |
o.cs1 [regbld ibd_rhrp::CS1 dva rdy ie $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \ |
o.as 0 \ |
o.itim 0 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A3: test seek type functions: iff no, as yes --------------" |
|
rlc log " A3.1 seek function, ie=0, valid da,dc---------------" |
|
# check that cs1.sc=1, ds.ata=1, and as.u0=1 |
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 $rbcs1func go] \ |
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ |
o.as [regbld ibd_rhrp::AS u0] \ |
o.itim 0 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A3.2 seek function, valid da,dc, idly=0 ------------" |
|
# check re-interrupt too |
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ |
i.dc 814 \ |
i.idly 0 \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ |
o.as [regbld ibd_rhrp::AS u0] \ |
o.itim 1 \ |
do.rint 1 \ |
or.icnt 2 \ |
or.cs1 [regbld ibd_rhrp::CS1 sc dva rdy] \ |
or.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
or.er1 0 \ |
or.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ |
or.as [regbld ibd_rhrp::AS u0] |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A3.3 seek function, invalid dc ---------------------" |
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEEK] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ |
i.dc 815 \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 [regbld ibd_rhrp::ER1 iae] \ |
o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \ |
o.as [regbld ibd_rhrp::AS u0] \ |
o.itim 1 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A3.4 search function, valid da,dc, idly=0 ----------" |
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ |
i.dc 0 \ |
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \ |
i.idly 0 \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ |
o.as [regbld ibd_rhrp::AS u0] \ |
o.itim 1 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A3.5 search function, valid da,dc, idly=2 ----------" |
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ |
i.dc 0 \ |
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \ |
i.idly 2 \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ |
o.as [regbld ibd_rhrp::AS u0] \ |
o.itim 3 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A3.5 search function, valid da,dc, idly=8 ----------" |
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ |
i.dc 0 \ |
i.da [regbld ibd_rhrp::DA {ta 0} {sa 21}] \ |
i.idly 8 \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 0 \ |
o.ds [regbld ibd_rhrp::DS ata mol dpr dry vv] \ |
o.as [regbld ibd_rhrp::AS u0] \ |
o.itim 9 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A3.5 search function, invalid sa, idly=8 -----------" |
# Note: idly is 8, but error ata's come immediately !! |
|
set rbcs1func [list func $ibd_rhrp::FUNC_SEAR] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ |
i.dc 0 \ |
i.da [regbld ibd_rhrp::DA {ta 0} {sa 22}] \ |
i.idly 8 \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 sc dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.er1 [regbld ibd_rhrp::ER1 iae] \ |
o.ds [regbld ibd_rhrp::DS ata erp mol dpr dry vv] \ |
o.as [regbld ibd_rhrp::AS u0] \ |
o.itim 1 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A4: test transfer functions: iff yes, as no ---------------" |
rlc log " A4.1 read function, valid da,dc --------------------" |
|
set rbcs1func [list func $ibd_rhrp::FUNC_READ] |
set opts [list \ |
i.cs1 [regbld ibd_rhrp::CS1 ie $rbcs1func go] \ |
o.icnt 1 \ |
o.cs1 [regbld ibd_rhrp::CS1 dva rdy $rbcs1func] \ |
o.cs2 [regbld ibd_rhrp::CS2 or ir] \ |
o.ds [regbld ibd_rhrp::DS mol dpr dry vv] \ |
do.lam 1 |
] |
tmpproc_dotest $cpu sym $opts |
|
/rhrp/test_rhrp_int2.tcl
0,0 → 1,337
# $Id: test_rhrp_int2.tcl 692 2015-06-21 11:53:24Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-05-20 692 1.0 Initial version |
# |
# Test interrupt response |
# A: |
|
# ---------------------------------------------------------------------------- |
rlc log "test_rhrp_int2: test interrupt response for nested xfer+seek --------" |
rlc log " setup: unit 0-3: RP06(mol)" |
package require ibd_rhrp |
ibd_rhrp::setup |
|
rlc set statmask $rw11::STAT_DEFMASK |
rlc set statvalue 0 |
|
# de-configure all drives (and clear errros and reset vv) |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] |
|
# configure drives |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS dpr mol] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS dpr mol] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS dpr mol] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS dpr mol] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 |
|
# clear errors: cs1.tre=1 via unit 0 |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-wma rpa.as [regbld ibd_rhrp::AS u3 u2 u1 u0] \ |
-rma rpa.ds -edata [regbld ibd_rhrp::DS dpr mol dry] |
|
# do pack ack on all drives |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_PACK] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_PACK] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_PACK] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 3}] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_PACK] |
|
# load test code |
$cpu ldasm -lst lst -sym sym { |
.include |lib/defs_cpu.mac| |
.include |lib/defs_rp.mac| |
; |
.include |lib/vec_cpucatch.mac| |
; |
. = 000254 ; setup RHRP interrupt vector |
v..rp: .word vh.rp |
.word cp.pr7 |
; |
. = 1000 ; data area |
stack: |
ibuf: .blkw <3+1+<3*3>> ; input buffer (3 for xfer; #seek; 3 per seek) |
obuf: .blkw <<4*6>+<4*6>+1> ; output buffer |
; |
sdone: .word 0 ; seek done |
idone: .word 0 ; interrupt done |
apat: .word 0 ; attn pattern |
; |
. = 2000 ; code area |
start: spl 7 ; lock out interrupts |
clr sdone ; clear flags |
clr idone |
; |
mov #obuf,r5 ; clear obuf |
mov #8.,r2 ; clear 8 sections with 6 words |
1$: clr (r5)+ |
clr (r5)+ |
clr (r5)+ |
clr (r5)+ |
clr (r5)+ |
clr (r5)+ |
sob r2,1$ |
clr (r5)+ |
; |
mov #obuf,r5 ; setup obuf pointer |
mov #ibuf,r0 ; setup regs from ibuf |
clrb @#rp.cs2 ; cs2 (unit=0) |
mov (r0)+,@#rp.da ; da |
mov (r0)+,@#rp.dc ; dc |
mov (r0)+,@#rp.cs1 ; cs1 |
; |
mov #177000,(r5)+ ; tag: regs after xfer started |
mov @#rp.cs1,(r5)+ ; cs1 |
mov @#rp.cs2,(r5)+ ; cs2 |
mov @#rp.er1,(r5)+ ; er1 |
mov @#rp.ds,(r5)+ ; ds |
mov @#rp.as,(r5)+ ; as |
; |
mov #1,r2 ; next unit |
mov #2,r3 ; next abit |
mov (r0)+,r1 ; # of seeks |
beq 30$ |
; |
20$: movb r2,@#rp.cs2 ; cs2 (unit=i) |
mov (r0)+,@#rp.da ; da |
mov (r0)+,@#rp.dc ; dc |
mov (r0)+,@#rp.cs1 ; cs1 |
; |
mov r2,(r5) |
add #177100,(r5)+ ; tag: regs after seek started |
mov @#rp.cs1,(r5)+ ; cs1 |
mov @#rp.cs2,(r5)+ ; cs2 |
mov @#rp.er1,(r5)+ ; er1 |
mov @#rp.ds,(r5)+ ; ds |
mov @#rp.as,(r5)+ ; as |
; |
bis r3,apat ; build apat |
inc r2 ; next unit |
asl r3 ; next abit |
; |
sob r1,20$ |
; |
30$: inc sdone ; signal seeks queued |
spl 0 ; allow interrupts |
wpnt: wait |
|
1$: tst idone ; wait for interrupt |
beq 1$ |
mov #177777,(r5)+ ; tag: all done |
halt ; halt if done |
stop: |
; |
|
; RHRP interrupt handler |
vh.rp: clrb @#rp.cs2 ; cs2 (unit=0) |
mov #177200,(r5)+ ; tag: regs after seek started |
mov @#rp.cs1,(r5)+ ; cs1 |
mov @#rp.cs2,(r5)+ ; cs2 |
mov @#rp.er1,(r5)+ ; er1 |
mov @#rp.ds,(r5)+ ; ds |
mov @#rp.as,r4 ; |
mov r4,(r5)+ ; as |
; |
mov #3,r1 ; max # of seeks |
mov #1,r2 ; next unit |
mov #2,r3 ; next abit |
; |
1$: bit r3,r4 ; bit set in as ? |
beq 2$ |
; |
movb r2,@#rp.cs2 ; cs2 (unit=i) |
mov r2,(r5) |
add #177300,(r5)+ ; tag: regs after seek started |
mov @#rp.cs1,(r5)+ ; cs1 |
mov @#rp.cs2,(r5)+ ; cs2 |
mov @#rp.er1,(r5)+ ; er1 |
mov @#rp.ds,(r5)+ ; ds |
mov r3,@#rp.as ; clear abit in as |
mov @#rp.as,(r5)+ ; as |
; |
2$: inc r2 ; next unit |
asl r3 ; next abit |
sob r1,1$ |
; |
inc idone |
rti ; and return |
} |
|
##puts $lst |
|
# define tmpproc for readback checks |
proc tmpproc_dotest {cpu symName opts} { |
upvar 1 $symName sym |
|
set tout 10.; # FIXME_code: parameter ?? |
|
# setup defs hash, first defaults, than write over concrete run values |
array set defs { i.nseek 0 \ |
i.idly 0 |
} |
array set defs $opts |
|
set fread [list func $ibd_rhrp::FUNC_READ] |
set fsear [list func $ibd_rhrp::FUNC_SEAR] |
set as 0 |
|
# build ibuf |
set ibuf {} |
lappend ibuf 01 0100 [regbld ibd_rhrp::CS1 ie $fread go] |
lappend ibuf $defs(i.nseek) |
for {set i 1} {$i<=$defs(i.nseek)} {incr i} { |
set da [expr { 010 + $i}] |
set dc [expr {0100 + $i}] |
lappend ibuf $da $dc [regbld ibd_rhrp::CS1 ie $fsear go] |
set as [expr {$as | [expr {01 << $i} ] } ] |
} |
|
# setup idly, write ibuf, setup stack, and start cpu at start: |
$cpu cp -wibr rpa.cs1 [regbld ibd_rhrp::RCS1 \ |
[list val $defs(i.idly)] \ |
[list func $ibd_rhrp::RFUNC_WIDLY] ] \ |
-wal $sym(ibuf) \ |
-bwm $ibuf \ |
-wsp $sym(stack) \ |
-stapc $sym(start) |
|
# here do minimal lam handling (harvest + send DONE) |
# wait for interrupt |
# and for sdone (all search issued flag) set |
rlc wtlam $tout apat |
for {set i 0} {$i<100} {incr i} { |
$cpu cp -wal $sym(sdone) \ |
-rmi sdone |
if {$sdone} {break} |
} |
$cpu cp -attn \ |
-wibr rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::RFUNC_DONE] |
|
# wait for halt |
$cpu wtcpu -reset $tout |
|
# check context |
$cpu cp -rpc -edata $sym(stop) \ |
-rsp -edata $sym(stack) \ |
-wal $sym(idone) \ |
-rmi -edata 1 |
|
# check setup xfer |
set osxcs1 [regbld ibd_rhrp::CS1 dva ie $fread] |
set osxcs2 [regbld ibd_rhrp::CS2 or ir] |
set osxds [regbld ibd_rhrp::DS mol dpr vv] |
$cpu cp -wal $sym(obuf) \ |
-rmi -edata 0177000 \ |
-rmi -edata $osxcs1 \ |
-rmi -edata $osxcs2 \ |
-rmi -edata 0 \ |
-rmi -edata $osxds \ |
-rmi -edata 0 |
|
# check setup search |
set mskcs1sc [rutil::com16 [regbld ibd_rhrp::CS1 sc]] |
for {set i 1} {$i<=$defs(i.nseek)} {incr i} { |
set osscs1 [regbld ibd_rhrp::CS1 dva ie $fsear] |
set osscs2 [regbld ibd_rhrp::CS2 or ir [list unit $i]] |
set ossds [regbld ibd_rhrp::DS pip mol dpr vv] |
$cpu cp -rmi -edata [expr {0177100 + $i}] \ |
-rmi -edata $osscs1 $mskcs1sc\ |
-rmi -edata $osscs2 \ |
-rmi -edata 0 \ |
-rmi -edata $ossds \ |
-rmi |
} |
|
# check interrupt xfer |
set sc [expr {$defs(i.nseek) > 0}] |
set oixcs1 [regbld ibd_rhrp::CS1 [list sc $sc] dva rdy $fread] |
set oixcs2 [regbld ibd_rhrp::CS2 or ir] |
set oixds [regbld ibd_rhrp::DS mol dpr dry vv] |
set oixas $as |
$cpu cp -rmi -edata 0177200 \ |
-rmi -edata $oixcs1 \ |
-rmi -edata $oixcs2 \ |
-rmi -edata 0 \ |
-rmi -edata $oixds \ |
-rmi -edata $oixas |
|
# check interrupt search |
set oisas $as |
for {set i 1} {$i<=$defs(i.nseek)} {incr i} { |
set oiscs1 [regbld ibd_rhrp::CS1 [list sc $sc] dva rdy $fsear] |
set oiscs2 [regbld ibd_rhrp::CS2 or ir [list unit $i]] |
set oisds [regbld ibd_rhrp::DS ata mol dpr dry vv] |
set oisas [expr {$oisas & [expr {~(01<<$i)} ] }] |
$cpu cp -rmi -edata [expr {0177300 + $i}] \ |
-rmi -edata $oiscs1 \ |
-rmi -edata $oiscs2 \ |
-rmi -edata 0 \ |
-rmi -edata $oisds \ |
-rmi -edata $oisas |
} |
|
# ckeck end tag |
$cpu cp -rmi -edata 0177777 |
|
return "" |
} |
|
# discard pending attn to be on save side |
rlc wtlam 0. |
rlc exec -attn |
|
rlc log " A1: test without search -----------------------------------" |
|
set opts [list \ |
i.nseek 0 \ |
i.idly 0 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A2: test with 1 search ------------------------------------" |
|
set opts [list \ |
i.nseek 1 \ |
i.idly 10 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A2: test with 2 search ------------------------------------" |
|
set opts [list \ |
i.nseek 2 \ |
i.idly 10 |
] |
tmpproc_dotest $cpu sym $opts |
|
rlc log " A2: test with 3 search ------------------------------------" |
|
set opts [list \ |
i.nseek 3 \ |
i.idly 10 |
] |
tmpproc_dotest $cpu sym $opts |
|
/rhrp/rhrp_all.dat
0,0 → 1,9
# $Id: rhrp_all.dat 692 2015-06-21 11:53:24Z mueller $ |
# |
## steering file for all rhrp tests |
# |
test_rhrp_basics.tcl |
test_rhrp_regs.tcl |
test_rhrp_func_reg.tcl |
test_rhrp_int.tcl |
test_rhrp_int2.tcl |
/rhrp/test_rhrp_regs.tcl
0,0 → 1,437
# $Id: test_rhrp_regs.tcl 692 2015-06-21 11:53:24Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-06-20 692 1.0.1 de-configure all drives at begin |
# 2015-03-29 660 1.0 Initial version |
# |
# Test register response |
# A: test ba, bae, cs1.bae, wc and db (cntl regs) |
# B: test da, dc (and cc for RP typ) |
# C: test of,mr1,mr2(for RM typ); test NI regs: er2,er3,ec1,ec2 |
# D: test hr (for RM typ); ensure unit distinct |
# E: test cs2.clr |
# F: test er1 |
|
# ---------------------------------------------------------------------------- |
rlc log "test_rhrp_regs: test register response ------------------------------" |
rlc log " setup context; unit 0:RP06, 1:RM05, 2: RP07, 3: off" |
package require ibd_rhrp |
ibd_rhrp::setup |
|
rlc set statmask $rw11::STAT_DEFMASK |
rlc set statvalue 0 |
|
# de-configure all drives (and clear errros and reset vv) |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS erp vv] |
|
# configure drives |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RM05 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP07 \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 3] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] |
|
# clear errors: cs1.tre=1 via unit 0 |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] |
|
# -- Section A --------------------------------------------------------------- |
rlc log " A1: test ba,bae and cs1.bae -------------------------------" |
rlc log " A1.1: loc write ba, read loc and rem ---------------" |
|
$cpu cp -wma rpa.ba 0xffff \ |
-rma rpa.ba -edata 0xfffe \ |
-ribr rpa.ba -edata 0xfffe \ |
-wma rpa.ba 0x0 \ |
-rma rpa.ba -edata 0x0 \ |
-ribr rpa.ba -edata 0x0 |
|
rlc log " A1.2: rem write ba, read loc and rem ---------------" |
|
$cpu cp -wibr rpa.ba 0x12ef \ |
-ribr rpa.ba -edata 0x12ee \ |
-rma rpa.ba -edata 0x12ee \ |
-wibr rpa.ba 0x0 \ |
-ribr rpa.ba -edata 0x0 \ |
-rma rpa.ba -edata 0x0 |
|
rlc log " A1.3: loc write bae, read l+r bae+cs1.bae ----------" |
|
set cs1msk [regbld ibd_rhrp::CS1 {bae -1}] |
foreach bae {077 071 000} { |
set cs1val [regbld ibd_rhrp::CS1 [list bae [expr {$bae & 03}]]] |
$cpu cp -wma rpa.bae $bae \ |
-rma rpa.bae -edata $bae \ |
-rma rpa.cs1 -edata $cs1val $cs1msk \ |
-ribr rpa.bae -edata $bae \ |
-ribr rpa.cs1 -edata $cs1val $cs1msk |
} |
|
rlc log " A1.4: rem write bae, read l+r bae+cs1.bae ----------" |
|
foreach bae {077 071 000} { |
set cs1val [regbld ibd_rhrp::CS1 [list bae [expr {$bae & 03}]]] |
$cpu cp -wibr rpa.bae $bae \ |
-ribr rpa.bae -edata $bae \ |
-ribr rpa.cs1 -edata $cs1val $cs1msk \ |
-rma rpa.bae -edata $bae \ |
-rma rpa.cs1 -edata $cs1val $cs1msk |
} |
|
rlc log " A1.5: loc write cs1.bae, read l+r bae+cs1.bae ------" |
|
$cpu cp -wibr rpa.bae 070; # set 3 lbs of bae |
|
foreach cs1bae {03 01 00} { |
set cs1val [regbld ibd_rhrp::CS1 [list bae $cs1bae]] |
set bae [expr {070 | $cs1bae}] |
$cpu cp -wma rpa.cs1 $cs1val \ |
-rma rpa.bae -edata $bae \ |
-rma rpa.cs1 -edata $cs1val $cs1msk \ |
-ribr rpa.bae -edata $bae \ |
-ribr rpa.cs1 -edata $cs1val $cs1msk |
} |
|
# Note: cs1.bae can only be loc written ! |
# No need to do this via rem, use bae !! |
# therefore no 'rem write cs1.bae' test |
|
rlc log " A1.6: loc write cs1.func, read loc, ensure distinct " |
|
set funcu0 [regbld ibd_rhrp::CS1 {func 001}] |
set funcu1 [regbld ibd_rhrp::CS1 {func 025}] |
set funcu2 [regbld ibd_rhrp::CS1 {func 037}] |
set funcmsk [regbld ibd_rhrp::CS1 {func -1}] |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 $funcu0 \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-wma rpa.cs1 $funcu1 \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-wma rpa.cs1 $funcu2 |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-rma rpa.cs1 -edata $funcu0 $funcmsk \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma rpa.cs1 -edata $funcu1 $funcmsk \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-rma rpa.cs1 -edata $funcu2 $funcmsk |
|
# Note: rem read of cs1.func always gives func frozen a go for xfer function ! |
# therefore no rem read cs1.func test here |
|
rlc log " A2: test wc; ensure wc,ba distinct ------------------------" |
rlc log " A2.1: loc write wc,ba, read loc and rem ------------" |
|
foreach {wc ba} {0xdead 0x1234 0xbeaf 0x5678} { |
$cpu cp -wma rpa.wc $wc \ |
-wma rpa.ba $ba \ |
-rma rpa.wc -edata $wc \ |
-rma rpa.ba -edata $ba \ |
-ribr rpa.wc -edata $wc \ |
-ribr rpa.ba -edata $ba |
} |
|
rlc log " A2.2: rem write wc,ba, read loc and rem ------------" |
|
foreach {wc ba} {0x4321 0x3456 0x5432 0x1234} { |
$cpu cp -wibr rpa.wc $wc \ |
-wibr rpa.ba $ba \ |
-ribr rpa.wc -edata $wc \ |
-ribr rpa.ba -edata $ba \ |
-rma rpa.wc -edata $wc \ |
-rma rpa.ba -edata $ba |
} |
|
rlc log " A3: test db; check cs2.or,ir; ensure ba,dt distinct --" |
|
set cs2msk [regbld ibd_rhrp::CS2 or ir {unit -1}] |
set cs2val [regbld ibd_rhrp::CS2 or ir {unit 0}] |
|
# clear cs2 -> set unit 0; later check that or,ir set, and unit 0 |
# only loc tested; rem side irrelevant |
foreach {db ba} {0xdead 0x1234 0xbeaf 0x5678} { |
$cpu cp -wma rpa.cs2 0 \ |
-wma rpa.db $db \ |
-wma rpa.ba $ba \ |
-rma rpa.cs2 -edata $cs2val $cs2msk \ |
-rma rpa.db -edata $db \ |
-rma rpa.ba -edata $ba |
} |
|
# -- Section B --------------------------------------------------------------- |
rlc log " B1: test da,dc; ensure unit distinct; check cc ------------" |
|
# define tmpproc for readback checks |
proc tmpproc_checkdadc {cpu tbl} { |
foreach {unit ta sa dc} $tbl { |
set da [regbld ibd_rhrp::DA [list ta $ta] [list sa $sa]] |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ |
-rma rpa.da -edata $da \ |
-rma rpa.dc -edata $dc \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ |
-ribr rpa.da -edata $da \ |
-ribr rpa.dc -edata $dc |
} |
} |
|
rlc log " B1.1: loc setup ------------------------------------" |
|
# unit ta sa dc |
# 5b 6b 10b |
set tbl { 0 007 006 00123 \ |
1 013 031 00345 \ |
2 037 077 01777 |
} |
|
foreach {unit ta sa dc} $tbl { |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ |
-wma rpa.da [regbld ibd_rhrp::DA [list ta $ta] [list sa $sa]] \ |
-wma rpa.dc $dc |
} |
|
rlc log " B1.2: loc+rem readback -----------------------------" |
tmpproc_checkdadc $cpu $tbl |
|
rlc log " B1.3: check cc for unit 0 (RP06) -------------------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-rma rpa.m13 -edata 00123 |
|
rlc log " B1.4: rem setup ------------------------------------" |
|
# unit ta sa dc |
# 5b 6b 10b |
set tbl { 0 005 004 00234 \ |
1 020 077 00456 \ |
2 032 023 01070 |
} |
|
foreach {unit ta sa dc} $tbl { |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ |
-wibr rpa.da [regbld ibd_rhrp::DA [list ta $ta] [list sa $sa]] \ |
-wibr rpa.dc $dc |
} |
|
rlc log " B1.5: loc+rem readback -----------------------------" |
tmpproc_checkdadc $cpu $tbl |
|
rlc log " B1.6: check cc for unit 0 (RP06) -------------------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-rma rpa.m13 -edata 00234 |
|
# -- Section C --------------------------------------------------------------- |
rlc log " C1: test of,mr1,mr2(for RM typ); test NI regs: er2,er3,ec1,ec2" |
|
# test fmt,eci,hci flags (NI, but stored), also off for RP |
set of_0 [regbld ibd_rhrp::OF fmt {odi 1} {off -1}] |
set of_1 [regbld ibd_rhrp::OF eci {odi 0}] |
set of_2 [regbld ibd_rhrp::OF hci {odi 0}] |
|
set mr1_0 0x7700 |
set mr1_1 0x7701 |
set mr1_2 0x7702 |
|
set mr2_1 0x6601 |
set mr2_2 0x6602 |
|
set da_0 [regbld ibd_rhrp::DA {ta 010} {sa 022}] |
set da_1 [regbld ibd_rhrp::DA {ta 011} {sa 021}] |
set da_2 [regbld ibd_rhrp::DA {ta 012} {sa 020}] |
|
set dc_0 0x40 |
set dc_1 0x41 |
set dc_2 0x42 |
|
rlc log " C1.1: loc write da,mr1,of,dc (mr2 for RM) ----------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.da $da_0 \ |
-wma rpa.mr1 $mr1_0 \ |
-wma rpa.of $of_0 \ |
-wma rpa.dc $dc_0 |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-wma rpa.da $da_1 \ |
-wma rpa.mr1 $mr1_1 \ |
-wma rpa.of $of_1 \ |
-wma rpa.dc $dc_1 \ |
-wma rpa.m14 $mr2_1 |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-wma rpa.da $da_2 \ |
-wma rpa.mr1 $mr1_2 \ |
-wma rpa.of $of_2 \ |
-wma rpa.dc $dc_2 \ |
-wma rpa.m14 $mr2_2 |
|
rlc log " C1.2: loc read da,mr1,of,dc (mr2 for RM) -----------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-rma rpa.da -edata $da_0 \ |
-rma rpa.mr1 -edata $mr1_0 \ |
-rma rpa.of -edata $of_0 \ |
-rma rpa.dc -edata $dc_0 |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma rpa.da -edata $da_1 \ |
-rma rpa.mr1 -edata $mr1_1 \ |
-rma rpa.of -edata $of_1 \ |
-rma rpa.dc -edata $dc_1 \ |
-rma rpa.m14 -edata $mr2_1 |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-rma rpa.da -edata $da_2 \ |
-rma rpa.mr1 -edata $mr1_2 \ |
-rma rpa.of -edata $of_2 \ |
-rma rpa.dc -edata $dc_2 \ |
-rma rpa.m14 -edata $mr2_2 |
|
rlc log " C2.1: loc write er2,er3,ec1,ec2 --------------------" |
|
# unit 0: RP typ -> m14 is er2; m15 is er3 |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.m14 0xaa00 \ |
-wma rpa.m15 0xaa10 \ |
-wma rpa.ec1 0xaa20 \ |
-wma rpa.ec1 0xaa30 |
|
# unit 1+2: RM typ -> m15 is er2 |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-wma rpa.m15 0xaa11 \ |
-wma rpa.ec1 0xaa21 \ |
-wma rpa.ec1 0xaa31 |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-wma rpa.m15 0xaa12 \ |
-wma rpa.ec1 0xaa22 \ |
-wma rpa.ec1 0xaa32 |
|
rlc log " C2.1: loc read er2,er3,ec1,ec2 (NI -> =0!) ---------" |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-rma rpa.m14 -edata 0x0 \ |
-rma rpa.m15 -edata 0x0 \ |
-rma rpa.ec1 -edata 0x0 \ |
-rma rpa.ec1 -edata 0x0 |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma rpa.m15 -edata 0x0 \ |
-rma rpa.ec1 -edata 0x0 \ |
-rma rpa.ec1 -edata 0x0 |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-rma rpa.m15 -edata 0x0 \ |
-rma rpa.ec1 -edata 0x0 \ |
-rma rpa.ec1 -edata 0x0 |
|
# -- Section D --------------------------------------------------------------- |
rlc log " D1: test hr (for RM typ); ensure unit distinct ------------" |
|
# test unit 1+2, they are RM typ (RM05 and RP07) |
|
set da [regbld ibd_rhrp::DA {ta 005} {sa 023}]; # some da |
set dc 00456; # some dc |
|
rlc log " D1.1: write da(1) and dc(2) ------------------------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-wma rpa.da $da \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-wma rpa.da $dc |
|
rlc log " D1.2: check hr(1) and hr(2) ------------------------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma rpa.m13 -edata [rutil::com16 $da] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-rma rpa.m13 -edata [rutil::com16 $dc] |
|
rlc log " D1.3: write da(2) and dc(1) ------------------------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-wma rpa.da $da \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-wma rpa.da $dc |
|
rlc log " D1.4: check hr(1) and hr(2) ------------------------" |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma rpa.m13 -edata [rutil::com16 $dc] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-rma rpa.m13 -edata [rutil::com16 $da] |
|
# FIXME: add code to check hr response for all mb reg writes |
|
# -- Section E --------------------------------------------------------------- |
rlc log " E1: test rem er1 write; clear via func=dclr ---------------" |
rlc log " E1.1: rem er1 set uns,iae,aoe,ilf; loc readback ----" |
|
set er1msk [regbld ibd_rhrp::ER1 uns iae aoe ilf] |
|
# use unit 1 |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] |
|
$cpu cp -rma rpa.er1 -edata 0x0 \ |
-wibr rpa.er1 [regbld ibd_rhrp::ER1 uns] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns] $er1msk \ |
-wibr rpa.er1 [regbld ibd_rhrp::ER1 iae] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns iae] $er1msk \ |
-wibr rpa.er1 [regbld ibd_rhrp::ER1 aoe] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns iae aoe] $er1msk \ |
-wibr rpa.er1 [regbld ibd_rhrp::ER1 ilf] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 uns iae aoe ilf] $er1msk |
|
rlc log " E1.2: clear er1 via func=dclr ----------------------" |
|
$cpu cp -wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-rma rpa.er1 -edata 0x0 |
|
rlc log " E1.3: rem er1 set in different units ---------------" |
|
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.er1 [regbld ibd_rhrp::ER1 iae] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 1] \ |
-wibr rpa.er1 [regbld ibd_rhrp::ER1 aoe] \ |
-wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 2] \ |
-wibr rpa.er1 [regbld ibd_rhrp::ER1 ilf] |
|
rlc log " E1.4: loc readback, show er1 is distinct -----------" |
|
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 iae] $er1msk \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 aoe] $er1msk \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 ilf] $er1msk |
|
rlc log " E1.5: show func=dclr distinct ----------------------" |
|
# clear unit 1, that that 1 clr and 0+2 untouched |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 iae] $er1msk \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma rpa.er1 -edata 0x0 \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-rma rpa.er1 -edata [regbld ibd_rhrp::ER1 ilf] $er1msk |
|
rlc log " E1.6: clear er1 in remaining units -----------------" |
|
# unit 0+2 still have er1 bits set from previous test |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-rma rpa.er1 -edata 0x0 \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 2}] \ |
-wma rpa.cs1 [ibd_rhrp::cs1_func $ibd_rhrp::FUNC_DCLR] \ |
-rma rpa.er1 -edata 0x0 |
/rhrp/test_rhrp_basics.tcl
0,0 → 1,200
# $Id: test_rhrp_basics.tcl 683 2015-05-17 21:54:35Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2015-03-29 660 1.0 Initial version |
# |
# Test basic access |
# 1. ibus/rbus ack (for cs1:cs3) and no ack (cs3+2) |
# 2. unit enable/disable and cs2.ned response |
# 3. drive type logic |
# 4. readability of all regs (enabled and diabled unit, check cs2.ned) |
|
# ---------------------------------------------------------------------------- |
rlc log "test_rhrp_basics: basic access tests --------------------------------" |
rlc log " setup context" |
package require ibd_rhrp |
ibd_rhrp::setup |
|
rlc set statmask $rw11::STAT_DEFMASK |
rlc set statvalue 0 |
|
rlc log " A1: test that cs1,cs3 give ack, cs3+2 gives no ack --------" |
|
set iaddrfail [expr {[cpu0 imap rpa.cs3] + 2}] |
|
rlc log " A1.1: rem read cs1,cs3,cs3+1 -----------------------" |
|
$cpu cp -ribr rpa.cs1 \ |
-ribr rpa.cs3 \ |
-ribr $iaddrfail -estaterr |
|
rlc log " A1.2: loc read cs1,cs3,cs3+1 -----------------------" |
|
$cpu cp -rma rpa.cs1 \ |
-rma rpa.cs3 \ |
-rma $iaddrfail -estaterr |
|
rlc log " A2: test unit enable, dt and cs2.ned ----------------------" |
rlc log " A2.1: disable unit 0 -------------------------------" |
|
# |
# select rem and loc unit 0; disable unit |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit 0] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS {dpr 0}] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] |
|
rlc log " A2.2: check dt read and cs2.ned --------------------" |
set cs2ned [regbld ibd_rhrp::CS2 ned] |
$cpu cp -wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-rma rpa.dt \ |
-rma rpa.cs2 -edata $cs2ned $cs2ned |
|
rlc log " A2.3: enable unit 0 as RP06; check cs2.ned, dt -----" |
|
# check for cs2.ned=0 response on dt read (after cs1.tre=1) |
# unit 0 selected rem and loc from previous section |
$cpu cp -wibr rpa.ds [regbld ibd_rhrp::DS {dpr 1}] \ |
-wibr rpa.dt $ibd_rhrp::DTE_RP06 \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-rma rpa.dt -edata $ibd_rhrp::DT_RP06 \ |
-rma rpa.cs2 -edata 0 $cs2ned |
|
rlc log " A3: set drive types, check proper dt response -------------" |
|
# dte dt |
set tbl [list $ibd_rhrp::DTE_RP04 $ibd_rhrp::DT_RP04 \ |
$ibd_rhrp::DTE_RP06 $ibd_rhrp::DT_RP06 \ |
$ibd_rhrp::DTE_RM04 $ibd_rhrp::DT_RM04 \ |
$ibd_rhrp::DTE_RM80 $ibd_rhrp::DT_RM80 \ |
$ibd_rhrp::DTE_RM05 $ibd_rhrp::DT_RM05 \ |
$ibd_rhrp::DTE_RP07 $ibd_rhrp::DT_RP07 ] |
|
# unit 0 enabled and selected rem and loc from previous section |
foreach {dte dt} $tbl { |
$cpu cp -wibr rpa.dt $dte \ |
-ribr rpa.dt -edata $dte \ |
-rma rpa.dt -edata $dt |
} |
|
rlc log " A4: check unit selection and that units are distinct ------" |
|
rlc log " A4.1: setup units: 0: RP04 1:off 2:RP06 3:off ------" |
|
# unit dpr dte dt |
set tbl [list 0 1 $ibd_rhrp::DTE_RP04 $ibd_rhrp::DT_RP04 \ |
1 0 0 0 \ |
2 1 $ibd_rhrp::DTE_RP06 $ibd_rhrp::DT_RP06 \ |
3 0 0 0] |
|
foreach {unit dpr dte dt} $tbl { |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ |
-wibr rpa.ds [regbld ibd_rhrp::DS [list dpr $dpr]] \ |
-wibr rpa.dt $dte |
} |
|
rlc log " A4.2: readback dt rem and loc; check cs2.ned -------" |
|
set dsmsk [regbld ibd_rhrp::DS dpr] |
set cs2msk [regbld ibd_rhrp::CS2 ned {unit 3}] |
foreach {unit dpr dte dt} $tbl { |
set dsval [regbld ibd_rhrp::DS [list dpr $dpr]] |
set cs2val [regbld ibd_rhrp::CS2 [list ned [expr {1-$dpr}]] [list unit $unit]] |
$cpu cp -wibr rpa.cs1 [ibd_rhrp::rcs1_wunit $unit] \ |
-ribr rpa.ds -edata $dsval $dsmsk \ |
-ribr rpa.dt -edata $dte \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-rma rpa.dt -edata $dt \ |
-rma rpa.cs2 -edata $cs2val $cs2msk |
} |
|
rlc log " A5: check cs2.ned for all regs on disabled unit -----------" |
|
# use setting from last section: drive 0 on, drive 1 off |
# addr mb |
set tbl [list rpa.cs1 1 \ |
rpa.wc 0 \ |
rpa.ba 0 \ |
rpa.da 1 \ |
rpa.cs2 0 \ |
rpa.ds 1 \ |
rpa.er1 1 \ |
rpa.as 1 \ |
rpa.la 1 \ |
rpa.db 0 \ |
rpa.mr1 1 \ |
rpa.dt 1 \ |
rpa.sn 1 \ |
rpa.of 1 \ |
rpa.dc 1 \ |
rpa.m13 1 \ |
rpa.m14 1 \ |
rpa.m15 1 \ |
rpa.ec1 1 \ |
rpa.ec2 1 \ |
rpa.bae 0 \ |
rpa.cs3 0 \ |
] |
|
# Note: First unit 1 (enabled) selected, and cs1.tre=1 done |
# Than unit 1 (disabled) selected, and registered read |
# This ensures that cs2.ned is really cleared, because a cs1.tre=1 |
# write while a disabled drive is selected will clear and set ned !! |
set cs2msk [regbld ibd_rhrp::CS2 ned {unit -1}] |
foreach {addr mb} $tbl { |
set cs2val [regbld ibd_rhrp::CS2 [list ned $mb] {unit 1}] |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 0}] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-wma rpa.cs2 [regbld ibd_rhrp::CS2 {unit 1}] \ |
-rma $addr \ |
-rma rpa.cs2 -edata $cs2val $cs2msk |
} |
|
rlc log " A6: check cs2.ned for all regs on enable unit -------------" |
|
# select drive 0 (on); cs1.tre=1; read all regs; check cs2 at end once (sticky) |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit 0]] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-rma rpa.cs1 \ |
-rma rpa.wc \ |
-rma rpa.ba \ |
-rma rpa.da |
|
$cpu cp -rma rpa.cs2 \ |
-rma rpa.ds \ |
-rma rpa.er1 \ |
-rma rpa.as \ |
-rma rpa.la \ |
-rma rpa.db \ |
-rma rpa.mr1 |
|
$cpu cp -rma rpa.dt \ |
-rma rpa.sn \ |
-rma rpa.of \ |
-rma rpa.dc \ |
-rma rpa.m13 \ |
-rma rpa.m14 \ |
-rma rpa.m15 |
|
$cpu cp -rma rpa.ec1 \ |
-rma rpa.ec2 \ |
-rma rpa.bae \ |
-rma rpa.cs3 \ |
-rma rpa.cs2 -edata 0 [regbld ibd_rhrp::CS2 ned] |
|
rlc log " A7: check that unit 3-7 are loc selectable, but off -------" |
rlc log " A7.1: loc read dt for unit 3-7 ; check cs2.unit+ned" |
|
set cs2msk [regbld ibd_rhrp::CS2 ned {unit -1}] |
foreach {unit} {4 5 6 7} { |
set cs2val [regbld ibd_rhrp::CS2 ned [list unit $unit]] |
$cpu cp -wma rpa.cs2 [regbld ibd_rhrp::CS2 [list unit $unit]] \ |
-wma rpa.cs1 [regbld ibd_rhrp::CS1 tre] \ |
-rma rpa.dt -edata 0 \ |
-rma rpa.cs2 -edata $cs2val $cs2msk |
} |
|
rhrp
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: all.dat
===================================================================
--- all.dat (nonexistent)
+++ all.dat (revision 33)
@@ -0,0 +1,7 @@
+# $Id: all.dat 683 2015-05-17 21:54:35Z mueller $
+#
+## steering file for all tests
+#
+@cpu_all.dat
+@dev_all.dat
+#
Index: tm11/tm11_all.dat
===================================================================
--- tm11/tm11_all.dat (nonexistent)
+++ tm11/tm11_all.dat (revision 33)
@@ -0,0 +1,6 @@
+# $Id: tm11_all.dat 683 2015-05-17 21:54:35Z mueller $
+#
+## steering file for all tm11 tests
+#
+test_tm11_regs.tcl
+test_tm11_int.tcl
Index: tm11/test_tm11_regs.tcl
===================================================================
--- tm11/test_tm11_regs.tcl (nonexistent)
+++ tm11/test_tm11_regs.tcl (revision 33)
@@ -0,0 +1,175 @@
+# $Id: test_tm11_regs.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2015- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2015-05-17 683 1.0 Initial version
+#
+# Test register response
+# A: register basics
+
+# ----------------------------------------------------------------------------
+rlc log "test_tm11_regs: test register response ------------------------------"
+package require ibd_tm11
+ibd_tm11::setup
+
+rlc set statmask $rw11::STAT_DEFMASK
+rlc set statvalue 0
+
+# -- Section A ---------------------------------------------------------------
+rlc log " A1: test read ---------------------------------------------"
+rlc log " A1.1: loc read sr,...,rl ---------------------------"
+
+$cpu cp -rma tma.sr \
+ -rma tma.cr \
+ -rma tma.bc \
+ -rma tma.ba \
+ -rma tma.db \
+ -rma tma.rl
+
+rlc log " A1.2: rem read sr,...,rl ---------------------------"
+
+$cpu cp -ribr tma.sr \
+ -ribr tma.cr \
+ -ribr tma.bc \
+ -ribr tma.ba \
+ -ribr tma.db \
+ -ribr tma.rl
+
+rlc log " A1.3: test that rl+2,+4 gives no ack (loc) ---------"
+
+set iaddr2 [expr {[cpu0 imap tma.rl] + 2}]
+set iaddr4 [expr {[cpu0 imap tma.rl] + 4}]
+
+$cpu cp -ribr $iaddr2 -estaterr \
+ -ribr $iaddr4 -estaterr
+
+# -- Section B ---------------------------------------------------------------
+rlc log " B1: test sr setup -------------------------------------------------"
+
+rlc log " B1.1: rem write via rl -----------------------------"
+# setup units with eof=!u1 eot=!u0 onl=1 bot=u0 wrl=u1
+set rsr0 [regbld ibd_tm11::RRL {eof 1} {eot 1} {onl 1} {bot 0} {wrl 0} {unit 0}]
+set rsr1 [regbld ibd_tm11::RRL {eof 1} {eot 0} {onl 1} {bot 1} {wrl 0} {unit 1}]
+set rsr2 [regbld ibd_tm11::RRL {eof 0} {eot 1} {onl 1} {bot 0} {wrl 1} {unit 2}]
+set rsr3 [regbld ibd_tm11::RRL {eof 0} {eot 0} {onl 1} {bot 1} {wrl 1} {unit 3}]
+# on readback SR has tur=1
+set sr0 [regbld ibd_tm11::SR {eof 1} {eot 1} {onl 1} {bot 0} {wrl 0} {tur 1}]
+set sr1 [regbld ibd_tm11::SR {eof 1} {eot 0} {onl 1} {bot 1} {wrl 0} {tur 1}]
+set sr2 [regbld ibd_tm11::SR {eof 0} {eot 1} {onl 1} {bot 0} {wrl 1} {tur 1}]
+set sr3 [regbld ibd_tm11::SR {eof 0} {eot 0} {onl 1} {bot 1} {wrl 1} {tur 1}]
+set sr7 [regbld ibd_tm11::SR {tur 1}]
+
+$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \
+ -wibr "tma.rl" $rsr0 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \
+ -wibr "tma.rl" $rsr1 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \
+ -wibr "tma.rl" $rsr2 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \
+ -wibr "tma.rl" $rsr3
+
+rlc log " B1.2: rem read via rl ------------------------------"
+
+$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \
+ -ribr "tma.rl" -edata $rsr0 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \
+ -ribr "tma.rl" -edata $rsr1 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \
+ -ribr "tma.rl" -edata $rsr2 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \
+ -ribr "tma.rl" -edata $rsr3
+
+rlc log " B1.3: loc read via sr ------------------------------"
+
+$cpu cp -wma "tma.cr" [regbld ibd_tm11::CR {unit 0}]\
+ -rma "tma.sr" -edata $sr0 \
+ -wma "tma.cr" [regbld ibd_tm11::CR {unit 1}]\
+ -rma "tma.sr" -edata $sr1 \
+ -wma "tma.cr" [regbld ibd_tm11::CR {unit 2}]\
+ -rma "tma.sr" -edata $sr2 \
+ -wma "tma.cr" [regbld ibd_tm11::CR {unit 3}]\
+ -rma "tma.sr" -edata $sr3
+
+rlc log " B1.4: ensure unit 4,..,7 signal offline ------------"
+
+$cpu cp -wma "tma.cr" [regbld ibd_tm11::CR {unit 4}]\
+ -rma "tma.sr" -edata $sr7 \
+ -wma "tma.cr" [regbld ibd_tm11::CR {unit 5}]\
+ -rma "tma.sr" -edata $sr7 \
+ -wma "tma.cr" [regbld ibd_tm11::CR {unit 6}]\
+ -rma "tma.sr" -edata $sr7 \
+ -wma "tma.cr" [regbld ibd_tm11::CR {unit 7}]\
+ -rma "tma.sr" -edata $sr7
+
+rlc log " B1.5: setup unit 0:3 as onl=1 bot=1 ----------------"
+
+# use use ONL=1 BOT=1 for all units -> no error flags
+set rsr0 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 0}]
+set rsr1 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 1}]
+set rsr2 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 2}]
+set rsr3 [regbld ibd_tm11::RRL {onl 1} {bot 1} {unit 3}]
+# on readback SR has tur=1
+set sr0 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}]
+set sr1 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}]
+set sr2 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}]
+set sr3 [regbld ibd_tm11::SR {onl 1} {bot 1} {tur 1}]
+$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \
+ -wibr "tma.rl" $rsr0 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \
+ -wibr "tma.rl" $rsr1 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \
+ -wibr "tma.rl" $rsr2 \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \
+ -wibr "tma.rl" $rsr3
+
+rlc log " B2.1: loc write loc/rem read of cr -----------------"
+# test all cr fields except ie and go (no interrupts and functions yet)
+set crlist [list \
+ [regbld ibd_tm11::CR {den 0} {pevn 0} {unit 0} {ea 0} {func 0}] \
+ [regbld ibd_tm11::CR {den 3} {pevn 0} {unit 0} {ea 0} {func 0}] \
+ [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 0} {ea 0} {func 0}] \
+ [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 7} {ea 0} {func 0}] \
+ [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 3} {ea 3} {func 0}] \
+ [regbld ibd_tm11::CR {den 3} {pevn 1} {unit 3} {ea 3} {func 7}] \
+ ]
+
+foreach cr $crlist {
+ # on cr read here always rdy=1
+ set crread [expr {$cr | [regbld ibd_tm11::CR {rdy 1}] } ]
+ $cpu cp -wma "tma.cr" $cr \
+ -rma "tma.cr" -edata $crread \
+ -ribr "tma.cr" -edata $crread
+}
+
+rlc log " B3.1: loc write loc/rem read for bc,ba -------------"
+# Note: ba ignores bit 0, only word addresses
+$cpu cp -wma "tma.bc" 0x0010 \
+ -wma "tma.ba" 0x0020 \
+ -rma "tma.bc" -edata 0x0010 \
+ -rma "tma.ba" -edata 0x0020 \
+ -ribr "tma.bc" -edata 0x0010 \
+ -ribr "tma.ba" -edata 0x0020
+$cpu cp -wma "tma.bc" 0x8888 \
+ -wma "tma.ba" 0x7777 \
+ -rma "tma.bc" -edata 0x8888 \
+ -rma "tma.ba" -edata 0x7776 \
+ -ribr "tma.bc" -edata 0x8888 \
+ -ribr "tma.ba" -edata 0x7776
+
+rlc log " B3.2: rem write loc/rem read for bc,ba -------------"
+
+$cpu cp -wibr "tma.bc" 0x1234 \
+ -wibr "tma.ba" 0x4321 \
+ -rma "tma.bc" -edata 0x1234 \
+ -rma "tma.ba" -edata 0x4320 \
+ -ribr "tma.bc" -edata 0x1234 \
+ -ribr "tma.ba" -edata 0x4320
+$cpu cp -wibr "tma.bc" 0x0000 \
+ -wibr "tma.ba" 0x0000 \
+ -rma "tma.bc" -edata 0x0000 \
+ -rma "tma.ba" -edata 0x0000 \
+ -ribr "tma.bc" -edata 0x0000 \
+ -ribr "tma.ba" -edata 0x0000
Index: tm11/test_tm11_int.tcl
===================================================================
--- tm11/test_tm11_int.tcl (nonexistent)
+++ tm11/test_tm11_int.tcl (revision 33)
@@ -0,0 +1,162 @@
+# $Id: test_tm11_int.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2015- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2015-05-17 683 1.0 Initial version
+#
+# Test interrupt response
+# A:
+
+# ----------------------------------------------------------------------------
+rlc log "test_tm11_int: test interrupt response ------------------------------"
+rlc log " setup: all units online"
+package require ibd_tm11
+ibd_tm11::setup
+
+rlc set statmask $rw11::STAT_DEFMASK
+rlc set statvalue 0
+
+# configure drives
+set rsronl [regbld ibd_tm11::RRL {onl 1} {bot 1}]
+$cpu cp -wibr "tma.cr" [ibd_tm11::rcr_wunit 0] \
+ -wibr "tma.rl" $rsronl \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 1] \
+ -wibr "tma.rl" $rsronl \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 2] \
+ -wibr "tma.rl" $rsronl \
+ -wibr "tma.cr" [ibd_tm11::rcr_wunit 3] \
+ -wibr "tma.rl" $rsronl
+
+# load test code
+$cpu ldasm -lst lst -sym sym {
+ .include |lib/defs_cpu.mac|
+ .include |lib/defs_tm.mac|
+;
+ .include |lib/vec_cpucatch.mac|
+;
+ . = 000224 ; setup TM11 interrupt vector
+v..tm: .word vh.tm
+ .word cp.pr7
+;
+ . = 1000 ; data area
+stack:
+ibuf: .blkw 3. ; input buffer
+obuf: .blkw 5. ; output buffer
+fbuf: .blkw 4. ; final buffer
+;
+ . = 2000 ; code area
+start: spl 7 ; lock out interrupts
+;
+ mov #obuf,r0 ; clear obuf
+ clr (r0)+
+ clr (r0)+
+ clr (r0)+
+ clr (r0)+
+ clr (r0)+
+;
+ mov #ibuf,r0 ; setup regs from ibuf
+ mov (r0)+,@#tm.bc ; bc
+ mov (r0)+,@#tm.ba ; ba
+ mov (r0)+,@#tm.cr ; cr
+ spl 0 ; allow interrupts
+;
+poll: tstb @#tm.cr ; check cr
+ bpl poll ; if rdy=0 keep polling
+;
+4$: mov #fbuf,r0 ; store final regs in fbuf
+ mov @#tm.sr,(r0)+ ; sr
+ mov @#tm.cr,(r0)+ ; cr
+ mov @#tm.bc,(r0)+ ; bc
+ mov @#tm.ba,(r0)+ ; ba
+
+ halt ; halt if done
+stop:
+
+; TM11 interrupt handler
+vh.tm: mov #obuf,r0 ; store regs in obuf
+ mov #1,(r0)+ ; flag
+ mov @#tm.sr,(r0)+ ; sr
+ mov @#tm.cr,(r0)+ ; cr
+ mov @#tm.bc,(r0)+ ; bc
+ mov @#tm.ba,(r0)+ ; ba
+ rti ; and return
+}
+
+##puts $lst
+
+# define tmpproc for readback checks
+proc tmpproc_dotest {cpu symName opts} {
+ upvar 1 $symName sym
+
+ set tout 10.; # FIXME_code: parameter ??
+
+# setup defs hash, first defaults, than write over concrete run values
+ array set defs { i.cr 0 \
+ i.bc 0 \
+ i.ba 0 \
+ o.sr 0 \
+ o.cr 0 \
+ o.bc 0 \
+ o.ba 0 \
+ do.lam 0
+ }
+ array set defs $opts
+
+ # build ibuf
+ set ibuf [list $defs(i.bc) $defs(i.ba) $defs(i.cr)]
+
+ # setup write ibuf, setup stack, and start cpu at start:
+ $cpu cp -wal $sym(ibuf) \
+ -bwm $ibuf \
+ -wsp $sym(stack) \
+ -stapc $sym(start)
+
+ # here do minimal lam handling (harvest + send DONE)
+ if {$defs(do.lam)} {
+ rlc wtlam $tout apat
+ $cpu cp -attn \
+ -wibr tma.cs [ibd_rhrp::cr_func $ibd_tm11::RFUNC_DONE]
+ }
+
+ $cpu wtcpu -reset $tout
+
+ # determine regs after cleanup
+ $cpu cp -rpc -edata $sym(stop) \
+ -rsp -edata $sym(stack) \
+ -wal $sym(obuf) \
+ -rmi -edata 1 \
+ -rmi -edata $defs(o.sr) \
+ -rmi -edata $defs(o.cr) \
+ -rmi -edata $defs(o.bc) \
+ -rmi -edata $defs(o.ba) \
+ -wal $sym(fbuf) \
+ -rmi -edata $defs(o.sr) \
+ -rmi -edata $defs(o.cr) \
+ -rmi -edata $defs(o.bc) \
+ -rmi -edata $defs(o.ba)
+
+ return ""
+}
+
+# discard pending attn to be on save side
+rlc wtlam 0.
+rlc exec -attn
+
+# -- Section A ---------------------------------------------------------------
+rlc log " A1.1 set cr.ie=1 -> software interrupt -------------"
+
+set opts [list \
+ i.cr [regbld ibd_tm11::CR ie] \
+ i.bc 0xff00 \
+ i.ba 0x8800 \
+ o.sr [regbld ibd_tm11::SR onl bot tur] \
+ o.cr [regbld ibd_tm11::CR rdy ie] \
+ o.bc 0xff00 \
+ o.ba 0x8800
+ ]
+
+tmpproc_dotest $cpu sym $opts
+
Index: tm11
===================================================================
--- tm11 (nonexistent)
+++ tm11 (revision 33)
tm11
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: cp/cp_all.dat
===================================================================
--- cp/cp_all.dat (nonexistent)
+++ cp/cp_all.dat (revision 33)
@@ -0,0 +1,10 @@
+# $Id: cp_all.dat 683 2015-05-17 21:54:35Z mueller $
+#
+## steering file for all cp tests
+#
+test_cp_gpr.tcl
+test_cp_psw.tcl
+test_cp_membasics.tcl
+test_cp_ibrbasics.tcl
+test_cp_cpubasics.tcl
+#
Index: cp/test_cp_ibrbasics.tcl
===================================================================
--- cp/test_cp_ibrbasics.tcl (nonexistent)
+++ cp/test_cp_ibrbasics.tcl (revision 33)
@@ -0,0 +1,98 @@
+# $Id: test_cp_ibrbasics.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2014- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-12-26 621 1.1 test membe
+# 2014-03-02 552 1.0 Initial version
+#
+# Test very basic memory interface gymnastics
+# 2. write/read IB space via bwm/brm (use MMU SAR SM I regs)
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_cp_ibrbasics: Test very basic ibus interface gymnastics --------"
+
+rlc log " write/read ibus space (MMU SAR SM I regs) via bwm/brm"
+$cpu cp -wal 0172240 \
+ -bwm {012340 012342 012344}
+
+$cpu cp -wal 0172240 \
+ -brm 3 -edata {012340 012342 012344}
+
+rlc log " write/read ibus space (MMU SAR SM I regs) via wibr/ribr"
+$cpu cp -ribr 0172240 -edata 012340 \
+ -ribr 0172242 -edata 012342 \
+ -ribr 0172244 -edata 012344
+$cpu cp -wibr 0172240 022340 \
+ -wibr 0172242 022342 \
+ -wibr 0172244 022344
+$cpu cp -ribr 0172240 -edata 022340 \
+ -ribr 0172242 -edata 022342 \
+ -ribr 0172244 -edata 022344
+
+rlc log " membe with wibr (non sticky)"
+$cpu cp -wibr 0172240 0x0100 \
+ -wibr 0172242 0x0302 \
+ -wibr 0172244 0x0504
+rlc log " membe = 0 (no byte selected)"
+$cpu cp -wmembe 0 \
+ -wibr 0172242 0xffff \
+ -rmembe -edata 0x03 \
+ -ribr 0172242 -edata 0x0302
+rlc log " membe = 1 (lsb selected)"
+$cpu cp -wmembe 0x01 \
+ -wibr 0172242 0xffaa \
+ -rmembe -edata 0x03 \
+ -ribr 0172242 -edata 0x03aa
+rlc log " membe = 2 (msb selected)"
+$cpu cp -wmembe 0x02 \
+ -wibr 0172242 0xbbff \
+ -rmembe -edata 0x03 \
+ -ribr 0172242 -edata 0xbbaa
+
+$cpu cp -ribr 0172240 -edata 0x0100 \
+ -ribr 0172242 -edata 0xbbaa \
+ -ribr 0172244 -edata 0x0504
+
+rlc log " membe with wibr (sticky)"
+$cpu cp -wibr 0172240 0x1110 \
+ -wibr 0172242 0x1312 \
+ -wibr 0172244 0x1514
+
+rlc log " membe = 0 + stick (no byte selected)"
+$cpu cp -wmembe 0 -stick \
+ -wibr 0172242 0xffff \
+ -rmembe -edata 0x04 \
+ -ribr 0172242 -edata 0x1312
+
+rlc log " membe = 1 + stick (lsb selected)"
+$cpu cp -wmembe 1 -stick \
+ -wibr 0172240 0xffaa \
+ -rmembe -edata 0x05 \
+ -wibr 0172242 0xffbb \
+ -rmembe -edata 0x05 \
+ -wibr 0172244 0xffcc \
+ -rmembe -edata 0x05
+$cpu cp -ribr 0172240 -edata 0x11aa \
+ -ribr 0172242 -edata 0x13bb \
+ -ribr 0172244 -edata 0x15cc
+
+rlc log " membe = 2 + stick (msb selected)"
+$cpu cp -wmembe 2 -stick \
+ -wibr 0172240 0xccff \
+ -rmembe -edata 0x06 \
+ -wibr 0172242 0xbbff \
+ -rmembe -edata 0x06 \
+ -wibr 0172244 0xaaff \
+ -rmembe -edata 0x06
+$cpu cp -ribr 0172240 -edata 0xccaa \
+ -ribr 0172242 -edata 0xbbbb \
+ -ribr 0172244 -edata 0xaacc
+rlc log " membe = 3 again"
+$cpu cp -wmembe 3 \
+ -rmembe -edata 0x03
+
+# --------------------------------------------------------------------
Index: cp/test_cp_membasics.tcl
===================================================================
--- cp/test_cp_membasics.tcl (nonexistent)
+++ cp/test_cp_membasics.tcl (revision 33)
@@ -0,0 +1,72 @@
+# $Id: test_cp_membasics.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2014- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-03-02 552 1.0 Initial version
+#
+# Test very basic memory interface gymnastics
+# 1. write/read address register
+# 2. write/read memory via wm/wmi/rm/rmi (16 bit mode)
+# 3. write/read memory via bwm/brm (16 bit mode)
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_cp_membasics: Test very basic memory interface gymnastics ------"
+
+# --------------------------------------------------------------------
+rlc log " write/read address register"
+
+# test wal
+$cpu cp -wal 002000 \
+ -ral -edata 002000 \
+ -rah -edata 000000
+
+# test wah+wal
+$cpu cp -wal 003000 \
+ -wah 000001 \
+ -ral -edata 003000 \
+ -rah -edata 000001
+
+# --------------------------------------------------------------------
+rlc log " write/read memory via wm/wmi/rm/rmi (16 bit mode)"
+
+# simple write/read without increment
+$cpu cp -wal 002000 \
+ -wm 001100 \
+ -ral -edata 002000 \
+ -rah -edata 000000 \
+ -rm -edata 001100
+
+# double write + single read, check overwrite
+$cpu cp -wal 002000 \
+ -wm 002200 \
+ -wm 002210 \
+ -ral -edata 002000 \
+ -rah -edata 000000 \
+ -rm -edata 002210
+
+# double write/read with increment
+$cpu cp -wal 002100 \
+ -wmi 003300 \
+ -wmi 003310 \
+ -wmi 003320 \
+ -ral -edata 002106 \
+ -rah -edata 000000
+
+$cpu cp -wal 002100 \
+ -rmi -edata 003300 \
+ -rmi -edata 003310 \
+ -rmi -edata 003320 \
+ -ral -edata 002106 \
+ -rah -edata 000000
+
+# --------------------------------------------------------------------
+rlc log " write/read memory via bwm/brm (16 bit mode)"
+$cpu cp -wal 02200 \
+ -bwm {007700 007710 007720 007730}
+
+$cpu cp -wal 02200 \
+ -brm 4 -edata {007700 007710 007720 007730}
Index: cp/test_cp_gpr.tcl
===================================================================
--- cp/test_cp_gpr.tcl (nonexistent)
+++ cp/test_cp_gpr.tcl (revision 33)
@@ -0,0 +1,64 @@
+# $Id: test_cp_gpr.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2013-03-31 502 1.0 Initial version
+#
+# Test that general purpose registers are writable and readable via cp
+# check all 16 registers, especially that
+# set 0 and 1 are distinct
+# k,s,u mode sp are distinct
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_cp_gpr: test cp access to general purpose registers ------------"
+rlc log " write set 0"
+$cpu cp -wps 0000000
+$cpu cp -wr0 0000001 \
+ -wr1 0000101
+$cpu cp -wr2 0000201 \
+ -wr3 0000301
+$cpu cp -wr4 0000401 \
+ -wr5 0000501
+
+rlc log " write set 1"
+$cpu cp -wps 0004000
+$cpu cp -wr0 0010001 \
+ -wr1 0010101
+$cpu cp -wr2 0010201 \
+ -wr3 0010301
+$cpu cp -wr4 0010401 \
+ -wr5 0010501
+
+rlc log " write all sp and pc"
+$cpu cp -wps 0000000 -wsp 0000601; # ksp
+$cpu cp -wps 0040000 -wsp 0010601; # ssp
+$cpu cp -wps 0140000 -wsp 0020601; # usp
+$cpu cp -wps 0000000 -wpc 0000701; # pc
+
+rlc log " read set 0"
+$cpu cp -wps 0000000; # set 0
+$cpu cp -rr0 -edata 0000001 \
+ -rr1 -edata 0000101
+$cpu cp -rr2 -edata 0000201 \
+ -rr3 -edata 0000301
+$cpu cp -rr4 -edata 0000401 \
+ -rr5 -edata 0000501
+
+rlc log " read set 1"
+$cpu cp -wps 0004000; # set 1
+$cpu cp -rr0 -edata 0010001 \
+ -rr1 -edata 0010101
+$cpu cp -rr2 -edata 0010201 \
+ -rr3 -edata 0010301
+$cpu cp -rr4 -edata 0010401 \
+ -rr5 -edata 0010501
+
+rlc log " read all sp and pc"
+$cpu cp -wps 0000000 -rsp -edata 0000601; # ksp
+$cpu cp -wps 0040000 -rsp -edata 0010601; # ssp
+$cpu cp -wps 0140000 -rsp -edata 0020601; # usp
+$cpu cp -wps 0000000 -rpc -edata 0000701; # pc
Index: cp/test_cp_psw.tcl
===================================================================
--- cp/test_cp_psw.tcl (nonexistent)
+++ cp/test_cp_psw.tcl (revision 33)
@@ -0,0 +1,49 @@
+# $Id: test_cp_psw.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013-2014 by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-12-26 621 1.0.1 adopt to 4k word ibus window
+# 2013-03-31 502 1.0 Initial version
+#
+# Test that psw is writable and readable via various ways
+# 1. direct cp access
+# 2. via 16bit memory addressing
+# 3. via 22bit memory addressing
+# 4. via ibr window
+#
+# This test not only verifies psw, but also all basic access methods
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_cp_psw: test psw access via all methods ------------------------"
+rlc log " write/read via cp"
+foreach w { 000000 000017 } {
+ $cpu cp -wps $w \
+ -rps -edata $w
+}
+
+rlc log " write/read via 16bit cp addressing"
+$cpu cp -wal 0177776
+foreach w { 000000 000017 } {
+ $cpu cp -wm $w \
+ -rm -edata $w \
+ -rps -edata $w
+}
+
+rlc log " write/read via 22bit cp addressing"
+$cpu cp -wal 0177776 -wah 000177
+foreach w { 000000 000017 } {
+ $cpu cp -wm $w \
+ -rm -edata $w \
+ -rps -edata $w
+}
+
+rlc log " write/read via ibr window"
+foreach w { 000000 000017 } {
+ $cpu cp -wibr 0177776 $w \
+ -ribr 0177776 -edata $w \
+ -rps -edata $w
+}
Index: cp/test_cp_cpubasics.tcl
===================================================================
--- cp/test_cp_cpubasics.tcl (nonexistent)
+++ cp/test_cp_cpubasics.tcl (revision 33)
@@ -0,0 +1,134 @@
+# $Id: test_cp_cpubasics.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013-2015 by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2015-05-09 676 1.1 w11a start/stop/suspend overhaul
+# 2013-03-31 502 1.0 Initial version
+#
+# Test very basic cpu interface gymnastics
+# 1. load code via ldasm
+# 2. execute code via -start, -stapc
+# 3. single step code via -step
+# 4. verify -suspend, -resume
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_cp_cpubasics: Test very basic cpu interface gymnastics ---------"
+rlc log " A1: start/stop/step basics --------------------------------"
+rlc log " load simple linear code via lsasm"
+
+#
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: inc r2
+ inc r2
+ inc r2
+ halt
+stop:
+}
+
+rlc log " read back and check"
+$cpu cp -wal $sym(start) \
+ -brm 4 -edata {0005202 0005202 0005202 0000000}
+
+rlc log " execute via -start"
+$cpu cp -wr2 00000 \
+ -wpc $sym(start) \
+ -start
+$cpu wtcpu -reset 1.0
+$cpu cp -rr2 -edata 00003 \
+ -rpc -edata $sym(stop)
+
+rlc log " execute via -stapc"
+$cpu cp -wr2 00100 \
+ -stapc $sym(start)
+$cpu wtcpu -reset 1.0
+$cpu cp -rr2 -edata 00103 \
+ -rpc -edata $sym(stop)
+
+rlc log " execute via -step"
+$cpu cp -wr2 00300 \
+ -wpc $sym(start)
+$cpu cp -step \
+ -rpc -edata [expr {$sym(start)+002}] \
+ -rr2 -edata 00301 \
+ -rstat -edata 000100
+$cpu cp -step \
+ -rpc -edata [expr {$sym(start)+004}] \
+ -rr2 -edata 00302 \
+ -rstat -edata 000100
+$cpu cp -step \
+ -rpc -edata [expr {$sym(start)+006}] \
+ -rr2 -edata 00303 \
+ -rstat -edata 000100
+$cpu cp -step \
+ -rpc -edata [expr {$sym(start)+010}] \
+ -rr2 -edata 00303 \
+ -rstat -edata 000020
+
+rlc log " A2: suspend/resume basics; cpugo,cpususp flags ------------"
+# define tmpproc for r2 increment checks
+proc tmpproc_checkr2inc {val} {
+ set emsg ""
+ if {$val == 0} {
+ set emsg "FAIL: r2 change zero"
+ rlc errcnt -inc
+ }
+ rlc log -bare ".. r2 increment $val $emsg"
+}
+
+#
+rlc log " load simple loop code via lsasm"
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: inc r2
+ br start
+stop:
+}
+
+set statgo [regbld rw11::STAT cpugo]
+set statgosu [regbld rw11::STAT cpususp cpugo]
+
+rlc log " execute via -stapc, check cpugo and that r2 increments"
+$cpu cp -wr2 00000 \
+ -stapc $sym(start) \
+ -rr2 rr2_1 -estat $statgo \
+ -rr2 rr2_2 -estat $statgo
+tmpproc_checkr2inc $rr2_1
+tmpproc_checkr2inc [expr {$rr2_2 - $rr2_1}]
+
+rlc log " suspend, check cpususp=1 and that r2 doesn't increment"
+$cpu cp -suspend \
+ -wr2 00000 \
+ -rr2 -edata 0 -estat $statgosu \
+ -rr2 -edata 0 -estat $statgosu
+
+rlc log " resume, check cpususp=0 and that r2 increments again"
+$cpu cp -resume \
+ -rr2 rr2_1 -estat $statgo \
+ -rr2 rr2_2 -estat $statgo
+tmpproc_checkr2inc $rr2_1
+tmpproc_checkr2inc [expr {$rr2_2 - $rr2_1}]
+
+rlc log " suspend than step, two steps should inc r2 once"
+$cpu cp -suspend \
+ -wr2 00000 \
+ -step \
+ -step \
+ -rr2 -edata 1 \
+ -step \
+ -step \
+ -rr2 -edata 2
+
+rlc log " stop while suspended, check cpugo=0,cpususp=1,attn=1; harvest attn"
+$cpu cp -stop -estat [regbld rw11::STAT cpususp attn]
+$cpu wtcpu -reset 1.0
+
+rlc log " creset, check cpususp=0"
+# Note: creset still has cpususp stat flag set because it clears with one
+# cycle delay. So do -estat after next command
+$cpu cp -creset \
+ -rr2 -estat 0
Index: cp
===================================================================
--- cp (nonexistent)
+++ cp (revision 33)
cp
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: cpu_all.dat
===================================================================
--- cpu_all.dat (nonexistent)
+++ cpu_all.dat (revision 33)
@@ -0,0 +1,7 @@
+# $Id: cpu_all.dat 683 2015-05-17 21:54:35Z mueller $
+#
+## steering file for all cpu tests
+#
+@cp/cp_all.dat
+@w11a/w11a_all.dat
+#
Index: w11a/test_w11a_inst_traps.tcl
===================================================================
--- w11a/test_w11a_inst_traps.tcl (nonexistent)
+++ w11a/test_w11a_inst_traps.tcl (revision 33)
@@ -0,0 +1,90 @@
+# $Id: test_w11a_inst_traps.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013-2014 by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
+# 2014-03-01 552 1.0.1 check that unused regs stay 0; use stack:; check sp;
+# 2013-04-01 502 1.0 Initial version
+#
+# Test trap type instructions: bpt,iot, emt nn, trap nn
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_w11a_inst_traps: test trap type instructions"
+
+# code register pre/post conditions beyond defaults
+# r5 #data -> #data+6*5*2
+$cpu ldasm -lst lst -sym sym {
+ . = 14
+ .word h.bpt ; vec 14: bpt
+ .word 340
+ .word h.iot ; vec 20: iot
+ .word 341
+ . = 30
+ .word h.emt ; vec 30: emt
+ .word 342
+ .word h.trp ; vec 34: trap
+ .word 343
+;
+ psw = 177776
+;
+ . = 1000
+stack:
+start: mov #350,@#psw
+ bpt
+350$: mov #351,@#psw
+ iot
+351$: mov #352,@#psw
+ emt 100
+352$: mov #353,@#psw
+ emt 200
+353$: mov #354,@#psw
+ trap 10
+354$: mov #355,@#psw
+ trap 20
+355$: halt
+stop:
+;
+h.bpt: mov @#psw,(r5)+ ; record psw
+ mov #1014,(r5)+ ; record trap id
+ br iexit
+h.iot: mov @#psw,(r5)+
+ mov #1020,(r5)+
+ br iexit
+h.emt: mov @#psw,(r5)+
+ mov #1030,(r5)+
+ br iexit
+h.trp: mov @#psw,(r5)+
+ mov #1034,(r5)+
+;
+iexit: mov (sp),r4 ; get stack PC
+ mov r4,(r5)+ ; record PC
+ mov 2(sp),(r5)+ ; record stack PS
+ mov -2(r4),(r5)+ ; record opcode of trap
+ rti
+;
+data: .blkw 6.*5.
+ .word 177777
+}
+
+rw11::asmrun $cpu sym [list r5 $sym(data) ]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 0 \
+ r1 0 \
+ r2 0 \
+ r3 0 \
+ r5 [expr {$sym(data) + 6*5*2}] \
+ sp $sym(stack) ]
+
+# data: trap ps; trap id; stack-pc; stack-ps opcode
+rw11::asmtmem $cpu $sym(data) \
+ [list 000340 001014 $sym(start:350$) 000350 0000003 \
+ 000341 001020 $sym(start:351$) 000351 0000004 \
+ 000342 001030 $sym(start:352$) 000352 0104100 \
+ 000342 001030 $sym(start:353$) 000353 0104200 \
+ 000343 001034 $sym(start:354$) 000354 0104410 \
+ 000343 001034 $sym(start:355$) 000355 0104420 \
+ 0177777 ]
Index: w11a/test_w11a_dstm_word_flow.tcl
===================================================================
--- w11a/test_w11a_dstm_word_flow.tcl (nonexistent)
+++ w11a/test_w11a_dstm_word_flow.tcl (revision 33)
@@ -0,0 +1,103 @@
+# $Id: test_w11a_dstm_word_flow.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013-2014 by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
+# 2014-03-01 552 1.0.1 check that unused regs stay 0
+# 2013-03-31 502 1.0 Initial version
+#
+# Test dstm flow with inc ... instructions for word access
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_w11a_dstm_word_flow: test dstm flow for word with inc ..."
+rlc log " r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5)"
+
+# code register pre/post conditions beyond defaults
+# r0 #010 -> #011
+# r1 #data1 -> #data1
+# r2 #data2 -> #data2+4
+# r3 #pdata3 -> #pdata3+4
+# r4 #data4e -> #data4e-4
+# r5 #pdat5e -> #pdat5e-4
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: inc r0
+ inc (r1)
+ inc (r2)+
+ inc (r2)+
+ inc @(r3)+
+ inc @(r3)+
+ inc -(r4)
+ inc -(r4)
+ inc @-(r5)
+ inc @-(r5)
+ halt
+stop:
+;
+data1: .word 20
+data2: .word 30,31
+data3: .word 40,41
+data4: .word 50,51
+data4e:
+data5: .word 60,61
+data5e:
+pdata3: .word data3,data3+2
+pdata5: .word data5,data5+2
+pdat5e:
+}
+
+rw11::asmrun $cpu sym [list r0 010 \
+ r1 $sym(data1) \
+ r2 $sym(data2) \
+ r3 $sym(pdata3) \
+ r4 $sym(data4e) \
+ r5 $sym(pdat5e) ]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 011 \
+ r1 $sym(data1) \
+ r2 [expr {$sym(data2) + 4}] \
+ r3 [expr {$sym(pdata3) + 4}] \
+ r4 [expr {$sym(data4e) - 4}] \
+ r5 [expr {$sym(pdat5e) - 4}] ]
+rw11::asmtmem $cpu $sym(data1) {021 031 032 041 042 051 052 061 062}
+
+# ----------------------------------------------------------------------------
+rlc log " nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
+
+# code register pre/post conditions beyond defaults
+# r0 #data0-020 -> ..same
+# r1 #pdata1-040 -> ..same
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: inc 20(r0)
+ inc @40(r1)
+ inc data2
+ inc @pdata3
+ inc @#data4
+ halt
+stop:
+;
+data0: .word 200
+data1: .word 210
+data2: .word 220
+data3: .word 230
+data4: .word 240
+data4e:
+pdata1: .word data1
+pdata3: .word data3
+}
+
+rw11::asmrun $cpu sym [list r0 [expr {$sym(data0)-020}] \
+ r1 [expr {$sym(pdata1)-040}] ]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 [expr {$sym(data0)-020}] \
+ r1 [expr {$sym(pdata1)-040}] \
+ r2 0 \
+ r3 0 \
+ r4 0 \
+ r5 0 ]
+rw11::asmtmem $cpu $sym(data0) {0201 0211 0221 0231 0241}
Index: w11a/test_w11a_srcr_word_flow.tcl
===================================================================
--- w11a/test_w11a_srcr_word_flow.tcl (nonexistent)
+++ w11a/test_w11a_srcr_word_flow.tcl (revision 33)
@@ -0,0 +1,181 @@
+# $Id: test_w11a_srcr_word_flow.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
+# 2014-03-01 552 1.0.1 check sp
+# 2013-03-31 502 1.0 Initial version
+#
+# Test srcr flow with mov ...,rx instructions for word access
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_w11a_srcr_word_flow: test srcr flow for word with mov ...,rx"
+rlc log " r0 (mode=0)"
+
+# code register pre/post conditions beyond defaults
+# r0 01234 -> ..same
+# r1 -> 01234
+# r2 -> #stack
+# r3 -> #start
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+stack:
+start: mov r0,r1
+ mov sp,r2
+ mov pc,r3
+lpc: halt
+stop:
+}
+
+rw11::asmrun $cpu sym [list r0 01234]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 01234 \
+ r1 01234 \
+ r2 $sym(stack) \
+ r3 $sym(lpc) \
+ r4 0 \
+ r5 0 \
+ sp $sym(stack) ]
+
+# ----------------------------------------------------------------------------
+rlc log " (r0),(r0)+,-(r0) (mode=1,2,4)"
+
+# code register pre/post conditions beyond defaults
+# r0 #data -> ..same
+# r1 -> 01001
+# r2 -> 01001
+# r3 -> 01002
+# r4 -> 01002
+# r5 -> 01001
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: mov (r0),r1
+ mov (r0)+,r2
+ mov (r0)+,r3
+ mov -(r0),r4
+ mov -(r0),r5
+ halt
+stop:
+;
+data: .word 1001
+ .word 1002
+}
+
+rw11::asmrun $cpu sym [list r0 $sym(data)]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 $sym(data) \
+ r1 001001 \
+ r2 001001 \
+ r3 001002 \
+ r4 001002 \
+ r5 001001 ]
+
+# ----------------------------------------------------------------------------
+rlc log " @(r0)+,@-(r0) (mode=3,5)"
+
+# code register pre/post conditions beyond defaults
+# r0 #pdata -> ..same
+# r1 -> 02001
+# r2 -> 02002
+# r3 -> #pdata+4
+# r4 -> 02002
+# r5 -> 02001
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: mov @(r0)+,r1
+ mov @(r0)+,r2
+ mov r0,r3
+ mov @-(r0),r4
+ mov @-(r0),r5
+ halt
+stop:
+;
+pdata: .word data0
+ .word data1
+data0: .word 2001
+ .word 0
+data1: .word 2002
+}
+
+rw11::asmrun $cpu sym [list r0 $sym(pdata)]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 $sym(pdata) \
+ r1 002001 \
+ r2 002002 \
+ r3 [expr {$sym(pdata)+4}] \
+ r4 002002 \
+ r5 002001 ]
+
+# ----------------------------------------------------------------------------
+rlc log " nn(r0),@nn(r0) (mode=6,7)"
+
+# code register pre/post conditions beyond defaults
+# r0 #data -> ..same
+# r1 -> 03001
+# r2 -> 03002
+# r3 -> 03003
+# r4 -> 03004
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: mov 2(r0),r1
+ mov @4(r0),r2
+ mov 6(r0),r3
+ mov @10(r0),r4
+ halt
+stop:
+;
+data: .word 177777
+ .word 003001
+ .word data0
+ .word 003003
+ .word data1
+
+data0: .word 003002
+data1: .word 003004
+}
+
+rw11::asmrun $cpu sym [list r0 $sym(data)]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 $sym(data) \
+ r1 003001 \
+ r2 003002 \
+ r3 003003 \
+ r4 003004 \
+ r5 0 ]
+
+# ----------------------------------------------------------------------------
+rlc log " #nn,@#nn,var,@var (mode=27,37,67,77)"
+
+# code register pre/post conditions beyond defaults
+# r1 -> 04001
+# r2 -> 04002
+# r3 -> 04003
+# r4 -> 04004
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: mov #004001,r1
+ mov @#data2,r2
+ mov data3,r3
+ mov @pdata4,r4
+ halt
+stop:
+;
+pdata4: .word data4
+
+data2: .word 004002
+data3: .word 004003
+data4: .word 004004
+}
+
+rw11::asmrun $cpu sym {}
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 0 \
+ r1 004001 \
+ r2 004002 \
+ r3 004003 \
+ r4 004004 \
+ r5 0 ]
Index: w11a/w11a_all.dat
===================================================================
--- w11a/w11a_all.dat (nonexistent)
+++ w11a/w11a_all.dat (revision 33)
@@ -0,0 +1,12 @@
+# $Id: w11a_all.dat 683 2015-05-17 21:54:35Z mueller $
+#
+## steering file for all w11a tests
+#
+test_w11a_srcr_word_flow.tcl
+test_w11a_dstw_word_flow.tcl
+test_w11a_dstm_word_flow.tcl
+test_w11a_dsta_flow.tcl
+test_w11a_inst_traps.tcl
+#
+test_w11a_div.tcl
+#
Index: w11a/test_w11a_div.tcl
===================================================================
--- w11a/test_w11a_div.tcl (nonexistent)
+++ w11a/test_w11a_div.tcl (revision 33)
@@ -0,0 +1,390 @@
+# $Id: test_w11a_div.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2014- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
+# 2014-07-20 570 1.0.2 add rw11::div_show_test; test late div quit cases
+# 2014-07-12 569 1.0.1 move sxt16/32 to rutil
+# 2014-07-11 568 1.0 Initial version
+# 2014-06-29 566 0.1 First draft
+#
+# Test div instruction
+#
+
+namespace eval rw11 {
+
+ #
+ # div_simh: calculate expected division result as pdp11 simh does it -------
+ #
+ # this pdp11 div emulation adopted from pdp11_cpu.c (git head 2014-06-09)
+ proc div_simh {ddi dri} {
+ set src2 $dri
+ set src $ddi
+ set qd [expr ($ddi>>16) & 0xffff]; # w11a default for V=1 bailouts
+ set rd [expr $ddi & 0xffff]; # "
+ set n [expr {($ddi<0) ^ ($dri<0)}]; # "
+ set z 0; # "
+
+ # quit if divident larger than possible 16 bit signed products
+ if {$src > 1073774591 || $src < -1073741823} {
+ return [list $qd $rd $n $z 1 0]
+ }
+ # quit if divisor zero
+ if {$src2 == 0} {
+ return [list $qd $rd $n $z 1 1]
+ }
+
+ if {$src2 & 0x8000} {
+ set src2 [expr $src2 | ~ 077777]
+ }
+ if {$src & 0x80000000} {
+ set src [expr $src | ~ 017777777777]
+ }
+
+ # Tcl "/" uses 'round down' sematics, while C (and PDP11) 'round to 0'
+ # ddi dri Tcl C/C++
+ # 34 5 q= 6 r= 4 q= 6 r= 4
+ # 34 -5 q= 7 r=-1 q=-6 r= 4
+ # -34 5 q=-7 r= 1 q=-6 r=-4
+ # -34 -5 q= 6 r=-4 q= 6 r=-4
+ # Tcl --> r same sign as divisor
+ # C --> r same sign as divident
+ # so add correction step to always get C/C++/PDP11 divide semantics
+ #
+ set q [expr $src / $src2]
+ set r [expr ($src - ($src2 * $q))]
+
+ if {$r!=0 && (($src<0) ^ ($r<0))} { # divident and remainder diff sign
+ set r [expr $r - $src2]
+ set q [expr $q + (($q<0)?1:-1)]
+ }
+
+ if {($q > 32767) || ($q < -32768)} {
+ return [list $qd $rd $n $z 1 0]
+ }
+
+ set n [expr {$q < 0}]
+ set z [expr {$q == 0}]
+ return [list $q $r $n $z 0 0]
+ }
+
+ #
+ # div_testd3: test division ddh,ddl,,dr + expected result ------------------
+ #
+ proc div_testd3 {cpu symName ddh ddl dr q r n z v c} {
+ upvar 1 $symName sym
+ set nzvc [expr {($n<<3) | ($z<<2) | ($v<<1) | $c}]
+ set dr16 [expr {$dr & 0xffff}]
+ set q16 [expr {$q & 0xffff}]
+ set r16 [expr {$r & 0xffff}]
+
+ # use rw11::div_show_test to enable generation of divtst files
+ if {[info exists rw11::div_show_test] && $rw11::div_show_test} {
+ set ddi [expr (($ddh&0xffff)<<16) + ($ddl&0xffff)]
+ set ddi [rutil::sxt32 $ddi]
+ set dri [rutil::sxt16 $dr16]
+ set qi [rutil::sxt16 $q16]
+ set ri [rutil::sxt16 $r16]
+ puts [format "%06o %06o %06o : %d%d%d%d %06o %06o # %11d/%6d:%6d,%6d" \
+ $ddh $ddl $dr16 $n $z $v $c $q16 $r16 $ddi $dri $qi $ri ]
+ }
+
+ rw11::asmrun $cpu sym [list r0 $ddh r1 $ddl r2 $dr16]
+ rw11::asmwait $cpu sym
+
+ if {!$v && !$c} { # test q and r only when V=0 C=0 expected
+ lappend treglist r0 $q16 r1 $r16
+ }
+ lappend treglist r3 $nzvc
+
+ set errcnt [rw11::asmtreg $cpu $treglist]
+
+ if {$errcnt} {
+ puts [format \
+ "div FAIL: dd=%06o,%06o dr=%06o exp: q=%06o r=%06o nzvc=%d%d%d%d" \
+ $ddh $ddl $dr16 $q16 $r16 $n $z $v $c]
+ }
+ return $errcnt
+ }
+
+ #
+ # div_testd2: test division dd,dr + expected result ------------------------
+ #
+ proc div_testd2 {cpu symName dd dr q r n z v c} {
+ upvar 1 $symName sym
+ set ddh [expr {($dd>>16) & 0xffff}]
+ set ddl [expr { $dd & 0xffff}]
+ return [div_testd3 $cpu sym $ddh $ddl $dr $q $r $n $z $v $c]
+ }
+
+ #
+ # div_testdqr: test division, give divisor, quotient and remainder ---------
+ #
+ proc div_testdqr {cpu symName dri qi ri} {
+ upvar 1 $symName sym
+ set dri [rutil::sxt16 $dri]
+ set qi [rutil::sxt16 $qi]
+ set ri [rutil::sxt16 $ri]
+ set ddi [expr {$dri*$qi + $ri}]
+
+ set simhres [div_simh $ddi $dri]
+ set q [lindex $simhres 0]
+ set r [lindex $simhres 1]
+ set n [lindex $simhres 2]
+ set z [lindex $simhres 3]
+ set v [lindex $simhres 4]
+ set c [lindex $simhres 5]
+
+ return [div_testd2 $cpu sym $ddi $dri $q $r $n $z $v $c]
+ }
+}
+
+# ----------------------------------------------------------------------------
+rlc log "test_div: test div instruction"
+
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+stack:
+start: div r2,r0
+ mov @#177776,r3
+ bic #177760,r3
+ halt
+stop:
+}
+
+rlc log " test basics (via testd2)"
+# dd dr q r n z v c
+rlc log " dr>0"
+rw11::div_testd2 $cpu sym 0 3 0 0 0 1 0 0
+rw11::div_testd2 $cpu sym 1 3 0 1 0 1 0 0
+rw11::div_testd2 $cpu sym 2 3 0 2 0 1 0 0
+rw11::div_testd2 $cpu sym 3 3 1 0 0 0 0 0
+rw11::div_testd2 $cpu sym 4 3 1 1 0 0 0 0
+rw11::div_testd2 $cpu sym -1 3 0 -1 0 1 0 0
+rw11::div_testd2 $cpu sym -2 3 0 -2 0 1 0 0
+rw11::div_testd2 $cpu sym -3 3 -1 0 1 0 0 0
+rw11::div_testd2 $cpu sym -4 3 -1 -1 1 0 0 0
+rlc log " dr<0"
+rw11::div_testd2 $cpu sym 0 -3 0 0 0 1 0 0
+rw11::div_testd2 $cpu sym 1 -3 0 1 0 1 0 0
+rw11::div_testd2 $cpu sym 2 -3 0 2 0 1 0 0
+rw11::div_testd2 $cpu sym 3 -3 -1 0 1 0 0 0
+rw11::div_testd2 $cpu sym 4 -3 -1 1 1 0 0 0
+rw11::div_testd2 $cpu sym -1 -3 0 -1 0 1 0 0
+rw11::div_testd2 $cpu sym -2 -3 0 -2 0 1 0 0
+rw11::div_testd2 $cpu sym -3 -3 1 0 0 0 0 0
+rw11::div_testd2 $cpu sym -4 -3 1 -1 0 0 0 0
+rlc log " dr==0"
+rw11::div_testd2 $cpu sym 0 0 0 0 0 1 1 1
+rw11::div_testd2 $cpu sym 1 0 0 0 0 1 1 1
+rw11::div_testd2 $cpu sym -1 0 0 0 0 1 1 1
+
+rlc log " test 4 quadrant basics (via testd2)"
+# dd dr q r n z v c
+rw11::div_testd2 $cpu sym 34 5 6 4 0 0 0 0
+rw11::div_testd2 $cpu sym 34 -5 -6 4 1 0 0 0
+rw11::div_testd2 $cpu sym -34 5 -6 -4 1 0 0 0
+rw11::div_testd2 $cpu sym -34 -5 6 -4 0 0 0 0
+
+rlc log " test 4 quadrant basics (via testdqr)"
+# dr q r
+rw11::div_testdqr $cpu sym 5 6 4;
+rw11::div_testdqr $cpu sym -5 -6 4;
+rw11::div_testdqr $cpu sym 5 -6 -4;
+rw11::div_testdqr $cpu sym -5 6 -4;
+
+rlc log " test q=100000 boundary cases (q = max neg value)"
+rlc log " case dd>0, dr<0 -- factor 21846"
+# dr q r
+rw11::div_testdqr $cpu sym -21846 0100000 0; # BAD-R4
+rw11::div_testdqr $cpu sym -21846 0100000 1; # BAD-R4
+rw11::div_testdqr $cpu sym -21846 0100000 21844; # BAD-R4
+rw11::div_testdqr $cpu sym -21846 0100000 21845; # BAD-R4
+rw11::div_testdqr $cpu sym -21846 0100000 21846; # v=1
+rw11::div_testdqr $cpu sym -21846 0100000 21847; # v=1
+
+rlc log " case dd<0, dr>0 -- factor 21846"
+rw11::div_testdqr $cpu sym 21846 0100000 0; # BAD-R4
+rw11::div_testdqr $cpu sym 21846 0100000 -1; # BAD-R4
+rw11::div_testdqr $cpu sym 21846 0100000 -21844; # BAD-R4
+rw11::div_testdqr $cpu sym 21846 0100000 -21845; # BAD-R4
+rw11::div_testdqr $cpu sym 21846 0100000 -21846; # v=1
+rw11::div_testdqr $cpu sym 21846 0100000 -21847; # v=1
+
+rlc log " case dd>0, dr<0 -- factor 21847"
+rw11::div_testdqr $cpu sym -21847 0100000 0; # BAD-R4
+rw11::div_testdqr $cpu sym -21847 0100000 1; # BAD-R4
+rw11::div_testdqr $cpu sym -21847 0100000 21845; # BAD-R4
+rw11::div_testdqr $cpu sym -21847 0100000 21846; # BAD-R4
+rw11::div_testdqr $cpu sym -21847 0100000 21847; # v=1
+rw11::div_testdqr $cpu sym -21847 0100000 21848; # v=1
+
+rlc log " case dd<0, dr>0 -- factor 21847"
+rw11::div_testdqr $cpu sym 21847 0100000 0; # BAD-R4
+rw11::div_testdqr $cpu sym 21847 0100000 -1; # BAD-R4
+rw11::div_testdqr $cpu sym 21847 0100000 -21845; # BAD-R4
+rw11::div_testdqr $cpu sym 21847 0100000 -21846; # BAD-R4
+rw11::div_testdqr $cpu sym 21847 0100000 -21847; # v=1
+rw11::div_testdqr $cpu sym 21847 0100000 -21848; # v=1
+
+#
+#
+rlc log " test q=077777 boundary cases (q = max pos value)"
+rlc log " case dd>0, dr>0 -- factor 21846"
+rw11::div_testdqr $cpu sym 21846 0077777 0; #
+rw11::div_testdqr $cpu sym 21846 0077777 1; #
+rw11::div_testdqr $cpu sym 21846 0077777 21844; #
+rw11::div_testdqr $cpu sym 21846 0077777 21845; #
+rw11::div_testdqr $cpu sym 21846 0077777 21846; # v=1
+rw11::div_testdqr $cpu sym 21846 0077777 21847; # v=1
+rlc log " case dd<0, dr<0 -- factor 21846"
+rw11::div_testdqr $cpu sym -21846 0077777 0; #
+rw11::div_testdqr $cpu sym -21846 0077777 -1; #
+rw11::div_testdqr $cpu sym -21846 0077777 -21844; #
+rw11::div_testdqr $cpu sym -21846 0077777 -21845; #
+rw11::div_testdqr $cpu sym -21846 0077777 -21846; # v=1
+rw11::div_testdqr $cpu sym -21846 0077777 -21847; # v=1
+rlc log " case dd>0, dr>0 -- factor 21847"
+rw11::div_testdqr $cpu sym 21847 0077777 0; #
+rw11::div_testdqr $cpu sym 21847 0077777 1; #
+rw11::div_testdqr $cpu sym 21847 0077777 21845; #
+rw11::div_testdqr $cpu sym 21847 0077777 21846; #
+rw11::div_testdqr $cpu sym 21847 0077777 21847; # v=1
+rw11::div_testdqr $cpu sym 21847 0077777 21848; # v=1
+rlc log " case dd<0, dr<0 -- factor 21847"
+rw11::div_testdqr $cpu sym -21847 0077777 0; #
+rw11::div_testdqr $cpu sym -21847 0077777 -1; #
+rw11::div_testdqr $cpu sym -21847 0077777 -21845; #
+rw11::div_testdqr $cpu sym -21847 0077777 -21846; #
+rw11::div_testdqr $cpu sym -21847 0077777 -21846; # v=1
+rw11::div_testdqr $cpu sym -21847 0077777 -21847; # v=1
+#
+#
+rlc log " test dr=100000 boundary cases (dr = max neg value)"
+rlc log " case dd<0, q>0"
+rw11::div_testdqr $cpu sym 0100000 1 0; #
+rw11::div_testdqr $cpu sym 0100000 1 -1; #
+rw11::div_testdqr $cpu sym 0100000 1 -32767; #
+rw11::div_testdqr $cpu sym 0100000 2 0; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 2 -1; #
+rw11::div_testdqr $cpu sym 0100000 2 -32767; #
+rw11::div_testdqr $cpu sym 0100000 3 0; #
+rw11::div_testdqr $cpu sym 0100000 3 -1; #
+rw11::div_testdqr $cpu sym 0100000 3 -32767; #
+rw11::div_testdqr $cpu sym 0100000 4 0; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 4 -1; #
+rw11::div_testdqr $cpu sym 0100000 4 -32767; #
+rw11::div_testdqr $cpu sym 0100000 6 0; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 32762 0; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 32764 0; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 32765 0; #
+rw11::div_testdqr $cpu sym 0100000 32766 0; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 32766 -1; #
+rw11::div_testdqr $cpu sym 0100000 32766 -32767; #
+rw11::div_testdqr $cpu sym 0100000 32767 0; #
+rw11::div_testdqr $cpu sym 0100000 32767 -1; #
+rw11::div_testdqr $cpu sym 0100000 32767 -32767; #
+rlc log " case dd>0, q<0"
+rw11::div_testdqr $cpu sym 0100000 -1 0; #
+rw11::div_testdqr $cpu sym 0100000 -1 1; #
+rw11::div_testdqr $cpu sym 0100000 -1 32767; #
+rw11::div_testdqr $cpu sym 0100000 -2 0; #
+rw11::div_testdqr $cpu sym 0100000 -2 1; #
+rw11::div_testdqr $cpu sym 0100000 -2 32767; #
+rw11::div_testdqr $cpu sym 0100000 -32767 0; #
+rw11::div_testdqr $cpu sym 0100000 -32767 1; #
+rw11::div_testdqr $cpu sym 0100000 -32767 32767; #
+rw11::div_testdqr $cpu sym 0100000 -32768 0; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 -32768 1; # BAD-R4
+rw11::div_testdqr $cpu sym 0100000 -32768 32767; # BAD-R4
+#
+#
+rlc log " test dr=077777 boundary cases (dr = max pos value)"
+rlc log " case dd>0, q>0"
+rw11::div_testdqr $cpu sym 077777 1 0; #
+rw11::div_testdqr $cpu sym 077777 1 1; #
+rw11::div_testdqr $cpu sym 077777 1 32766; #
+rw11::div_testdqr $cpu sym 077777 2 0; #
+rw11::div_testdqr $cpu sym 077777 2 1; #
+rw11::div_testdqr $cpu sym 077777 2 32766; #
+rw11::div_testdqr $cpu sym 077777 32766 0; #
+rw11::div_testdqr $cpu sym 077777 32766 1; #
+rw11::div_testdqr $cpu sym 077777 32766 32766; #
+rw11::div_testdqr $cpu sym 077777 32767 0; #
+rw11::div_testdqr $cpu sym 077777 32767 1; #
+rw11::div_testdqr $cpu sym 077777 32767 32766; #
+rlc log " case dd<0, q<0"
+rw11::div_testdqr $cpu sym 077777 -1 0; #
+rw11::div_testdqr $cpu sym 077777 -1 -1; #
+rw11::div_testdqr $cpu sym 077777 -1 -32766; #
+rw11::div_testdqr $cpu sym 077777 -2 0; #
+rw11::div_testdqr $cpu sym 077777 -2 -1; #
+rw11::div_testdqr $cpu sym 077777 -2 -32766; #
+rw11::div_testdqr $cpu sym 077777 -32767 0; #
+rw11::div_testdqr $cpu sym 077777 -32767 -1; #
+rw11::div_testdqr $cpu sym 077777 -32767 -32766; #
+rw11::div_testdqr $cpu sym 077777 -32768 0; # BAD-R4
+rw11::div_testdqr $cpu sym 077777 -32768 -1; # BAD-R4
+rw11::div_testdqr $cpu sym 077777 -32768 -32766; # BAD-R4
+#
+#
+rlc log " test dd max cases"
+rlc log " case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591"
+rw11::div_testdqr $cpu sym -32768 -32768 -1; #
+rw11::div_testdqr $cpu sym -32768 -32768 0; # BAD-R4
+rw11::div_testdqr $cpu sym -32768 -32768 1; # BAD-R4
+rw11::div_testdqr $cpu sym -32768 -32768 32766; # BAD-R4
+rw11::div_testdqr $cpu sym -32768 -32768 32767; # c.c BAD-R4
+rw11::div_testdqr $cpu sym -32768 -32768 32768; # v=1
+rw11::div_testdqr $cpu sym -32768 -32768 32769; # v=1
+rlc log " case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055"
+rw11::div_testdqr $cpu sym 32767 32767 -1; #
+rw11::div_testdqr $cpu sym 32767 32767 0; #
+rw11::div_testdqr $cpu sym 32767 32767 1; #
+rw11::div_testdqr $cpu sym 32767 32767 32765; #
+rw11::div_testdqr $cpu sym 32767 32767 32766; # c.c
+rw11::div_testdqr $cpu sym 32767 32767 32767; # v=1
+rw11::div_testdqr $cpu sym 32767 32767 32768; # v=1
+rlc log " case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822"
+rw11::div_testdqr $cpu sym 32767 -32768 1; #
+rw11::div_testdqr $cpu sym 32767 -32768 0; # BAD-R4
+rw11::div_testdqr $cpu sym 32767 -32768 -1; # BAD-R4
+rw11::div_testdqr $cpu sym 32767 -32768 -32765; # BAD-R4
+rw11::div_testdqr $cpu sym 32767 -32768 -32766; # c.c BAD-R4
+rw11::div_testdqr $cpu sym 32767 -32768 -32767; # v=1
+rw11::div_testdqr $cpu sym 32767 -32768 -32768; # v=1
+rlc log " case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823"
+rw11::div_testdqr $cpu sym -32768 32767 1; #
+rw11::div_testdqr $cpu sym -32768 32767 0; #
+rw11::div_testdqr $cpu sym -32768 32767 -1; #
+rw11::div_testdqr $cpu sym -32768 32767 -32766; #
+rw11::div_testdqr $cpu sym -32768 32767 -32767; # c.c
+rw11::div_testdqr $cpu sym -32768 32767 -32768; # v=1
+rw11::div_testdqr $cpu sym -32768 32767 -32769; # v=1
+#
+#
+rlc log " test late div quit cases in 2 quadrant algorithm"
+# dd dr q r n z v c
+rw11::div_testd2 $cpu sym -32767 -1 32767 0 0 0 0 0; #
+rw11::div_testd2 $cpu sym -32768 -1 0 0 0 0 1 0; #
+rw11::div_testd2 $cpu sym -32769 -1 0 0 0 0 1 0; #
+#
+rw11::div_testd2 $cpu sym -65534 -2 32767 0 0 0 0 0; #
+rw11::div_testd2 $cpu sym -65535 -2 32767 -1 0 0 0 0; #
+rw11::div_testd2 $cpu sym -65536 -2 0 0 0 0 1 0; #
+rw11::div_testd2 $cpu sym -65537 -2 0 0 0 0 1 0; #
+#
+#
+rlc log " test big divident overflow cases"
+# dd dr q r n z v c
+rw11::div_testd2 $cpu sym 0x7fffffff 1 0 0 0 0 1 0; #
+rw11::div_testd2 $cpu sym 0x7fffffff 2 0 0 0 0 1 0; #
+rw11::div_testd2 $cpu sym 0x7fffffff -1 0 0 1 0 1 0; #
+rw11::div_testd2 $cpu sym 0x7fffffff -2 0 0 1 0 1 0; #
+rw11::div_testd2 $cpu sym 0x80000000 1 0 0 1 0 1 0; #
+rw11::div_testd2 $cpu sym 0x80000000 2 0 0 1 0 1 0; #
+rw11::div_testd2 $cpu sym 0x80000000 -1 0 0 0 0 1 0; #
+rw11::div_testd2 $cpu sym 0x80000000 -2 0 0 0 0 1 0; #
Index: w11a/test_w11a_dsta_flow.tcl
===================================================================
--- w11a/test_w11a_dsta_flow.tcl (nonexistent)
+++ w11a/test_w11a_dsta_flow.tcl (revision 33)
@@ -0,0 +1,147 @@
+# $Id: test_w11a_dsta_flow.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013-2014 by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
+# 2014-03-01 552 1.0.1 use stack:; check sp;
+# 2013-03-31 502 1.0 Initial version
+#
+# Test dsta flow with jsr pc,... instructions
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_w11a_dsta_flow: test dsta flow with jsr pc,..."
+rlc log " (r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=1,2,3,4,5)"
+
+# code register pre/post conditions beyond defaults
+# r0 #sub00 -> ..same
+# r1 #sub10 -> #sub10+2
+# r2 #psub2 -> #psub2+4
+# r3 #sub30+2 -> #sub30
+# r4 #psub4e -> #psub4
+# r5 #data -> #data+7*2*2
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+stack:
+start: jsr pc,(r0)
+100$: jsr pc,(r1)+
+110$: jsr pc,@(r2)+
+120$: jsr pc,@(r2)+
+121$: jsr pc,-(r3)
+130$: jsr pc,@-(r4)
+140$: jsr pc,@-(r4)
+141$: halt
+stop:
+;
+psub2: .word sub20, sub21
+psub4: .word sub41, sub40
+psub4e:
+sub00: mov #100,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub10: mov #110,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub20: mov #120,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub21: mov #121,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub30: mov #130,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub40: mov #140,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub41: mov #141,(r5)+
+ mov (sp),(r5)+
+ rts pc
+data: .blkw 2*7.
+ .word 177777
+}
+
+rw11::asmrun $cpu sym [list r0 $sym(sub00) \
+ r1 $sym(sub10) \
+ r2 $sym(psub2) \
+ r3 [expr {$sym(sub30)+2}] \
+ r4 $sym(psub4e) \
+ r5 $sym(data) ]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 $sym(sub00) \
+ r1 [expr {$sym(sub10)+2}] \
+ r2 [expr {$sym(psub2)+4}] \
+ r3 $sym(sub30) \
+ r4 $sym(psub4) \
+ r5 [expr {$sym(data) + 7*2*2}] \
+ sp $sym(stack) ]
+rw11::asmtmem $cpu $sym(data) [list \
+ 0100 $sym(start:100$) \
+ 0110 $sym(start:110$) \
+ 0120 $sym(start:120$) \
+ 0121 $sym(start:121$) \
+ 0130 $sym(start:130$) \
+ 0140 $sym(start:140$) \
+ 0141 $sym(start:141$) \
+ 0177777 ]
+
+# ----------------------------------------------------------------------------
+rlc log " nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
+
+# code register pre/post conditions beyond defaults
+# r0 #sub00-020 -> ..same
+# r1 #psub10-040 -> ..same
+# r5 #data -> #data+5*2*2
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+stack:
+start: jsr pc,20(r0)
+1100$: jsr pc,@40(r1)
+1110$: jsr pc,sub20
+1120$: jsr pc,@psub30
+1130$: jsr pc,@#sub40
+1140$: halt
+stop:
+;
+psub10: .word sub10
+psub30: .word sub30
+sub00: mov #1100,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub10: mov #1110,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub20: mov #1120,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub30: mov #1130,(r5)+
+ mov (sp),(r5)+
+ rts pc
+sub40: mov #1140,(r5)+
+ mov (sp),(r5)+
+ rts pc
+data: .blkw 2*5.
+ .word 177777
+}
+
+rw11::asmrun $cpu sym [list r0 [expr {$sym(sub00)-020}] \
+ r1 [expr {$sym(psub10)-040}] \
+ r5 $sym(data) ]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 [expr {$sym(sub00)-020}] \
+ r1 [expr {$sym(psub10)-040}] \
+ r2 0 \
+ r3 0 \
+ r4 0 \
+ r5 [expr {$sym(data) + 5*2*2}] \
+ sp $sym(stack) ]
+rw11::asmtmem $cpu $sym(data) [list \
+ 01100 $sym(start:1100$) \
+ 01110 $sym(start:1110$) \
+ 01120 $sym(start:1120$) \
+ 01130 $sym(start:1130$) \
+ 01140 $sym(start:1140$) \
+ 0177777 ]
Index: w11a/test_w11a_dstw_word_flow.tcl
===================================================================
--- w11a/test_w11a_dstw_word_flow.tcl (nonexistent)
+++ w11a/test_w11a_dstw_word_flow.tcl (revision 33)
@@ -0,0 +1,102 @@
+# $Id: test_w11a_dstw_word_flow.tcl 683 2015-05-17 21:54:35Z mueller $
+#
+# Copyright 2013-2014 by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
+# 2014-03-01 552 1.0.1 check that unused regs stay 0
+# 2013-03-31 502 1.0 Initial version
+#
+# Test dstw flow with mov #nnn,... instructions for word access
+#
+
+# ----------------------------------------------------------------------------
+rlc log "test_w11a_dstw_word_flow: test dstw flow for word with mov #nnn,..."
+rlc log " r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5)"
+
+# code register pre/post conditions beyond defaults
+# r0 -> 0100
+# r1 #data1 -> ..same
+# r2 #data2 -> #data2+4
+# r3 #pdata3 -> #pdata3+4
+# r4 #data4e -> #data4e-4
+# r5 #pdat5e -> #pdat5e-4
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: mov #100,r0
+ mov #110,(r1)
+ mov #120,(r2)+
+ mov #121,(r2)+
+ mov #130,@(r3)+
+ mov #131,@(r3)+
+ mov #141,-(r4)
+ mov #140,-(r4)
+ mov #151,@-(r5)
+ mov #150,@-(r5)
+ halt
+stop:
+;
+data1: .word 0
+data2: .word 0,0
+data3: .word 0,0
+data4: .word 0,0
+data4e:
+data5: .word 0,0
+data5e:
+pdata3: .word data3,data3+2
+pdata5: .word data5,data5+2
+pdat5e:
+}
+
+rw11::asmrun $cpu sym [list r1 $sym(data1) \
+ r2 $sym(data2) \
+ r3 $sym(pdata3) \
+ r4 $sym(data4e) \
+ r5 $sym(pdat5e) ]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 0100 \
+ r1 $sym(data1) \
+ r2 [expr {$sym(data2) + 4}] \
+ r3 [expr {$sym(pdata3) + 4}] \
+ r4 [expr {$sym(data4e) - 4}] \
+ r5 [expr {$sym(pdat5e) - 4}] ]
+rw11::asmtmem $cpu $sym(data1) {0110 0120 0121 0130 0131 0140 0141 0150 0151}
+
+# ----------------------------------------------------------------------------
+rlc log " nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
+
+# code register pre/post conditions beyond defaults
+# r0 #data0-020 -> ..same
+# r1 #pdata0-040 -> ..same
+$cpu ldasm -lst lst -sym sym {
+ . = 1000
+start: mov #200,20(r0)
+ mov #210,@40(r1)
+ mov #220,data2
+ mov #230,@pdata3
+ mov #240,@#data4
+ halt
+stop:
+;
+data0: .word 0
+data1: .word 0
+data2: .word 0
+data3: .word 0
+data4: .word 0
+data4e:
+pdata1: .word data1
+pdata3: .word data3
+}
+
+rw11::asmrun $cpu sym [list r0 [expr {$sym(data0)-020}] \
+ r1 [expr {$sym(pdata1)-040}] ]
+rw11::asmwait $cpu sym
+rw11::asmtreg $cpu [list r0 [expr {$sym(data0)-020}] \
+ r1 [expr {$sym(pdata1)-040}] \
+ r2 0 \
+ r3 0 \
+ r4 0 \
+ r5 0 ]
+rw11::asmtmem $cpu $sym(data0) {0200 0210 0220 0230 0240}
Index: w11a
===================================================================
--- w11a (nonexistent)
+++ w11a (revision 33)
w11a
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log
Index: dev_all.dat
===================================================================
--- dev_all.dat (nonexistent)
+++ dev_all.dat (revision 33)
@@ -0,0 +1,7 @@
+# $Id: dev_all.dat 687 2015-06-05 09:03:34Z mueller $
+#
+## steering file for all devices tests
+#
+@rhrp/rhrp_all.dat
+@tm11/tm11_all.dat
+#
Index: .
===================================================================
--- . (nonexistent)
+++ . (revision 33)
.
Property changes :
Added: svn:ignore
## -0,0 +1,33 ##
+*.dep_ghdl
+*.dep_isim
+*.dep_xst
+work-obj93.cf
+*.vcd
+*.ghw
+*.sav
+*.tmp
+*.exe
+ise
+xflow.his
+*.ngc
+*.ncd
+*.pcf
+*.bit
+*.msk
+isim
+isim.log
+isim.wdb
+fuse.log
+*_[sft]sim.vhd
+*_tsim.sdf
+*_xst.log
+*_tra.log
+*_twr.log
+*_map.log
+*_par.log
+*_tsi.log
+*_pad.log
+*_bgn.log
+*_svn.log
+*_sum.log
+*_[dsft]sim.log