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    /w11/tags/w11a_V0.74/rtl/bplib/sysmon
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Rev 37 → Rev 38

/sysmon_rbus_core.vhd
0,0 → 1,374
-- $Id: sysmon_rbus_core.vhd 784 2016-07-09 22:17:01Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sysmon_rbus_core - syn
-- Description: SYSMON interface to rbus (generic)
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic (all with SYSMON or XADC)
-- Tool versions: viv 2015.4-2016.1; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-25 767 1.0.1 don't init N_REGS (vivado fix for fsm inference)
-- BUGFIX: use s_init in regs_init (was s_idle)
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
-- - in general 1-to-1 mapping to sysmon/xadc address space
-- --> see function in sysmon/xadc user guide
-- - 8 addresses are implemented on the controller (base is ibase, default x"78")
-- --> see function below
--
-- Addr Bits Name r/w/f Function
-- 000 cntl -/-/f cntl
-- 15 reset -/-/f reset SYSMON
-- 001 stat r/w/- stat
-- 3 jlock r/c/- JTAGLOCKED seen
-- 2 jmod r/c/- JTAGMODIFIED seen
-- 1 jbusy r/c/- JTAGBUSY seen
-- 0 ot r/c/- OT seen
-- 010 almh r/w/- alm history
-- *:00 alm r/c/- ALM(*:0) seen
-- 011 -/-/- <unused>
-- 100 temp r/-/- current temp value
-- 101 alm r/-/- current alm value
-- *:00 alm r/-/- alm(*:0)
-- 110 -/-/- <unused>
-- 111 eos r/-/- eos counter
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
 
-- ----------------------------------------------------------------------------
 
entity sysmon_rbus_core is -- SYSMON interface to rbus
generic (
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SM_DEN : out slbit; -- sysmon: drp enable
SM_DWE : out slbit; -- sysmon: drp write enable
SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address
SM_DI : out slv16; -- sysmon: data input
SM_DO : in slv16; -- sysmon: data output
SM_DRDY : in slbit; -- sysmon: data ready
SM_EOS : in slbit; -- sysmon: end of scan
SM_RESET : out slbit; -- sysmon: reset
SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms
SM_OT : in slbit; -- sysmon: overtemperature
SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY
SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED
SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED
TEMP : out slv(TEWIDTH-1 downto 0) -- die temp
);
end sysmon_rbus_core;
 
architecture syn of sysmon_rbus_core is
type state_type is (
s_init, -- init: wait for jtaglocked down
s_idle, -- idle: dispatch
s_wait, -- wait: wait on drdy
s_twait -- twait: wait on drdy of temp read
);
 
type regs_type is record
rbsel : slbit; -- rbus select
state : state_type; -- state
eoscnt : slv16; -- eos counter
stat_ot : slbit; -- stat: ot
stat_jlock : slbit; -- stat: jtag locked
stat_jmod : slbit; -- stat: jtag modified
stat_jbusy : slbit; -- stat: jtag busy
almh : slv(ALWIDTH-1 downto 0); -- almh
temp : slv(TEWIDTH-1 downto 0); -- temp value
tpend : slbit; -- temp pending
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- rbsel
s_init, -- state
(others=>'0'), -- eoscnt
'0','0','0','0', -- stat_ot, stat_j*
slv(to_unsigned(0,ALWIDTH)), -- almh
slv(to_unsigned(0,TEWIDTH)), -- temp
'0' -- tpend
);
 
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
 
-- only internal regs have names, only 3 LSB in constant
constant rbaddr_cntl: slv3 := "000"; -- 0 -/-/f
constant rbaddr_stat: slv3 := "001"; -- 1 r/w/-
constant rbaddr_almh: slv3 := "010"; -- 2 r/w/-
constant rbaddr_temp: slv3 := "100"; -- 4 r/-/-
constant rbaddr_alm: slv3 := "101"; -- 5 r/-/-
constant rbaddr_eos: slv3 := "111"; -- 7 r/-/-
 
constant cntl_rbf_reset: integer := 15;
 
constant stat_rbf_jlock: integer := 3;
constant stat_rbf_jmod: integer := 2;
constant stat_rbf_jbusy: integer := 1;
constant stat_rbf_ot: integer := 0;
 
begin
 
assert DAWIDTH=7 or DAWIDTH=8
report "assert(DAWIDTH=7 or DAWIDTH=8): unsupported DAWIDTH"
severity failure;
assert ALWIDTH<=16
report "assert ALWIDTH<16: unsupported ALWIDTH"
severity failure;
assert TEWIDTH=10 or TEWIDTH=12
report "assert(TEWIDTH=10 or TEWIDTH=12): unsupported TEWIDTH"
severity failure;
assert IBASE(2 downto 0) = "000"
report "assert IBASE(2:0) = 000: invalid IBASE"
severity failure;
 
proc_regs: process (CLK)
begin
 
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
 
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, SM_DO, SM_DRDY, SM_EOS, SM_ALM, SM_OT,
SM_JTAGLOCKED, SM_JTAGMODIFIED, SM_JTAGBUSY)
 
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
 
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
 
variable irb_addr_ext : slbit := '0';
variable irb_addr_int : slbit := '0';
 
variable ism_den : slbit := '0';
variable ism_dwe : slbit := '0';
variable ism_daddr : slv(DAWIDTH-1 downto 0) := (others=>'0');
variable ism_reset : slbit := '0';
 
begin
 
r := R_REGS;
n := R_REGS;
 
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
 
irbena := RB_MREQ.re or RB_MREQ.we;
 
-- check for internal rbus controler register window
irb_addr_int := '0';
if RB_MREQ.addr(DAWIDTH-1 downto 3) = IBASE(DAWIDTH-1 downto 3) then
irb_addr_int := '1';
end if;
ism_den := '0';
ism_dwe := '0';
ism_daddr := RB_MREQ.addr(DAWIDTH-1 downto 0); -- default
ism_reset := '0';
-- handle EOS
if SM_EOS = '1' then
n.tpend := '1'; -- queue temp read
n.eoscnt := slv(unsigned(r.eoscnt) + 1); -- and count it
end if;
 
-- update stat and almh register fields
n.stat_ot := r.stat_ot or SM_OT;
n.stat_jlock := r.stat_jlock or SM_JTAGLOCKED;
n.stat_jmod := r.stat_jmod or SM_JTAGMODIFIED;
n.stat_jbusy := r.stat_jbusy or SM_JTAGBUSY;
n.almh := r.almh or SM_ALM;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 7)=RB_ADDR(15 downto 7) then
n.rbsel := '1';
end if;
irb_ack := r.rbsel and irbena; -- ack all accesses
irb_busy := irb_ack; -- busy is default
-- internal state machine
case r.state is
when s_init => -- init: wait for jtaglocked down ----
if SM_JTAGLOCKED = '0' then
n.stat_jlock := '0'; -- clear status
n.state := s_idle; -- start working
end if;
when s_idle => -- idle: dispatch --------------------
if r.tpend = '1' then -- temp update pending ?
n.tpend := '0'; -- mark done
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := "0000000"; -- temp is reg 00h
ism_dwe := '0'; -- do read
ism_den := '1'; -- start drp cycle
n.state := s_twait;
end if;
elsif r.rbsel = '1' then -- rbus access ?
if irb_addr_int ='1' then -- internal controller regs
irb_busy := '0';
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
ism_reset := RB_MREQ.din(cntl_rbf_reset);
end if;
 
when rbaddr_stat =>
if RB_MREQ.we = '1' then
n.stat_jlock := r.stat_jlock and
not RB_MREQ.din(stat_rbf_jlock);
n.stat_jmod := r.stat_jmod and
not RB_MREQ.din(stat_rbf_jmod);
n.stat_jbusy := r.stat_jbusy and
not RB_MREQ.din(stat_rbf_jbusy);
n.stat_ot := r.stat_ot and
not RB_MREQ.din(stat_rbf_ot);
end if;
 
when rbaddr_almh =>
if RB_MREQ.we = '1' then
n.almh := r.almh and not RB_MREQ.din(r.almh'range);
end if;
 
when rbaddr_temp =>
irb_err := RB_MREQ.we;
when rbaddr_alm =>
irb_err := RB_MREQ.we;
when rbaddr_eos =>
irb_err := RB_MREQ.we;
 
when others =>
irb_err := irbena;
end case;
else -- sysmon reg access
if irbena = '1' then
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := RB_MREQ.addr(ism_daddr'range);
ism_dwe := RB_MREQ.we;
ism_den := '1'; -- start drp cycle
n.state := s_wait;
else
irb_err := '1'; -- quit with error if jlocked
end if;
end if;
 
end if;
end if;
 
when s_wait => -- wait: wait on drdy ----------------
n.state := s_wait;
if SM_DRDY = '1' then
irb_busy := '0';
n.state := s_idle;
end if;
when s_twait => -- twait: wait on drdy of temp read --
n.state := s_twait;
if SM_DRDY = '1' then
n.temp := SM_DO(15 downto 16-TEWIDTH); -- take msb's
n.state := s_idle;
end if;
when others => null; -- <> ------------------------------
end case; -- case r.state
 
-- rbus output driver
if r.rbsel = '1' then
if irb_addr_int = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_jlock) := r.stat_jlock;
irb_dout(stat_rbf_jmod) := r.stat_jmod;
irb_dout(stat_rbf_jbusy) := r.stat_jbusy;
irb_dout(stat_rbf_ot) := r.stat_ot;
 
when rbaddr_almh =>
irb_dout(r.almh'range) := r.almh;
 
when rbaddr_temp =>
irb_dout(r.temp'range) := r.temp;
 
when rbaddr_alm =>
irb_dout(SM_ALM'range) := SM_ALM;
 
when rbaddr_eos =>
irb_dout := r.eoscnt;
 
when others =>
irb_dout := (others=>'0');
end case;
else
irb_dout := SM_DO;
end if;
end if;
 
N_REGS <= n;
 
SM_DEN <= ism_den;
SM_DWE <= ism_dwe;
SM_DADDR <= ism_daddr;
SM_DI <= RB_MREQ.din;
SM_RESET <= ism_reset;
 
TEMP <= r.temp;
 
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
 
end process proc_next;
 
end syn;
/sysmonrbuslib.vhd
0,0 → 1,214
-- $Id: sysmonrbuslib.vhd 770 2016-05-28 14:15:00Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sysmonrbuslib
-- Description: generic (all with SYSMON or XADC)
--
-- Dependencies: -
-- Tool versions: viv2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-05-28 770 1.0.1 ensure to_unsigned() has a type natural argument
-- 2016-03-13 742 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.slvtypes.all;
use work.rblib.all;
 
package sysmonrbuslib is
 
subtype bv is bit_vector; -- vector
subtype bv16 is bit_vector(15 downto 0); -- 16 bit word
-- config reg #0 fields as bit masks (to be or'ed)
constant xadc_conf0_cavg: bv16 := x"8000"; -- 15 dis calib avr
constant xadc_conf0_avg_off: bv16 := x"0000"; -- 13:12 avr mode: off
constant xadc_conf0_avg_16: bv16 := x"1000"; -- " avr mode: 16 samples
constant xadc_conf0_avg_64: bv16 := x"2000"; -- " avr mode: 64 samples
constant xadc_conf0_avg_256: bv16 := x"3000"; -- " avr mode: 256 samples
constant xadc_conf0_mux: bv16 := x"0800"; -- 11 ena ext mux
constant xadc_conf0_bu: bv16 := x"0400"; -- 10 ena bipolar
constant xadc_conf0_ec: bv16 := x"0200"; -- 9 ena event mode
constant xadc_conf0_acq: bv16 := x"0100"; -- 8 ena inc settle
-- bit 4:0 holds channel select, not used, only for single channel mode
 
-- config reg #1 fields as bit masks (to be or'ed)
constant xadc_conf1_seq_default: bv16 := x"0000"; -- 15:12 seq mode: default
constant xadc_conf1_seq_spass: bv16 := x"1000"; -- " seq mode: single pass
constant xadc_conf1_seq_cont: bv16 := x"2000"; -- " seq mode: continuous
constant xadc_conf1_seq_schan: bv16 := x"3000"; -- " seq mode: single chan
constant xadc_conf1_dis_alm6: bv16 := x"0800"; -- 11 dis alm(6)
constant xadc_conf1_dis_alm5: bv16 := x"0400"; -- 10 dis alm(5)
constant xadc_conf1_dis_alm4: bv16 := x"0200"; -- 9 dis alm(4)
constant xadc_conf1_dis_alm3: bv16 := x"0100"; -- 8 dis alm(3)
 
constant xadc_conf1_cal3_supog: bv16 := x"0080"; -- 7 ena sup off+gain
constant xadc_conf1_cal2_supo: bv16 := x"0040"; -- 6 ena sup off
constant xadc_conf1_cal1_adcog: bv16 := x"0020"; -- 5 ena adc off+gain
constant xadc_conf1_cal0_adco: bv16 := x"0010"; -- 4 ena adc off
 
constant xadc_conf1_dis_alm2: bv16 := x"0008"; -- 3 dis alm(2)
constant xadc_conf1_dis_alm1: bv16 := x"0004"; -- 2 dis alm(1)
constant xadc_conf1_dis_alm0: bv16 := x"0002"; -- 1 dis alm(0)
constant xadc_conf1_dis_ot: bv16 := x"0001"; -- 0 dis ot
 
-- bit numbers for sequence registers (even word for build-in channels)
constant xadc_select_vccbram: integer := 14;
constant xadc_select_vrefn: integer := 13;
constant xadc_select_vrefp: integer := 12;
constant xadc_select_vpvn: integer := 11;
constant xadc_select_vccaux: integer := 10;
constant xadc_select_vccint: integer := 9;
constant xadc_select_temp: integer := 8;
constant xadc_select_vccoddr: integer := 7;
constant xadc_select_vccpaux: integer := 6;
constant xadc_select_vccpint: integer := 5;
constant xadc_select_calib: integer := 0;
 
-- defaults for plain build-in power monitoring
constant xadc_init_40_default: bv16 := xadc_conf0_cavg or
xadc_conf0_avg_16;
 
constant xadc_init_41_default: bv16 := xadc_conf1_seq_cont or
xadc_conf1_dis_alm6 or
xadc_conf1_dis_alm5 or
xadc_conf1_dis_alm4 or
xadc_conf1_cal3_supog or
xadc_conf1_cal2_supo or
xadc_conf1_cal1_adcog or
xadc_conf1_cal0_adco;
 
constant xadc_init_48_default: bv16 := (xadc_select_vccbram => '1',
xadc_select_vccaux => '1',
xadc_select_vccint => '1',
xadc_select_temp => '1',
xadc_select_calib => '1',
others => '0');
 
-- OT limit and reset are in general hardwired to 125 and 70 deg
-- the 4 lsbs of reg 53 contain the 'automatic shutdown enable'
-- must be set to "0011' to enable. done by default, seems prudent
constant xadc_init_53_default: bv16 := x"ca33"; -- OT LIMIT (125) + OT ENABLE
constant xadc_init_57_default: bv16 := x"ae40"; -- OT RESET (70)
 
constant xadc_init_4a_default: bv16 := (others => '0');
 
pure function xadc_temp2alim(temp : real) return bv16;
pure function xadc_svolt2alim (volt : real) return bv16;
 
component sysmon_rbus_core is -- SYSMON interface to rbus
generic (
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SM_DEN : out slbit; -- sysmon: drp enable
SM_DWE : out slbit; -- sysmon: drp write enable
SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address
SM_DI : out slv16; -- sysmon: data input
SM_DO : in slv16; -- sysmon: data output
SM_DRDY : in slbit; -- sysmon: data ready
SM_EOS : in slbit; -- sysmon: end of scan
SM_RESET : out slbit; -- sysmon: reset
SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms
SM_OT : in slbit; -- sysmon: overtemperature
SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY
SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED
SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED
TEMP : out slv(TEWIDTH-1 downto 0) -- die temp
);
end component;
 
component sysmonx_rbus_base is -- XADC interface to rbus (basic monitor)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types)
INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12 -- xadc: die temp
);
end component;
 
component sysmonx_rbus_arty is -- XADC interface to rbus (arty pwrmon)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types)
INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12; -- xadc: die temp
VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon)
VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon)
);
end component;
 
end package sysmonrbuslib;
 
-- ----------------------------------------------------------------------------
package body sysmonrbuslib is
 
-- -------------------------------------
pure function xadc_temp2alim(temp : real) return bv16 is
variable ival : natural := 0;
begin
ival := natural(((temp + 273.14) * 16.0 * 4096.0) / 503.975);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_temp2alim;
 
-- -------------------------------------
pure function xadc_svolt2alim (volt : real) return bv16 is
variable ival : natural := 0;
begin
ival := natural((volt * 16.0 * 4096.0) / 3.0);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_svolt2alim;
 
 
end package body sysmonrbuslib;
/sysmon_rbus_core.vbom
0,0 → 1,7
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
sysmonrbuslib.vbom
# components
# design
sysmon_rbus_core.vhd
/Makefile
0,0 → 1,37
# $Id: Makefile 761 2016-04-17 08:53:48Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-04-15 761 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#
/tb/sysmon_stim_arty.dat
0,0 → 1,2
TIME TEMP VCCINT VCCAUX VCCBRAM VAUXP[1] VAUXN[1] VAUXP[2] VAUXN[2] VAUXP[9] VAUXN[9] VAUXP[10] VAUXN[10]
00000 25.0 0.95 1.80 0.95 0.840 0.000 0.000 0.000 0.062 0.000 0.050 0.000
/tb/sysmon_stim_n4.dat
0,0 → 1,2
TIME TEMP VCCINT VCCAUX VCCBRAM
00000 25.0 1.00 1.80 1.00
/tb
tb Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb Index: sysmonx_rbus_base.vhd =================================================================== --- sysmonx_rbus_base.vhd (nonexistent) +++ sysmonx_rbus_base.vhd (revision 38) @@ -0,0 +1,192 @@ +-- $Id: sysmonx_rbus_base.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sysmonx_rbus_base - syn +-- Description: 7series XADC interface to rbus (basic supply monitor version) +-- +-- Dependencies: sysmon_rbus_core +-- +-- Test bench: - +-- +-- Target Devices: 7series +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-13 742 1.0 Initial version +-- 2016-03-06 738 0.1 First draft +------------------------------------------------------------------------------ +-- +-- rbus registers: see sysmon_rbus_core and XADC user guide +-- +-- XADC usage: +-- - only build-in sensors: temp, Vccint, Vccaux, Vccbram +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; +use work.rblib.all; +use work.sysmonrbuslib.all; + +-- ---------------------------------------------------------------------------- + +entity sysmonx_rbus_base is -- XADC interface to rbus (basic monitor) + generic ( + INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade) + INIT_TEMP_LOW : real := 60.0; -- INIT_54 + INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types) + INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types) + INIT_VCCAUX_UP : real := 1.89; -- INIT_52 + INIT_VCCAUX_LOW : real := 1.71; -- INIT_56 + INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types) + INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types) + CLK_MHZ : integer := 250; -- clock frequency in MHz + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + ALM : out slv8; -- xadc: alarms + OT : out slbit; -- xadc: over temp + TEMP : out slv12 -- xadc: die temp + ); +end sysmonx_rbus_base; + +architecture syn of sysmonx_rbus_base is + + constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio + constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16))); + + signal SM_DEN : slbit := '0'; + signal SM_DWE : slbit := '0'; + signal SM_DADDR : slv7 := (others=>'0'); + signal SM_DI : slv16 := (others=>'0'); + signal SM_DO : slv16 := (others=>'0'); + signal SM_DRDY : slbit := '0'; + signal SM_EOS : slbit := '0'; + signal SM_EOC : slbit := '0'; + signal SM_RESET : slbit := '0'; + signal SM_CHAN : slv5 := (others=>'0'); + signal SM_ALM : slv8 := (others=>'0'); + signal SM_OT : slbit := '0'; + signal SM_JTAGLOCKED : slbit := '0'; + signal SM_JTAGMODIFIED : slbit := '0'; + signal SM_JTAGBUSY : slbit := '0'; + +begin + + SM : XADC + generic map ( + INIT_40 => xadc_init_40_default, -- conf #0 + INIT_41 => xadc_init_41_default, -- conf #1 + INIT_42 => init_42, + INIT_43 => x"0000", -- test #0 - don't use, stay 0 + INIT_44 => x"0000", -- test #1 - " + INIT_45 => x"0000", -- test #2 - " + INIT_46 => x"0000", -- test #3 - " + INIT_47 => x"0000", -- test #4 - " + INIT_48 => xadc_init_48_default, -- seq #0: sel 0 + INIT_49 => x"0000", -- seq #1: sel 1: no aux + INIT_4A => xadc_init_4a_default, -- seq #2: avr 0 + INIT_4B => x"0000", -- seq #3: avr 1: " + INIT_4C => x"0000", -- seq #4: mode 0: unipolar + INIT_4D => x"0000", -- seq #5: mode 1: " + INIT_4E => x"0000", -- seq #6: time 0: fast + INIT_4F => x"0000", -- seq #7: time 1: " + INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0) + INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1) + INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2) + INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT + INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0) + INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1) + INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2) + INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT + INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3) + INIT_59 => x"0000", -- alm #09: ccpint up (4) + INIT_5A => x"0000", -- alm #10: ccpaux up (5) + INIT_5B => x"0000", -- alm #11: ccdram up (6) + INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3) + INIT_5D => x"0000", -- alm #13: ccpint low (4) + INIT_5E => x"0000", -- alm #14: ccpaux low (5) + INIT_5F => x"0000", -- alm #15: ccdram low (6) +-- IS_CONVSTCLK_INVERTED => '0', +-- IS_DCLK_INVERTED => '0', + SIM_DEVICE => "7SERIES", + SIM_MONITOR_FILE => "sysmon_stim") + port map ( + DCLK => CLK, + DEN => SM_DEN, + DWE => SM_DWE, + DADDR => SM_DADDR, + DI => SM_DI, + DO => SM_DO, + DRDY => SM_DRDY, + EOC => SM_EOC, -- connected for tb usage + EOS => SM_EOS, + BUSY => open, + RESET => SM_RESET, + CHANNEL => SM_CHAN, -- connected for tb usage + MUXADDR => open, + ALM => SM_ALM, + OT => SM_OT, + CONVST => '0', + CONVSTCLK => '0', + JTAGBUSY => SM_JTAGBUSY, + JTAGLOCKED => SM_JTAGLOCKED, + JTAGMODIFIED => SM_JTAGMODIFIED, + VAUXN => (others=>'0'), + VAUXP => (others=>'0'), + VN => '0', + VP => '0' + ); + + SMRB : sysmon_rbus_core + generic map ( + DAWIDTH => 7, + ALWIDTH => 8, + TEWIDTH => 12, + IBASE => x"78", + RB_ADDR => RB_ADDR) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + SM_DEN => SM_DEN, + SM_DWE => SM_DWE, + SM_DADDR => SM_DADDR, + SM_DI => SM_DI, + SM_DO => SM_DO, + SM_DRDY => SM_DRDY, + SM_EOS => SM_EOS, + SM_RESET => SM_RESET, + SM_ALM => SM_ALM, + SM_OT => SM_OT, + SM_JTAGBUSY => SM_JTAGBUSY, + SM_JTAGLOCKED => SM_JTAGLOCKED, + SM_JTAGMODIFIED => SM_JTAGMODIFIED, + TEMP => TEMP + ); + + ALM <= SM_ALM; + OT <= SM_OT; + +end syn; Index: sysmonx_rbus_base.vbom =================================================================== --- sysmonx_rbus_base.vbom (nonexistent) +++ sysmonx_rbus_base.vbom (revision 38) @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +sysmonrbuslib.vbom +@lib:unisim +# components +sysmon_rbus_core.vbom +# design +sysmonx_rbus_base.vhd Index: sysmonx_rbus_arty.vhd =================================================================== --- sysmonx_rbus_arty.vhd (nonexistent) +++ sysmonx_rbus_arty.vhd (revision 38) @@ -0,0 +1,226 @@ +-- $Id: sysmonx_rbus_arty.vhd 742 2016-03-13 14:40:19Z mueller $ +-- +-- Copyright 2016- by Walter F.J. Mueller +-- +-- This program is free software; you may redistribute and/or modify it under +-- the terms of the GNU General Public License as published by the Free +-- Software Foundation, either version 2, or at your option any later version. +-- +-- This program is distributed in the hope that it will be useful, but +-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for complete details. +-- +------------------------------------------------------------------------------ +-- Module Name: sysmonx_rbus_arty - syn +-- Description: 7series XADC interface to rbus (arty pwrmon version) +-- +-- Dependencies: sysmon_rbus_core +-- +-- Test bench: - +-- +-- Target Devices: 7series +-- Tool versions: viv 2015.4; ghdl 0.33 +-- +-- Revision History: +-- Date Rev Version Comment +-- 2016-03-12 741 1.0 Initial version +-- 2016-03-06 738 0.1 First draft +------------------------------------------------------------------------------ +-- +-- rbus registers: see sysmon_rbus_core and XADC user guide +-- +-- XADC usage: +-- - build-in sensors: temp, Vccint, Vccaux, Vccbram +-- - arty power monitoring: +-- VAUX( 1) VPWR(0) <- 1/5.99 of JPR5V0 (main 5 V line) +-- VAUX( 2) VPWR(1) <- 1/16 of VU (external power jack) +-- VAUX( 9) VPWR(2) <- 250mV/A from shunt on JPR5V0 (main 5 V line) +-- VAUX(10) VPWR(3) <- 500mV/A from shunt on VCC0V95 (FPGA core) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.ALL; + +use work.slvtypes.all; +use work.rblib.all; +use work.sysmonrbuslib.all; + +-- ---------------------------------------------------------------------------- + +entity sysmonx_rbus_arty is -- XADC interface to rbus (for arty) + generic ( + INIT_OT_LIMIT : real := 125.0; -- INIT_53 + INIT_OT_RESET : real := 70.0; -- INIT_57 + INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade) + INIT_TEMP_LOW : real := 60.0; -- INIT_54 + INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types) + INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types) + INIT_VCCAUX_UP : real := 1.89; -- INIT_52 + INIT_VCCAUX_LOW : real := 1.71; -- INIT_56 + INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types) + INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types) + CLK_MHZ : integer := 250; -- clock frequency in MHz + RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16))); + port ( + CLK : in slbit; -- clock + RESET : in slbit := '0'; -- reset + RB_MREQ : in rb_mreq_type; -- rbus: request + RB_SRES : out rb_sres_type; -- rbus: response + ALM : out slv8; -- xadc: alarms + OT : out slbit; -- xadc: over temp + TEMP : out slv12; -- xadc: die temp + VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon) + VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon) + ); +end sysmonx_rbus_arty; + +architecture syn of sysmonx_rbus_arty is + + constant vpwrmap_0 : integer := 1; -- map vpwr(0) -> xadc vaux + constant vpwrmap_1 : integer := 2; -- map vpwr(1) -> xadc vaux + constant vpwrmap_2 : integer := 9; -- map vpwr(2) -> xadc vaux + constant vpwrmap_3 : integer := 10; -- map vpwr(3) -> xadc vaux + + constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio + constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16))); + + constant init_49 : bv16 := (vpwrmap_0 => '1', -- seq #1: (enable pwrmon) + vpwrmap_1 => '1', + vpwrmap_2 => '1', + vpwrmap_3 => '1', + others => '0'); + + signal VAUXN : slv16 := (others=>'0'); + signal VAUXP : slv16 := (others=>'0'); + + signal SM_DEN : slbit := '0'; + signal SM_DWE : slbit := '0'; + signal SM_DADDR : slv7 := (others=>'0'); + signal SM_DI : slv16 := (others=>'0'); + signal SM_DO : slv16 := (others=>'0'); + signal SM_DRDY : slbit := '0'; + signal SM_EOS : slbit := '0'; + signal SM_EOC : slbit := '0'; + signal SM_RESET : slbit := '0'; + signal SM_CHAN : slv5 := (others=>'0'); + signal SM_ALM : slv8 := (others=>'0'); + signal SM_OT : slbit := '0'; + signal SM_JTAGLOCKED : slbit := '0'; + signal SM_JTAGMODIFIED : slbit := '0'; + signal SM_JTAGBUSY : slbit := '0'; + +begin + + SM : XADC + generic map ( + INIT_40 => xadc_init_40_default, -- conf #0 + INIT_41 => xadc_init_41_default, -- conf #1 + INIT_42 => init_42, + INIT_43 => x"0000", -- test #0 - don't use, stay 0 + INIT_44 => x"0000", -- test #1 - " + INIT_45 => x"0000", -- test #2 - " + INIT_46 => x"0000", -- test #3 - " + INIT_47 => x"0000", -- test #4 - " + INIT_48 => xadc_init_48_default, -- seq #0: sel 0 + INIT_49 => init_49, -- seq #1: sel 1 (enable pwrmon) + INIT_4A => xadc_init_4a_default, -- seq #2: avr 0 + INIT_4B => x"0000", -- seq #3: avr 1: " + INIT_4C => x"0000", -- seq #4: mode 0: unipolar + INIT_4D => x"0000", -- seq #5: mode 1: " + INIT_4E => x"0000", -- seq #6: time 0: fast + INIT_4F => x"0000", -- seq #7: time 1: " + INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0) + INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1) + INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2) + INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT + INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0) + INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1) + INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2) + INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT + INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3) + INIT_59 => x"0000", -- alm #09: ccpint up (4) + INIT_5A => x"0000", -- alm #10: ccpaux up (5) + INIT_5B => x"0000", -- alm #11: ccdram up (6) + INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3) + INIT_5D => x"0000", -- alm #13: ccpint low (4) + INIT_5E => x"0000", -- alm #14: ccpaux low (5) + INIT_5F => x"0000", -- alm #15: ccdram low (6) +-- IS_CONVSTCLK_INVERTED => '0', +-- IS_DCLK_INVERTED => '0', + SIM_DEVICE => "7SERIES", + SIM_MONITOR_FILE => "sysmon_stim") + port map ( + DCLK => CLK, + DEN => SM_DEN, + DWE => SM_DWE, + DADDR => SM_DADDR, + DI => SM_DI, + DO => SM_DO, + DRDY => SM_DRDY, + EOC => SM_EOC, -- connected for tb usage + EOS => SM_EOS, + BUSY => open, + RESET => SM_RESET, + CHANNEL => SM_CHAN, -- connected for tb usage + MUXADDR => open, + ALM => SM_ALM, + OT => SM_OT, + CONVST => '0', + CONVSTCLK => '0', + JTAGBUSY => SM_JTAGBUSY, + JTAGLOCKED => SM_JTAGLOCKED, + JTAGMODIFIED => SM_JTAGMODIFIED, + VAUXN => VAUXN, + VAUXP => VAUXP, + VN => '0', + VP => '0' + ); + + VAUXN <= (vpwrmap_0 => VPWRN(0), + vpwrmap_1 => VPWRN(1), + vpwrmap_2 => VPWRN(2), + vpwrmap_3 => VPWRN(3), + others=>'0'); + VAUXP <= (vpwrmap_0 => VPWRP(0), + vpwrmap_1 => VPWRP(1), + vpwrmap_2 => VPWRP(2), + vpwrmap_3 => VPWRP(3), + others=>'0'); + + SMRB : sysmon_rbus_core + generic map ( + DAWIDTH => 7, + ALWIDTH => 8, + TEWIDTH => 12, + IBASE => x"78", + RB_ADDR => RB_ADDR) + port map ( + CLK => CLK, + RESET => RESET, + RB_MREQ => RB_MREQ, + RB_SRES => RB_SRES, + SM_DEN => SM_DEN, + SM_DWE => SM_DWE, + SM_DADDR => SM_DADDR, + SM_DI => SM_DI, + SM_DO => SM_DO, + SM_DRDY => SM_DRDY, + SM_EOS => SM_EOS, + SM_RESET => SM_RESET, + SM_ALM => SM_ALM, + SM_OT => SM_OT, + SM_JTAGBUSY => SM_JTAGBUSY, + SM_JTAGLOCKED => SM_JTAGLOCKED, + SM_JTAGMODIFIED => SM_JTAGMODIFIED, + TEMP => TEMP + ); + + ALM <= SM_ALM; + OT <= SM_OT; + +end syn; Index: sysmonx_rbus_arty.vbom =================================================================== --- sysmonx_rbus_arty.vbom (nonexistent) +++ sysmonx_rbus_arty.vbom (revision 38) @@ -0,0 +1,9 @@ +# libs +../../vlib/slvtypes.vhd +../../vlib/rbus/rblib.vhd +sysmonrbuslib.vbom +@lib:unisim +# components +sysmon_rbus_core.vbom +# design +sysmonx_rbus_arty.vhd Index: sysmonrbuslib.vbom =================================================================== --- sysmonrbuslib.vbom (nonexistent) +++ sysmonrbuslib.vbom (revision 38) @@ -0,0 +1,3 @@ +# libs +../../vlib/slvtypes.vhd +sysmonrbuslib.vhd Index: . =================================================================== --- . (nonexistent) +++ . (revision 38)
. Property changes : Added: svn:ignore ## -0,0 +1,42 ## +*.gz +*.tar +*.tgz +*.dep_* +work-obj93.cf +*.vcd +*.ghw +*.sav +*.tmp +*.exe +ise +xflow.his +*.ngc +*.ncd +*.pcf +*.bit +*.msk +*.svf +*.log +isim +*_[sfot]sim.vhd +*_tsim.sdf +rlink_cext_fifo_[rt]x +rlink_cext_conf +tmu_ofile +*.dsk +*.tap +*.lst +*.cof +.Xil +project_mflow +xsim.dir +webtalk_* +*_[sfot]sim +*_[IX]Sim +*_[IX]Sim_[sfot]sim +*.dcp +*.jou +*.pb +*.prj +*.rpt +*.wdb

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