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/trunk/rtl/vlib/rri/tb/rritblib.vhd.bak File deleted
/trunk/doc/w11a_os_guide.txt
0,0 → 1,158
# $ $Id: w11a_os_guide.txt 316 2010-07-16 19:07:47Z mueller $
 
1. I/O emulation setup ----------------------------------------------------
 
All UNIBUS peripherals which exchange data (currently DL11, LP11, PC11, RK11)
are currently emulated via a backend process. In the current version the
communication between FPGA board and backend is via the serial port, either
directly or via a USB-RS232 adapter. A direct connection is limited to 115k
Baud on most PCs, while a connection via a USB-RS232 adapter was tested up
to 460k Baud.
 
Notes: - A USB-RS232 cable with a Prolific Technology PL2303 chip simply
never gave reliable connections for higher Baud rates.
- A USB-RS232 cable with a FTDI FT232R chip, like the cable offered
by FTDI as US232R-100 worked fine.
- For FTDI USB-RS232 cables it is essential to set the latency
timer to 1 ms (from the power in default of 16 ms), e.g. with
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
- the following assumes that a USB-RS232 cable with FTDI chip is used
 
A 460k Baud connection gives in practice a disk throughput of about 20 kB/s.
This allows to test the system but is a bit slow to real usage. In an OS
with good disk caching like 2.11BSD the impact of such a 'slow disk' is
actually smaller than the bare numbers suggest.
 
2. FPGA Board setup -------------------------------------------------------
 
- connect the USB-RS232 cable to the RS232 port of the s3board or nexys2
- set the latency timer of the USB-RS232, e.g. with
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
- ensure that all 8 switches are in '0' position
- load the w11a design into the FPGA, e.g. via impact
 
3. Unix V5 system ---------------------------------------------------------
 
- A disk set is available from
http://www-linux.gsi.de/~mueller/retro/oc_w11/data/unix_v5_rkset.tgz
Download, unpack and copy the disk images (*.dsk) to
$RETROBASE/rtl/sys_gen/w11a/tb
 
- Setup USB-RS232 cable, start xterm in vt100 mode and the server backend
 
cd $RETROBASE/rtl/sys_gen/w11a/tb
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
telnet_starter -d DL0 &
dorri -u0,460 @uv5_boot.pcmd
 
- the boot dialog in the console xterm window will look like
(required input is in {..}, with {<CR>} denoting a carriage return:
 
@{unix}
login: {root}
 
Now you are at the shell prompt and can excercise the system, e.g.
 
# {ls -al}
total 62
drwxr-xr-x 9 bin 160 Jan 29 16:14 .
drwxr-xr-x 9 bin 160 Jan 29 16:14 ..
drwxr-xr-x 2 bin 944 Nov 26 18:13 bin
drwxr-xr-x 2 bin 80 Nov 26 18:13 dev
drwxr-xr-x 2 bin 240 Mar 21 12:07 etc
drwxr-xr-x 2 bin 224 Nov 26 18:13 lib
drwxr-xr-x 2 bin 32 Nov 26 18:13 mnt
drwxrwxrwx 2 bin 32 Nov 26 18:13 tmp
-rwxrwxrwx 1 bin 25802 Mar 21 12:07 unix
drwxr-xr-x 14 bin 224 Nov 26 18:13 usr
 
There is no 'halt' or 'shutdown' command, just ^D out of the server
session. The disks aren't cached, so no need to sync either.
 
4. 2.11BSD system ---------------------------------------------------------
- A disk set is available from
http://www-linux.gsi.de/~mueller/retro/oc_w11/data/211bsd_rkset.tgz
Download, unpack and copy the disk images (*.dsk) to
$RETROBASE/rtl/sys_gen/w11a/tb
 
- Setup USB-RS232 cable, start two xterm in vt100 mode and the server backend
 
cd $RETROBASE/rtl/sys_gen/w11a/tb
sudo $RETROBASE/tools/bin/set_ftdi_lat USB0 1
telnet_starter -d DL0 &
telnet_starter -d DL1 &
dorri -u0,460 @211bsd_rk_boot.pcmd
 
- the boot dialog in the console xterm window will look like
(required input is in {..}, with {<CR>} denoting a carriage return:
 
70Boot from rk(0,0,0) at 0177404
: {<CR>}
: rk(0,0,0)unix
Boot: bootdev=03000 bootcsr=0177404
2.11 BSD UNIX #26: Thu Jan 1 19:49:13 PST 2009
root@curly.2bsd.com:/usr/src/sys/RETRONFPRK
phys mem = 3932160
avail mem = 3577856
user mem = 307200
January 4 16:45:33 init: configure system
dz ? csr 160100 vector 310 skipped: No CSR.
lp 0 csr 177514 vector 200 attached
rk ? csr 177400 vector 220 didn't interrupt.
rl ? csr 174400 vector 160 skipped: No CSR.
tm ? csr 172520 vector 224 skipped: No CSR.
xp ? csr 176700 vector 254 skipped: No CSR.
cn 1 csr 176500 vector 300 attached
erase, kill ^U, intr ^C
 
In first '#' prompt the system is in single-user mode. Just enter a ^D
to continue the system startup to multi-user mode:
 
#^D
checking quotas: done.
Assuming non-networking system ...
checking for core dump...
preserving editor files
clearing /tmp
standard daemons: update cron accounting.
starting lpd
starting local daemons:Sun Jan 4 16:46:37 PST 2009
January 4 16:46:37 init: kernel security level changed from 0 to 1
January 4 16:46:40 getty: /dev/tty01: Device not configured
January 4 16:46:40 getty: /dev/tty00: Device not configured
2.11 BSD UNIX (curly.2bsd.com) (console)
login: {root}
erase, kill ^U, intr ^C
 
Now the system is in multi-user mode, daemons runnng. You can explore
the system, e.g. with a 'pstat -T' or a 'mount' command. At end is
important to shutdown properly with a 'halt':
 
# {pstat -T}
7/186 files
39/208 inodes
11/150 processes
6/ 46 texts active, 28 used
2/135 swapmap entries, 366 kB used, 2069 kB free, 2063 kB max
33/150 coremap entries, 2960 kB free, 2867 kB max
1/ 10 ub_map entries, 10 free, 10 max
# {mount}
/dev/rk0h on /
/dev/rk2h on /tmp
/dev/rk3h on /bin
/dev/rk4h on /usr
# {halt}
syncing disks... done
halting
 
Now the server process can be stopped with two ^D.
/trunk/doc/w11a_seq_flow.txt
0,0 → 1,24
$ $Id: w11a_seq_flow.txt 315 2010-07-11 22:18:39Z mueller $
 
The states are
1. grouped by 'flows', related states are in a dashed box
2. grouped in classes by color
- blue: idle/fetch/decode states
- cyan: console handling states
- light orange: source address mode flow
- dark orange: destination address mode flows
- green: states for main opcode handling
- red: states for error handling
 
The grey 'fork_...' hexagons represent three transition groups which are
common to the control flow of several states. There is no corresponding
state, these symbols just help to reduce the number of transition lines
on the flow chart.
 
The transitions are color coded too:
- green: normal 'forward' transition in a flow
- blue: i/o wait loop
- red: error/trap handling
- magenta: fatal errors to cpufail state
- thick black: link to a fork_ symbol
- black: all other transitions
/trunk/doc/w11a_tb_guide.txt
0,0 → 1,153
# $ $Id: w11a_tb_guide.txt 316 2010-07-16 19:07:47Z mueller $
 
== Guide to running w11a test benches ==
 
1. Unit tests benches -----------------------------------------------------
 
All unit test benches have the same simple structure:
 
- a stimulus process reads test patterns as well as the expected
responses from a stimulus file
 
- the responses are checked in very simple cases by the stimulus process,
in general by a monitoring process
 
- the test bench produces a comprehensive log file. For each checked
response the line contains the word "CHECK" and either an "OK" or a
"FAIL", in the later case in general with an indication of whats wrong.
Other unexpected behaviour, like timeouts, will also result in a line
containing the word "FAIL".
 
- at the end a line with the word "DONE" is printed.
 
- the test bench is run like
 
tbw <testbenchname> [stimfile] | tee <logfile> | egrep "(FAIL|DONE)"
 
where
- 'tbw' is a small perl script setting up a symbolic link to the
stimulus file, the default extracted from the file tbw.dat, if
an optional file name is give this one will be used instead.
- 'tee' ensured that the full log is saved
- 'egrep' filters FAIL and DONE lines, a successful run will
produce a single DONE line
 
- Most tests can be run against
- the functional model
- gate level models at three stages
- the post-xst model (produced by netgen from ngc xst output)
- the post-map model (produced by netgen from ncd ngdbuild output)
- the post-par model (produced by netgen from ncd par output)
This is simply done using
make <testbench>_ssim for post-xst
make <testbench>_fsim for post-map
make <testbench>_tsim for post-par
all the rest is handled by the build environment.
An example of a post-synthesis model is given for the w11a core test.
 
2. Available unit tests benches -------------------------------------------
 
In the following the available tests are listed with
- the 'make' command to build them
- the pipe setup to run them
- the expected output (the run time measured on a 3 GHz system)
 
- serport receiver test
cd $RETROBASE/rtl/vlib/serport/tb
make tb_serport_uart_rx
time tbw tb_serport_uart_rx |\
tee tb_serport_uart_rx_dsim.log | egrep "(FAIL|DONE)"
-> 1269955 ns 63488: DONE
 
- serport receiver/transmitter test
make tb_serport_uart_rxtx
time tbw tb_serport_uart_rxtx |\
tee tb_serport_uart_rxtx_dsim.log | egrep "(FAIL|DONE)"
-> 52335 ns 2607: DONE
 
- serport autobauder test
make tb_serport_autobaud
time tbw tb_serport_autobaud |\
tee tb_serport_autobaud_dsim.log | egrep "(FAIL|DONE)"
-> 367475 ns 18364: DONE
 
- rri core test
 
cd $RETROBASE/rtl/vlib/rri/tb
make tb_rri_core
time tbw tb_rri_core |\
tee tb_rri_core_dsim.log | egrep "(FAIL|DONE)"
-> 61855 ns 3083: DONE
-> real 0m0.163s user 0m0.128s sys 0m0.020s
 
- rri core test via serial port interface
 
make tb_rri_serport
time tbw tb_rri_serport |\
tee tb_rri_serport_dsim.log | egrep "(FAIL|DONE)"
-> 273355 ns 13658: DONE
-> real 0m0.939s user 0m0.924s sys 0m0.008s
 
- w11a core test (using behavioural model)
 
cd $RETROBASE/rtl/w11a/tb
make tb_pdp11_core
time tbw tb_pdp11_core |\
tee tb_pdp11_core_dsim.log | egrep "(FAIL|DONE)"
-> 1220255 ns 61003: DONE
-> real 0m14.964s user 0m14.977s sys 0m0.108s
 
- w11a core test (using post-synthesis model)
 
make ghdl_tmp_clean tb_pdp11_core_ssim
time tbw tb_pdp11_core_ssim |\
tee tb_pdp11_core_ssim.log | egrep "(FAIL|DONE)"
-> 1220255 ns 61003: DONE
-> real 1m8.230s user 1m8.144s sys 0m0.124s
 
3. System tests benches ---------------------------------------------------
 
The system tests allow to verify to verify the full 11/70 SoC design.
In this case vhdl test bench code contains
- (simple) models of the memories used on the FPGA boards
- drivers for the rri connection (currently just serialport)
- code to interface the rri data stream to a UNIX 'named pipe',
implemented with a C routine which is called via VHPI from VHDL.
This way the whole ghdl simulation can be controlled via a di-directional
byte stream.
 
The rri backend process, currently a perl script named pi_rri, can connect
either via a named pipe to a ghdl simulation, or via a serial port to a
FPGA board. This way the same tests can be executed in simulation and
on real hardware.
 
4. Available system tests benches -----------------------------------------
 
The stimulus file used in the w11a core test can be executed in the
full system context (both s3board and nexys2 versions) with the
following commands. Note that the cycle number printed in the DONE
line can now vary slightly because the response time of the rri
backend process and thus scheduling of backend vs. ghdl process
can affect the result.
 
- sys_w11a_s3 system test
 
cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
make tb_w11a_s3
time pi_rri --fifo --timeout=40. --cmax=3 \
--run="tbw tb_w11a_s3" -- \
@../../../../w11a/tb/tb_pdp11_core_stim.dat |\
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 7766215 ns 388301: DONE
-> real 0m51.300s user 0m51.711s sys 0m0.772s
 
- sys_w11a_n2 system test
 
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
make tb_w11a_n2
time pi_rri --fifo --timeout=40. --cmax=3 \
--run="tbw tb_w11a_n2" -- \
@../../../../w11a/tb/tb_pdp11_core_stim.dat |\
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EW]:|FAIL|PEND|DONE)"
-> 7766855 ns 388333: DONE
-> real 0m51.243s user 0m51.647s sys 0m0.776s
/trunk/doc/w11a_seq_flow.DOT
0,0 → 1,939
// $Id: w11a_seq_flow.DOT 315 2010-07-11 22:18:39Z mueller $
//
// The create pdf use
//
// cpp w11a_seq_flow.DOT w11a_seq_flow.dot
// dot -Tps2 w11a_seq_flow.dot > w11a_seq_flow.ps
// ps2pdf w11a_seq_flow.ps
//
 
#define FORKSTATE
#define CLUSTER
 
#define COLssys cyan
#define COLscons cyan4
#define COLssrc gold
#define COLsdst goldenrod
#define COLsoper greenyellow
#define COLsint limegreen
#define COLserr tomato
 
#define COLtflow forestgreen
 
#define COLterr red
#define COLtfat deeppink4
#define COLtwait blue
 
#define FSZnode 12
#define FSZbnode 24
#define FSZgraph 18
#define FSZlabel 64
 
digraph G {
 
node [fontname="helvetica"];
 
fontsize=FSZlabel;
fontcolor=blue;
labelloc="t";
label="W11A Sequencer (Rev 230)";
 
// aspect="0.7,500";
// ratio="0.7";
 
// pad="10,10";
aspect="1.4,500";
ratio="1.4";
rankdir="LR";
 
 
// for ps flow
// size="8,12";
// pad="3,3"; // needed, otherwise some stuff cut off
 
 
#ifdef CLUSTER
ranksep=0.2; // default is 0.5 in
nodesep=0.1; // default is 0.25 in
#else
ranksep=0.2; // default is 0.5 in
nodesep=0.1; // default is 0.25 in
#endif
 
// to use when CLUSTER on
 
node [fontsize=FSZnode];
node [style=filled];
 
#define do_memread_i(s,w) s -> w [color=COLtflow];
#define do_memread_d(s,w) s -> w [color=COLtflow];
#define do_memread_srcinc(s,w) s -> w [color=COLtflow];
#define do_memwrite(s,w) s -> w [color=COLtflow];
#define do_memcheck(s) s -> s [color=COLtwait, penwidth=2]; \
s -> vmerr [color=COLterr];\
s[color=blue];
 
#ifdef FORKSTATE
#define do_fork_dstr(s) s -> fork_dstr [fillcolor=gray20, penwidth=3];
fork_dstr [fontsize=FSZbnode, style=filled,
color=lightgrey, shape=doubleoctagon];
fork_dstr -> dstr_def;
fork_dstr -> dstr_inc;
fork_dstr -> dstr_dec;
fork_dstr -> dstr_ind;
 
#define do_fork_opg(s) s -> fork_opg [fillcolor=gray20, penwidth=3];
fork_opg [fontsize=FSZbnode, style=filled,
color=lightgrey, shape=doubleoctagon];
fork_opg -> opg_gen;
fork_opg -> dstw_def;
fork_opg -> dstw_inc;
fork_opg -> dstw_dec;
fork_opg -> dstw_ind;
fork_opg -> opg_mul;
fork_opg -> opg_div;
fork_opg -> opg_ash;
fork_opg -> opg_ashc;
fork_opg -> cpufail [color=COLtfat];
 
#define do_fork_opa(s) s -> fork_opa [fillcolor=gray20, penwidth=3];
fork_opa [fontsize=FSZbnode, style=filled,
color=lightgrey, shape=doubleoctagon];
fork_opa -> opa_jmp;
fork_opa -> opa_jsr;
fork_opa -> opa_mtp_mem;
fork_opa -> opa_mfp_reg;
fork_opa -> opa_mfp_mem;
fork_opa -> cpufail [color=COLtfat];
 
#else
 
#define do_fork_dstr(s) \
s -> dstr_def;\
s -> dstr_inc;\
s -> dstr_dec;\
s -> dstr_ind;
 
#define do_fork_opg(s) \
s -> opg_gen;\
s -> dstw_def;\
s -> dstw_inc;\
s -> dstw_dec;\
s -> dstw_ind;\
s -> opg_mul;\
s -> opg_div;\
s -> opg_ash;\
s -> opg_ashc;\
s -> cpufail [color=COLtfat];
 
#define do_fork_opa(s) \
s -> opa_jmp;\
s -> opa_jsr;\
s -> opa_mtp_mem;\
s -> opa_mfp_reg;\
s -> opa_mfp_mem;\
s -> cpufail [color=COLtfat];
 
#endif
 
#define do_fork_next(s) \
s -> idle;\
s -> trap_disp;\
s -> ifetch [color=COLtflow];
 
#define do_fork_next_pref(s) \
s -> idle;\
s -> trap_disp;\
s -> ifetch_w [color=COLtflow];
 
#define do_start_int(s) s-> int_getpc [color=COLtflow];
 
// state list --------------------------
 
idle [fillcolor=COLssys, fontsize=FSZbnode];
cp_regread [fillcolor=COLscons];
cp_rps [fillcolor=COLscons];
cp_memr_w [fillcolor=COLscons];
cp_memw_w [fillcolor=COLscons];
ifetch [fillcolor=COLssys, fontsize=FSZbnode];
ifetch_w [fillcolor=COLssys, fontsize=FSZbnode];
idecode [fillcolor=COLssys, fontsize=FSZbnode];
 
srcr_def [fillcolor=COLssrc];
srcr_def_w [fillcolor=COLssrc];
srcr_inc [fillcolor=COLssrc];
srcr_inc_w [fillcolor=COLssrc];
srcr_dec [fillcolor=COLssrc];
srcr_dec1 [fillcolor=COLssrc];
srcr_ind [fillcolor=COLssrc];
srcr_ind1_w [fillcolor=COLssrc];
srcr_ind2 [fillcolor=COLssrc];
srcr_ind2_w [fillcolor=COLssrc];
 
dstr_def [fillcolor=COLsdst];
dstr_def_w [fillcolor=COLsdst];
dstr_inc [fillcolor=COLsdst];
dstr_inc_w [fillcolor=COLsdst];
dstr_dec [fillcolor=COLsdst];
dstr_dec1 [fillcolor=COLsdst];
dstr_ind [fillcolor=COLsdst];
dstr_ind1_w [fillcolor=COLsdst];
dstr_ind2 [fillcolor=COLsdst];
dstr_ind2_w [fillcolor=COLsdst];
 
dstw_def [fillcolor=COLsdst];
dstw_def_w [fillcolor=COLsdst];
dstw_inc [fillcolor=COLsdst];
dstw_inc_w [fillcolor=COLsdst];
dstw_incdef_w [fillcolor=COLsdst];
dstw_dec [fillcolor=COLsdst];
dstw_dec1 [fillcolor=COLsdst];
dstw_ind [fillcolor=COLsdst];
dstw_ind_w [fillcolor=COLsdst];
dstw_def246 [fillcolor=COLsdst];
 
dsta_inc [fillcolor=COLsdst];
dsta_incdef_w [fillcolor=COLsdst];
dsta_dec [fillcolor=COLsdst];
dsta_dec1 [fillcolor=COLsdst];
dsta_ind [fillcolor=COLsdst];
dsta_ind_w [fillcolor=COLsdst];
 
op_halt [fillcolor=COLsoper];
op_wait [fillcolor=COLsoper];
op_trap [fillcolor=COLsoper];
op_reset [fillcolor=COLsoper];
op_rts [fillcolor=COLsoper];
op_rtpop [fillcolor=COLsoper];
op_rtpop_w [fillcolor=COLsoper];
op_spl [fillcolor=COLsoper];
op_mcc [fillcolor=COLsoper];
op_br [fillcolor=COLsoper];
op_mark [fillcolor=COLsoper];
op_mark1 [fillcolor=COLsoper];
op_mark_pop [fillcolor=COLsoper];
op_mark_pop_w [fillcolor=COLsoper];
op_sob [fillcolor=COLsoper];
op_sob1 [fillcolor=COLsoper];
 
opg_gen [fillcolor=COLsoper, fontsize=FSZbnode];
opg_gen_rmw_w [fillcolor=COLsoper];
opg_mul [fillcolor=COLsoper];
opg_mul1 [fillcolor=COLsoper];
opg_div [fillcolor=COLsoper];
opg_div_cn [fillcolor=COLsoper];
opg_div_cr [fillcolor=COLsoper];
opg_div_sq [fillcolor=COLsoper];
opg_div_sr [fillcolor=COLsoper];
opg_div_zero [fillcolor=COLsoper];
opg_ash [fillcolor=COLsoper];
opg_ash_cn [fillcolor=COLsoper];
opg_ashc [fillcolor=COLsoper];
opg_ashc_cn [fillcolor=COLsoper];
opg_ashc_wl [fillcolor=COLsoper];
 
opa_jsr [fillcolor=COLsoper];
opa_jsr1 [fillcolor=COLsoper];
opa_jsr_push [fillcolor=COLsoper];
opa_jsr_push_w [fillcolor=COLsoper];
opa_jsr2 [fillcolor=COLsoper];
opa_jmp [fillcolor=COLsoper];
opa_mtp [fillcolor=COLsoper];
opa_mtp_pop_w [fillcolor=COLsoper];
opa_mtp_reg [fillcolor=COLsoper];
opa_mtp_mem [fillcolor=COLsoper];
opa_mtp_mem_w [fillcolor=COLsoper];
opa_mfp_reg [fillcolor=COLsoper];
opa_mfp_mem [fillcolor=COLsoper];
opa_mfp_mem_w [fillcolor=COLsoper];
opa_mfp_dec [fillcolor=COLsoper];
opa_mfp_push [fillcolor=COLsoper];
opa_mfp_push_w [fillcolor=COLsoper];
trap_4 [fillcolor=COLserr];
trap_10 [fillcolor=COLserr];
trap_disp [fillcolor=COLsint];
 
int_ext [fillcolor=COLsint];
int_getpc [fillcolor=COLsint];
int_getpc_w [fillcolor=COLsint];
int_getps [fillcolor=COLsint];
int_getps_w [fillcolor=COLsint];
int_getsp [fillcolor=COLsint];
int_decsp [fillcolor=COLsint];
int_pushps [fillcolor=COLsint];
int_pushps_w [fillcolor=COLsint];
int_pushpc [fillcolor=COLsint];
int_pushpc_w [fillcolor=COLsint];
 
rti_getpc [fillcolor=COLsoper];
rti_getpc_w [fillcolor=COLsoper];
rti_getps [fillcolor=COLsoper];
rti_getps_w [fillcolor=COLsoper];
rti_newpc [fillcolor=COLsoper];
vmerr [fillcolor=COLserr];
cpufail [fillcolor=COLserr];
 
// transition list ---------------------
// idle
idle -> idle;
idle -> cp_regread;
idle -> cp_memr_w;
idle -> cp_memw_w;
idle -> cp_rps;
idle -> int_ext;
idle -> ifetch;
idle -> op_wait;
 
// cp_regread
cp_regread -> idle;
 
// cp_rps
cp_rps -> idle;
 
// cp_memr_w
cp_memr_w -> cp_memr_w[color=COLtwait, penwidth=2];
cp_memr_w -> idle;
 
// cp_memw_w
cp_memw_w -> cp_memw_w[color=COLtwait, penwidth=2];
cp_memw_w -> idle;
 
// ifetch
do_memread_i(ifetch, ifetch_w)
 
// ifetch_w
do_memcheck(ifetch_w)
ifetch_w -> idecode;
 
// idecode
idecode -> op_halt;
idecode -> op_wait;
idecode -> rti_getpc;
idecode -> op_trap;
idecode -> op_reset;
idecode -> op_rts;
idecode -> op_spl;
idecode -> op_mcc;
idecode -> op_br;
idecode -> op_mark;
idecode -> op_sob;
idecode -> opa_mtp;
idecode -> cpufail [color=COLtfat];
idecode -> srcr_def;
idecode -> srcr_inc;
idecode -> srcr_dec;
idecode -> srcr_ind;
do_fork_dstr(idecode)
do_fork_opa(idecode)
idecode -> dsta_inc;
idecode -> dsta_dec;
idecode -> dsta_ind;
do_fork_opg(idecode)
idecode -> trap_10 [color=COLterr];
 
// srcr_def
do_memread_d(srcr_def, srcr_def_w)
 
// srcr_def_w
do_memcheck(srcr_def_w)
do_fork_dstr(srcr_def_w)
do_fork_opg(srcr_def_w)
 
// srcr_inc
do_memread_d(srcr_inc, srcr_inc_w)
 
// srcr_inc_w
do_memcheck(srcr_inc_w)
do_fork_dstr(srcr_inc_w)
do_fork_opg(srcr_inc_w)
 
// srcr_dec
srcr_dec -> srcr_dec1 [color=COLtflow];
 
// srcr_dec1
do_memread_d(srcr_dec1, srcr_ind1_w)
 
// srcr_ind
do_memread_i(srcr_ind, srcr_ind1_w)
 
// srcr_ind1_w
do_memcheck(srcr_ind1_w)
srcr_ind1_w -> srcr_ind2 [color=COLtflow];
 
// srcr_ind2
do_memread_d(srcr_ind2, srcr_ind2_w)
 
// srcr_ind2_w
do_memcheck(srcr_ind2_w)
do_fork_dstr(srcr_ind2_w)
do_fork_opg(srcr_ind2_w)
 
// dstr_def
do_memread_d(dstr_def, dstr_def_w)
 
// dstr_def_w
do_memcheck(dstr_def_w)
do_fork_opg(dstr_def_w)
 
// dstr_inc
do_memread_d(dstr_inc, dstr_inc_w)
 
// dstr_inc_w
do_memcheck(dstr_inc_w)
dstr_inc_w -> dstr_def [color=COLtflow];
do_fork_opg(dstr_inc_w)
 
// dstr_dec
dstr_dec -> dstr_dec1 [color=COLtflow];
 
// dstr_dec1
do_memread_d(dstr_dec1,dstr_inc_w)
 
// dstr_ind
do_memread_i(dstr_ind, dstr_ind1_w)
 
// dstr_ind1_w
do_memcheck(dstr_ind1_w)
dstr_ind1_w -> dstr_ind2 [color=COLtflow];
 
// dstr_ind2
do_memread_d(dstr_ind2, dstr_ind2_w)
 
// dstr_ind2_w
do_memcheck(dstr_ind2_w)
dstr_ind2_w -> dstr_def [color=COLtflow];
do_fork_opg(dstr_ind2_w)
 
// dstw_def
do_memwrite(dstw_def, dstw_def_w)
 
// dstw_def_w
do_memcheck(dstw_def_w)
do_fork_next(dstw_def_w)
 
// dstw_inc
do_memwrite(dstw_inc, dstw_inc_w)
do_memread_d(dstw_inc, dstw_incdef_w)
 
// dstw_inc_w
do_memcheck(dstw_inc_w)
do_fork_next(dstw_inc_w)
 
// dstw_incdef_w
do_memcheck(dstw_incdef_w)
dstw_incdef_w -> dstw_def246 [color=COLtflow];
 
// dstw_dec
dstw_dec -> dstw_dec1 [color=COLtflow];
 
// dstw_dec1
do_memwrite(dstw_dec1, dstw_def_w)
do_memread_d(dstw_dec1, dstw_incdef_w)
 
// dstw_ind
do_memread_i(dstw_ind, dstw_ind_w)
 
// dstw_ind_w
do_memcheck(dstw_ind_w)
dstw_ind_w -> dstw_dec1 [color=COLtflow];
 
// dstw_def246
do_memwrite(dstw_def246, dstw_def_w)
 
// dsta_inc
do_fork_opa(dsta_inc)
do_memread_d(dsta_inc, dsta_incdef_w)
 
// dsta_incdef_w
do_memcheck(dsta_incdef_w)
do_fork_opa(dsta_incdef_w)
 
// dsta_dec
dsta_dec -> dsta_dec1 [color=COLtflow];
 
// dsta_dec1
do_fork_opa(dsta_dec1)
do_memread_d(dsta_dec1, dsta_incdef_w)
 
// dsta_ind
do_memread_i(dsta_ind, dsta_ind_w)
 
// dsta_ind_w
do_memcheck(dsta_ind_w)
dsta_ind_w -> dsta_dec1 [color=COLtflow];
 
// op_halt
op_halt -> idle [color=COLtflow];
op_halt -> trap_4 [color=COLterr];
 
// op_wait
op_wait -> idle;
op_wait -> op_wait [color=COLtflow];
 
// op_trap
do_start_int(op_trap)
 
// op_reset
op_reset -> idle [color=COLtflow];
 
// op_rts
op_rts -> op_rtpop [color=COLtflow];
 
// op_rtpop
do_memread_srcinc(op_rtpop, op_rtpop_w)
 
// op_rtpop_w
do_memcheck(op_rtpop_w)
do_fork_next(op_rtpop_w)
 
// op_spl
op_spl -> ifetch;
do_fork_next(op_spl)
 
// op_mcc
do_fork_next(op_mcc)
 
// op_br
do_fork_next(op_br)
//do_fork_next_pref(op_br)
op_br -> ifetch_w; // explicit to avoid doubling...
 
// op_mark
op_mark -> op_mark1 [color=COLtflow];
 
// op_mark1
op_mark1 -> op_mark_pop [color=COLtflow];
 
// op_mark_pop
do_memread_srcinc(op_mark_pop, op_mark_pop_w)
 
// op_mark_pop_w
do_memcheck(op_mark_pop_w)
do_fork_next(op_mark_pop_w)
 
// op_sob
op_sob -> op_sob1 [color=COLtflow];
do_fork_next(op_sob)
 
// op_sob1
do_fork_next(op_sob1)
 
// opg_gen
do_memwrite(opg_gen, opg_gen_rmw_w)
do_memcheck(opg_gen)
opg_gen -> idecode;
// opg_gen -> idle; (already in do_fork!!)
do_fork_next_pref(opg_gen)
 
// opg_gen_rmw_w
do_memcheck(opg_gen_rmw_w)
do_fork_next(opg_gen_rmw_w)
 
// opg_mul
opg_mul -> opg_mul1 [color=COLtflow];
 
// opg_mul1
do_fork_next(opg_mul1)
 
// opg_div
opg_div -> opg_div_cn;
 
// opg_div_cn
opg_div_cn -> opg_div_zero;
opg_div_cn -> opg_div_cr [color=COLtflow];
opg_div_cn -> opg_div_cn;
 
// opg_div_cr
opg_div_cr -> opg_div_sq [color=COLtflow];
 
// opg_div_sq
opg_div_sq -> opg_div_sr [color=COLtflow];
 
// opg_div_sr
do_fork_next(opg_div_sr)
 
// opg_div_zero
do_fork_next(opg_div_zero)
 
// opg_ash
opg_ash -> opg_ash_cn [color=COLtflow];
 
// opg_ash_cn
opg_ash_cn -> opg_ash_cn;
do_fork_next_pref(opg_ash_cn)
 
// opg_ashc
opg_ashc -> opg_ashc_cn [color=COLtflow];
 
// opg_ashc_cn
opg_ashc_cn -> opg_ashc_cn;
opg_ashc_cn -> opg_ashc_wl [color=COLtflow];
 
// opg_ashc_wl
do_fork_next(opg_ashc_wl)
 
// opa_jsr
opa_jsr -> trap_10 [color=COLterr];
opa_jsr -> opa_jsr1 [color=COLtflow];
 
// opa_jsr1
opa_jsr1 -> opa_jsr_push [color=COLtflow];
 
// opa_jsr_push
opa_jsr_push -> opa_jsr_push_w [color=COLtflow];
 
// opa_jsr_push_w
do_memcheck(opa_jsr_push_w)
opa_jsr_push_w -> opa_jsr2 [color=COLtflow];
 
// opa_jsr2
do_fork_next(opa_jsr2)
 
// opa_jmp
opa_jmp -> trap_10 [color=COLterr];
do_fork_next(opa_jmp)
 
// opa_mtp
do_memread_srcinc(opa_mtp, opa_mtp_pop_w)
 
// opa_mtp_pop_w
do_memcheck(opa_mtp_pop_w)
opa_mtp_pop_w -> opa_mtp_reg;
opa_mtp_pop_w -> opa_mtp_mem;
opa_mtp_pop_w -> dsta_inc;
opa_mtp_pop_w -> dsta_dec;
opa_mtp_pop_w -> dsta_ind;
opa_mtp_pop_w -> cpufail [color=COLtfat];
 
// opa_mtp_reg
do_fork_next(opa_mtp_reg)
 
// opa_mtp_mem
opa_mtp_mem -> opa_mtp_mem_w [color=COLtflow];
 
// opa_mtp_mem_w
do_memcheck(opa_mtp_mem_w)
do_fork_next(opa_mtp_mem_w)
 
// opa_mfp_reg
opa_mfp_reg -> opa_mfp_dec [color=COLtflow];
 
// opa_mfp_mem
opa_mfp_mem -> opa_mfp_mem_w [color=COLtflow];
 
// opa_mfp_mem_w
do_memcheck(opa_mfp_mem_w)
opa_mfp_mem_w -> opa_mfp_dec [color=COLtflow];
 
// opa_mfp_dec
opa_mfp_dec -> opa_mfp_push [color=COLtflow];
 
// opa_mfp_push
opa_mfp_push -> opa_mfp_push_w [color=COLtflow];
 
// opa_mfp_push_w
do_memcheck(opa_mfp_push_w)
do_fork_next(opa_mfp_push_w)
// trap_4
do_start_int(trap_4)
 
// trap_10
do_start_int(trap_10)
 
// trap_disp
do_start_int(trap_disp)
 
// int_ext
do_start_int(int_ext)
 
// int_getpc
do_memread_srcinc(int_getpc, int_getpc_w)
 
// int_getpc_w
do_memcheck(int_getpc_w)
int_getpc_w -> idle;
int_getpc_w -> int_getps [color=COLtflow];
 
// int_getps
do_memread_srcinc(int_getps, int_getps_w)
 
// int_getps_w
do_memcheck(int_getps_w)
int_getps_w -> idle;
int_getps_w -> int_getsp [color=COLtflow];
 
// int_getsp
int_getsp -> int_decsp [color=COLtflow];
 
// int_decsp
int_decsp -> int_pushps [color=COLtflow];
 
// int_pushps
int_pushps -> int_pushps_w [color=COLtflow];
 
// int_pushps_w
do_memcheck(int_pushps_w)
int_pushps_w -> int_pushpc [color=COLtflow];
 
// int_pushpc
int_pushpc -> int_pushpc_w [color=COLtflow];
 
// int_pushpc_w
do_memcheck(int_pushpc_w)
do_fork_next(int_pushpc_w)
 
// rti_getpc
do_memread_srcinc(rti_getpc, rti_getpc_w)
 
// rti_getpc_w
do_memcheck(rti_getpc_w)
rti_getpc_w -> rti_getps [color=COLtflow];
 
// rti_getps
do_memread_srcinc(rti_getps, rti_getps_w)
 
// rti_getps_w
do_memcheck(rti_getps_w)
rti_getps_w -> rti_newpc [color=COLtflow];
 
// rti_newpc
rti_newpc -> ifetch;
do_fork_next(rti_newpc)
// vmerr
vmerr -> cpufail [color=COLtfat];
vmerr -> trap_4 [color=COLtflow];
do_start_int(vmerr)
 
// cpufail
cpufail -> idle [color=COLtflow];
 
// subgraph definitions ----------------
#ifdef CLUSTER
 
subgraph cluster_srcr {
srcr_def;
srcr_def_w;
srcr_inc;
srcr_inc_w;
srcr_dec;
srcr_dec1;
srcr_ind;
srcr_ind1_w;
srcr_ind2;
srcr_ind2_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "SRCR flow";
style=dashed;
color=blue;
}
 
subgraph cluster_dstr {
dstr_def;
dstr_def_w;
dstr_inc;
dstr_inc_w;
dstr_dec;
dstr_dec1;
dstr_ind;
dstr_ind1_w;
dstr_ind2;
dstr_ind2_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "DSTR flow";
style=dashed;
color=blue;
}
 
subgraph cluster_dstw {
dstw_def;
dstw_def_w;
dstw_inc;
dstw_inc_w;
dstw_incdef_w;
dstw_dec;
dstw_dec1;
dstw_ind;
dstw_ind_w;
dstw_def246;
fontsize=FSZgraph;
fontcolor=blue;
label = "DSTW flow";
style=dashed;
color=blue;
}
 
subgraph cluster_dsta {
dsta_inc;
dsta_incdef_w;
dsta_dec;
dsta_dec1;
dsta_ind;
dsta_ind_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "DSTA flow";
style=dashed;
color=blue;
}
 
subgraph cluster_rts {
op_rts;
op_rtpop;
op_rtpop_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "RTS flow";
style=dashed;
color=blue;
}
 
subgraph cluster_mark {
op_mark;
op_mark1;
op_mark_pop;
op_mark_pop_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "MARK flow";
style=dashed;
color=blue;
}
 
//#ifdef never
subgraph cluster_sob {
op_sob;
op_sob1;
fontsize=FSZgraph;
fontcolor=blue;
label = "SOB flow";
style=dashed;
color=blue;
}
 
subgraph cluster_mul {
opg_mul;
opg_mul1;
fontsize=FSZgraph;
fontcolor=blue;
label = "MUL flow";
style=dashed;
color=blue;
}
//#endif
 
subgraph cluster_div {
opg_div;
opg_div_cn;
opg_div_cr;
opg_div_sq;
opg_div_sr;
opg_div_zero;
fontsize=FSZgraph;
fontcolor=blue;
label = "DIV flow";
style=dashed;
color=blue;
}
 
//#ifdef never
subgraph cluster_ash {
opg_ash;
opg_ash_cn;
fontsize=FSZgraph;
fontcolor=blue;
label = "ASH flow";
style=dashed;
color=blue;
}
//#endif
 
subgraph cluster_ashc{
opg_ashc;
opg_ashc_cn;
opg_ashc_wl;
fontsize=FSZgraph;
fontcolor=blue;
label = "ASHC flow";
style=dashed;
color=blue;
}
 
subgraph cluster_jsr {
opa_jsr;
opa_jsr1;
opa_jsr_push;
opa_jsr_push_w;
opa_jsr2;
fontsize=FSZgraph;
fontcolor=blue;
label = "JSR flow";
style=dashed;
color=blue;
}
 
subgraph cluster_mtp {
opa_mtp;
opa_mtp_pop_w;
opa_mtp_reg;
opa_mtp_mem;
opa_mtp_mem_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "MTP flow";
style=dashed;
color=blue;
}
 
subgraph cluster_mfp {
opa_mfp_reg;
opa_mfp_mem;
opa_mfp_mem_w;
opa_mfp_dec;
opa_mfp_push;
opa_mfp_push_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "MFP flow";
style=dashed;
color=blue;
}
 
subgraph cluster_int {
int_ext;
int_getpc;
int_getpc_w;
int_getps;
int_getps_w;
int_getsp;
int_decsp;
int_pushps;
int_pushps_w;
int_pushpc;
int_pushpc_w;
fontsize=FSZgraph;
fontcolor=blue;
label = "INT flow";
style=dashed;
color=blue;
}
 
subgraph cluster_rti {
rti_getpc;
rti_getpc_w;
rti_getps;
rti_getps_w;
rti_newpc;
fontsize=FSZgraph;
fontcolor=blue;
label = "RTI flow";
style=dashed;
color=blue;
}
#endif
}
/trunk/doc/w11a_known_issues.txt
0,0 → 1,92
# $ $Id: w11a_known_issues.txt 316 2010-07-16 19:07:47Z mueller $
 
1. Known differences between w11a and KB-11C (11/70)
 
- the SPL instruction in the 11/70 always fetched the next instruction
regardless of pending device or even console interrupts. This is known
as the 'spl bug', see
http://minnie.tuhs.org/pipermail/pups/2006-September/001082.html
http://minnie.tuhs.org/pipermail/pups/2006-October/001083.html
In the w11a the SPL has 11/70 semantics in kernel mode, thus next no
traps or interrupts, but in supervisor and user mode SPL really acts as
nop, so traps and interrupts are taken as for all other instructions.
--> The w11a isn't bug compatible with the 11/70.
 
- A 'red stack violation' looses PSW, a 0 is pushed in stack.
 
- The 'instrution complete flag' in SSR0 is not implemented, it is
permanently '0', SSR2 will not record vector addresses in case of a
vector fetch fault. Recovery of vector fetch faults is therefore not
possible, but only 11/45 and 11/70 supported this, no OS used that, and
it's even unclear whether it can be practically used.
 
- the 11/70 maps the 18 bit UNIBUS address space into the upper part of
the 22bit extended mode address space. With UNIBUS mapping enabled, this
allowed to access via 17000000:17757777 the memory exactly as a UNIBUS
device would see it. The w11a doesn't implement this remapping, an access
in the range 17000000:17757777 causes a NXM fault.
 
All four points relate to very 11/70 specific behaviour, not operating system
depends on them, therefore they are considered acceptable implementation
differences
 
2. Known limitations
 
- some programs use timing loops based on the execution speed of the
original processors. This can lead to spurious timeouts, especially
in old test programs.
--> a 'CPU throttle mechanism' will be added in a future version to
circumvent this for some old test codes.
 
- the emulated I/O can lead to apparently slow device reaction times,
especially when the server runs as normal user process. This can lead
to timeout, again mostly in test programs.
--> a 'watch dog' mechanism will be added in a future version which
suspends the CPU when the server doesn't respond fast enough.
 
3. Known bugs
 
- TCK-036 pri=L: RK11: hardware poll not working
The RK11/RK05 hardware poll logic is probably no reflecting the
behaviour of the real drive.
 
- TCK-035 pri=L: RK11: no proper NXM check in 18bit systems
No NXM error is generated when a RK11 read or write reaches the top
of memory in 18 bit addressing. Crash dump routines use this to detect
end-of-memory.
 
- TCK-032 pri=M: RK11: polling on DRY in RKDS doesn't work
DRY in RKDS goes 1->0 immediately with RDY in RKCS when a function is
started. In a real RK05 drive DRY went to 0 after a short delay. Some
basic hardware tests are sensitive to this.
 
- TCK-030 pri=L: CPU: SSR0 trap bit set when access aborted
The 'trap bit' (bit 12: 10000) is set even when the access is aborted.
 
- TCK-029 pri=L: CPU: AIB A bit set for all accesses
The MMU trap condition isn't properly decoded
- TCK-028 pri=H: CPU: interrupt and trap precedence
In case of multiple trap, fault, or interrupt conditions the precedence
isn't implemented correctly.
 
- TCK-026 pri=L: CPU: src+dst delta added in ssr1 when same register
The ssr1 content after a fault is logically correct in w11a, but
different from 11/70.
 
- TCK-025 pri=L: CPU: no mmu trap when bit9 clearing instruction traps
In the 11/70 the instruction which affects mmu trap can cause a trap
already, in w11a only the next instruction will trap.
 
- TCK-014 pri=M: RK11: write protect action too slow
Some simple RK11 drivers, especially in tests, don't poll for completion
of a write protect command. Due to the emulated I/O this can cause errors.
 
- TCK-007 pri=H: CPU: no trap-4 after emt on odd stack
- TCK-006 pri=H: CPU: no yel-stack trap after jsr pc,nnn(pc)
- TCK-004 pri=H: CPU: yel-stack by interrupt causes loop-up
- TCK-003 pri=H: CPU: yel-stack by iot pushes two stack frames
All four issues are caused by an incorrect implementation of the trap
logic, which leads to a different precendence when multiple trap, fault,
or interrupt occur.
 

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