URL
https://opencores.org/ocsvn/w11/w11/trunk
Subversion Repositories w11
Compare Revisions
- This comparison shows the changes necessary to convert path
/w11
- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/trunk/tools/tcl/rlink/util.tcl
1,6 → 1,6
# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: util.tcl 758 2016-04-02 18:01:39Z mueller $ |
# |
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,6 → 13,7
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-04-02 758 2.1 add USR_ACCESS register support (RLUA0/RLUA1) |
# 2014-12-21 617 2.0.1 add rbtout definition in STAT |
# 2014-12-07 609 2.0 use new rlink v4 iface; remove SINIT again |
# 2014-08-09 580 1.0.2 add run_rri |
32,6 → 33,10
regdsc RLCNTL {anena 15} {atoena 14} {atoval 7 8} |
regdsc RLSTAT {lcmd 15 8} {babo 7} {rbsize 2 3} |
|
# RLUSRACC describes the 32 bit value returned by the usracc property |
# assuming that standart Xilinx TIMESTAMP format is used for USR_ACCESS |
regdsc RLUSRACC {day 31 5} {mon 26 4} {yr 22 6} {hr 16 5} {min 11 6} {sec 5 6} |
|
# 'pseudo register', describes 3rd word in return list element for -rlist |
regdsc FLAGS {vol 16} \ |
{chkdata 13} {chkstat 12} \ |
44,16 → 49,16
variable ADDR_RLSTAT 0xfffe |
variable ADDR_RLID1 0xfffd |
variable ADDR_RLID0 0xfffc |
# define rlink optinal regs addresses (are system constants too) |
variable ADDR_RLUA1 0xfffb |
variable ADDR_RLUA0 0xfffa |
|
# |
# setup: amap definitions for core config regs |
# setup: currently noop, amap definitions done at cpp level |
# |
proc setup {} { |
rlc amap -insert rl.cntl $rlink::ADDR_RLCNTL |
rlc amap -insert rl.stat $rlink::ADDR_RLSTAT |
rlc amap -insert rl.id1 $rlink::ADDR_RLID1 |
rlc amap -insert rl.id0 $rlink::ADDR_RLID0 |
} |
|
# |
# init: reset rlink: disable enables; clear attn register |
# |
63,6 → 68,7
-attn |
return "" |
} |
|
# |
# anena: enable/disable attn notify messages |
# |
70,6 → 76,7
rlc exec \ |
-wreg $rlink::ADDR_RLCNTL [regbld rlink::RLCNTL [list anena $ena]] |
} |
|
# |
# isopen: returns 1 if open and 0 if close |
# |
77,6 → 84,7
if {[rlc open] eq ""} { return 0 } |
return 1 |
} |
|
# |
# isfifo: returns 1 if open and fifo, 0 otherwise |
# |
85,6 → 93,7
if {$name ne "" && [regexp -- {^fifo:} $name]} { return 1 } |
return 0 |
} |
|
# |
# issim: returns 1 if open and in simulation mode, 0 otherwise |
# |
107,4 → 116,16
return $errcnt |
} |
|
# |
# format_usracc: format usracc timestamp |
# |
proc format_usracc {usracc} { |
reggetkv rlink::RLUSRACC $usracc "ua_" |
set ua_yr [expr {$ua_yr + 2000}] |
set rval [format "%04d-%02d-%02d %02d:%02d:%02d" \ |
$ua_yr $ua_mon $ua_day $ua_hr $ua_min $ua_sec] |
return $rval |
} |
|
|
} |
/trunk/tools/tcl/rbtest/test_flow.tcl
0,0 → 1,70
# $Id: test_flow.tcl 777 2016-06-19 20:24:15Z mueller $ |
# |
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
# Software Foundation, either version 2, or at your option any later version. |
# |
# This program is distributed in the hope that it will be useful, but |
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
# for complete details. |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 777 1.0 Initial version |
# |
|
package provide rbtest 1.0 |
|
package require rutiltpp |
package require rutil |
package require rlink |
|
namespace eval rbtest { |
# |
# Test flow control |
# |
proc test_flow {{bufmax 512} {bufmin 4}} { |
# |
set errcnt 0 |
rlc errcnt -clear |
# |
rlc log "rbtest::test_flow - init: clear cntl" |
rlc exec -init te.cntl [regbld rbtest::INIT cntl] |
# |
#------------------------------------------------------------------------- |
rlc log " test 1: create back pressure with wreg after a rblk" |
set rbase 0x8000 |
set wbase 0xc000 |
set nw $bufmin |
set nmax [expr {[rlc get bsizeprudent] / 2}]; # /2 because rblk and wblk ! |
if {$bufmax < $nmax} {set nmax $bufmax} |
while {$nw <= $nmax} { |
rlc log [format " buffer size: %4d" $nw] |
set rbuf {} |
set wbuf {} |
for {set i 0} {$i < $nw} {incr i} { |
lappend rbuf [expr {$rbase + $i}] |
lappend wbuf [expr {$wbase + $i}] |
} |
rlc exec \ |
-wreg te.data $rbase \ |
-rblk te.dinc $nw -edata $rbuf -edone $nw \ |
-wreg te.data $wbase \ |
-wblk te.dinc $wbuf \ |
-rreg te.cntl -edata 0 |
set nw [expr {2*$nw}] |
incr rbase 0x0400 |
incr wbase 0x0400 |
} |
# |
#------------------------------------------------------------------------- |
rlc log "rbtest::test_flow - cleanup: clear cntl" |
rlc exec -init te.cntl [regbld rbtest::INIT cntl] |
# |
incr errcnt [rlc errcnt -clear] |
return $errcnt |
} |
} |
/trunk/tools/tcl/rbtest/test_all.tcl
1,6 → 1,6
# $Id: test_all.tcl 662 2015-04-05 08:02:54Z mueller $ |
# $Id: test_all.tcl 777 2016-06-19 20:24:15Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,6 → 13,7
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 777 1.2 add test_flow |
# 2015-04-03 662 1.1 add test_labo |
# 2011-03-27 374 1.0 Initial version |
# 2011-03-13 369 0.1 First draft |
32,6 → 33,7
incr errcnt [rbtest::test_labo] |
incr errcnt [rbtest::test_stat $statmsk] |
incr errcnt [rbtest::test_attn $attnmsk] |
incr errcnt [rbtest::test_flow 256] |
return $errcnt |
} |
} |
/trunk/tools/tcl/rbtest/test_data.tcl
1,6 → 1,6
# $Id: test_data.tcl 661 2015-04-03 18:28:41Z mueller $ |
# $Id: test_data.tcl 777 2016-06-19 20:24:15Z mueller $ |
# |
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
13,6 → 13,7
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-19 777 2.1.1 add dinc tests |
# 2015-04-03 661 2.1 drop estatdef, use estattout |
# 2014-12-21 617 2.0.1 use rbtout stat bit for timeout |
# 2014-11-09 603 2.0 use rlink v4 address layout and iface |
119,6 → 120,37
-rreg te.ncyc -edata [expr {$nbusy + 1 }] |
} |
# |
# ------------------------------------------------------------------------- |
rlc log " test 5a: test dinc: post-increment on read" |
rlc exec \ |
-wreg te.data 0x1100 \ |
-rreg te.dinc -edata 0x1100 \ |
-rreg te.dinc -edata 0x1101 \ |
-rreg te.dinc -edata 0x1102 \ |
-rreg te.data -edata 0x1103 |
# |
# ------------------------------------------------------------------------- |
rlc log " test 5b: test dinc: write-check and post-increment on write" |
# clear wchk, do proper writes |
rlc exec \ |
-wreg te.cntl [regbld rbtest::CNTL {wchk 0} {nbusy 0}] \ |
-wreg te.data 0x1200 \ |
-wreg te.dinc 0x1200 \ |
-wreg te.dinc 0x1201 \ |
-wreg te.dinc 0x1202 \ |
-rreg te.data -edata 0x1203 \ |
-rreg te.cntl -edata [regbld rbtest::CNTL {wchk 0}] |
# wchk still clear; bad write (ff03, expected 1203); check wchk; |
# good write; check wchk (must stick); check that data write clears wchk |
rlc exec \ |
-wreg te.dinc 0xff03 \ |
-rreg te.cntl -edata [regbld rbtest::CNTL {wchk 1}] \ |
-wreg te.dinc 0x1204 \ |
-rreg te.cntl -edata [regbld rbtest::CNTL {wchk 1}] \ |
-rreg te.dinc -edata 0x1205 \ |
-wreg te.data 0x1300 \ |
-rreg te.cntl -edata [regbld rbtest::CNTL {wchk 0}] |
# |
#------------------------------------------------------------------------- |
rlc log "rbtest::test_data - cleanup: clear cntl and data" |
rlc exec -init te.cntl [regbld rbtest::INIT data cntl] |
/trunk/tools/src/librlink/RlinkConnect.hpp
1,6 → 1,6
// $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkConnect.hpp 758 2016-04-02 18:01:39Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,6 → 13,8
// |
// Revision History: |
// Date Rev Version Comment |
// 2016-04-02 758 2.5 add USR_ACCESS register support (RLUA0/RLUA1) |
// 2016-03-20 748 2.4 add fTimeout,(Set)Timeout(); |
// 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon |
// 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask |
// 2015-01-06 631 2.1 full rlink v4 implementation |
37,7 → 39,7
|
/*! |
\file |
\version $Id: RlinkConnect.hpp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkConnect.hpp 758 2016-04-02 18:01:39Z mueller $ |
\brief Declaration of class \c RlinkConnect. |
*/ |
|
109,6 → 111,7
bool SndAttn(RerrMsg& emsg); |
|
uint32_t SysId() const; |
uint32_t UsrAcc() const; |
size_t RbufSize() const; |
size_t BlockSizeMax() const; |
size_t BlockSizePrudent() const; |
129,6 → 132,7
void SetPrintLevel(uint32_t lvl); |
void SetDumpLevel(uint32_t lvl); |
void SetTraceLevel(uint32_t lvl); |
void SetTimeout(double timeout); |
|
uint32_t LogBaseAddr() const; |
uint32_t LogBaseData() const; |
136,6 → 140,7
uint32_t PrintLevel() const; |
uint32_t DumpLevel() const; |
uint32_t TraceLevel() const; |
double Timeout() const; |
|
bool LogOpen(const std::string& name, RerrMsg& emsg); |
void LogUseStream(std::ostream* pstr, |
156,6 → 161,8
static const uint16_t kRbaddr_RLSTAT = 0xfffe; //!< rlink core reg RLSTAT |
static const uint16_t kRbaddr_RLID1 = 0xfffd; //!< rlink core reg RLID1 |
static const uint16_t kRbaddr_RLID0 = 0xfffc; //!< rlink core reg RLID0 |
static const uint16_t kRbaddr_RLUA1 = 0xfffb; //!< rlink opt. reg RLUA1 |
static const uint16_t kRbaddr_RLUA0 = 0xfffa; //!< rlink opt. reg RLUA0 |
|
static const uint16_t kRLCNTL_M_AnEna = kWBit15;//!< RLCNTL: an enable |
static const uint16_t kRLCNTL_M_AtoEna= kWBit14;//!< RLCNTL: ato enable |
236,11 → 243,13
uint32_t fPrintLevel; //!< print 0=off,1=err,2=chk,3=all |
uint32_t fDumpLevel; //!< dump 0=off,1=err,2=chk,3=all |
uint32_t fTraceLevel; //!< trace 0=off,1=buf,2=char |
double fTimeout; //!< response timeout |
boost::shared_ptr<RlogFile> fspLog; //!< log file ptr |
boost::recursive_mutex fConnectMutex; //!< mutex to lock whole connect |
uint16_t fAttnNotiPatt; //!< attn notifier pattern |
double fTsLastAttnNoti; //!< time stamp last attn notify |
uint32_t fSysId; //!< SYSID of connected device |
uint32_t fUsrAcc; //!< USR_ACCESS of connected device |
size_t fRbufSize; //!< Rbuf size (in bytes) |
}; |
|
/trunk/tools/src/librlink/RlinkConnect.ipp
1,6 → 1,6
// $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ |
// $Id: RlinkConnect.ipp 758 2016-04-02 18:01:39Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,6 → 13,8
// |
// Revision History: |
// Date Rev Version Comment |
// 2016-04-02 758 2.4 add USR_ACCESS register support (RLUA0/RLUA1) |
// 2016-03-20 748 2.3 add fTimeout,(Set)Timeout(); |
// 2015-04-12 666 2.2 add LinkInit,LinkInitDone; transfer xon |
// 2015-01-06 631 2.1 full rlink v4 implementation |
// 2013-03-05 495 1.2.1 add Exec() without emsg (will send emsg to LogFile) |
26,7 → 28,7
|
/*! |
\file |
\version $Id: RlinkConnect.ipp 666 2015-04-12 21:17:54Z mueller $ |
\version $Id: RlinkConnect.ipp 758 2016-04-02 18:01:39Z mueller $ |
\brief Implemenation (inline) of RlinkConnect. |
*/ |
|
106,6 → 108,13
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
inline uint32_t RlinkConnect::UsrAcc() const |
{ |
return fUsrAcc; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
inline size_t RlinkConnect::RbufSize() const |
{ |
return fRbufSize; |
240,6 → 249,14
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline double RlinkConnect::Timeout() const |
{ |
return fTimeout; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
inline RlogFile& RlinkConnect::LogFile() const |
{ |
return *fspLog; |
/trunk/tools/src/librlink/RlinkConnect.cpp
1,6 → 1,6
// $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ |
// $Id: RlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,6 → 13,8
// |
// Revision History: |
// Date Rev Version Comment |
// 2016-04-02 758 2.5 add USR_ACCESS register support (RLUA0/RLUA1) |
// 2016-03-20 748 2.4 add fTimeout,(Set)Timeout(); |
// 2015-05-10 678 2.3.1 WaitAttn(): BUGFIX: return 0. (not -1.) if poll |
// 2015-04-12 666 2.3 add LinkInit,LinkInitDone; transfer xon |
// 2015-04-02 661 2.2 expect logic: stat expect in Command, invert mask |
36,7 → 38,7
|
/*! |
\file |
\version $Id: RlinkConnect.cpp 679 2015-05-13 17:38:46Z mueller $ |
\version $Id: RlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ |
\brief Implemenation of RlinkConnect. |
*/ |
|
72,6 → 74,8
const uint16_t RlinkConnect::kRbaddr_RLSTAT; |
const uint16_t RlinkConnect::kRbaddr_RLID1; |
const uint16_t RlinkConnect::kRbaddr_RLID0; |
const uint16_t RlinkConnect::kRbaddr_RLUA1; |
const uint16_t RlinkConnect::kRbaddr_RLUA0; |
|
const uint16_t RlinkConnect::kRLCNTL_M_AnEna; |
const uint16_t RlinkConnect::kRLCNTL_M_AtoEna; |
108,11 → 112,13
fPrintLevel(2), // default print: error and checks |
fDumpLevel(0), // default dump: no |
fTraceLevel(0), // default trace: no |
fTimeout(10.), // default timeout: 10 sec |
fspLog(new RlogFile(&cout)), |
fConnectMutex(), |
fAttnNotiPatt(0), |
fTsLastAttnNoti(-1), |
fSysId(0xffffffff), |
fUsrAcc(0x00000000), |
fRbufSize(2048) |
{ |
for (size_t i=0; i<8; i++) fSeqNumber[i] = 0; |
174,6 → 180,7
fLinkInitDone = false; |
fRbufSize = 2048; // use minimum (2kB) as startup |
fSysId = 0xffffffff; |
fUsrAcc = 0x00000000; |
|
if (! fpPort->Url().FindOpt("noinit")) { |
if (!LinkInit(emsg)) { |
216,10 → 223,22
clist.AddRreg(kRbaddr_RLID1); |
clist.AddRreg(kRbaddr_RLID0); |
|
// RLUA0/1 are optional registers, available for 7Series and higher |
clist.AddRreg(kRbaddr_RLUA1); |
clist.SetLastExpectStatus(0,0); // disable stat check |
clist.AddRreg(kRbaddr_RLUA0); |
clist.SetLastExpectStatus(0,0); // disable stat check |
|
if (!Exec(clist, emsg)) return false; |
|
fLinkInitDone = true; |
|
|
// handle rlink core registers: setup mappings, keep data |
AddrMapInsert("rl.cntl", kRbaddr_RLCNTL); |
AddrMapInsert("rl.stat", kRbaddr_RLSTAT); |
AddrMapInsert("rl.id1", kRbaddr_RLID1); |
AddrMapInsert("rl.id0", kRbaddr_RLID0); |
|
uint16_t rlstat = clist[0].Data(); |
uint16_t rlid1 = clist[1].Data(); |
uint16_t rlid0 = clist[2].Data(); |
227,6 → 246,21
fRbufSize = size_t(1) << (10 + (rlstat & kRLSTAT_M_RBSize)); |
fSysId = uint32_t(rlid1)<<16 | uint32_t(rlid0); |
|
// handle rlink optional registers: USR_ACCESS |
const uint8_t staterr = RlinkCommand::kStat_M_RbTout | |
RlinkCommand::kStat_M_RbNak | |
RlinkCommand::kStat_M_RbErr; |
if ((clist[3].Status() & staterr) == 0 && // RLUA1 ok |
(clist[4].Status() & staterr) == 0) { // RLUA0 ok |
|
AddrMapInsert("rl.ua1", kRbaddr_RLUA1); |
AddrMapInsert("rl.ua0", kRbaddr_RLUA0); |
|
uint16_t rlua1 = clist[3].Data(); |
uint16_t rlua0 = clist[4].Data(); |
fUsrAcc = uint32_t(rlua1)<<16 | uint32_t(rlua0); |
} |
|
return true; |
} |
|
575,6 → 609,15
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
void RlinkConnect::SetTimeout(double timeout) |
{ |
fTimeout = timeout; |
return; |
} |
|
//------------------------------------------+----------------------------------- |
//! FIXME_docs |
|
bool RlinkConnect::LogOpen(const std::string& name, RerrMsg& emsg) |
{ |
if (!fspLog->Open(name, emsg)) { |
702,8 → 745,8
if (!fSndPkt.SndPacket(fpPort.get(), emsg)) return false; |
|
// FIXME_code: handle recoveries |
// FIXME_code: use proper value for timeout |
bool ok = ReadResponse(15., emsg); |
// FIXME_code: use proper value for timeout (rest time for Exec ?) |
bool ok = ReadResponse(fTimeout, emsg); |
if (!ok) Rexception("RlinkConnect::ExecPart()","faulty response"); |
|
int ncmd = DecodeResponse(clist, ibeg, iend); |
/trunk/tools/src/librlinktpp/RtclRlinkConnect.cpp
1,6 → 1,6
// $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ |
// $Id: RtclRlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ |
// |
// Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
// |
// This program is free software; you may redistribute and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
13,6 → 13,8
// |
// Revision History: |
// Date Rev Version Comment |
// 2016-04-02 758 1.4.6 add USR_ACCESS register support (UsrAcc->usracc) |
// 2016-03-20 748 1.4.5 M_get/set: add timeout |
// 2015-05-09 676 1.4.3 M_errcnt: add -increment; M_log: add -bare,-info.. |
// 2015-04-19 668 1.4.2 M_wtlam: allow tout=0 for pending attn cleanup |
// 2015-04-12 666 1.4.1 add M_init |
38,7 → 40,7
|
/*! |
\file |
\version $Id: RtclRlinkConnect.cpp 676 2015-05-09 16:31:54Z mueller $ |
\version $Id: RtclRlinkConnect.cpp 758 2016-04-02 18:01:39Z mueller $ |
\brief Implemenation of class RtclRlinkConnect. |
*/ |
|
115,6 → 117,8
boost::bind(&RlinkConnect::DumpLevel, pobj)); |
fGets.Add<uint32_t> ("tracelevel", |
boost::bind(&RlinkConnect::TraceLevel, pobj)); |
fGets.Add<double> ("timeout", |
boost::bind(&RlinkConnect::Timeout, pobj)); |
fGets.Add<const string&> ("logfile", |
boost::bind(&RlinkConnect::LogFileName, pobj)); |
|
122,6 → 126,8
boost::bind(&RlinkConnect::LinkInitDone, pobj)); |
fGets.Add<uint32_t> ("sysid", |
boost::bind(&RlinkConnect::SysId, pobj)); |
fGets.Add<uint32_t> ("usracc", |
boost::bind(&RlinkConnect::UsrAcc, pobj)); |
fGets.Add<size_t> ("rbufsize", |
boost::bind(&RlinkConnect::RbufSize, pobj)); |
fGets.Add<size_t> ("bsizemax", |
141,6 → 147,8
boost::bind(&RlinkConnect::SetDumpLevel, pobj, _1)); |
fSets.Add<uint32_t> ("tracelevel", |
boost::bind(&RlinkConnect::SetTraceLevel, pobj, _1)); |
fSets.Add<double> ("timeout", |
boost::bind(&RlinkConnect::SetTimeout, pobj, _1)); |
fSets.Add<const string&> ("logfile", |
boost::bind(&RlinkConnect::SetLogFileName, pobj, _1)); |
|
/trunk/tools/bin/tbrun_tbwrri
1,5 → 1,5
#!/bin/bash |
# $Id: tbrun_tbwrri 745 2016-03-18 22:10:34Z mueller $ |
# $Id: tbrun_tbwrri 778 2016-06-25 15:18:01Z mueller $ |
# |
# Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
6,6 → 6,11
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-25 778 1.2.4 drop make ghdl_tmp_clean logic |
# 2016-06-18 776 1.2.3 use ti_rri --tout to set connection timeout |
# 2016-06-05 773 1.2.2 use _bsim.log for behavioural sim log |
# 2016-03-20 748 1.2.1 BUGFIX: add portsel oob for -hxon |
# use 120 sec timeout for simulation |
# 2016-03-18 745 1.2 use --sxon and --hxon instead of --xon |
# 2015-04-11 666 1.1 add --fusp,--xon |
# 2014-12-27 622 1.0 Initial version |
98,23 → 103,14
tbenchname=$(basename $tbench) |
tbenchpath=$(dirname $tbench) |
|
# check for ghdl with _ssim, _fsim, _tsim |
isghdlxsim="" |
if [[ $tbench =~ _[sft]sim$ ]] ; then |
isghdlxsim=true |
logsuff="" |
fi |
|
# issue makes |
if [[ -n "$isghdlxsim" ]] ; then docmd "make -C $tbenchpath ghdl_tmp_clean"; fi |
docmd "make -C $tbenchpath $tbenchname" |
exitstat=$? |
if [[ -n "$isghdlxsim" ]] ; then docmd "make -C $tbenchpath ghdl_tmp_clean"; fi |
|
if (( $exitstat > 0 )) ; then exit $exitstat; fi |
|
# determine logfile name |
logsuff="_dsim" |
logsuff="_bsim" |
if [[ $tbenchname =~ _[sft]sim$ ]] ; then logsuff=""; fi |
if [[ -n "$optlsuf" ]] ; then logsuff="_$optlsuf"; fi |
|
144,6 → 140,7
fi |
|
cmd+=" --logl=3" |
cmd+=" --tout=120." # 120 sec timeout for simulation |
|
if [[ -n "$optpack" ]] ; then cmd+=" --pack=$optpack"; fi |
if [[ -n "$optrri" ]] ; then cmd+=" $optrri"; fi |
165,6 → 162,10
cmd+=" \"rlc oob -sbdata 16 0x2\"" # swi = 0010 -> 1st ser XON |
fi |
|
if [[ -n "$opthxon" ]] ; then |
cmd+=" \"rlc oob -sbdata 8 0x2\"" # portsel = 0010 -> 1st ser XON |
fi |
|
if (( $ncfxcount > 0 )) ; then cmd+=" \"rlc init\""; fi |
|
while (( $# > 0 )) ; do |
/trunk/tools/bin/xise_msg_summary
0,0 → 1,27
#!/bin/bash |
# $Id: xise_msg_summary 772 2016-06-05 12:55:11Z mueller $ |
# |
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Vers Comment |
# 2016-06-05 772 1.0 Initial version |
# |
|
for f in `find -name "*.imfset" | sort` |
do |
dnam=`dirname $f` |
bnam=`basename $f .imfset` |
echo "" |
echo "####################################################################" |
echo "### ${dnam}/${bnam} ###" |
pushd ${dnam} > /dev/null |
if [ ! -r ${bnam}_xst.log ] |
then |
echo No ${bnam}_xst.log available |
else |
make ${bnam}.mfsum |
fi |
popd > /dev/null |
done |
trunk/tools/bin/xise_msg_summary
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/tools/bin/tbw
===================================================================
--- trunk/tools/bin/tbw (revision 35)
+++ trunk/tools/bin/tbw (revision 36)
@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
-# $Id: tbw 727 2016-02-07 13:58:47Z mueller $
+# $Id: tbw 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2007-2016 by Walter F.J. Mueller
#
@@ -14,6 +14,9 @@
#
# Revision History:
# Date Rev Version Comment
+# 2016-06-25 778 1.5.1 support all sim modes
+# 2016-04-17 762 1.5 make '-run' default for [IX]Sim, add '-norun'
+# 2016-03-20 748 1.4 recode OPTIONS handling and -fifo handling
# 2016-02-06 727 1.3 add XSim support
# 2015-01-04 629 1.2.6 BUGFIX: setup proper dsc values after -fifo
# 2014-12-23 619 1.2.5 add -fifo and -verbose options
@@ -43,13 +46,17 @@
use strict; # require strict checking
use POSIX qw(mkfifo);
use FileHandle;
+use File::Spec;
+use Cwd 'abs_path';
my $tb_code;
my $is_isim;
my $is_isim_run;
my $is_xsim;
-my $is_fifo;
-my $is_verbose;
+my $opt_run;
+my $opt_norun;
+my $opt_fifo;
+my $opt_verbose;
my @args_pos; # list of positional args
my @args_nam; # list of named args
@@ -59,7 +66,7 @@
autoflush STDOUT 1; # autoflush, so nothing lost on exec later
-if (scalar(@ARGV) && $ARGV[0] =~ /^-*help$/) { # -help or --help given
+if (scalar(@ARGV) && $ARGV[0] =~ m/^-+help$/) { # -help or --help given
print_usage;
exit 0;
}
@@ -70,6 +77,8 @@
exit 1;
}
+# process test-bench-filename
+
$tb_code = shift @ARGV;
my $tb_code_path = ".";
my $tb_code_name = $tb_code;
@@ -78,39 +87,35 @@
$tb_code_name = $2;
}
+# process -run, -fifo and -verbose options (can be in any order now)
+
+while (scalar(@ARGV)) {
+ my $opt = $ARGV[0];
+ if ($opt =~ m/^-+norun$/) { $opt_norun = 1; shift @ARGV;}
+ elsif ($opt =~ m/^-+fifo$/) { $opt_fifo = 1; shift @ARGV;}
+ elsif ($opt =~ m/^-+verbose$/) { $opt_verbose = 1; shift @ARGV;}
+ elsif ($opt =~ m/^-+run$/) {
+ print "tbw-I: legacy option '-run' seen and ignored; is now default\n";
+ shift @ARGV;
+ }
+ else { last;}
+}
+
my $tb_code_stem = $tb_code_name;
-$tb_code_stem =~ s/_[fost]sim$//; # drop _ssim,_fsim, _osim, or _tsim
+$tb_code_stem =~ s/_[fsorept]sim$//; # drop sim mode suffix
if ($tb_code_stem =~ /_ISim$/) { # is it an ISim executable ?
+ $tb_code_stem =~ s/_ISim$//; # drop _ISim
$is_isim = 1;
- $tb_code_stem =~ s/_ISim$//; # drop _ISim
- if (scalar(@ARGV) && $ARGV[0] eq "-run") {
- $is_isim_run = 1;
- shift @ARGV;
- }
+ $is_isim_run = not $opt_norun;
}
if ($tb_code_stem =~ /_XSim$/) { # is it an XSim executable ?
+ $tb_code_stem =~ s/_XSim$//; # drop _XSim
$is_xsim = 1;
- $tb_code_stem =~ s/_XSim$//; # drop _XSim
- if (scalar(@ARGV) && $ARGV[0] eq "-run") { # map -run to '-R'
- $ARGV[0] = "-R";
- }
+ unshift @ARGV,'-R' unless $opt_norun; # run all unless '-norun' given
}
-
-if (scalar(@ARGV) && $ARGV[0] eq "-fifo") {
- push @file_dsc, {tag=>'rlink_cext_fifo_rx', val=>''};
- push @file_dsc, {tag=>'rlink_cext_fifo_tx', val=>''};
- push @file_dsc, {tag=>'rlink_cext_conf', val=>''};
- $is_fifo = 1;
- shift @ARGV;
-}
-if (scalar(@ARGV) && $ARGV[0] eq "-verbose") {
- $is_verbose = 1;
- shift @ARGV;
-}
-
if (not -e $tb_code) {
print "tbw-E: $tb_code not existing or not executable\n";
print_usage;
@@ -124,7 +129,7 @@
my $tbwdat_file = "tbw.dat";
$tbwdat_file = "$tb_code_path/tbw.dat" unless (-r "tbw.dat");
-if ((!$is_fifo) && -r $tbwdat_file) {
+if (-r $tbwdat_file) {
my $ok = 0;
my $done = 0;
@@ -145,20 +150,22 @@
print "tbw-E: bad line in tbw.dat:\n $_\n";
}
}
+} else {
+ print "tbw-W: failed to find $tbwdat_file\n";
}
#
# if no tbw.dat or no matching stanza found, setup defaults
#
-
-if (!$is_fifo) {
- unless (scalar (@file_dsc)) {
+unless (scalar (@file_dsc)) {
+ if ($opt_fifo) {
+ push @file_dsc, {tag=>'rlink_cext_fifo_rx', val=>''};
+ push @file_dsc, {tag=>'rlink_cext_fifo_tx', val=>''};
+ push @file_dsc, {tag=>'rlink_cext_conf', val=>''};
+ } else {
push @file_dsc, {tag=>$tb_code_stem . "_stim",
val=>$tb_code_stem . "_stim.dat"};
}
-} else {
- push @file_dsc, {tag=>"rlink_cext_fifo_rx",
- val=>""};
}
#
@@ -199,7 +206,7 @@
}
}
-if ($is_verbose) {
+if ($opt_verbose) {
foreach my $dsc (@file_dsc) {
my $tag = $dsc->{tag};
my $val = $dsc->{val};
@@ -238,10 +245,21 @@
$val = "/dev/null" if ($val eq ""); # null file case
}
+ # handle file names
+ # - if absolute path keep then
+ # - if relative path seen note that it is relative to test bench code path
+ # --> prepent test bench path, canonize, and convert to a relative path
+ # name relavive to cwd !
+ unless ($val =~ m|^/|) {
+ $val = $tb_code_path . '/' . $val;
+ $val = File::Spec->abs2rel(abs_path($val));
+ }
+
if (not -r $val) {
print "tbw-F: file for $tag not existing or not readable: $val\n";
exit 1;
}
+
if (-l $tag) {
my $cur_link = readlink $tag;
if ($cur_link ne $val) {
/trunk/tools/bin/ti_w11
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: ti_w11 745 2016-03-18 22:10:34Z mueller $ |
# $Id: ti_w11 776 2016-06-18 17:22:51Z mueller $ |
# |
# Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
6,6 → 6,9
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 776 1.3.5 use ti_rri --tout now |
# 2016-03-20 748 1.3.4 BUGFIX: add portsel oob for -fx; |
# use 120 sec timeout for simulation; add -ll,-dl,-tl |
# 2016-03-18 745 1.3.3 add arty support, add -fx |
# 2015-11-01 712 1.3.2 use sb_cntl pin 12 for tmu; add -ghw option |
# 2015-05-14 680 1.3.1 use now -f1,-f1e,-f2,-f2e (fx now f1e) |
31,6 → 34,10
my $opt_b; |
my $opt_io = ''; |
my $opt_f = ''; |
my $opt_ll = '2'; |
my $opt_dl = ''; |
my $opt_tl = ''; |
my $opt_to = ''; |
my $opt_tmu; |
my $opt_ghw; |
my $tirri; |
150,6 → 157,15
exit 1; |
} |
} |
} elsif ($curarg =~ m{^-ll(\d)$} ) { # -ll<n> (setup --logl) |
$opt_ll = $1; |
shift @ARGV; |
} elsif ($curarg =~ m{^-dl(\d)$} ) { # -dl<n> (setup --dmpl) |
$opt_dl = $1; |
shift @ARGV; |
} elsif ($curarg =~ m{^-tl(\d)$} ) { # -tl<n> (setup --tiol) |
$opt_tl = $1; |
shift @ARGV; |
} else { |
last; |
} |
203,11 → 219,19
exit 1; |
} |
|
# setup timeout |
if ($opt_io eq 'f') { |
$opt_to = '120.'; # 120 sec timeout for simulation |
} |
|
# |
# setup all other ti_rri options |
# |
|
push @arglist, '--logl=2'; |
push @arglist, "--logl=${opt_ll}"; |
push @arglist, "--dmpl=${opt_dl}" if $opt_dl ne ''; |
push @arglist, "--tiol=${opt_tl}" if $opt_tl ne ''; |
push @arglist, "--tout=${opt_to}" if $opt_to ne ''; |
push @arglist, '--int' unless $opt_b; |
push @arglist, '--pack=rw11'; |
push @arglist, @tiopts; # add options from ARGV |
225,6 → 249,8
if ($opt_f eq 'c') { |
push @arglist, 'rlc oob -sbdata 8 0x4'; # portsel = 0100 -> fx2 |
push @arglist, 'rlc oob -sbdata 16 0x4'; # swi = 0100 -> fx2 |
} elsif ($opt_f eq 'x') { |
push @arglist, 'rlc oob -sbdata 8 0x2'; # portsel = 0010 -> 1st ser XON |
} elsif ($opt_f eq '1x') { |
push @arglist, 'rlc oob -sbdata 8 0x2'; # portsel = 0010 -> 1st ser XON |
push @arglist, 'rlc oob -sbdata 16 0x2'; # swi = 0010 -> 1st ser XON |
310,9 → 336,10
print " -fx use 1st serport with hardwired xon\n"; |
print " -f1 use 1st serport\n"; |
print " -f1x use 1st serport with switched xon\n"; |
print " -f2 use 2nd serport (fusp)\n"; |
print " -f2 use 2nd serport (fusp)\n"; |
print " -f2x use 2nd serport with switched xon\n"; |
print " -tmu activate trace and monitoring unit\n"; |
print " -ghw activate ghdl wave dump with --wave=<stem>.ghw\n"; |
print " setup options for FPGA connects:\n"; |
print " -u use --cuff connect\n"; |
print " -t.. use --term connect\n"; |
/trunk/tools/bin/tbrun_tbw
1,5 → 1,5
#!/bin/bash |
# $Id: tbrun_tbw 727 2016-02-07 13:58:47Z mueller $ |
# $Id: tbrun_tbw 779 2016-06-26 15:37:16Z mueller $ |
# |
# Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
6,6 → 6,9
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-25 778 1.1.3 drop make ghdl_tmp_clean logic |
# 2016-06-05 773 1.1.2 use _bsim.log for behavioral sim log |
# 2016-04-17 762 1.1.1 don't create '-run' for [IX]Sim anymore (now default) |
# 2016-02-06 727 1.1 add vivado xsim support; Makefile.ise support |
# 2014-12-27 622 1.0.1 add --stack, --ghw, --tbw, --pcom |
# 2014-12-26 621 1.0 Initial version |
76,24 → 79,15
isghdl="" |
fi |
|
# check for ghdl with _ssim, _fsim, _osim, _tsim |
isghdlxsim="" |
if [[ -n "$isghdl" ]] && [[ $tbench =~ _[sfot]sim$ ]] ; then |
isghdlxsim=true |
logsuff="" |
fi |
|
# issue makes |
if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi |
docmd "make $makeopts $tbench" |
exitstat=$? |
if [[ -n "$isghdlxsim" ]] ; then docmd "make ghdl_tmp_clean"; fi |
|
if (( $exitstat > 0 )) ; then exit $exitstat; fi |
|
# determine logfile name |
logsuff="_dsim" |
if [[ $tbench =~ _[sfot]sim$ ]] ; then logsuff=""; fi |
logsuff="_bsim" |
if [[ $tbench =~ _[fsorept]sim$ ]] ; then logsuff=""; fi |
if [[ -n "$optlsuf" ]] ; then logsuff="_$optlsuf"; fi |
|
logfile="${tbench}${logsuff}.log" |
100,8 → 94,6
|
# now build actual test command (a tbw|filter|tee|egrep pipe) |
cmd="time tbw $tbench" |
if [[ -n "$isisim" ]] ; then cmd+=" -run"; fi |
if [[ -n "$isxsim" ]] ; then cmd+=" -run"; fi |
if [[ -n "$stimfile" ]] ; then cmd+=" $stimfile"; fi |
if [[ -n "$opttbw" ]] ; then cmd+=" $opttbw"; fi |
if [[ -n "$optstack" ]] ; then cmd+=" --stack-max-size=$optstack"; fi |
/trunk/tools/bin/xviv_ghdl_unisim
1,11 → 1,12
#!/bin/bash |
# $Id: xviv_ghdl_unisim 642 2015-02-06 18:53:12Z mueller $ |
# $Id: xviv_ghdl_unisim 762 2016-04-17 21:33:42Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Vers Comment |
# 2016-04-17 762 1.1 update for viv 2016.1 |
# 2015-02-02 642 1.0 Initial version |
# |
|
114,8 → 115,15
cd unimacro |
# |
cp $XTWV_PATH/data/vhdl/src/unimacro/*.vhd . |
|
if [ -r $XTWV_PATH/data/vhdl/src/unimacro/vhdl_analyze_order ] |
then |
cp $XTWV_PATH/data/vhdl/src/unimacro/vhdl_analyze_order . |
else |
ls -1 *.vhd > vhdl_analyze_order |
fi |
# |
for file in *.vhd |
for file in `cat vhdl_analyze_order` |
do |
echo "# ghdl ... $file" |
ghdl -a -P../unisim -fexplicit --ieee=synopsys --work=unimacro \ |
/trunk/tools/bin/xviv_msg_summary
0,0 → 1,27
#!/bin/bash |
# $Id: xviv_msg_summary 772 2016-06-05 12:55:11Z mueller $ |
# |
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Vers Comment |
# 2016-06-05 772 1.0 Initial version |
# |
|
for f in `find -name "*.vmfset" | sort` |
do |
dnam=`dirname $f` |
bnam=`basename $f .vmfset` |
echo "" |
echo "####################################################################" |
echo "### ${dnam}/${bnam} ###" |
pushd ${dnam} > /dev/null |
if [ ! -r ${bnam}_syn.log ] |
then |
echo No ${bnam}_syn.log available |
else |
make ${bnam}.mfsum |
fi |
popd > /dev/null |
done |
trunk/tools/bin/xviv_msg_summary
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/tools/bin/xviv_sim_vhdl_cleanup
===================================================================
--- trunk/tools/bin/xviv_sim_vhdl_cleanup (nonexistent)
+++ trunk/tools/bin/xviv_sim_vhdl_cleanup (revision 36)
@@ -0,0 +1,16 @@
+#!/bin/bash
+# $Id: xviv_sim_vhdl_cleanup 774 2016-06-12 17:08:47Z mueller $
+#
+# Copyright 2014-2016 by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+# Revision History:
+# Date Rev Version Comment
+# 2016-06-12 774 1.0 Initial version
+#
+
+# cleanup vivado generated vhdl models for ghdl
+# 1. remove 'attribute RTL_KEEP' decorations
+# ghdl 0.33 does not accept decorations of port signals !
+
+sed -i.bak -e '/^ *attribute *RTL_KEEP/ d' $1
trunk/tools/bin/xviv_sim_vhdl_cleanup
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/tools/bin/ti_rri
===================================================================
--- trunk/tools/bin/ti_rri (revision 35)
+++ trunk/tools/bin/ti_rri (revision 36)
@@ -1,8 +1,8 @@
#! /usr/bin/env tclshcpp
# -*- tcl -*-
-# $Id: ti_rri 631 2015-01-09 21:36:51Z mueller $
+# $Id: ti_rri 776 2016-06-18 17:22:51Z mueller $
#
-# Copyright 2011-2015 by Walter F.J. Mueller
+# Copyright 2011-2016 by Walter F.J. Mueller
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -15,6 +15,7 @@
#
# Revision History:
# Date Rev Version Comment
+# 2015-01-09 776 1.2.2 add --tout option to setup rlc timeout before connect
# 2015-01-09 631 1.2.1 use rlc get/set rather config
# 2014-11-07 601 1.2 use tclshcpp (C++ based) rather tclsh
# 2013-05-19 521 1.1.6 setup proper interactive handling; add --run reap
@@ -41,6 +42,7 @@
# --logl=n ; default 2
# --dmpl=n ; default 0
# --tiol=n ; default 0
+# --tout=n ; default 1.
# --int
# --help
# --
@@ -63,6 +65,7 @@
logl_ 2
dmpl_ 0
tiol_ 0
+ tout_ 1.
int 0
help 0
}
@@ -119,6 +122,7 @@
^--?logl=.+$ { regexp -- {=(.*)} $arg dummy opts(logl_) }
^--?dmpl=.+$ { regexp -- {=(.*)} $arg dummy opts(dmpl_) }
^--?tiol=.+$ { regexp -- {=(.*)} $arg dummy opts(tiol_) }
+ ^--?tout=.+$ { regexp -- {=(.*)} $arg dummy opts(tout_) }
^--?int$ { set opts(int) 1 }
^--?help$ { set opts(help) 1 }
^--$ { set optsendseen 1 }
@@ -152,10 +156,11 @@
puts { --term=[NAME[,BAUD[,OPTS]]]}
puts { --cuff[=ARGS] open cuff type rlink port. Optional arguments are:}
puts { --cuff=[NAME[,OPTS]]}
- puts { --log=FILE set log file name. Default is to write to stdout.}
- puts { --logl=LVL set log level, default is '2' allowed values 0-3.}
+ puts { --log=FILE set log file name. Default is to write to stdout}
+ puts { --logl=LVL set log level, default is '2' allowed values 0-3}
puts { --dmpl=LVL set dump level, default is '0', values like logl}
- puts { --tiol=LVL set i/o trace level, default is '0', allowed 0-2.}
+ puts { --tiol=LVL set i/o trace level, default is '0', allowed 0-2}
+ puts { --tout=dt set timeout, default is '1.', must be >0.}
puts { --int enter interactive mode even when commands given}
puts { --help display this help and exit}
puts { -- all following arguments are treated as tcl commands}
@@ -216,6 +221,7 @@
rlc set printlevel $opts(logl_)
rlc set dumplevel $opts(dmpl_)
rlc set tracelevel $opts(tiol_)
+rlc set timeout $opts(tout_)
# first start, if specified with --run, the test bench
# exec sh -c $cmd is used to execute a shell command including [], '',""
/trunk/tools/bin/vbomconv
1,5 → 1,5
#!/usr/bin/perl -w |
# $Id: vbomconv 734 2016-02-20 22:43:20Z mueller $ |
# $Id: vbomconv 778 2016-06-25 15:18:01Z mueller $ |
# |
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
14,6 → 14,14
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-24 778 1.17.1 -vsyn_prj: add [rep]sim models & VBOMCONV_XSIM_LANG |
# -ghdl_(i|m|a): use --workdir |
# 2016-06-19 777 1.17 -vsyn_prj: sim and syn source sets based on -UUT |
# -vsim_prj: finally functioning tsim builds |
# 2016-04-30 766 1.16.2 use -UUT property instead of @uut |
# 2016-04-23 764 1.16.1 --vsim_prj: use 'nosort' |
# 2016-04-22 763 1.16 --vsim_prj: use bash+pipefail, check exit status |
# 2016-03-27 752 1.15 1st support for file properties (xdc -SCOPE_REF) |
# 2016-02-20 734 1.14 add [ise,viv]; add preliminary --(vsyn|vsim)_export; |
# 2016-02-14 731 1.13 add @uut tag handling; |
# 2016-02-07 728 1.12 add vivado xsim support; protect for empty xdc set |
58,6 → 66,7
use 5.005; # require Perl 5.005 or higher |
use strict; # require strict checking |
use FileHandle; |
use Cwd 'getcwd'; |
|
use Getopt::Long; |
|
88,6 → 97,8
sub copy_edir; |
sub write_vbomdep; |
sub canon_fname; |
sub parse_props; |
sub setup_props; |
|
my @vbom_queue; # list of pending vbom's |
my @srcfile_list; # list of sources in compile order |
101,6 → 112,7
my %vbom_rank; # key=vbom; val=vbom ranks |
my %srcfile_rank; # key=source file; val=file rank |
my %srcfile_synsim; # key=source file; val=syn or sim |
my %srcfile_prop; # key=source file; hash of props |
my %para_tbl; # substitution table |
my @ucf_cpp_list; |
my $is_ghdl = 0; # ghdl simulation target |
112,6 → 124,10
my $is_ise = 0; # ISE target |
my $is_viv = 0; # vivado target |
my $is_any = 0; # ignore tags (for --flist) |
my $is_bsim = 0; # is behavioural simulation |
my $is_fsim = 0; # is functional simulation |
my $is_tsim = 0; # is timing simulation |
my $is_veri = 0; # is verilog model based |
my $nactions = 0; # number of action commands |
my $top_vbom; # top level vbom (from argv) |
my $eff_vbom; # effective vbom ([fot]sim->ssim map) |
122,16 → 138,23
my $has_unisim; # @lib:unisim seen or implied |
my $has_unimacro; # @lib:unimacro seen |
my $has_simprim; # @lib:simprim seen or implied |
my $is_ssim; |
my $is_fsim; |
my $is_osim; |
my $is_tsim; |
my $sim_mode = 'bsim'; |
my $do_trace = exists $opts{trace}; |
my $level = 0; # vbom nesting level |
my $xst_writevhdl = 1; |
my $xlpath=$opts{xlpath}; |
my $no_xlpath = ! defined $xlpath || $xlpath eq ""; |
my $xsim_lang = 'verilog'; # xsim model language |
|
$xsim_lang = $ENV{VBOMCONV_XSIM_LANG} if defined $ENV{VBOMCONV_XSIM_LANG}; |
if ($xsim_lang ne 'verilog' && $xsim_lang ne 'vhdl') { |
print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG is '$xsim_lang'\n"; |
print STDERR "vbomconv-E: VBOMCONV_XSIM_LANG must be 'verilog' or 'vhdl'\n"; |
exit 1; |
} |
|
$is_veri = $xsim_lang eq 'verilog'; |
|
autoflush STDOUT 1; # autoflush, so nothing lost on exec later |
|
if (exists $opts{help}) { |
147,6 → 170,10
exit 1; |
} |
|
# get number of CPUs (used later....) |
my $nproc = `nproc`; |
chomp $nproc; |
|
# check that only one action is defined, mark xst, gdhl, or isim class |
|
foreach (keys %opts) { |
198,16 → 225,19
$top = $stem; |
$top =~ s{^.*/}{}; |
|
# now prepare virtual _fsim, _osim, and _tsim vbom's |
# now prepare virtual _[forept]sim vbom's |
# they are inferred from the _ssim vbom's |
|
$is_ssim = 1 if $top_vbom =~ m{_ssim\.vbom$}; # detect _ssim |
$is_fsim = 1 if $top_vbom =~ m{_fsim\.vbom$}; # detect _fsim |
$is_osim = 1 if $top_vbom =~ m{_osim\.vbom$}; # detect _osim |
$is_tsim = 1 if $top_vbom =~ m{_tsim\.vbom$}; # detect _tsim |
if ($top_vbom =~ m{_([sforept]sim)\.vbom$}) { |
$sim_mode = $1; |
} |
|
$is_bsim = 1 if $sim_mode eq 'bsim'; |
$is_fsim = 1 if $sim_mode =~ m/^[fsor]sim$/; |
$is_tsim = 1 if $sim_mode =~ m/^[ept]sim$/; |
|
$eff_vbom = $top_vbom; |
$eff_vbom =~ s{_[fot]sim\.vbom$}{_ssim.vbom}; # map [fot]sim -> ssim |
$eff_vbom =~ s{_[forept]sim\.vbom$}{_ssim.vbom}; # map [forept]sim -> ssim |
|
# traverse all vbom's start with command line argument |
|
294,7 → 324,7
print STDERR "\n"; |
print STDERR "properties:\n"; |
print STDERR " \@top: $top\n"; |
print STDERR " \@uut: $uut\n" if defined $uut; |
print STDERR " \-UUT: $uut\n" if defined $uut; |
} |
|
# --ghdh_a -- ghdl analysis command ---------------------------------- |
304,10 → 334,11
print STDERR "vbomconv-E: --xlpath required with ghdl_a or ghdl_a_cmd"; |
exit 1; |
} |
my $workdir = "ghdl.${sim_mode}"; |
|
foreach (@srcfile_list) { |
my $file = $_; |
my $cmd = "ghdl -a"; |
my $cmd = "ghdl -a --workdir=${workdir}"; |
$cmd .= " -P$xlpath/unisim" if $has_unisim; |
$cmd .= " -P$xlpath/unimacro" if $has_unimacro; |
$cmd .= " -P$xlpath/simprim" if $has_simprim; |
334,16 → 365,19
# --ghdh_i -- ghdl inspection command -------------------------------- |
|
if (exists $opts{ghdl_i} || exists $opts{ghdl_i_cmd}) { |
my $workdir = "ghdl.${sim_mode}"; |
my %ghdl_work; |
|
system "mkdir ${workdir}" unless -d ${workdir}; |
|
# read ghdl "work-obj93.cf" file. It has the format |
# file . "<filename>" "<file_date>" "ghdl -i or -a date>": |
# entity <entity> at nn( nn) + nn on nn; |
# architecture <arch> of <entity> at nn( nn) + nn on nn; |
|
if (-r "work-obj93.cf") { |
open (WFILE, "work-obj93.cf") or |
die "can't open for read work-obj93.cf: $!"; |
if (-r "${workdir}/work-obj93.cf") { |
open (WFILE, "${workdir}/work-obj93.cf") or |
die "can't open for ${workdir}/read work-obj93.cf: $!"; |
while (<WFILE>) { |
if (m{^file \. \"(.*?)\"}) { |
$ghdl_work{$1} = 1; |
352,7 → 386,7
close (WFILE); |
} |
|
my $cmd = "ghdl -i"; |
my $cmd = "ghdl -i --workdir=${workdir}"; |
my $nfile = 0; |
|
foreach (@srcfile_list) { |
382,6 → 416,7
# the right thing. |
|
if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) { |
my $workdir = "ghdl.${sim_mode}"; |
my $cmd = ""; |
|
if ($no_xlpath && ($has_unisim || $has_unimacro || $has_simprim) ) { |
393,7 → 428,7
$cmd .= "rm $stem\n" ; # rm to force elaboration |
} |
|
$cmd .= "ghdl -m"; |
$cmd .= "ghdl -m --workdir=${workdir}"; |
$cmd .= " -o $stem"; |
# -fexplicit needed for ISE 13.1,13.3 |
$cmd .= ' -fexplicit' if $has_unisim or $has_unimacro or $has_simprim; |
401,7 → 436,7
$cmd .= " -P$xlpath/unimacro" if $has_unimacro; |
$cmd .= " -P$xlpath/simprim" if $has_simprim; |
$cmd .= " --ieee=synopsys"; |
$cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_osim or $is_tsim; |
$cmd .= " --no-vital-checks" if $sim_mode ne 'bsim'; |
|
foreach (@srcfile_list) { |
next unless /\.c$/; # C source ? |
442,12 → 477,21
# --vsyn_prj --------------------------------------------------------- |
|
if (exists $opts{vsyn_prj}) { |
# setup sources |
# determine source and simulation file sets |
my @fl_syn; |
my @fl_sim; |
foreach my $fi (@srcfile_list) { |
if ($srcfile_synsim{$fi} eq 'syn') { |
push @fl_syn, $fi; |
} else { |
push @fl_sim, $fi; |
} |
} |
print "#\n"; |
print "# setup sources\n"; |
print "# setup sources for synthesis\n"; |
print "#\n"; |
print "set src_files {\n"; |
foreach (@srcfile_list) { |
print "set syn_files {\n"; |
foreach (@fl_syn) { |
print " $_\n"; |
} |
print "}\n"; |
454,9 → 498,26
print "\n"; |
|
print "set obj [get_filesets sources_1]\n"; |
print "add_files -norecurse -fileset \$obj \$src_files\n"; |
print "set_property \"top\" \"$top\" \$obj\n"; |
print "add_files -norecurse -fileset \$obj \$syn_files\n"; |
# defined top only when not doing test bench |
print "set_property \"top\" \"$top\" \$obj\n" unless defined $uut; |
|
if (defined $uut) { |
print "#\n"; |
print "# setup sources for simulation\n"; |
print "#\n"; |
print "set sim_files {\n"; |
foreach (@fl_sim) { |
print " $_\n"; |
} |
print "}\n"; |
print "\n"; |
|
print "set obj [get_filesets sim_1]\n"; |
print "add_files -norecurse -fileset \$obj \$sim_files\n"; |
print "set_property SOURCE_SET sources_1 \$obj\n"; |
} |
|
# setup constraints |
print "#\n"; |
print "# setup constraints\n"; |
473,6 → 534,15
if (scalar @xdcfile_list) { |
print "set obj [get_filesets constrs_1]\n"; |
print "add_files -norecurse -fileset \$obj \$xdc_files\n"; |
print "\n"; |
foreach my $fnam (@xdcfile_list) { |
if (exists $srcfile_prop{$fnam}->{-SCOPE_REF}) { |
my $target = $srcfile_prop{$fnam}->{-SCOPE_REF}; |
$target = $srcfile_prop{$fnam}->{VBstem} if $target eq ''; |
print "set_property SCOPED_TO_REF $target \\\n"; |
print " [get_files $fnam]\n"; |
} |
} |
} |
|
print "\n"; |
481,24 → 551,45
# --vsim_prj --------------------------------------------------------- |
|
if (exists $opts{vsim_prj}) { |
print "#!/bin/sh\n"; |
my $workdir = "xsim.${sim_mode}"; |
my $fname_forwarder = "${stem}_XSim"; |
$fname_forwarder =~ s/_([sorept]sim)_XSim/_XSim_$1/; |
|
print "#!/bin/bash\n"; |
# pipefail ensures that in pipes like xvlog | tee ect the exits status is |
# from the last failed command, and not simply from last command (tee). |
# that ensures that the xvlog exit codes can be tested |
print "set -o pipefail\n"; |
print "#\n"; |
print "# generated by vbomconv -vsim_prj $top_vbom\n"; |
print "#\n"; |
|
print "# ---------- delete old forwarder\n"; |
print "rm -f $fname_forwarder\n"; |
print "#\n"; |
|
print "# ---------- setup fresh working directory\n"; |
print "rm -rf ${workdir}\n"; |
print "mkdir ${workdir}\n"; |
print "pushd ${workdir}\n"; |
print "#\n"; |
|
# compile verilog before vhdl ! |
# currently verilog only used for DPI interface code |
# currently verilog only used for DPI interface code or simulation models |
# xvhdl relies in strict compilation order, also across languages, and fails |
# when a not yet compiles module is instantiated via entiry work.... |
# when a not yet compiled module is instantiated via entiry work.xxx |
|
if (scalar @srcfile_list_v) { |
print "# ---------- xvlog step\n"; |
my $tfile_xvlog_prj = "tmp_${stem}_xvlog.prj"; |
print "cat > $tfile_xvlog_prj <<tmp_xvlog_end_token\n"; |
print "#compile verilog source files\n"; |
foreach (@srcfile_list_v) { |
my $type = (m/\.v$/) ? "verilog" : "sv "; |
print "$type work $_\n"; |
print "$type xil_defaultlib ../$_\n"; |
} |
print "#do not sort compile order\n"; |
print "nosort\n"; |
print "tmp_xvlog_end_token\n"; |
print "#\n"; |
|
505,7 → 596,9
my $opts_xvlog = "-m64 --relax"; |
print "xtwv xvlog $opts_xvlog -prj $tfile_xvlog_prj 2>&1 |\\\n"; |
print " tee xvlog_${stem}.log\n"; |
print 'exitstatus=$?' . "\n"; |
print "rm -f $tfile_xvlog_prj\n"; |
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; |
print "#\n"; |
} |
|
513,9 → 606,12
print "# ---------- xvhdl step\n"; |
my $tfile_xvhdl_prj = "tmp_${stem}_xvhdl.prj"; |
print "cat > $tfile_xvhdl_prj <<tmp_xvhdl_end_token\n"; |
print "#compile vhdl source files\n"; |
foreach (@srcfile_list_vhd) { |
print "vhdl work $_\n"; |
print "vhdl xil_defaultlib ../$_\n"; |
} |
print "#do not sort compile order\n"; |
print "nosort\n"; |
print "tmp_xvhdl_end_token\n"; |
print "#\n"; |
|
522,7 → 618,9
my $opts_xvhdl = "-m64 --relax"; |
print "xtwv xvhdl $opts_xvhdl -prj $tfile_xvhdl_prj 2>&1 |\\\n"; |
print " tee xvhdl_${stem}.log\n"; |
print 'exitstatus=$?' . "\n"; |
print "rm -f $tfile_xvhdl_prj\n"; |
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; |
print "#\n"; |
} |
|
530,30 → 628,49
print "# ---------- xsc step\n"; |
print "xtwv xsc"; |
foreach (@srcfile_list_c) { |
print " \\\n $_"; |
print " \\\n ../$_"; |
} |
print "\n"; |
print 'exitstatus=$?' . "\n"; |
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; |
print "#\n"; |
} |
|
# Note: xelab -mt auto doesn't seem to work, use --mt `nproc` |
print "# ---------- xelab step\n"; |
print "xtwv xelab --relax --debug typical --mt auto -m64 \\\n"; |
print " -L work \\\n"; |
print "xtwv xelab --relax --debug typical --mt $nproc -m64 \\\n"; |
print " -L xil_defaultlib"; |
print " -L simprims_ver" if $is_tsim; |
print " -L unisims_ver" if $is_veri && ! ($is_bsim || $is_tsim); |
print " \\\n"; |
if (scalar @srcfile_list_c) { |
print " --sv_lib dpi \\\n"; |
} |
print " --snapshot $stem work.$top \\\n"; |
print " -log xelab_${stem}.log\n"; |
print "\n"; |
if ($is_tsim) { |
print " -transport_int_delays -pulse_r 0 -pulse_int_r 0 \\\n"; |
} |
print " --snapshot $stem \\\n"; |
print " -log xelab_${stem}.log \\\n"; |
print " xil_defaultlib.$top"; |
print " xil_defaultlib.glbl" if $is_tsim || ($is_veri && ! $is_bsim); |
print " \n"; |
print 'exitstatus=$?' . "\n"; |
print 'if (($exitstatus > 0)); then exit $exitstatus; fi' . "\n"; |
print "#\n"; |
|
my $cwd = getcwd(); |
# use in forwarder full absolute path to relevant xsim.dir |
# this allows to call the tb from every directory |
|
print "# ---------- create forwarder\n"; |
my $fname_forwarder = "${stem}_XSim"; |
$fname_forwarder =~ s/_([sot]sim)_XSim/_XSim_$1/; |
print "if [ -x \"xsim.dir/${stem}/xsimk\" ]\n"; |
print "popd\n"; |
print "if [ -x \"${workdir}/xsim.dir/${stem}/xsimk\" ]\n"; |
print "then\n"; |
print "#\n"; |
print "cat > $fname_forwarder <<forwarder_end_token\n"; |
print "#!/bin/sh\n"; |
print "rm -rf xsim.dir\n"; |
print "ln -s ${cwd}/${workdir}/xsim.dir xsim.dir\n"; |
# Note: double escape \"\\\$\@\" needed to ensure file contains "$@" |
print "exec xtwv xsim ${stem} \"\\\$\@\"\n"; |
print "forwarder_end_token\n"; |
566,21 → 683,17
|
if (exists $opts{dep_ghdl}) { |
|
my $stem_fsim = $stem; |
my $stem_osim = $stem; |
my $stem_tsim = $stem; |
$stem_fsim =~ s/_ssim$/_fsim/; |
$stem_osim =~ s/_ssim$/_osim/; |
$stem_tsim =~ s/_ssim$/_tsim/; |
|
print "#\n"; |
print "$stem : $stem.dep_ghdl\n"; |
if ($is_ssim) { |
print "$stem_fsim : $stem.dep_ghdl\n"; |
print "$stem_osim : $stem.dep_ghdl\n"; |
print "$stem_tsim : $stem.dep_ghdl\n"; |
|
if ($sim_mode eq 'ssim') { |
foreach my $type (qw(f o r t)) { |
my $stem_ghdl = $stem; |
$stem_ghdl =~ s/_ssim$/_${type}sim/; |
print "$stem_ghdl : $stem.dep_ghdl\n"; |
} |
print "#\n"; |
} |
print "#\n"; |
|
foreach (@srcfile_list) { |
if (/\.c$/) { |
589,7 → 702,7
$ofile =~ s/\.c$/.o/; # object file name |
print "$stem : $ofile\n"; # depend on C source object file |
# C source object compilation dependence |
open (ODEPFILE, ">$ofile.dep_ghdl") or |
open (ODEPFILE, ">$ofile.dep_ghdl") or |
die "can't write $ofile.dep_ghdl: $!"; |
print ODEPFILE "$ofile : $_\n"; |
print ODEPFILE "\t\$(COMPILE.c) \$(OUTPUT_OPTION) \$<\n"; |
599,44 → 712,26
} |
} |
|
if ($is_ssim) { |
# Notes: _fsim only for ISE useful |
# _tsim only for VIV useful |
if ($sim_mode eq 'ssim') { |
foreach my $type (qw(f o r t)) { |
my $stem_ghdl = $stem; |
$stem_ghdl =~ s/_ssim$/_${type}sim/; |
|
print "#\n"; |
foreach (@srcfile_list) { |
my $file = $_; # copy to break alias for following s/// |
if (/\.c$/) { |
$file =~ s{^.*/}{}; # remove directory path |
$file =~ s/\.c$/.o/; # depend on object file for C sources |
} else { |
$file =~ s/_ssim\.vhd$/_fsim.vhd/; |
print "#\n"; |
foreach (@srcfile_list) { |
my $file = $_; # copy to break alias for following s/// |
if (/\.c$/) { |
$file =~ s{^.*/}{}; # remove directory path |
$file =~ s/\.c$/.o/; # depend on object file for C sources |
} else { |
$file =~ s/_ssim\.vhd$/_${type}sim.vhd/; |
} |
print "$stem_ghdl : $file\n"; |
} |
print "$stem_fsim : $file\n"; |
} |
|
print "#\n"; |
foreach (@srcfile_list) { |
my $file = $_; # copy to break alias for following s/// |
if (/\.c$/) { |
$file =~ s{^.*/}{}; # remove directory path |
$file =~ s/\.c$/.o/; # depend on object file for C sources |
} else { |
$file =~ s/_ssim\.vhd$/_osim.vhd/; |
} |
print "$stem_osim : $file\n"; |
} |
|
print "#\n"; |
foreach (@srcfile_list) { |
my $file = $_; # copy to break alias for following s/// |
if (/\.c$/) { |
$file =~ s{^.*/}{}; # remove directory path |
$file =~ s/\.c$/.o/; # depend on object file for C sources |
} else { |
$file =~ s/_ssim\.vhd$/_tsim.vhd/; |
} |
print "$stem_tsim : $file\n"; |
} |
|
} |
|
write_vbomdep("$stem.dep_ghdl"); |
673,7 → 768,7
if (exists $opts{dep_isim}) { |
my $stem_isim = $stem . "_ISim"; |
|
$stem_isim =~ s/_ssim_ISim$/_ISim_ssim/ if ($is_ssim); |
$stem_isim =~ s/_ssim_ISim$/_ISim_ssim/ if ($sim_mode eq 'ssim'); |
|
my $stem_fsim_isim = $stem_isim; |
my $stem_tsim_isim = $stem_isim; |
682,7 → 777,7
|
print "#\n"; |
print "$stem_isim : $stem.dep_isim\n"; |
if ($is_ssim) { |
if ($sim_mode eq 'ssim') { |
print "$stem_fsim_isim : $stem.dep_isim\n"; |
print "$stem_tsim_isim : $stem.dep_isim\n"; |
} |
692,7 → 787,7
print "$stem_isim : $_\n"; |
} |
|
if ($is_ssim) { |
if ($sim_mode eq 'ssim') { |
|
print "#\n"; |
foreach (@srcfile_list) { |
741,18 → 836,17
if (exists $opts{dep_vsim}) { |
my $stem_vsim = $stem . "_XSim"; |
|
$stem_vsim =~ s/_ssim_XSim$/_XSim_ssim/ if ($is_ssim); |
$stem_vsim =~ s/_ssim_XSim$/_XSim_ssim/ if ($sim_mode eq 'ssim'); |
|
my $stem_osim_vsim = $stem_vsim; |
my $stem_tsim_vsim = $stem_vsim; |
$stem_osim_vsim =~ s/_ssim$/_osim/; |
$stem_tsim_vsim =~ s/_ssim$/_tsim/; |
|
print "#\n"; |
print "$stem_vsim : $stem.dep_vsim\n"; |
if ($is_ssim) { |
print "$stem_osim_vsim : $stem.dep_vsim\n"; |
print "$stem_tsim_vsim : $stem.dep_vsim\n"; |
|
if ($sim_mode eq 'ssim') { |
foreach my $type (qw(o r e p t)) { |
my $stem_xsim = $stem_vsim; |
$stem_xsim =~ s/_ssim$/_${type}sim/; |
print "$stem_xsim : $stem.dep_vsim\n"; |
} |
} |
print "#\n"; |
|
760,22 → 854,24
print "$stem_vsim : $_\n"; |
} |
|
if ($is_ssim) { |
if ($sim_mode eq 'ssim') { |
|
print "#\n"; |
foreach (@srcfile_list) { |
my $file = $_; # copy to break alias for following s/// |
$file =~ s/_ssim\.vhd$/_osim.vhd/; |
print "$stem_osim_vsim : $file\n"; |
} |
# Note: when --dep_vsim is used for a _ssim.vbom read_vbom will remap |
# _ssim.vhd to _ssim.v depending on $xsim_lang. [ept]sim always uses |
# verilog, that's why there is a explict mapping below. |
|
print "#\n"; |
foreach (@srcfile_list) { |
my $file = $_; # copy to break alias for following s/// |
$file =~ s/_ssim\.vhd$/_tsim.v/; |
print "$stem_tsim_vsim : $file\n"; |
foreach my $type (qw(o r e p t)) { |
my $stem_xsim = $stem_vsim; |
$stem_xsim =~ s/_ssim$/_${type}sim/; |
|
print "#\n"; |
foreach (@srcfile_list) { |
my $file = $_; # copy to break alias for following s/// |
$file =~ s/_ssim\.(v|vhd)$/_${type}sim.$1/; |
$file =~ s/_([ept])sim\.vhd$/_${1}sim.v/; # see Note above |
print "$stem_xsim : $file\n"; |
} |
} |
# |
} |
|
write_vbomdep("$stem.dep_vsim"); |
874,7 → 970,7
} elsif ($fname =~ m{\.xdc}) { # .xdc |
push @fl_xdc, $fname; |
} else { |
print STDERR "vbomconv-W: file $fname not procesed (unknown type)\n"; |
print STDERR "vbomconv-W: file $fname not processed (unknown type)\n"; |
} |
} |
|
1064,7 → 1160,6
|
my $tag; |
my $val = $_; |
my $uut_seen; |
|
# detect tag:val lines |
if (m{^\s*(.*?)\s*:\s*(.*?)\s*$}) { |
1083,7 → 1178,10
|
# process @xdc:<file> lines |
} elsif ($tag eq '@xdc') { |
push @{$vbom_xdc{$vbom}}, canon_fname($vbom_path, $val); |
my ($fname,$rphash) = parse_props($val); |
$fname = canon_fname($vbom_path, $fname); |
setup_props($fname, $rphash); |
push @{$vbom_xdc{$vbom}}, $fname; |
next; |
|
# process @lib:<name> lines |
1100,12 → 1198,6
} |
next; |
|
# process @uut:<file> lines |
} elsif ($tag eq '@uut') { |
$uut_seen = 1; |
# Note: fall through in this case, process as normal file name |
# actual @uut tag handling later with canonized file names. |
|
# catch invalid @ tags |
} else { |
print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n"; |
1114,25 → 1206,49
|
} |
|
# now do _fsim, _osim, _tsim mapping |
$val =~ s{_ssim\.vhd$}{_fsim.vhd} if $is_fsim; |
$val =~ s{_ssim\.vhd$}{_osim.vhd} if $is_osim; |
$val =~ s{_ssim\.vhd$}{_tsim.vhd} if $is_tsim && $is_ise; # ISE |
$val =~ s{_ssim\.vhd$}{_tsim.v} if $is_tsim && $is_viv; # Vivado |
# split in filename and property list |
my ($fname,$rphash) = parse_props($val); |
|
# process normal .vhd or .vbom file lines |
# now do model source file mapping |
my $fname_old = $fname; |
if ($is_ise || $is_ghdl) { |
$fname =~ s{_ssim\.vhd$}{_fsim.vhd} if $sim_mode eq 'fsim'; |
$fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim'; |
$fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim'; |
$fname =~ s{_ssim\.vhd$}{_tsim.vhd} if $sim_mode eq 'tsim'; |
} |
if ($is_viv) { |
$fname =~ s{_ssim\.vhd$}{_esim.v} if $sim_mode eq 'esim'; |
$fname =~ s{_ssim\.vhd$}{_psim.v} if $sim_mode eq 'psim'; |
$fname =~ s{_ssim\.vhd$}{_tsim.v} if $sim_mode eq 'tsim'; |
if ($is_veri) { |
$fname =~ s{_ssim\.vhd$}{_ssim.v} if $sim_mode eq 'ssim'; |
$fname =~ s{_ssim\.vhd$}{_osim.v} if $sim_mode eq 'osim'; |
$fname =~ s{_ssim\.vhd$}{_rsim.v} if $sim_mode eq 'rsim'; |
} else { |
$fname =~ s{_ssim\.vhd$}{_osim.vhd} if $sim_mode eq 'osim'; |
$fname =~ s{_ssim\.vhd$}{_rsim.vhd} if $sim_mode eq 'rsim'; |
} |
} |
print STDERR "--- map $fname_old -> $fname\n" |
if $do_trace && $fname_old ne $fname; |
|
# process normal .vhd, .v, or .vbom file lines |
# canonize file name unless not already done by filename substitution |
my $fullname; |
if ($val =~ m{^!(.*)$}) { |
if ($fname =~ m{^!(.*)$}) { |
$fullname = $1; |
} else { |
$fullname = canon_fname($vbom_path, $val); |
$fullname = canon_fname($vbom_path, $fname); |
} |
|
# process @uut tag here, with canonized file names |
if ($uut_seen) { |
# handle properties |
setup_props($fullname, $rphash); |
|
# process -UUT property here, with canonized file names |
if (exists $rphash->{-UUT}) { |
if (defined $uut) { |
print STDERR "vbomconv-E: duplicate \@uut:, 1st '$uut' 2nd '$val'\n"; |
print STDERR "vbomconv-E: duplicate -UUT:, 1st '$uut' 2nd '$val'\n"; |
exit 1; |
} |
$uut = $fullname; |
1139,10 → 1255,10
} |
|
# determine whether additional libs needed |
if ($fullname =~ m{_[so]sim\.vhd$}) { # ends in _ssim.vhd or _osim.vhd |
if ($fullname =~ m{_[sor]sim\.vhd$}) { # is ssim, osim or rsim |
$has_unisim = 1; |
} |
if ($fullname =~ m{_[ft]sim\.vhd$}) { # ends in _fsim.vhd or _tsim.vhd |
if ($fullname =~ m{_[ft]sim\.vhd$}) { # is fsim or tsim |
$has_simprim = 1; |
} |
|
1219,7 → 1335,7
|
# if @uut seen separate them |
if (defined $uut) { |
if ($uut =~ m{\.vbom}) { # uut is vbom (functional sim) |
if ($uut =~ m{\.vbom}) { # uut is vbom (behavioral sim) |
scan_synsim($uut); |
} else { # uut is file (post syn sim) |
$srcfile_synsim{$uut} = 'syn'; |
1283,7 → 1399,50
} |
|
#------------------------------------------------------------------------------- |
sub parse_props { |
my ($val) = @_; |
my $fname = $val; |
my %phash = (); |
if ($val =~ /^\s*(\S+)\s+(-.+)$/) { # "fname -xxx..." seen |
$fname = $1; |
my $plist = $2; |
foreach my $pitem (split /\s+/,$plist) { |
if ($pitem =~ m/^(.*)\:(.*)$/) { # -key:val (not k=v !!) |
$phash{$1} = $2; |
} else { |
$phash{$pitem} = ''; |
} |
} |
} |
|
return ($fname, \%phash); |
|
} |
|
#------------------------------------------------------------------------------- |
sub setup_props { |
my ($fname, $rphash) = @_; |
$srcfile_prop{$fname} = $rphash; |
my $path = '.'; |
my $name = $fname; |
if ($fname =~ m|^(.+)/(.+)$|) { |
$path = $1; |
$name = $2; |
} |
my $stem = $name; |
my $type = ''; |
if ($name =~ m/^(.+)(\..*)/) { |
$stem = $1; |
$type = $2; |
} |
$srcfile_prop{$fname}->{VBpath} = $path; |
$srcfile_prop{$fname}->{VBstem} = $stem; |
$srcfile_prop{$fname}->{VBtype} = $type; |
return; |
} |
|
#------------------------------------------------------------------------------- |
|
sub print_help { |
print "usage: vbomconf <command> file.vbom\n"; |
print " --help this message\n"; |
/trunk/tools/bin/xviv_msg_filter
0,0 → 1,270
#!/usr/bin/perl -w |
# $Id: xviv_msg_filter 772 2016-06-05 12:55:11Z mueller $ |
# |
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# |
# This program is free software; you may redistribute and/or modify it under |
# the terms of the GNU General Public License as published by the Free |
# Software Foundation, either version 2, or at your option any later version. |
# |
# This program is distributed in the hope that it will be useful, but |
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY |
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
# for complete details. |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-04 772 1.0 Initial version |
# |
|
use 5.14.0; # require Perl 5.14 or higher |
use strict; # require strict checking |
use FileHandle; |
|
use Getopt::Long; |
|
my %opts = (); |
|
GetOptions(\%opts, "help", "pacc") || exit 1; |
|
sub print_help; |
sub read_mfs; |
sub read_log; |
|
my $type = shift @ARGV; |
my $mfsnam = shift @ARGV; |
my $lognam = shift @ARGV; |
my @flist; |
my @mlist; |
my $nackcnt = 0; |
my $ackcnt = 0; |
my $imisscnt = 0; |
my $rmisscnt = 0; |
my $timebad = 0; |
my $timegood = 0; |
|
my $retrobase = $ENV{RETROBASE}; |
|
autoflush STDOUT 1 if (-p STDOUT); # autoflush if output into pipe |
|
if (exists $opts{help}) { |
print_help; |
exit 0; |
} |
|
if (!defined $type || !defined $mfsnam || !defined $lognam) { |
print STDERR "xviv_msg_filter-E: one of 'type mfset log' missing \n\n"; |
print_help; |
exit 1; |
} |
|
if ($type !~ m{^(syn|imp)$}) { |
print STDERR "xviv_msg_filter-E: type must be syn or imp\n"; |
exit 1; |
} |
|
if (read_mfs($mfsnam)) {exit 1;} |
if (read_log($lognam)) {exit 1;} |
|
foreach my $m (@mlist) { |
my $msev = $m->[0]; |
my $mcode = $m->[1]; |
my $mtext = $m->[2]; |
my $msgmatch = 0; |
|
# check for timing closure |
# bad: [Route 35-39] The design did not meet timing requirements |
# bad: [Timing 38-282] The design failed to meet the timing ... |
# good: [Route 35-61] The design met the timing requirement |
$timebad += 1 if $type eq 'imp' && $mcode eq 'Route 35-39'; |
$timebad += 1 if $type eq 'imp' && $mcode eq 'Timing 38-282'; |
$timegood += 1 if $type eq 'imp' && $mcode eq 'Route 35-61'; |
|
foreach my $f (@flist) { |
my $fmode = $f->[0]; |
my $fcode = $f->[1]; |
my $frege = $f->[2]; |
if ($frege eq '') { |
$msgmatch = $mcode eq $fcode; |
} else { |
$msgmatch = $mcode eq $fcode && $mtext =~ m{$frege}; |
} |
if ($msgmatch) { |
#print "+++m '$fmode' '$fcode' '$frege' : '$mcode' '$mtext'\n"; |
$f->[3] += 1; |
last; |
} |
} |
|
$msgmatch = 1 if $msev eq 'INFO'; # accept all INFO |
|
if ($msgmatch) { |
$m->[3] += 1; |
} else { |
$nackcnt += 1; |
} |
} |
|
if ($nackcnt) { |
print "Unexpected messages of type [$type] from $lognam:\n"; |
foreach my $m (@mlist) { |
next if $m->[3]; |
|
# now prety print the message |
# remove $RETROBASE from file names |
my $mtext = $m->[2]; |
$mtext =~ s/${retrobase}/.../g if defined $retrobase; |
# and break it up into 80 character wide lines |
my @mwl = split /\s+/,$mtext; |
unshift @mwl, '[' . $m->[1] . ']'; |
unshift @mwl, $m->[0] . ':'; |
my $pref = ' '; |
my $line = ' '; |
while (scalar(@mwl)) { |
my $word = shift @mwl; |
if (length($line) + length($word) + 1 > 80) { |
print "$line\n"; |
$line = $pref; |
} |
$line .= ' ' . $word; |
} |
print "$line\n" if $line ne $pref; |
} |
print "\n"; |
} |
|
foreach my $f (@flist) { |
if ($f->[3] != 0) { # matches seen |
$ackcnt += 1; |
} else { # matches not seen |
if ($f->[0] eq 'i') { # complain if 'i' |
$imisscnt += 1; |
} elsif ($f->[0] eq 'r') { # complain if 'r' |
$rmisscnt += 1; |
} |
} |
} |
|
if ($ackcnt && exists $opts{pacc}) { |
print "Accepted messages for type [$type] from $lognam:\n"; |
foreach my $f (@flist) { |
next if $f->[3] == 0; |
printf "%4d: [%s] %s\n", $f->[3], $f->[1], $f->[2]; |
} |
print "\n"; |
} |
|
if ($imisscnt) { |
print "Ignore filter rules with no matches for type [$type] from $lognam:\n"; |
foreach my $f (@flist) { |
next if $f->[3] != 0; |
printf "%4d: [%s] %s\n", $f->[3], $f->[1], $f->[2] if $f->[0] eq 'i'; |
} |
print "\n"; |
} |
|
if ($rmisscnt) { |
print "Missed required messages for type [$type] from $lognam:\n"; |
foreach my $f (@flist) { |
next if $f->[3] != 0; |
printf "%4d: [%s] %s\n", $f->[3], $f->[1], $f->[2] if $f->[0] eq 'r'; |
} |
print "\n"; |
} |
|
if ($type eq 'imp' && ($timebad > 0 || $timegood == 0)) { |
printf "!! ------------------------------ !!\n"; |
printf "!! FAILED TO REACH TIMING CLOSURE !!\n"; |
printf "!! ------------------------------ !!\n"; |
} |
|
#------------------------------------------------------------------------------- |
sub read_mfs { |
my ($fname) = @_; |
|
if (not -r $fname) { |
print STDERR "xviv_msg_filter-E: \'$fname\' not existing or readable\n"; |
return 1; |
} |
|
my $fh = new FileHandle; |
$fh->open($fname) or die "can't open for read $fname: $!"; |
|
my $intyp = 0; |
|
while (<$fh>) { |
chomp; |
s/#.*//; # remove comments after # |
s/\s+$//; # remove trailing blanks |
next if /^\s*$/; # drop empty lines |
|
if (/^\@(.+)$/) { # @<filename> found |
my $rc = read_mfs($1); |
return $rc if $rc; |
next; |
} |
|
if (m{^\[([a-z]{3})\]$}) { # [typ] tag found |
if ($1 eq $type) { |
$intyp = 1; |
} else { |
$intyp = 0; |
} |
next; |
} |
|
next unless $intyp; # only process relevant lines |
|
if (/^([iIr])\s+\[(.+?)\]\s*(.*)\s*$/) { |
#print "+++0m '$1' '$2' '$3'\n"; |
my $fmode = $1; |
my $fcode = $2; |
my $frege = $3; |
$frege =~ s/\[/\\\[/g; |
$frege =~ s/\]/\\\]/g; |
push @flist, [$fmode,$fcode,$frege, 0]; |
} else { |
printf STDERR "xviv_msg_filter-E: bad line in mfset: '%s'\n", $_; |
} |
} |
|
$fh->close(); |
|
return 0; |
} |
|
#------------------------------------------------------------------------------- |
sub read_log { |
my ($fname) = @_; |
|
if (not -r $fname) { |
print STDERR "xviv_msg_filter-E: \'$fname\' not existing or readable\n"; |
return 1; |
} |
|
open (LFILE, $fname) or die "can't open for read $fname: $!"; |
|
while (<LFILE>) { |
chomp; |
if (m{^(INFO|WARNING|CRITICAL WARNING|ERROR):\s*\[(.+?)\]\s*(.*)}) { |
#print "+++0l '$1' '$2' '$3'\n"; |
push @mlist, [$1,$2,$3,0]; |
} |
} |
|
close (LFILE); |
|
return 0; |
} |
|
#------------------------------------------------------------------------------- |
|
sub print_help { |
print "usage: xviv_msg_filter [options] type mfset log\n"; |
print " type log file type: syn or imp\n"; |
print " mfset message filter set file\n"; |
print " log log file\n"; |
print " Options:\n"; |
print " --pacc print summary of accepted messages\n"; |
print " --help this message\n"; |
} |
trunk/tools/bin/xviv_msg_filter
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/tools/bin/makeise
===================================================================
--- trunk/tools/bin/makeise (nonexistent)
+++ trunk/tools/bin/makeise (revision 36)
@@ -0,0 +1,8 @@
+#!/bin/bash
+# $Id: makeise 761 2016-04-17 08:53:48Z mueller $
+#
+# Copyright 2016- by Walter F.J. Mueller
+# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
+#
+
+exec make -f Makefile.ise "$@"
trunk/tools/bin/makeise
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/tools/dox/w11_vhd_all.Doxyfile
===================================================================
--- trunk/tools/dox/w11_vhd_all.Doxyfile (revision 35)
+++ trunk/tools/dox/w11_vhd_all.Doxyfile (revision 36)
@@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - vhd"
-PROJECT_NUMBER = 0.72
+PROJECT_NUMBER = 0.73
PROJECT_BRIEF = "W11 CPU core and support modules"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd
Index: trunk/tools/dox/w11_cpp.Doxyfile
===================================================================
--- trunk/tools/dox/w11_cpp.Doxyfile (revision 35)
+++ trunk/tools/dox/w11_cpp.Doxyfile (revision 36)
@@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - cpp"
-PROJECT_NUMBER = 0.72
+PROJECT_NUMBER = 0.73
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp
Index: trunk/tools/dox/w11_tcl.Doxyfile
===================================================================
--- trunk/tools/dox/w11_tcl.Doxyfile (revision 35)
+++ trunk/tools/dox/w11_tcl.Doxyfile (revision 36)
@@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - tcl"
-PROJECT_NUMBER = 0.72
+PROJECT_NUMBER = 0.73
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl
Index: trunk/rtl/make_viv/generic_ghdl.mk
===================================================================
--- trunk/rtl/make_viv/generic_ghdl.mk (revision 35)
+++ trunk/rtl/make_viv/generic_ghdl.mk (revision 36)
@@ -1,10 +1,11 @@
-# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $
+# $Id: generic_ghdl.mk 778 2016-06-25 15:18:01Z mueller $
#
-# Copyright 2015- by Walter F.J. Mueller
+# Copyright 2015-2016 by Walter F.J. Mueller
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
+# 2016-06-24 778 1.1 add rsim model; use ghdl.?sim as workdir
# 2015-02-14 646 1.0 Initial version (cloned from make_ise)
#
GHDLIEEE = --ieee=synopsys
@@ -14,12 +15,16 @@
vbomconv --ghdl_i $<
vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $<
#
-# rules for _[o]sim to use 'virtual' [o]sim vbom's (derived from _ssim)
+# rules for _[or]sim to use 'virtual' [or]sim vbom's (derived from _ssim)
#
%_osim : %_ssim.vbom
vbomconv --ghdl_i $*_osim.vbom
vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_osim.vbom
#
+%_rsim : %_ssim.vbom
+ vbomconv --ghdl_i $*_rsim.vbom
+ vbomconv --ghdl_m --xlpath=$(GHDLXLPATH) $*_rsim.vbom
+#
%.dep_ghdl: %.vbom
vbomconv --dep_ghdl $< > $@
#
@@ -29,10 +34,9 @@
#
ghdl_clean: ghdl_tmp_clean
rm -f $(EXE_all)
- rm -f $(EXE_all:%=%_[so]sim)
- rm -f cext_*.o
+ rm -f $(EXE_all:%=%_[sor]sim)
#
ghdl_tmp_clean:
- find -maxdepth 1 -name "*.o" | grep -v "^\./cext_" | xargs rm -f
- rm -f work-obj93.cf
+ rm -rf ghdl.[bsor]sim
+ rm -f cext_*.o e~*.o
#
Index: trunk/rtl/make_viv/generic_xsim.mk
===================================================================
--- trunk/rtl/make_viv/generic_xsim.mk (revision 35)
+++ trunk/rtl/make_viv/generic_xsim.mk (revision 36)
@@ -1,4 +1,4 @@
-# $Id: generic_xsim.mk 733 2016-02-20 12:24:13Z mueller $
+# $Id: generic_xsim.mk 778 2016-06-25 15:18:01Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
@@ -5,6 +5,7 @@
#
# Revision History:
# Date Rev Version Comment
+# 2016-06-24 778 1.1 add [rep]sim models; use xsim.?sim as workdir
# 2016-02-06 727 1.0 Initial version
#
%_XSim : %.vbom
@@ -13,7 +14,7 @@
$*_vsim.sh
rm -rf $*_vsim.sh
#
-# rule to build XSim ssim model from _ssim vbom
+# rule to build XSim ssim model from _ssim vbom (post synth, functional)
#
%_XSim_ssim : %_ssim.vbom
vbomconv -vsim_prj $< > $*_vsim.sh
@@ -21,7 +22,7 @@
$*_vsim.sh
rm -rf $*_vsim.sh
#
-# rule to build XSim osim model from _ssim vbom
+# rule to build XSim osim model from _ssim vbom (post opt, functional)
#
%_XSim_osim : %_ssim.vbom
vbomconv -vsim_prj $*_osim.vbom > $*_vsim.sh
@@ -29,8 +30,32 @@
$*_vsim.sh
rm -rf $*_vsim.sh
#
-# rule to build XSim tsim model from _ssim vbom
+# rule to build XSim rsim model from _ssim vbom (post route, functional)
#
+%_XSim_rsim : %_ssim.vbom
+ vbomconv -vsim_prj $*_rsim.vbom > $*_vsim.sh
+ chmod +x $*_vsim.sh
+ $*_vsim.sh
+ rm -rf $*_vsim.sh
+#
+# rule to build XSim esim model from _ssim vbom (post synth, timing)
+#
+%_XSim_esim : %_ssim.vbom
+ vbomconv -vsim_prj $*_esim.vbom > $*_vsim.sh
+ chmod +x $*_vsim.sh
+ $*_vsim.sh
+ rm -rf $*_vsim.sh
+#
+# rule to build XSim psim model from _ssim vbom (post opt, timing)
+#
+%_XSim_psim : %_ssim.vbom
+ vbomconv -vsim_prj $*_psim.vbom > $*_vsim.sh
+ chmod +x $*_vsim.sh
+ $*_vsim.sh
+ rm -rf $*_vsim.sh
+#
+# rule to build XSim tsim model from _ssim vbom (post rou, timing)
+#
%_XSim_tsim : %_ssim.vbom
vbomconv -vsim_prj $*_tsim.vbom > $*_vsim.sh
chmod +x $*_vsim.sh
@@ -48,13 +73,18 @@
rm -f $(EXE_all:%=%_XSim)
rm -f $(EXE_all:%=%_XSim_ssim)
rm -f $(EXE_all:%=%_XSim_osim)
+ rm -f $(EXE_all:%=%_XSim_rsim)
+ rm -f $(EXE_all:%=%_XSim_esim)
+ rm -f $(EXE_all:%=%_XSim_psim)
rm -f $(EXE_all:%=%_XSim_tsim)
+ rm -rf xsim.[bsorept]sim
#
xsim_tmp_clean:
- rm -f isim.log isim.wdb
- rm -f xsim.jou xsim.log
- rm -f xsim_*.backup.jou xsim_*.backup.log
- rm -f webtalk.jou webtalk.log
- rm -f webtalk_*.backup.jou webtalk_*.backup.log
- rm -rf xsim.dir
+ rm -f *.wdb
+ rm -f xsim.jou xsim_*.backup.jou
+ rm -f xsim.log xsim_*.backup.log
+ rm -f webtalk.jou webtalk_*.backup.jou
+ rm -f webtalk.log webtalk_*.backup.log
+ rm -rf xsim.[bsorept]sim/xsim.dir/xil_defaultlib
+ rm -f xsim.dir
#
Index: trunk/rtl/make_viv/viv_tools_build.tcl
===================================================================
--- trunk/rtl/make_viv/viv_tools_build.tcl (revision 35)
+++ trunk/rtl/make_viv/viv_tools_build.tcl (revision 36)
@@ -1,11 +1,17 @@
-# $Id: viv_tools_build.tcl 738 2016-03-06 13:02:53Z mueller $
+# $Id: viv_tools_build.tcl 767 2016-05-26 07:47:51Z mueller $
#
-# Copyright 2015- by Walter F.J. Mueller
+# Copyright 2015-2016 by Walter F.J. Mueller
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
-# 2016-02-28 649 1.1.1 add 2015.4 specific setups
+# 2016-05-22 767 1.2 cleaner setup handling; use explore flows
+# add 2016.1 specific setups
+# 2016-04-02 758 1.1.5 remove USR_ACCESS setup, must be done in xdc
+# 2016-03-26 752 1.1.4 more steps supported: prj,opt,pla
+# 2016-03-25 751 1.1.3 suppress some messages
+# 2016-03-19 748 1.1.2 set bitstream USR_ACCESS to TIMESTAMP
+# 2016-02-28 738 1.1.1 add 2015.4 specific setups
# 2015-02-21 649 1.1 add 2014.4 specific setups
# 2015-02-14 646 1.0 Initial version
#
@@ -45,6 +51,13 @@
#
# --------------------------------------------------------------------
#
+proc rvtb_rm_file {src} {
+ exec rm -f $src
+}
+
+#
+# --------------------------------------------------------------------
+#
proc rvtb_cp_file {src dst} {
if {[file readable $src]} {
exec cp -p $src $dst
@@ -58,7 +71,6 @@
# --------------------------------------------------------------------
#
proc rvtb_build_check {step} {
- get_msg_config -rules
return ""
}
@@ -65,30 +77,67 @@
#
# --------------------------------------------------------------------
#
+proc rvtb_version_is {val} {
+ set vers [version -short]
+ return [expr {$vers eq $val}]
+}
+#
+# --------------------------------------------------------------------
+#
+proc rvtb_version_min {val} {
+ set vers [version -short]
+ return [expr {[string compare $vers $val] >= 0}]
+}
+
+#
+# --------------------------------------------------------------------
+#
+proc rvtb_version_max {val} {
+ set vers [version -short]
+ return [expr {[string compare $vers $val] <= 0}]
+}
+
+#
+# --------------------------------------------------------------------
+#
+proc rvtb_version_in {min max} {
+ set vers [version -short]
+ return [expr {[string compare $vers $min] >= 0 && \
+ [string compare $vers $max] <= 0}]
+}
+
+#
+# --------------------------------------------------------------------
+#
proc rvtb_default_build {stem step} {
-
- # general setups
- switch [version -short] {
- "2014.4" {
- # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
- # set here to avoid messages during create_project
- set_msg_config -suppress -id {Board 49-26}
- }
- "2015.4" {
- # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html
- set_param synth.elaboration.rodinMoreOptions \
- {rt::set_parameter ignoreVhdlAssertStmts false}
- }
+ # supported step values
+ # prj setup project
+ # syn run synthesis
+ # opt run synthesis + implementation up to step opt_design
+ # pla run synthesis + implementation up to step place_design
+ # imp run synthesis + implementation (but not bit file generation)
+ # bit Synthesize + Implement + generate bit file
+
+ if {![regexp -- {^(prj|syn|opt|pla|imp|bit)$} $step]} {
+ error "bad step name $step"
}
+ # general setups (prior to project creation) ------------------
+ # version dependent setups
+ if {[rvtb_version_is "2014.4"]} {
+ # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
+ # set here to avoid messages during create_project
+ set_msg_config -suppress -id {Board 49-26}
+ }
+
# read setup
set setup_file [rvtb_locate_setup_file $stem]
if {$setup_file ne ""} {source -notrace $setup_file}
- # Create project
+ # Create project ----------------------------------------------
rvtb_trace_cmd "create_project project_mflow ./project_mflow"
- # Setup project properties
+ # Setup project properties -------------------------------
set obj [get_projects project_mflow]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" $::rvtb_part $obj
@@ -95,26 +144,73 @@
set_property "simulator_language" "Mixed" $obj
set_property "target_language" "VHDL" $obj
- # version dependent setups
- switch [version -short] {
- "2014.4" {
- # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
- # repeated here because create_project apparently clears msg_config
- set_msg_config -suppress -id {Board 49-26}
- }
+ # general setups -----------------------------------------
+ # suppress message which don't convey useful information
+ set_msg_config -suppress -id {DRC 23-20}; # DSP48 output pilelining
+ set_msg_config -suppress -id {Project 1-120}; # WebTalk mandatory
+ set_msg_config -suppress -id {Common 17-186}; # WebTalk info send
+
+ # Setup list of extra synthesis options (for later rodinMoreOptions)
+ set synth_more_opts {}
+
+ # version independent setups -----------------------------
+
+ # setup synthesis and implementation strategies
+ set_property strategy Flow_PerfOptimized_high [get_runs synth_1]
+ set_property strategy Performance_Explore [get_runs impl_1]
+
+ # FSM recognition threshold (default is 5)
+ # see http://www.xilinx.com/support/answers/58574.html
+ lappend synth_more_opts {rt::set_parameter minFsmStates 3}
+
+ # version dependent setups -------------------------------
+ if {[rvtb_version_is "2014.4"]} {
+ # suppress nonsense "cannot add Board Part xilinx.com:kc705..." messages
+ # repeated here because create_project apparently clears msg_config
+ set_msg_config -suppress -id {Board 49-26}
}
+ if {[rvtb_version_is "2015.4"]} {
+ # enable vhdl asserts, see http://www.xilinx.com/support/answers/65415.html
+ lappend synth_more_opts {rt::set_parameter ignoreVhdlAssertStmts false}
+ }
+
+ if {[rvtb_version_min "2016.1"]} {
+ # enable vhdl asserts via global option (after 2016.1)
+ set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
+ }
+
+ # now setup extra synthesis options
+ # see http://www.xilinx.com/support/answers/58248.html
+ # -> since used via 'set_param' it's a parameter
+ # -> only last definition counts
+ # -> use ';' separated list
+ # -> these options are **NOT** preserved in project file !!
+ if {[llength $synth_more_opts]} {
+ puts "# extra synthesis options:"
+ foreach opt $synth_more_opts { puts "# $opt"}
+ set_param synth.elaboration.rodinMoreOptions [join $synth_more_opts "; "]
+ }
+
# Setup filesets
set vbom_prj [exec vbomconv -vsyn_prj "${stem}.vbom"]
eval $vbom_prj
update_compile_order -fileset sources_1
+ if {$step eq "prj"} {
+ puts "rvtb_default_build-I: new project setup for ${stem}"
+ return ""
+ }
+
# some handy variables
set path_runs "project_mflow/project_mflow.runs"
set path_syn1 "${path_runs}/synth_1"
set path_imp1 "${path_runs}/impl_1"
- # build: synthesize
+ # build: synthesize ------------------------------------------------
+ puts "# current rodinMoreOptions:"
+ puts [get_param synth.elaboration.rodinMoreOptions]
+
rvtb_trace_cmd "launch_runs synth_1"
rvtb_trace_cmd "wait_on_run synth_1"
@@ -121,49 +217,82 @@
rvtb_mv_file "$path_syn1/runme.log" "${stem}_syn.log"
rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt"
- rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp"
+ rvtb_cp_file "$path_syn1/${stem}.dcp" "${stem}_syn.dcp"
if {$step eq "syn"} {return [rvtb_build_check $step]}
- # build: implement
- rvtb_trace_cmd "launch_runs impl_1"
+ # build: implement -------------------------------------------------
+ set launch_opt ""
+ if {$step eq "opt"} {set launch_opt "-to_step opt_design"}
+ if {$step eq "pla"} {set launch_opt "-to_step place_design"}
+
+ rvtb_trace_cmd "launch_runs ${launch_opt} impl_1"
rvtb_trace_cmd "wait_on_run impl_1"
rvtb_cp_file "$path_imp1/runme.log" "${stem}_imp.log"
+ rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp"
+ rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt"
+
+ if {$step eq "opt"} {
+ rvtb_trace_cmd "open_checkpoint $path_imp1/${stem}_opt.dcp"
+ report_utilization -file "${stem}_opt_util.rpt"
+ report_utilization -hierarchical -file "${stem}_opt_util_h.rpt"
+ return [rvtb_build_check $step]
+ }
+
+ rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp"
+ rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt"
+ rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \
+ "${stem}_pla_util.rpt"
+ rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \
+ "${stem}_pla_clk_set.rpt"
+
+ if {$step eq "pla"} {
+ return [rvtb_build_check $step]
+ }
+
+ rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp"
rvtb_cp_file "$path_imp1/${stem}_route_status.rpt" "${stem}_rou_sta.rpt"
rvtb_cp_file "$path_imp1/${stem}_drc_routed.rpt" "${stem}_rou_drc.rpt"
- rvtb_cp_file "$path_imp1/${stem}_io_placed.rpt" "${stem}_pla_io.rpt"
- rvtb_cp_file "$path_imp1/${stem}_clock_utilization_placed.rpt" \
- "${stem}_pla_clk.rpt"
rvtb_cp_file "$path_imp1/${stem}_timing_summary_routed.rpt" \
"${stem}_rou_tim.rpt"
- rvtb_cp_file "$path_imp1/${stem}_utilization_placed.rpt" \
- "${stem}_pla_util.rpt"
- rvtb_cp_file "$path_imp1/${stem}_drc_opted.rpt" "${stem}_opt_drc.rpt"
- rvtb_cp_file "$path_imp1/${stem}_control_sets_placed.rpt" \
- "${stem}_pla_cset.rpt"
rvtb_cp_file "$path_imp1/${stem}_power_routed.rpt" "${stem}_rou_pwr.rpt"
+ rvtb_cp_file "$path_imp1/${stem}_clock_utilization_routed.rpt" \
+ "${stem}_rou_clk_util.rpt"
- rvtb_cp_file "$path_imp1/${stem}_opt.dcp" "${stem}_opt.dcp"
- rvtb_cp_file "$path_imp1/${stem}_placed.dcp" "${stem}_pla.dcp"
- rvtb_cp_file "$path_imp1/${stem}_routed.dcp" "${stem}_rou.dcp"
-
# additional reports
rvtb_trace_cmd "open_run impl_1"
- report_utilization -file "${stem}_rou_util.rpt"
+ report_utilization -file "${stem}_rou_util.rpt"
report_utilization -hierarchical -file "${stem}_rou_util_h.rpt"
- report_datasheet -file "${stem}_rou_ds.rpt"
+ report_datasheet -file "${stem}_rou_ds.rpt"
+ report_cdc -file "${stem}_rou_cdc.rpt"
+ report_clock_interaction -delay_type min_max -significant_digits 3 \
+ -file "${stem}_rou_clk_int.rpt"
+ if {[get_property SSN_REPORT [get_property PART [current_project]]]} {
+ report_ssn -format TXT -file "${stem}_rou_ssn.rpt"
+ }
if {$step eq "imp"} {return [rvtb_build_check $step]}
- # build: bitstream
+ # build: bitstream -------------------------------------------------
+ # check for critical warnings, e.g.
+ # [Timing 38-282] The design failed to meet the timing requirements.
+ # in that case abort build
+
+ rvtb_rm_file "./${stem}.bit"
+
+ if {[get_msg_config -severity {critical warning} -count]} {
+ puts "rvtb_default_build-E: abort due to critical warnings seen before"
+ puts "rvtb_default_build-E: no bitfile generated"
+ return [rvtb_build_check $step]
+ }
+
rvtb_trace_cmd "launch_runs impl_1 -to_step write_bitstream"
rvtb_trace_cmd "wait_on_run impl_1"
- rvtb_mv_file "$path_imp1/${stem}.bit" "."
- rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log"
+ rvtb_mv_file "$path_imp1/runme.log" "${stem}_bit.log"
+ rvtb_mv_file "$path_imp1/${stem}.bit" "."
return [rvtb_build_check $step]
}
-
/trunk/rtl/make_viv/viv_tools_model.tcl
1,38 → 1,59
# $Id: viv_tools_model.tcl 646 2015-02-15 12:04:55Z mueller $ |
# $Id: viv_tools_model.tcl 778 2016-06-25 15:18:01Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-24 778 1.1 support mode [sor]sim_vhdl [sorepd]sim_veri |
# 2016-06-19 777 1.0.1 use full absolute path name for sdf annotate |
# 2015-02-14 646 1.0 Initial version |
# |
|
# |
# -------------------------------------------------------------------- |
# |
# supported modes |
# base ----- func ----- timing |
# vhdl veri veri |
# post synth _syn.dcp ssim_vhd ssim_v esim_v |
# post phys_opt _opt.dcp osim_vhd osim_v psim_v |
# post route _rou.dcp rsim_vhd rsim_v tsim_v |
# |
proc rvtb_default_model {stem mode} { |
|
switch $mode { |
ssim { |
open_checkpoint "${stem}_syn.dcp" |
write_vhdl -mode funcsim -force "${stem}_ssim.vhd" |
} |
if {[regexp -- {^([sor])sim_(vhd|v)$} $mode matched type lang] || |
[regexp -- {^([ept])sim_(v)$} $mode matched type lang]} { |
|
osim { |
open_checkpoint "${stem}_opt.dcp" |
write_vhdl -mode funcsim -force "${stem}_osim.vhd" |
switch $type { |
s - |
e {open_checkpoint "${stem}_syn.dcp"} |
o - |
p {open_checkpoint "${stem}_opt.dcp"} |
r - |
t {open_checkpoint "${stem}_rou.dcp"} |
} |
|
tsim { |
open_checkpoint "${stem}_rou.dcp" |
write_verilog -mode timesim -force -sdf_anno true "${stem}_tsim.v" |
write_sdf -mode timesim -force "${stem}_tsim.sdf" |
if {$lang eq "vhd"} { |
write_vhdl -mode funcsim -force "${stem}_${type}sim.vhd" |
} else { |
if {$type eq "s" || $type eq "o" || $type eq "r"} { |
write_verilog -mode funcsim -force "${stem}_${type}sim.v" |
} else { |
# use full absolute path name for sdf annotate |
# reason: the _tsim.v is sometimes generated in system path and |
# used from the tb path. xelab doesn't find the sdf in that case |
# Solution are absolute path (ugly) or symlink (ugly, who does setup..) |
write_verilog -mode timesim -force \ |
-sdf_anno true \ |
-sdf_file "[pwd]/${stem}_${type}sim.sdf" \ |
"${stem}_${type}sim.v" |
write_sdf -mode timesim -force \ |
-process_corner slow \ |
"${stem}_${type}sim.sdf" |
} |
} |
|
default { |
error "-E: bad mode: $mode"; |
} |
} else { |
error "rvtb_default_model-E: bad mode: $mode"; |
} |
|
return ""; |
} |
/trunk/rtl/make_viv/generic_vivado.mk
1,10 → 1,14
# $Id: generic_vivado.mk 733 2016-02-20 12:24:13Z mueller $ |
# $Id: generic_vivado.mk 778 2016-06-25 15:18:01Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-24 778 1.3 add rsim.vhd and [sorep]sim.v targets |
# 2016-06-11 774 1.2.1 call xviv_sim_vhdl_cleanup for %_[so]sim rules |
# 2016-05-27 769 1.2 add xviv_msg_filter support |
# 2016-03-26 752 1.1 new %.vivado; separate %_opt.dcp,%_pla.dcp,%_rou.dcp |
# 2015-02-15 646 1.0 Initial version |
# 2015-01-25 637 0.1 First draft |
#--- |
37,6 → 41,18
# when chaining, don't delete 'expensive' intermediate files: |
.SECONDARY : |
# |
# Setup vivado project |
# input: %.vbom vbom project description |
# output: .PHONY |
# |
%.vivado : %.vbom |
rm -rf project_mflow |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_BOARD_SETUP} \ |
-source ${VIV_BUILD_FLOW} \ |
-tclargs $* prj |
# |
# Synthesize + Implement -> generate bit file |
# input: %.vbom vbom project description |
# output: %.bit |
48,7 → 64,21
-source ${VIV_BOARD_SETUP} \ |
-source ${VIV_BUILD_FLOW} \ |
-tclargs $* bit |
@ if [ -r $*.vmfset ]; then make $*.mfsum; fi |
# |
# Print log file summary |
# input: %_*.log (not depended) |
# output: .PHONY |
%.mfsum: %.vmfset |
@ echo "=== Synthesis flow summary ==================================" |
@ if [ -r $*_syn.log ]; \ |
then xviv_msg_filter syn $*.vmfset $*_syn.log; \ |
else echo " !!! no $*_syn.log found"; fi |
@ echo "=== Implementation flow summary==============================" |
@ if [ -r $*_imp.log ]; \ |
then xviv_msg_filter imp $*.vmfset $*_imp.log; \ |
else echo " !!! no $*_imp.log found"; fi |
# |
# Configure FPGA with vivado hardware server |
# input: %.bit |
# output: .PHONY |
62,6 → 92,7
# |
# Partial Synthesize + Implement -> generate dcp for model generation |
# |
# run synthesis only |
%_syn.dcp : %.vbom |
rm -rf project_mflow |
xtwv vivado -mode batch \ |
69,12 → 100,32
-source ${VIV_BOARD_SETUP} \ |
-source ${VIV_BUILD_FLOW} \ |
-tclargs $* syn |
%_opt.dcp %_rou.dcp : %.vbom |
# |
# run synthesis + implementation up to step opt_design |
%_opt.dcp : %.vbom |
rm -rf project_mflow |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_BOARD_SETUP} \ |
-source ${VIV_BUILD_FLOW} \ |
-tclargs $* opt |
# |
# run synthesis + implementation up to step place_design |
%_pla.dcp : %.vbom |
rm -rf project_mflow |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_BOARD_SETUP} \ |
-source ${VIV_BUILD_FLOW} \ |
-tclargs $* pla |
# |
# run synthesis + implementation (but not bit file generation) |
%_rou.dcp : %.vbom |
rm -rf project_mflow |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_BOARD_SETUP} \ |
-source ${VIV_BUILD_FLOW} \ |
-tclargs $* imp |
# |
# Post-synthesis functional simulation model (Vhdl/Unisim) |
85,7 → 136,8
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* ssim |
-tclargs $* ssim_vhd |
xviv_sim_vhdl_cleanup $@ |
# |
# Post-optimization functional simulation model (Vhdl/Unisim) |
# input: %_opt.dcp |
95,8 → 147,72
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* osim |
-tclargs $* osim_vhd |
xviv_sim_vhdl_cleanup $@ |
# |
# Post-routing functional simulation model (Vhdl/Unisim) |
# input: %_rou.dcp |
# output: %_rsim.vhd |
# |
%_rsim.vhd : %_rou.dcp |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* rsim_vhd |
xviv_sim_vhdl_cleanup $@ |
# |
# Post-synthesis functional simulation model (Verilog/Unisim) |
# input: %_syn.dcp |
# output: %_ssim.v |
# |
%_ssim.v : %_syn.dcp |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* ssim_v |
# |
# Post-optimization functional simulation model (Verilog/Unisim) |
# input: %_opt.dcp |
# output: %_osim.v |
# |
%_osim.v : %_opt.dcp |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* osim_v |
# |
# Post-routing functional simulation model (Verilog/Unisim) |
# input: %_rou.dcp |
# output: %_rsim.v |
# |
%_rsim.v : %_rou.dcp |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* rsim_v |
# |
# Post-synthesis timing simulation model (Verilog/Simprim) |
# input: %_syn.dcp |
# output: %_esim.v |
# %_esim.sdf |
# |
%_esim.v %_esim.sdf : %_syn.dcp |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* esim_v |
# |
# Post-optimization timing simulation model (Verilog/Simprim) |
# input: %_opt.dcp |
# output: %_psim.v |
# %_psim.sdf |
# |
%_psim.v %_psim.sdf : %_opt.dcp |
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* psim_v |
# |
# Post-routing timing simulation model (Verilog/Simprim) |
# input: %_rou.dcp |
# output: %_tsim.v |
106,7 → 222,7
xtwv vivado -mode batch \ |
-source ${VIV_INIT} \ |
-source ${VIV_MODEL_FLOW} \ |
-tclargs $* tsim |
-tclargs $* tsim_v |
# |
# vivado project quick starter |
# |
133,9 → 249,9
rm -f *.jou |
rm -f *.log |
rm -f *.rpt |
rm -f *_[so]sim.vhd |
rm -f *_tsim.v |
rm -f *_tsim.sdf |
rm -f *_[sor]sim.vhd |
rm -f *_[sorept]sim.v |
rm -f *_[ept]sim.sdf |
# |
viv_tmp_clean: |
rm -rf ./project_mflow |
/trunk/rtl/make_viv/viv_tools_config.tcl
1,10 → 1,11
# $Id: viv_tools_config.tcl 646 2015-02-15 12:04:55Z mueller $ |
# $Id: viv_tools_config.tcl 758 2016-04-02 18:01:39Z mueller $ |
# |
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-04-02 758 1.1 add USR_ACCESS readback |
# 2015-02-14 646 1.0 Initial version |
# |
|
11,6 → 12,19
# |
# -------------------------------------------------------------------- |
# |
proc rvtb_format_usracc {usracc} { |
set sec [expr { ($usracc >> 0) & 0x3f } ]; # 6 bit 05:00 |
set min [expr { ($usracc >> 6) & 0x3f } ]; # 6 bit 11:06 |
set hr [expr { ($usracc >> 12) & 0x1f } ]; # 5 bit 16:12 |
set yr [expr {(($usracc >> 17) & 0x3f)+2000} ]; # 6 bit 22:17 |
set mo [expr { ($usracc >> 23) & 0x0f } ]; # 4 bit 26:23 |
set day [expr { ($usracc >> 27) & 0x1f } ]; # 5 bit 31:27 |
return [format "%04d-%02d-%02d %02d:%02d:%02d" $yr $mo $day $hr $min $sec] |
} |
|
# |
# -------------------------------------------------------------------- |
# |
proc rvtb_default_config {stem} { |
# open and connect to hardware server |
open_hw |
25,5 → 39,13
# and configure FPGA |
program_hw_devices [lindex [get_hw_devices] 0] |
|
# and check USR_ACCESS setting |
set usracc_raw [get_property REGISTER.USR_ACCESS [lindex [get_hw_devices] 0] ] |
set usracc_num "0x$usracc_raw" |
set usracc_fmt [rvtb_format_usracc $usracc_num] |
puts "" |
puts "USR_ACCESS: 0x$usracc_raw $usracc_fmt" |
puts "" |
|
return ""; |
} |
/trunk/rtl/ibus/Makefile
File deleted
/trunk/rtl/ibus/ibdr_rk11.vbom
4,6 → 4,7
iblib.vhd |
# components |
[sim]../vlib/memlib/ram_1swar_gen.vbom |
[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom |
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom |
[vsyn]../vlib/memlib/ram_1swar_gen.vbom |
# design |
ibdr_rk11.vhd |
/trunk/rtl/ibus/ibd_ibmon.vbom
4,6 → 4,7
iblib.vhd |
# components |
[sim]../vlib/memlib/ram_1swsr_wfirst_gen.vbom |
[xst,vsyn]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom |
[xst]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom |
[vsyn]../vlib/memlib/ram_1swsr_wfirst_gen.vbom |
# design |
ibd_ibmon.vhd |
/trunk/rtl/ibus/ibdr_rk11.vhd
1,6 → 1,6
-- $Id: ibdr_rk11.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: ibdr_rk11.vhd 767 2016-05-26 07:47:51Z mueller $ |
-- |
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
18,7 → 18,7
-- Dependencies: ram_1swar_gen |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
29,6 → 29,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-22 787 1.3.1 don't init N_REGS (vivado fix for fsm inference) |
-- 2015-05-01 672 1.3 BUGFIX: interrupt after dreset,seek command start |
-- 2011-11-18 427 1.2.2 now numeric_std clean |
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM; |
168,7 → 169,7
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) |
|
signal MEM_1_WE : slbit := '0'; |
signal MEM_0_WE : slbit := '0'; |
/trunk/rtl/ibus/ibdr_rl11.vhd
1,6 → 1,6
-- $Id: ibdr_rl11.vhd 655 2015-03-04 20:35:21Z mueller $ |
-- $Id: ibdr_rl11.vhd 767 2016-05-26 07:47:51Z mueller $ |
-- |
-- Copyright 2014-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
18,7 → 18,7
-- Dependencies: ram_1swar_gen |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 |
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
27,6 → 27,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-22 787 1.0.2 don't init N_REGS (vivado fix for fsm inference) |
-- 2015-03-04 655 1.0.1 seek: ignore da(6:5), don't check for 0 anymore |
-- 2015-02-28 653 1.0 Initial verison |
-- 2014-06-09 561 0.1 First draft |
238,7 → 239,7
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) |
|
signal MEM_1_WE : slbit := '0'; |
signal MEM_0_WE : slbit := '0'; |
/trunk/rtl/ibus/iblib.vhd
1,6 → 1,6
-- $Id: iblib.vhd 672 2015-05-02 21:58:28Z mueller $ |
-- $Id: iblib.vhd 770 2016-05-28 14:15:00Z mueller $ |
-- |
-- Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
16,9 → 16,10
-- Description: Definitions for ibus interface and bus entities |
-- |
-- Dependencies: - |
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type |
-- 2015-04-24 668 2.1 add ibd_ibmon |
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon |
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw |
115,8 → 116,8
end component; |
|
type intmap_type is record -- interrupt map entry type |
vec : integer; -- vector address |
pri : integer; -- priority |
vec : natural; -- vector address |
pri : natural; -- priority |
end record intmap_type; |
constant intmap_init : intmap_type := (0,0); |
|
/trunk/rtl/ibus/ibd_iist.vhd
1,6 → 1,6
-- $Id: ibd_iist.vhd 641 2015-02-01 22:12:15Z mueller $ |
-- $Id: ibd_iist.vhd 767 2016-05-26 07:47:51Z mueller $ |
-- |
-- Copyright 2009-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2009-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
18,7 → 18,7
-- Dependencies: - |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31 |
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
29,6 → 29,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-22 787 0.8.2 don't init N_REGS (vivado fix for fsm inference) |
-- 2011-11-18 427 0.8.1 now numeric_std clean |
-- 2010-10-17 333 0.8 use ibus V2 interface |
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im |
218,7 → 219,7
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) |
|
begin |
|
/trunk/rtl/ibus/ibdr_rl11.vbom
4,6 → 4,7
iblib.vhd |
# components |
[sim]../vlib/memlib/ram_1swar_gen.vbom |
[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom |
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom |
[vsyn]../vlib/memlib/ram_1swar_gen.vbom |
# design |
ibdr_rl11.vhd |
/trunk/rtl/ibus/ibdr_rhrp.vhd
1,6 → 1,6
-- $Id: ibdr_rhrp.vhd 692 2015-06-21 11:53:24Z mueller $ |
-- $Id: ibdr_rhrp.vhd 767 2016-05-26 07:47:51Z mueller $ |
-- |
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
18,7 → 18,7
-- Dependencies: ram_1swar_gen |
-- Test bench: - |
-- Target Devices: generic |
-- Tool versions: ise 14.7; viv 2014.4; ghdl 0.31 |
-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
28,6 → 28,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-22 787 1.0.4 don't init N_REGS (vivado fix for fsm inference) |
-- 2015-06-20 692 1.0.3 BUGFIX: fix func-go when drive/init busy checks |
-- 2015-06-05 690 1.0.2 use 'not unit' for lsb of rpsn to avoid SI detect |
-- BUGFIX: set rmr only for write to busy unit |
401,7 → 402,7
); |
|
signal R_REGS : regs_type := regs_init; |
signal N_REGS : regs_type := regs_init; |
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer) |
|
signal MEM_1_WE : slbit := '0'; |
signal MEM_0_WE : slbit := '0'; |
/trunk/rtl/ibus/Makefile.ise
0,0 → 1,32
# -*- makefile-gmake -*- |
# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2014-07-27 545 1.1.1 make reference board configurable via XTW_BOARD |
# 2011-08-13 405 1.1 use includes from rtl/make |
# 2008-08-22 161 1.0 Initial version |
# |
VBOM_all = $(wildcard *.vbom) |
NGC_all = $(VBOM_all:.vbom=.ngc) |
# |
# reference board for test synthesis is Spartan-6 based Nexys3 |
ifndef XTW_BOARD |
XTW_BOARD=nexys3 |
endif |
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk |
# |
.PHONY : all clean |
# |
all : $(NGC_all) |
# |
clean : ise_clean |
# |
#---- |
# |
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
endif |
# |
/trunk/rtl/ibus/ibdr_rhrp.vbom
4,6 → 4,7
iblib.vhd |
# components |
[sim]../vlib/memlib/ram_1swar_gen.vbom |
[xst,vsyn]../vlib/memlib/ram_1swar_gen_unisim.vbom |
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom |
[vsyn]../vlib/memlib/ram_1swar_gen.vbom |
# design |
ibdr_rhrp.vhd |
/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vhd
File deleted
/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop.c
File deleted
/trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop.vbom
File deleted
/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/.cvsignore
File deleted
/trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic/Makefile
File deleted
trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic
Property changes :
Deleted: svn:ignore
## -1,43 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
-sys_tst_fx2loop_ic_n2.ucf
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.ucf_cpp (nonexistent)
@@ -1,15 +0,0 @@
-## $Id: sys_tst_fx2loop_ic3_n2.ucf_cpp 453 2012-01-15 17:51:18Z mueller $
-##
-## Revision History:
-## Date Rev Version Comment
-## 2011-12-26 445 1.0 Initial version
-##
-
-NET "I_CLK50" TNM_NET = "I_CLK50";
-TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
-OFFSET = IN 10 ns BEFORE "I_CLK50";
-OFFSET = OUT 20 ns AFTER "I_CLK50";
-
-#include "bplib/nexys2/nexys2_pins.ucf"
-#include "bplib/nexys2/nexys2_pins_fx2.ucf"
-#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/.cvsignore (nonexistent)
@@ -1 +0,0 @@
-sys_tst_fx2loop_ic3_n2.ucf
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/Makefile (nonexistent)
@@ -1,30 +0,0 @@
-# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
-#
-# Revision History:
-# Date Rev Version Comment
-# 2012-01-15 453 1.0 Initial version
-#
-#
-VBOM_all = $(wildcard *.vbom)
-BIT_all = $(VBOM_all:.vbom=.bit)
-#
-include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk
-FX2_FILE = nexys2_jtag_3fifo_ic.ihx
-#
-.PHONY : all clean
-#
-all : $(BIT_all)
-#
-clean : ise_clean
- rm -f $(VBOM_all:.vbom=.ucf)
-#
-#----
-#
-include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
-include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
-#
-ifndef DONTINCDEP
-include $(VBOM_all:.vbom=.dep_xst)
-include $(VBOM_all:.vbom=.dep_ghdl)
-endif
-#
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.vbom (nonexistent)
@@ -1,8 +0,0 @@
-# conf
-sys_conf = sys_conf.vhd
-# libs
-# components
-# design
-../sys_tst_fx2loop_n2.vbom
-@ucf_cpp: sys_tst_fx2loop_ic3_n2.ucf
-@top: sys_tst_fx2loop_n2
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_conf.vhd (nonexistent)
@@ -1,58 +0,0 @@
--- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
---
--- Copyright 2012- by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Package Name: sys_conf
--- Description: Definitions for sys_tst_fx2loop_ic3_n2 (for synthesis)
---
--- Dependencies: -
--- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--- Revision History:
--- Date Rev Version Comment
--- 2012-01-15 453 1.0 Initial version
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.slvtypes.all;
-
-package sys_conf is
-
- constant sys_conf_clkfx_divide : positive := 1;
- constant sys_conf_clkfx_multiply : positive := 2;
-
- constant sys_conf_fx2_type : string := "ic3";
-
- -- dummy values defs for generic parameters of as controller
- constant sys_conf_fx2_rdpwldelay : positive := 1;
- constant sys_conf_fx2_rdpwhdelay : positive := 1;
- constant sys_conf_fx2_wrpwldelay : positive := 1;
- constant sys_conf_fx2_wrpwhdelay : positive := 1;
- constant sys_conf_fx2_flagdelay : positive := 1;
-
- -- pktend timer setting
- -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
- constant sys_conf_fx2_petowidth : positive := 10;
-
- constant sys_conf_fx2_ccwidth : positive := 5;
-
- constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-
- -- derived constants
-
- constant sys_conf_clksys : integer :=
- (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
- constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
-
-end package sys_conf;
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2.mfset (nonexistent)
@@ -1,58 +0,0 @@
-# $Id: sys_tst_fx2loop_ic3_n2.mfset 453 2012-01-15 17:51:18Z mueller $
-#
-# ----------------------------------------------------------------------------
-[xst]
-INFO:.*Mux is complete : default of case is discarded
-
-Unconnected output port 'LOCKED' of component 'dcm_sfs'
-Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
-
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-
-Input is never used
-Input > is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-
-Signal is assigned but never used
-Signal is assigned but never used
-Signal is assigned but never used
-
-#
-# ----------------------------------------------------------------------------
-[tra]
-INFO:.* - TNM 'I_CLK50', used in period specification.*was traced into DCM_SP
-The Offset constraint .*, is specified without a duration
-
-#
-# ----------------------------------------------------------------------------
-[map]
-The signal is incomplete
-The signal _IBUF> is incomplete
-The signal _IBUF> is incomplete
-The signal _IBUF> is incomplete
-INFO:.*
-
-#
-# ----------------------------------------------------------------------------
-[par]
-A clock IOB / clock component pair have been found that are not placed at
-The Offset constraint .*, is specified without a duration
-The signal I_MEM_WAIT_IBUF has no load
-The signal I_BTN<1>_IBUF has no load
-The signal I_BTN<2>_IBUF has no load
-The signal I_BTN<3>_IBUF has no load
-There are 4 loadless signals in this design
-
-#
-# ----------------------------------------------------------------------------
-[bgn]
-Spartan-3 1200E and 1600E devices do not support bitstream
-To achieve optimal frequency synthesis performance .* consult
-The signal is incomplete
-The signal _IBUF> is incomplete
-The signal _IBUF> is incomplete
-The signal _IBUF> is incomplete
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3 (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3 (nonexistent)
trunk/rtl/sys_gen/tst_fx2loop/nexys2/ic3
Property changes :
Deleted: svn:ignore
## -1,43 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
-sys_tst_fx2loop_ic3_n2.ucf
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vhd (nonexistent)
@@ -1,316 +0,0 @@
--- $Id: sys_tst_fx2loop_n2.vhd 649 2015-02-21 21:10:16Z mueller $
---
--- Copyright 2011-2015 by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Module Name: sys_tst_fx2loop_n2 - syn
--- Description: test of Cypress EZ-USB FX2 controller
---
--- Dependencies: vlib/xlib/dcm_sfs
--- vlib/genlib/clkdivce
--- bpgen/sn_humanio
--- tst_fx2loop_hiomap
--- tst_fx2loop
--- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
--- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
--- bplib/nxcramlib/nx_cram_dummy
---
--- Test bench: -
---
--- Target Devices: generic
--- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
---
--- Synthesized (xst):
--- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
--- 2012-04-09 461 13.3 O76d xc3s1200e-4 307 390 64 325 p 9.9 as2/100
--- 2012-04-09 461 13.3 O76d xc3s1200e-4 358 419 64 369 p 9.4 ic2/100
--- 2012-04-09 461 13.3 O76c xc3s1200e-4 436 537 96 476 p 8.9 ic3/100
---
--- Revision History:
--- Date Rev Version Comment
--- 2015-01-25 638 1.1.1 retire fx2_2fifoctl_as
--- 2012-01-15 453 1.1 now generic for as,ic,ic3 controllers
--- 2011-12-26 445 1.0 Initial version
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.slvtypes.all;
-use work.xlib.all;
-use work.genlib.all;
-use work.bpgenlib.all;
-use work.tst_fx2looplib.all;
-use work.fx2lib.all;
-use work.nxcramlib.all;
-use work.sys_conf.all;
-
--- ----------------------------------------------------------------------------
-
-entity sys_tst_fx2loop_n2 is -- top level
- -- implements nexys2_aif + fx2 pins
- port (
- I_CLK50 : in slbit; -- 50 MHz board clock
- I_RXD : in slbit; -- receive data (board view)
- O_TXD : out slbit; -- transmit data (board view)
- I_SWI : in slv8; -- n2 switches
- I_BTN : in slv4; -- n2 buttons
- O_LED : out slv8; -- n2 leds
- O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
- O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
- O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
- O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
- O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
- O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
- O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
- O_MEM_CLK : out slbit; -- cram: clock
- O_MEM_CRE : out slbit; -- cram: command register enable
- I_MEM_WAIT : in slbit; -- cram: mem wait
- O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16; -- cram: data lines
- O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
- I_FX2_IFCLK : in slbit; -- fx2: interface clock
- O_FX2_FIFO : out slv2; -- fx2: fifo address
- I_FX2_FLAG : in slv4; -- fx2: fifo flags
- O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
- O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
- O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
- O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
- IO_FX2_DATA : inout slv8 -- fx2: data lines
- );
-end sys_tst_fx2loop_n2;
-
-architecture syn of sys_tst_fx2loop_n2 is
-
- signal CLK : slbit := '0';
- signal RESET : slbit := '0';
-
- signal CE_USEC : slbit := '0';
- signal CE_MSEC : slbit := '0';
-
- signal SWI : slv8 := (others=>'0');
- signal BTN : slv4 := (others=>'0');
- signal LED : slv8 := (others=>'0');
- signal DSP_DAT : slv16 := (others=>'0');
- signal DSP_DP : slv4 := (others=>'0');
-
- signal LED_MAP : slv8 := (others=>'0');
-
- signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
- signal HIO_STAT : hio_stat_type := hio_stat_init;
-
- signal FX2_RXDATA : slv8 := (others=>'0');
- signal FX2_RXVAL : slbit := '0';
- signal FX2_RXHOLD : slbit := '0';
- signal FX2_RXAEMPTY : slbit := '0';
- signal FX2_TXDATA : slv8 := (others=>'0');
- signal FX2_TXENA : slbit := '0';
- signal FX2_TXBUSY : slbit := '0';
- signal FX2_TXAFULL : slbit := '0';
- signal FX2_TX2DATA : slv8 := (others=>'0');
- signal FX2_TX2ENA : slbit := '0';
- signal FX2_TX2BUSY : slbit := '1';
- signal FX2_TX2AFULL : slbit := '0';
- signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
-
-begin
-
- assert (sys_conf_clksys mod 1000000) = 0
- report "assert sys_conf_clksys on MHz grid"
- severity failure;
-
- DCM : dcm_sfs
- generic map (
- CLKFX_DIVIDE => sys_conf_clkfx_divide,
- CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
- CLKIN_PERIOD => 20.0)
- port map (
- CLKIN => I_CLK50,
- CLKFX => CLK,
- LOCKED => open
- );
-
- CLKDIV : clkdivce
- generic map (
- CDUWIDTH => 7, -- good for up to 127 MHz !
- USECDIV => sys_conf_clksys_mhz,
- MSECDIV => 1000)
- port map (
- CLK => CLK,
- CE_USEC => CE_USEC,
- CE_MSEC => CE_MSEC
- );
-
- HIO : sn_humanio
- generic map (
- DEBOUNCE => sys_conf_hio_debounce)
- port map (
- CLK => CLK,
- RESET => '0',
- CE_MSEC => CE_MSEC,
- SWI => SWI,
- BTN => BTN,
- LED => LED,
- DSP_DAT => DSP_DAT,
- DSP_DP => DSP_DP,
- I_SWI => I_SWI,
- I_BTN => I_BTN,
- O_LED => O_LED,
- O_ANO_N => O_ANO_N,
- O_SEG_N => O_SEG_N
- );
-
- RESET <= BTN(0); -- BTN(0) will reset tester !!
-
- HIOMAP : tst_fx2loop_hiomap
- port map (
- CLK => CLK,
- RESET => RESET,
- HIO_CNTL => HIO_CNTL,
- HIO_STAT => HIO_STAT,
- FX2_MONI => FX2_MONI,
- SWI => SWI,
- BTN => BTN,
- LED => LED_MAP,
- DSP_DAT => DSP_DAT,
- DSP_DP => DSP_DP
- );
-
- proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
- FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
- begin
-
- if SWI(4) = '1' then
- LED(7) <= '0';
- LED(6) <= '0';
- LED(5) <= FX2_TX2BUSY;
- LED(4) <= FX2_TX2ENA;
- LED(3) <= FX2_TXBUSY;
- LED(2) <= FX2_TXENA;
- LED(1) <= FX2_RXHOLD;
- LED(0) <= FX2_RXVAL;
- else
- LED <= LED_MAP;
- end if;
-
- end process proc_led;
-
-
- TST : tst_fx2loop
- port map (
- CLK => CLK,
- RESET => RESET,
- CE_MSEC => CE_MSEC,
- HIO_CNTL => HIO_CNTL,
- HIO_STAT => HIO_STAT,
- FX2_MONI => FX2_MONI,
- RXDATA => FX2_RXDATA,
- RXVAL => FX2_RXVAL,
- RXHOLD => FX2_RXHOLD,
- TXDATA => FX2_TXDATA,
- TXENA => FX2_TXENA,
- TXBUSY => FX2_TXBUSY,
- TX2DATA => FX2_TX2DATA,
- TX2ENA => FX2_TX2ENA,
- TX2BUSY => FX2_TX2BUSY
- );
-
- FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
- CNTL : fx2_2fifoctl_ic
- generic map (
- RXFAWIDTH => 5,
- TXFAWIDTH => 5,
- PETOWIDTH => sys_conf_fx2_petowidth,
- CCWIDTH => sys_conf_fx2_ccwidth,
- RXAEMPTY_THRES => 1,
- TXAFULL_THRES => 1)
- port map (
- CLK => CLK,
- RESET => RESET,
- RXDATA => FX2_RXDATA,
- RXVAL => FX2_RXVAL,
- RXHOLD => FX2_RXHOLD,
- RXAEMPTY => FX2_RXAEMPTY,
- TXDATA => FX2_TXDATA,
- TXENA => FX2_TXENA,
- TXBUSY => FX2_TXBUSY,
- TXAFULL => FX2_TXAFULL,
- MONI => FX2_MONI,
- I_FX2_IFCLK => I_FX2_IFCLK,
- O_FX2_FIFO => O_FX2_FIFO,
- I_FX2_FLAG => I_FX2_FLAG,
- O_FX2_SLRD_N => O_FX2_SLRD_N,
- O_FX2_SLWR_N => O_FX2_SLWR_N,
- O_FX2_SLOE_N => O_FX2_SLOE_N,
- O_FX2_PKTEND_N => O_FX2_PKTEND_N,
- IO_FX2_DATA => IO_FX2_DATA
- );
- end generate FX2_CNTL_IC;
-
- FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
- CNTL : fx2_3fifoctl_ic
- generic map (
- RXFAWIDTH => 5,
- TXFAWIDTH => 5,
- PETOWIDTH => sys_conf_fx2_petowidth,
- CCWIDTH => sys_conf_fx2_ccwidth,
- RXAEMPTY_THRES => 1,
- TXAFULL_THRES => 1,
- TX2AFULL_THRES => 1)
- port map (
- CLK => CLK,
- RESET => RESET,
- RXDATA => FX2_RXDATA,
- RXVAL => FX2_RXVAL,
- RXHOLD => FX2_RXHOLD,
- RXAEMPTY => FX2_RXAEMPTY,
- TXDATA => FX2_TXDATA,
- TXENA => FX2_TXENA,
- TXBUSY => FX2_TXBUSY,
- TXAFULL => FX2_TXAFULL,
- TX2DATA => FX2_TX2DATA,
- TX2ENA => FX2_TX2ENA,
- TX2BUSY => FX2_TX2BUSY,
- TX2AFULL => FX2_TX2AFULL,
- MONI => FX2_MONI,
- I_FX2_IFCLK => I_FX2_IFCLK,
- O_FX2_FIFO => O_FX2_FIFO,
- I_FX2_FLAG => I_FX2_FLAG,
- O_FX2_SLRD_N => O_FX2_SLRD_N,
- O_FX2_SLWR_N => O_FX2_SLWR_N,
- O_FX2_SLOE_N => O_FX2_SLOE_N,
- O_FX2_PKTEND_N => O_FX2_PKTEND_N,
- IO_FX2_DATA => IO_FX2_DATA
- );
- end generate FX2_CNTL_IC3;
-
- SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
- port map (
- O_MEM_CE_N => O_MEM_CE_N,
- O_MEM_BE_N => O_MEM_BE_N,
- O_MEM_WE_N => O_MEM_WE_N,
- O_MEM_OE_N => O_MEM_OE_N,
- O_MEM_ADV_N => O_MEM_ADV_N,
- O_MEM_CLK => O_MEM_CLK,
- O_MEM_CRE => O_MEM_CRE,
- I_MEM_WAIT => I_MEM_WAIT,
- O_MEM_ADDR => O_MEM_ADDR,
- IO_MEM_DATA => IO_MEM_DATA
- );
-
- O_FLA_CE_N <= '1'; -- keep Flash memory disabled
-
- O_TXD <= I_RXD; -- loop-back in serial port...
-
-end syn;
-
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2/sys_tst_fx2loop_n2.vbom (nonexistent)
@@ -1,28 +0,0 @@
-# this is the vbom for the 'generic' top level entity
-# to be referenced in the vbom's of the specific systems
-# ./ic/sys_tst_fx2loop_ic_n2
-# ./ic3/sys_tst_fx2loop_ic3_n2
-#
-# libs
-../../../vlib/slvtypes.vhd
-../../../vlib/xlib/xlib.vhd
-../../../vlib/genlib/genlib.vhd
-../../../bplib/bpgen/bpgenlib.vbom
-../tst_fx2looplib.vbom
-../../../bplib/fx2lib/fx2lib.vhd
-../../../bplib/nxcramlib/nxcramlib.vhd
-${sys_conf}
-# components
-[xst,vsyn]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
-[ghdl,isim,vsim]../../../vlib/xlib/dcm_sfs_gsim.vbom
-../../../vlib/genlib/clkdivce.vbom
-../../../bplib/bpgen/sn_humanio.vbom
-../tst_fx2loop_hiomap.vbom
-../tst_fx2loop.vbom
-../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
-../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
-../../../bplib/nxcramlib/nx_cram_dummy.vbom
-# design
-sys_tst_fx2loop_n2.vhd
-## no @ucf_cpp
-
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys2
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys2 (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys2 (nonexistent)
trunk/rtl/sys_gen/tst_fx2loop/nexys2
Property changes :
Deleted: svn:ignore
## -1,42 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.vbom (nonexistent)
@@ -1,8 +0,0 @@
-# conf
-sys_conf = sys_conf.vhd
-# libs
-# components
-# design
-../sys_tst_fx2loop_n3.vbom
-@ucf_cpp: sys_tst_fx2loop_ic3_n3.ucf
-@top: sys_tst_fx2loop_n3
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd (nonexistent)
@@ -1,63 +0,0 @@
--- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
---
--- Copyright 2012-2013 by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Package Name: sys_conf
--- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis)
---
--- Dependencies: -
--- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--- Revision History:
--- Date Rev Version Comment
--- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
--- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk
--- 2012-04-09 461 1.0 Initial version
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.slvtypes.all;
-
-package sys_conf is
-
- constant sys_conf_clksys_vcodivide : positive := 2;
- constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
- constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
- constant sys_conf_clksys_gentype : string := "DCM";
-
- constant sys_conf_fx2_type : string := "ic3";
-
- -- dummy values defs for generic parameters of as controller
- constant sys_conf_fx2_rdpwldelay : positive := 1;
- constant sys_conf_fx2_rdpwhdelay : positive := 1;
- constant sys_conf_fx2_wrpwldelay : positive := 1;
- constant sys_conf_fx2_wrpwhdelay : positive := 1;
- constant sys_conf_fx2_flagdelay : positive := 1;
-
- -- pktend timer setting
- -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
- constant sys_conf_fx2_petowidth : positive := 10;
-
- constant sys_conf_fx2_ccwidth : positive := 5;
-
- constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-
- -- derived constants
-
- constant sys_conf_clksys : integer :=
- ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
- sys_conf_clksys_outdivide;
- constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
-
-end package sys_conf;
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/.cvsignore (nonexistent)
@@ -1 +0,0 @@
-sys_tst_fx2loop_ic3_n3.ucf
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_tst_fx2loop_ic3_n3.ucf_cpp (nonexistent)
@@ -1,20 +0,0 @@
-## $Id: sys_tst_fx2loop_ic3_n3.ucf_cpp 461 2012-04-09 21:17:54Z mueller $
-##
-## Revision History:
-## Date Rev Version Comment
-## 2012-04-09 461 1.0 Initial version
-##
-
-NET "I_CLK100" TNM_NET = "I_CLK100";
-TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
-OFFSET = IN 10 ns BEFORE "I_CLK100";
-OFFSET = OUT 20 ns AFTER "I_CLK100";
-
-## std board
-##
-#include "bplib/nexys3/nexys3_pins.ucf"
-##
-## FX2 interface
-##
-#include "bplib/nexys3/nexys3_pins_fx2.ucf"
-#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3/Makefile (nonexistent)
@@ -1,30 +0,0 @@
-# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
-#
-# Revision History:
-# Date Rev Version Comment
-# 2012-04-09 461 1.0 Initial version
-#
-#
-VBOM_all = $(wildcard *.vbom)
-BIT_all = $(VBOM_all:.vbom=.bit)
-#
-include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk
-FX2_FILE = nexys3_jtag_3fifo_ic.ihx
-#
-.PHONY : all clean
-#
-all : $(BIT_all)
-#
-clean : ise_clean
- rm -f $(VBOM_all:.vbom=.ucf)
-#
-#----
-#
-include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
-include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
-#
-ifndef DONTINCDEP
-include $(VBOM_all:.vbom=.dep_xst)
-include $(VBOM_all:.vbom=.dep_ghdl)
-endif
-#
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3 (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3 (nonexistent)
trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic3
Property changes :
Deleted: svn:ignore
## -1,43 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
-sys_tst_fx2loop_ic3_n3.ucf
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd (nonexistent)
@@ -1,330 +0,0 @@
--- $Id: sys_tst_fx2loop_n3.vhd 638 2015-01-25 22:01:38Z mueller $
---
--- Copyright 2012-2015 by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Module Name: sys_tst_fx2loop_n3 - syn
--- Description: test of Cypress EZ-USB FX2 controller
---
--- Dependencies: vlib/xlib/s6_cmt_sfs
--- vlib/genlib/clkdivce
--- bpgen/sn_humanio
--- tst_fx2loop_hiomap
--- tst_fx2loop
--- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
--- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
--- bplib/nxcramlib/nx_cram_dummy
---
--- Test bench: -
---
--- Target Devices: generic
--- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
---
--- Synthesized (xst):
--- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
--- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150
--- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175
--- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100
---
--- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150
--- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175
--- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100
---
--- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100
--- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100
---
--- Revision History:
--- Date Rev Version Comment
--- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
--- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk
--- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2)
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.slvtypes.all;
-use work.xlib.all;
-use work.genlib.all;
-use work.bpgenlib.all;
-use work.tst_fx2looplib.all;
-use work.fx2lib.all;
-use work.nxcramlib.all;
-use work.sys_conf.all;
-
--- ----------------------------------------------------------------------------
-
-entity sys_tst_fx2loop_n3 is -- top level
- -- implements nexys3_aif + fx2 pins
- port (
- I_CLK100 : in slbit; -- 100 MHz clock
- I_RXD : in slbit; -- receive data (board view)
- O_TXD : out slbit; -- transmit data (board view)
- I_SWI : in slv8; -- n3 switches
- I_BTN : in slv5; -- n3 buttons
- O_LED : out slv8; -- n3 leds
- O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
- O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
- O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
- O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
- O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
- O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
- O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
- O_MEM_CLK : out slbit; -- cram: clock
- O_MEM_CRE : out slbit; -- cram: command register enable
- I_MEM_WAIT : in slbit; -- cram: mem wait
- O_MEM_ADDR : out slv23; -- cram: address lines
- IO_MEM_DATA : inout slv16; -- cram: data lines
- O_PPCM_CE_N : out slbit; -- ppcm: ...
- O_PPCM_RST_N : out slbit; -- ppcm: ...
- I_FX2_IFCLK : in slbit; -- fx2: interface clock
- O_FX2_FIFO : out slv2; -- fx2: fifo address
- I_FX2_FLAG : in slv4; -- fx2: fifo flags
- O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
- O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
- O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
- O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
- IO_FX2_DATA : inout slv8 -- fx2: data lines
- );
-end sys_tst_fx2loop_n3;
-
-architecture syn of sys_tst_fx2loop_n3 is
-
- signal CLK : slbit := '0';
- signal RESET : slbit := '0';
-
- signal CE_USEC : slbit := '0';
- signal CE_MSEC : slbit := '0';
-
- signal SWI : slv8 := (others=>'0');
- signal BTN : slv5 := (others=>'0');
- signal LED : slv8 := (others=>'0');
- signal DSP_DAT : slv16 := (others=>'0');
- signal DSP_DP : slv4 := (others=>'0');
-
- signal LED_MAP : slv8 := (others=>'0');
-
- signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
- signal HIO_STAT : hio_stat_type := hio_stat_init;
-
- signal FX2_RXDATA : slv8 := (others=>'0');
- signal FX2_RXVAL : slbit := '0';
- signal FX2_RXHOLD : slbit := '0';
- signal FX2_RXAEMPTY : slbit := '0';
- signal FX2_TXDATA : slv8 := (others=>'0');
- signal FX2_TXENA : slbit := '0';
- signal FX2_TXBUSY : slbit := '0';
- signal FX2_TXAFULL : slbit := '0';
- signal FX2_TX2DATA : slv8 := (others=>'0');
- signal FX2_TX2ENA : slbit := '0';
- signal FX2_TX2BUSY : slbit := '1';
- signal FX2_TX2AFULL : slbit := '0';
- signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
-
-begin
-
- assert (sys_conf_clksys mod 1000000) = 0
- report "assert sys_conf_clksys on MHz grid"
- severity failure;
-
- GEN_CLKSYS : s6_cmt_sfs
- generic map (
- VCO_DIVIDE => sys_conf_clksys_vcodivide,
- VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
- OUT_DIVIDE => sys_conf_clksys_outdivide,
- CLKIN_PERIOD => 10.0,
- CLKIN_JITTER => 0.01,
- STARTUP_WAIT => false,
- GEN_TYPE => sys_conf_clksys_gentype)
- port map (
- CLKIN => I_CLK100,
- CLKFX => CLK,
- LOCKED => open
- );
-
- CLKDIV : clkdivce
- generic map (
- CDUWIDTH => 8, -- good for up to 255 MHz !
- USECDIV => sys_conf_clksys_mhz,
- MSECDIV => 1000)
- port map (
- CLK => CLK,
- CE_USEC => CE_USEC,
- CE_MSEC => CE_MSEC
- );
-
- HIO : sn_humanio
- generic map (
- BWIDTH => 5,
- DEBOUNCE => sys_conf_hio_debounce)
- port map (
- CLK => CLK,
- RESET => '0',
- CE_MSEC => CE_MSEC,
- SWI => SWI,
- BTN => BTN,
- LED => LED,
- DSP_DAT => DSP_DAT,
- DSP_DP => DSP_DP,
- I_SWI => I_SWI,
- I_BTN => I_BTN,
- O_LED => O_LED,
- O_ANO_N => O_ANO_N,
- O_SEG_N => O_SEG_N
- );
-
- RESET <= BTN(0); -- BTN(0) will reset tester !!
-
- HIOMAP : tst_fx2loop_hiomap
- port map (
- CLK => CLK,
- RESET => RESET,
- HIO_CNTL => HIO_CNTL,
- HIO_STAT => HIO_STAT,
- FX2_MONI => FX2_MONI,
- SWI => SWI,
- BTN => BTN(3 downto 0),
- LED => LED_MAP,
- DSP_DAT => DSP_DAT,
- DSP_DP => DSP_DP
- );
-
- proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
- FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
- begin
-
- if SWI(4) = '1' then
- LED(7) <= '0';
- LED(6) <= '0';
- LED(5) <= FX2_TX2BUSY;
- LED(4) <= FX2_TX2ENA;
- LED(3) <= FX2_TXBUSY;
- LED(2) <= FX2_TXENA;
- LED(1) <= FX2_RXHOLD;
- LED(0) <= FX2_RXVAL;
- else
- LED <= LED_MAP;
- end if;
-
- end process proc_led;
-
-
- TST : tst_fx2loop
- port map (
- CLK => CLK,
- RESET => RESET,
- CE_MSEC => CE_MSEC,
- HIO_CNTL => HIO_CNTL,
- HIO_STAT => HIO_STAT,
- FX2_MONI => FX2_MONI,
- RXDATA => FX2_RXDATA,
- RXVAL => FX2_RXVAL,
- RXHOLD => FX2_RXHOLD,
- TXDATA => FX2_TXDATA,
- TXENA => FX2_TXENA,
- TXBUSY => FX2_TXBUSY,
- TX2DATA => FX2_TX2DATA,
- TX2ENA => FX2_TX2ENA,
- TX2BUSY => FX2_TX2BUSY
- );
-
- FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
- CNTL : fx2_2fifoctl_ic
- generic map (
- RXFAWIDTH => 5,
- TXFAWIDTH => 5,
- PETOWIDTH => sys_conf_fx2_petowidth,
- CCWIDTH => sys_conf_fx2_ccwidth,
- RXAEMPTY_THRES => 1,
- TXAFULL_THRES => 1)
- port map (
- CLK => CLK,
- RESET => RESET,
- RXDATA => FX2_RXDATA,
- RXVAL => FX2_RXVAL,
- RXHOLD => FX2_RXHOLD,
- RXAEMPTY => FX2_RXAEMPTY,
- TXDATA => FX2_TXDATA,
- TXENA => FX2_TXENA,
- TXBUSY => FX2_TXBUSY,
- TXAFULL => FX2_TXAFULL,
- MONI => FX2_MONI,
- I_FX2_IFCLK => I_FX2_IFCLK,
- O_FX2_FIFO => O_FX2_FIFO,
- I_FX2_FLAG => I_FX2_FLAG,
- O_FX2_SLRD_N => O_FX2_SLRD_N,
- O_FX2_SLWR_N => O_FX2_SLWR_N,
- O_FX2_SLOE_N => O_FX2_SLOE_N,
- O_FX2_PKTEND_N => O_FX2_PKTEND_N,
- IO_FX2_DATA => IO_FX2_DATA
- );
- end generate FX2_CNTL_IC;
-
- FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
- CNTL : fx2_3fifoctl_ic
- generic map (
- RXFAWIDTH => 5,
- TXFAWIDTH => 5,
- PETOWIDTH => sys_conf_fx2_petowidth,
- CCWIDTH => sys_conf_fx2_ccwidth,
- RXAEMPTY_THRES => 1,
- TXAFULL_THRES => 1,
- TX2AFULL_THRES => 1)
- port map (
- CLK => CLK,
- RESET => RESET,
- RXDATA => FX2_RXDATA,
- RXVAL => FX2_RXVAL,
- RXHOLD => FX2_RXHOLD,
- RXAEMPTY => FX2_RXAEMPTY,
- TXDATA => FX2_TXDATA,
- TXENA => FX2_TXENA,
- TXBUSY => FX2_TXBUSY,
- TXAFULL => FX2_TXAFULL,
- TX2DATA => FX2_TX2DATA,
- TX2ENA => FX2_TX2ENA,
- TX2BUSY => FX2_TX2BUSY,
- TX2AFULL => FX2_TX2AFULL,
- MONI => FX2_MONI,
- I_FX2_IFCLK => I_FX2_IFCLK,
- O_FX2_FIFO => O_FX2_FIFO,
- I_FX2_FLAG => I_FX2_FLAG,
- O_FX2_SLRD_N => O_FX2_SLRD_N,
- O_FX2_SLWR_N => O_FX2_SLWR_N,
- O_FX2_SLOE_N => O_FX2_SLOE_N,
- O_FX2_PKTEND_N => O_FX2_PKTEND_N,
- IO_FX2_DATA => IO_FX2_DATA
- );
- end generate FX2_CNTL_IC3;
-
- SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
- port map (
- O_MEM_CE_N => O_MEM_CE_N,
- O_MEM_BE_N => O_MEM_BE_N,
- O_MEM_WE_N => O_MEM_WE_N,
- O_MEM_OE_N => O_MEM_OE_N,
- O_MEM_ADV_N => O_MEM_ADV_N,
- O_MEM_CLK => O_MEM_CLK,
- O_MEM_CRE => O_MEM_CRE,
- I_MEM_WAIT => I_MEM_WAIT,
- O_MEM_ADDR => O_MEM_ADDR,
- IO_MEM_DATA => IO_MEM_DATA
- );
-
- O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
- O_PPCM_RST_N <= '1'; --
-
- O_TXD <= I_RXD; -- loop-back in serial port...
-
-end syn;
-
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom (nonexistent)
@@ -1,28 +0,0 @@
-# this is the vbom for the 'generic' top level entity
-# to be referenced in the vbom's of the specific systems
-# ./ic/sys_tst_fx2loop_ic_n3
-# ./ic3/sys_tst_fx2loop_ic3_n3
-#
-# libs
-../../../vlib/slvtypes.vhd
-../../../vlib/xlib/xlib.vhd
-../../../vlib/genlib/genlib.vhd
-../../../bplib/bpgen/bpgenlib.vbom
-../tst_fx2looplib.vbom
-../../../bplib/fx2lib/fx2lib.vhd
-../../../bplib/nxcramlib/nxcramlib.vhd
-${sys_conf}
-# components
-[xst,vsyn]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
-[ghdl,isim,vsim]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
-../../../vlib/genlib/clkdivce.vbom
-../../../bplib/bpgen/sn_humanio.vbom
-../tst_fx2loop_hiomap.vbom
-../tst_fx2loop.vbom
-../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
-../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
-../../../bplib/nxcramlib/nx_cram_dummy.vbom
-# design
-sys_tst_fx2loop_n3.vhd
-## no @ucf_cpp
-
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp (nonexistent)
@@ -1,48 +0,0 @@
-## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $
-##
-## Revision History:
-## Date Rev Version Comment
-## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints
-## 2012-04-09 461 1.0 Initial version
-##
-
-NET "I_CLK100" TNM_NET = "I_CLK100";
-TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
-OFFSET = IN 10 ns BEFORE "I_CLK100";
-OFFSET = OUT 20 ns AFTER "I_CLK100";
-
-## constrain pad->net clock delay
-NET CLK TNM = TNM_CLK;
-TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
-NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
-TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
-
-## constrain async pad->pad delays
-TIMEGRP TG_SLOW_INS = PADS(I_RXD);
-TIMEGRP TG_SLOW_OUTS = PADS(O_TXD);
-TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns;
-
-## FX2 controller specific constraints
-## constrain cdc path in fifos and reset
-TIMESPEC TS_CDC_FIFO =
- FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*
- *FIFO/R_REG?_rst?
- *FIFO/R_REG?_rst?_s)
- TO FFS(*FIFO/R_REG?_?addr_c*
- *FIFO/R_REG?_rst?_c
- *FIFO/R_REG?_rst?_sc)
- 5 ns DATAPATHONLY;
-
-## constrain cdc path in monitor
-TIMESPEC TS_CDC_FX2MONI = FROM FFS
- TO FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY;
-
-##
-## std board
-##
-#include "bplib/nexys3/nexys3_pins.ucf"
-##
-## FX2 interface
-##
-#include "bplib/nexys3/nexys3_pins_fx2.ucf"
-#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/.cvsignore (nonexistent)
@@ -1 +0,0 @@
-sys_tst_fx2loop_ic_n3.ucf
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/Makefile (nonexistent)
@@ -1,30 +0,0 @@
-# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
-#
-# Revision History:
-# Date Rev Version Comment
-# 2012-04-09 461 1.0 Initial version
-#
-#
-VBOM_all = $(wildcard *.vbom)
-BIT_all = $(VBOM_all:.vbom=.bit)
-#
-include ${RETROBASE}/rtl/make_ise/xflow_default_nexys3.mk
-FX2_FILE = nexys3_jtag_2fifo_ic.ihx
-#
-.PHONY : all clean
-#
-all : $(BIT_all)
-#
-clean : ise_clean
- rm -f $(VBOM_all:.vbom=.ucf)
-#
-#----
-#
-include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
-include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
-#
-ifndef DONTINCDEP
-include $(VBOM_all:.vbom=.dep_xst)
-include $(VBOM_all:.vbom=.dep_ghdl)
-endif
-#
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.vbom (nonexistent)
@@ -1,8 +0,0 @@
-# conf
-sys_conf = sys_conf.vhd
-# libs
-# components
-# design
-../sys_tst_fx2loop_n3.vbom
-@ucf_cpp: sys_tst_fx2loop_ic_n3.ucf
-@top: sys_tst_fx2loop_n3
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd (nonexistent)
@@ -1,63 +0,0 @@
--- $Id: sys_conf.vhd 649 2015-02-21 21:10:16Z mueller $
---
--- Copyright 2012-2013 by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Package Name: sys_conf
--- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis)
---
--- Dependencies: -
--- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--- Revision History:
--- Date Rev Version Comment
--- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
--- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk
--- 2012-04-09 461 1.0 Initial version
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.slvtypes.all;
-
-package sys_conf is
-
- constant sys_conf_clksys_vcodivide : positive := 2;
- constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
- constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
- constant sys_conf_clksys_gentype : string := "DCM";
-
- constant sys_conf_fx2_type : string := "ic2";
-
- -- dummy values defs for generic parameters of as controller
- constant sys_conf_fx2_rdpwldelay : positive := 1;
- constant sys_conf_fx2_rdpwhdelay : positive := 1;
- constant sys_conf_fx2_wrpwldelay : positive := 1;
- constant sys_conf_fx2_wrpwhdelay : positive := 1;
- constant sys_conf_fx2_flagdelay : positive := 1;
-
- -- pktend timer setting
- -- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
- constant sys_conf_fx2_petowidth : positive := 10;
-
- constant sys_conf_fx2_ccwidth : positive := 5;
-
- constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-
- -- derived constants
-
- constant sys_conf_clksys : integer :=
- ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
- sys_conf_clksys_outdivide;
- constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
-
-end package sys_conf;
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic (nonexistent)
trunk/rtl/sys_gen/tst_fx2loop/nexys3/ic
Property changes :
Deleted: svn:ignore
## -1,43 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
-sys_tst_fx2loop_ic_n3.ucf
Index: trunk/rtl/sys_gen/tst_fx2loop/nexys3
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/nexys3 (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/nexys3 (nonexistent)
trunk/rtl/sys_gen/tst_fx2loop/nexys3
Property changes :
Deleted: svn:ignore
## -1,42 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
Index: trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vhd (nonexistent)
@@ -1,109 +0,0 @@
--- $Id: tst_fx2looplib.vhd 649 2015-02-21 21:10:16Z mueller $
---
--- Copyright 2011-2012 by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Package Name: tst_fx2looplib
--- Description: Definitions for tst_fx2loop records and helpers
---
--- Dependencies: -
--- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
--- Revision History:
--- Date Rev Version Comment
--- 2012-01-15 453 1.1 drop pecnt, add rxhold,(tx|tx2)busy in hio_stat
--- 2011-12-26 445 1.0 Initial version
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.slvtypes.all;
-use work.fx2lib.all;
-
-package tst_fx2looplib is
-
- constant c_ctltyp_2fifo_as : integer := 0; -- fx2ctl type: 2fifo_as
- constant c_ctltyp_2fifo_ic : integer := 1; -- fx2ctl type: 2fifo_ic
- constant c_ctltyp_3fifo_ic : integer := 2; -- fx2ctl type: 3fifo_ic
-
- constant c_mode_idle : slv2 := "00"; -- mode: idle (no tx activity)
- constant c_mode_rxblast : slv2 := "01"; -- mode: rxblast (check rx activity)
- constant c_mode_txblast : slv2 := "10"; -- mode: txblast (saturate tx)
- constant c_mode_loop : slv2 := "11"; -- mode: loop (rx->tx loop-back)
-
- type hio_cntl_type is record -- humanio controls
- mode : slv2; -- mode (idle,(tx|tx)blast,loop)
- tx2blast : slbit; -- enable tx2 blast
- throttle : slbit; -- enable 1 msec tx throttling
- end record hio_cntl_type;
-
- constant hio_cntl_init : hio_cntl_type := (
- c_mode_idle, -- mode
- '0','0' -- tx2blast,throttle
- );
-
- type hio_stat_type is record -- humanio status
- rxhold : slbit; -- rx hold
- txbusy : slbit; -- tx busy
- tx2busy : slbit; -- tx2 busy
- rxsecnt : slv16; -- rx sequence error counter
- rxcnt : slv32; -- rx word counter
- txcnt : slv32; -- tx word counter
- tx2cnt : slv32; -- tx2 word counter
- end record hio_stat_type;
-
- constant hio_stat_init : hio_stat_type := (
- '0','0','0', -- rxhold,txbusy,tx2busy
- (others=>'0'), -- rxsecnt
- (others=>'0'), -- rxcnt
- (others=>'0'), -- txcnt
- (others=>'0') -- tx2cnt
- );
-
--- -------------------------------------
-
-component tst_fx2loop is -- tester for serport components
- port (
- CLK : in slbit; -- clock
- RESET : in slbit; -- reset
- CE_MSEC : in slbit; -- msec pulse
- HIO_CNTL : in hio_cntl_type; -- humanio controls
- HIO_STAT : out hio_stat_type; -- humanio status
- FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor
- RXDATA : in slv8; -- receiver data out
- RXVAL : in slbit; -- receiver data valid
- RXHOLD : out slbit; -- receiver data hold
- TXDATA : out slv8; -- transmit data in
- TXENA : out slbit; -- transmit data enable
- TXBUSY : in slbit; -- transmit busy
- TX2DATA : out slv8; -- transmit 2 data in
- TX2ENA : out slbit; -- transmit 2 data enable
- TX2BUSY : in slbit -- transmit 2 busy
- );
-end component;
-
-component tst_fx2loop_hiomap is -- default human I/O mapper
- port (
- CLK : in slbit; -- clock
- RESET : in slbit; -- reset
- HIO_CNTL : out hio_cntl_type; -- tester controls from hio
- HIO_STAT : in hio_stat_type; -- tester status to display by hio
- FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
- SWI : in slv8; -- switch settings
- BTN : in slv4; -- button settings
- LED : out slv8; -- led data
- DSP_DAT : out slv16; -- display data
- DSP_DP : out slv4 -- display decimal points
- );
-end component;
-
-end package tst_fx2looplib;
Index: trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/tst_fx2looplib.vbom (nonexistent)
@@ -1,4 +0,0 @@
-# libs
-../../vlib/slvtypes.vhd
-../../bplib/fx2lib/fx2lib.vhd
-tst_fx2looplib.vhd
Index: trunk/rtl/sys_gen/tst_fx2loop/.cvsignore
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/.cvsignore (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/.cvsignore (nonexistent)
@@ -1,2 +0,0 @@
-tst_fx2loop
-tst_fx2loop_si
Index: trunk/rtl/sys_gen/tst_fx2loop/Makefile
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/Makefile (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/Makefile (nonexistent)
@@ -1,41 +0,0 @@
-# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
-#
-# Revision History:
-# Date Rev Version Comment
-# 2014-11-08 602 1.3 rename realclean->distclean
-# 2013-01-05 470 1.2 fix LDLIBS (must come after objs)
-# 2012-02-26 458 1.1 add tst_fx2loop_si
-# 2011-12-26 445 1.0 Initial version
-#
-VBOM_all = $(wildcard *.vbom)
-NGC_all = $(VBOM_all:.vbom=.ngc)
-#
-include ${RETROBASE}/rtl/make_ise/xflow_default_nexys2.mk
-#
-.PHONY : all clean distclean
-#
-all : tst_fx2loop tst_fx2loop_si
-#
-clean : ise_clean
- rm -f tst_fx2loop
- rm -f tst_fx2loop_si
-#
-distclean :
- rm -f tst_fx2loop tst_fx2loop_si
-#
-CFLAGS = -Wall -O2 -g
-LDLIBS = -lusb-1.0
-#
-tst_fx2loop : tst_fx2loop.c
- ${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS}
-tst_fx2loop_si : tst_fx2loop_si.c
- ${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS}
-#
-#----
-#
-include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
-#
-ifndef DONTINCDEP
-include $(VBOM_all:.vbom=.dep_xst)
-endif
-#
Index: trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vhd (nonexistent)
@@ -1,194 +0,0 @@
--- $Id: tst_fx2loop_hiomap.vhd 649 2015-02-21 21:10:16Z mueller $
---
--- Copyright 2011-2012 by Walter F.J. Mueller
---
--- This program is free software; you may redistribute and/or modify it under
--- the terms of the GNU General Public License as published by the Free
--- Software Foundation, either version 2, or at your option any later version.
---
--- This program is distributed in the hope that it will be useful, but
--- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
--- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
--- for complete details.
---
-------------------------------------------------------------------------------
--- Module Name: tst_fx2loop_hiomap - syn
--- Description: default human I/O mapper
---
--- Dependencies: -
--- Test bench: -
---
--- Target Devices: generic
--- Tool versions: xst 13.3-14.7; ghdl 0.29-0.31
---
--- Revision History:
--- Date Rev Version Comment
--- 2012-01-15 453 1.0.2 re-arrange DP,DSP usage
--- 2012-01-03 449 1.0.1 use new fx2ctl_moni layout
--- 2011-12-26 445 1.0 Initial version
-------------------------------------------------------------------------------
---
--- Usage of Switches, Buttons, LEDs:
---
--- BTN(3) -- unused --
--- (2) -- unused --
--- (1) -- unused --
--- (0) reset state [!! decoded by top level design !!]
---
--- SWI(7:5) select display
--- (4) -- unused --
--- (3) throttle
--- (2) tx2blast
--- (1:0) mode 00 idle
--- 01 rxblast
--- 10 txblast
--- 11 loop
---
--- LED(7) MONI.fifo_ep4
--- (6) MONI.fifo_ep6
--- (5) MONI.fifo_ep8
--- (4) MONI.flag_ep4_empty
--- (3) MONI.flag_ep4_almost
--- (2) MONI.flag_ep6_full
--- (1) MONI.flag_ep6_almost
--- (0) rxsecnt > 0 (sequence error)
---
--- DSP data as selected by SWI(7:5)
--- 000 -> rxsecnt
--- 001 -> -- unused -- (display ffff)
--- 010 -> rxcnt.l
--- 011 -> rxcnt.h
--- 100 -> txcnt.l
--- 101 -> txcnt.h
--- 110 -> tx2cnt.l
--- 111 -> tx2cnt.h
---
--- DP(3) FX2_TXBUSY (shows tx back preasure)
--- (2) FX2_MONI.slwr (shows tx activity)
--- (1) FX2_RXHOLD (shows rx back preasure)
--- (0) FX2_MONI.slrd (shows rx activity)
---
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-use work.slvtypes.all;
-use work.fx2lib.all;
-use work.tst_fx2looplib.all;
-
--- ----------------------------------------------------------------------------
-
-entity tst_fx2loop_hiomap is -- default human I/O mapper
- port (
- CLK : in slbit; -- clock
- RESET : in slbit; -- reset
- HIO_CNTL : out hio_cntl_type; -- tester controls from hio
- HIO_STAT : in hio_stat_type; -- tester status to diaplay by hio
- FX2_MONI : in fx2ctl_moni_type; -- fx2ctl monitor to display by hio
- SWI : in slv8; -- switch settings
- BTN : in slv4; -- button settings
- LED : out slv8; -- led data
- DSP_DAT : out slv16; -- display data
- DSP_DP : out slv4 -- display decimal points
- );
-end tst_fx2loop_hiomap;
-
-architecture syn of tst_fx2loop_hiomap is
-
- type regs_type is record
- dspdat : slv16; -- display data
- dummy : slbit; --
- end record regs_type;
-
- constant regs_init : regs_type := (
- (others=>'0'), -- dspdat
- '0'
- );
-
- signal R_REGS : regs_type := regs_init; -- state registers
- signal N_REGS : regs_type := regs_init; -- next value state regs
-
-begin
-
- proc_regs: process (CLK)
- begin
-
- if rising_edge(CLK) then
- if RESET = '1' then
- R_REGS <= regs_init;
- else
- R_REGS <= N_REGS;
- end if;
- end if;
-
- end process proc_regs;
-
- proc_next: process (R_REGS, HIO_STAT, FX2_MONI, SWI, BTN)
-
- variable r : regs_type := regs_init;
- variable n : regs_type := regs_init;
-
- variable icntl : hio_cntl_type := hio_cntl_init;
- variable iled : slv8 := (others=>'0');
- variable idat : slv16 := (others=>'0');
- variable idp : slv4 := (others=>'0');
-
- begin
-
- r := R_REGS;
- n := R_REGS;
-
- icntl := hio_cntl_init;
- iled := (others=>'0');
- idat := (others=>'0');
- idp := (others=>'0');
-
- -- setup tester controls
-
- icntl.mode := SWI(1 downto 0);
- icntl.tx2blast := SWI(2);
- icntl.throttle := SWI(3);
-
- -- setup leds
- iled(7) := FX2_MONI.fifo_ep4;
- iled(6) := FX2_MONI.fifo_ep6;
- iled(5) := FX2_MONI.fifo_ep8;
- iled(4) := FX2_MONI.flag_ep4_empty;
- iled(3) := FX2_MONI.flag_ep4_almost;
- iled(2) := FX2_MONI.flag_ep6_full;
- iled(1) := FX2_MONI.flag_ep6_almost;
- if unsigned(HIO_STAT.rxsecnt) > 0 then iled(0) := '1'; end if;
-
- -- setup display data
-
- case SWI(7 downto 5) is
- when "000" => idat := HIO_STAT.rxsecnt;
- when "001" => idat := (others=>'1');
- when "010" => idat := HIO_STAT.rxcnt(15 downto 0);
- when "011" => idat := HIO_STAT.rxcnt(31 downto 16);
- when "100" => idat := HIO_STAT.txcnt(15 downto 0);
- when "101" => idat := HIO_STAT.txcnt(31 downto 16);
- when "110" => idat := HIO_STAT.tx2cnt(15 downto 0);
- when "111" => idat := HIO_STAT.tx2cnt(31 downto 16);
- when others => null;
- end case;
- n.dspdat := idat;
-
- -- setup display decimal points
-
- idp(3) := HIO_STAT.txbusy; -- tx back preasure
- idp(2) := FX2_MONI.slwr; -- tx activity
- idp(1) := HIO_STAT.rxhold; -- rx back preasure
- idp(0) := FX2_MONI.slrd; -- rx activity
-
- N_REGS <= n;
-
- HIO_CNTL <= icntl;
- LED <= iled;
- DSP_DAT <= r.dspdat;
- DSP_DP <= idp;
-
- end process proc_next;
-
-end syn;
Index: trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop/tst_fx2loop_hiomap.vbom (nonexistent)
@@ -1,7 +0,0 @@
-# libs
-../../vlib/slvtypes.vhd
-../../bplib/fx2lib/fx2lib.vhd
-tst_fx2looplib.vbom
-# components
-# design
-tst_fx2loop_hiomap.vhd
Index: trunk/rtl/sys_gen/tst_fx2loop
===================================================================
--- trunk/rtl/sys_gen/tst_fx2loop (revision 35)
+++ trunk/rtl/sys_gen/tst_fx2loop (nonexistent)
trunk/rtl/sys_gen/tst_fx2loop
Property changes :
Deleted: svn:ignore
## -1,44 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
-tst_fx2loop
-tst_fx2loop_si
Index: trunk/rtl/sys_gen/tst_rlink/Makefile
===================================================================
--- trunk/rtl/sys_gen/tst_rlink/Makefile (revision 35)
+++ trunk/rtl/sys_gen/tst_rlink/Makefile (nonexistent)
@@ -1,26 +0,0 @@
-# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
-#
-# Revision History:
-# Date Rev Version Comment
-# 2011-12-11 438 1.0 Initial version
-#
-VBOM_all = $(wildcard *.vbom)
-NGC_all = $(VBOM_all:.vbom=.ngc)
-#
-include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk
-#
-.PHONY : all clean
-#
-all : $(NGC_all)
-#
-clean : ise_clean
-#
-#
-#----
-#
-include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
-#
-ifndef DONTINCDEP
-include $(VBOM_all:.vbom=.dep_xst)
-endif
-#
Index: trunk/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd
===================================================================
--- trunk/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd (revision 35)
+++ trunk/rtl/sys_gen/tst_rlink/arty/sys_conf.vhd (revision 36)
@@ -1,4 +1,4 @@
--- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $
+-- $Id: sys_conf.vhd 754 2016-03-28 12:26:13Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller
--
@@ -19,6 +19,7 @@
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
+-- 2016-03-28 754 1.2 run at 120 MHz
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2016-02-16 731 1.0 Initial version
------------------------------------------------------------------------------
@@ -32,8 +33,8 @@
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
- constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
- constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
+ constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz
+ constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- configure rlink and hio interfaces --------------------------------------
/trunk/rtl/sys_gen/tst_rlink/arty/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,7 → 16,7
-- Description: Definitions for sys_tst_rlink_arty (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: viv 2015.4; ghdl 0.33 |
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-12 741 1.1 add sysmon_rbus |
/trunk/rtl/sys_gen/tst_rlink/arty/tb/Makefile
1,7 → 1,9
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ |
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 776 1.1.1 add xsim_clean |
# 2016-04-22 763 1.1 add include dep_vsim |
# 2016-02-14 731 1.0 Initial version |
# |
EXE_all = tb_tst_rlink_arty |
8,17 → 10,25
# |
include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk |
# |
.PHONY : all all_ssim clean |
.PHONY : all all_ssim all_osim clean |
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
all_osim : $(EXE_all:=_osim) |
# |
clean : viv_clean ghdl_clean |
all_XSim : $(EXE_all:=_XSim) |
all_XSim_ssim : $(EXE_all:=_XSim_ssim) |
all_XSim_osim : $(EXE_all:=_XSim_osim) |
all_XSim_tsim : $(EXE_all:=_XSim_tsim) |
# |
clean : viv_clean ghdl_clean xsim_clean |
# |
#----- |
# |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
25,6 → 35,7
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_vsyn) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_vsim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
/trunk/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_arty.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_tst_rlink_arty.vhd 758 2016-04-02 18:01:39Z mueller $ |
-- |
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
24,8 → 24,8
-- bplib/bpgen/rgbdrv_master |
-- bplib/bpgen/rgbdrv_analog_rbus |
-- bplib/sysmon/sysmonx_rbus_arty |
-- vlib/rbus/rbd_usracc |
-- vlib/rbus/rb_sres_or_4 |
-- vlib/rbus/rb_sres_or_3 |
-- |
-- Test bench: tb/tb_tst_rlink_arty |
-- |
34,6 → 34,7
-- |
-- Synthesized (xst): |
-- Date Rev viv Target flop lutl lutm bram slic |
-- 2016-03-27 753 2015.4 xc7a35t-1L 980 1396 36 3.0 494 meminf |
-- 2016-03-13 743 2015.4 xc7a35t-1L 980 1390 64 4.5 514 +XADC |
-- 2016-02-20 734 2015.4 xc7a35t-1L 941 1352 64 4.5 478 |
-- 2016-02-14 731 2015.4 xc7a35t-1L 777 1313 64 4.5 399 |
40,6 → 41,8
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-04-02 758 1.1.5 add rbd_usracc (bitfile+jtag timestamp access) |
-- 2016-03-19 748 1.1.4 define rlink SYSID |
-- 2016-03-13 743 1.1.3 hardwire XON=1, all SWI now unused |
-- 2016-03-12 741 1.1.2 use sysmonx_rbus_arty now |
-- 2016-03-06 740 1.1.1 add A_VPWRN/P to baseline config |
67,6 → 70,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.bpgenrbuslib.all; |
117,6 → 121,7
signal RB_SRES_RGB2 : rb_sres_type := rb_sres_init; |
signal RB_SRES_RGB3 : rb_sres_type := rb_sres_init; |
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; |
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
133,6 → 138,10
constant rbaddr_rgb3 : slv16 := x"fc0c"; -- fe0c/0004: 1111 1100 0000 11xx |
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx |
|
constant sysid_proj : slv16 := x"0101"; -- tst_rlink |
constant sysid_board : slv8 := x"07"; -- arty |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
198,12 → 207,12
generic map ( |
BTOWIDTH => 6, |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, |
OFAWIDTH => 5, |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDWIDTH => 12, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink |
RBMON_RBADDR => (others=>'0')) |
336,11 → 345,19
RB_SRES_OR => RB_SRES_RGB |
); |
|
RB_SRES_OR1 : rb_sres_or_3 |
UARB : rbd_usracc |
port map ( |
CLK => CLK, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_USRACC |
); |
|
RB_SRES_OR1 : rb_sres_or_4 |
port map ( |
RB_SRES_1 => RB_SRES_TST, |
RB_SRES_2 => RB_SRES_RGB, |
RB_SRES_3 => RB_SRES_SYSMON, |
RB_SRES_4 => RB_SRES_USRACC, |
RB_SRES_OR => RB_SRES |
); |
|
/trunk/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/bpgen/bpgenrbuslib.vbom |
20,8 → 21,8
../../../bplib/bpgen/rgbdrv_master.vbom |
../../../bplib/bpgen/rgbdrv_analog_rbus.vbom |
../../../bplib/sysmon/sysmonx_rbus_arty.vbom |
../../../vlib/rbus/rbd_usracc.vbom |
../../../vlib/rbus/rb_sres_or_4.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
# design |
sys_tst_rlink_arty.vhd |
@xdc:../../../bplib/arty/arty_pclk.xdc |
/trunk/rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset
0,0 → 1,27
# $Id: sys_tst_rlink_arty.vmfset 773 2016-06-05 20:03:15Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# unconnected ports -------------------------------------------- |
I [Synth 8-3331] RB_MREQ # generic |
# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 |
i [Synth 8-3331] rlink_sp1c.*CE_USEC |
|
# unused sequential element ------------------------------------ |
# --> many HIO pins not used # OK 2016-06-05 |
i [Synth 8-3332] IOB_(SWI|BTN)/R_DI_reg[\d*] |
i [Synth 8-3332] DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*] |
|
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 |
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] |
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] |
# ENAESC=0, therefore esc logic inactive # OK 2016-06-05 |
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] |
i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] |
# --> SER_MONI.rxovr indeed unused # OK 2016-06-05 |
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/tst_rlink/basys3/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_conf.vhd 754 2016-03-28 12:26:13Z mueller $ |
-- |
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
19,6 → 19,7
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-28 754 1.2 run at 120 MHz |
-- 2016-03-12 741 1.1 add sysmon_rbus |
-- 2016-02-26 735 1.0.2 use s7_cmt_sfs |
-- 2015-01-16 636 1.0 Initial version |
33,8 → 34,8
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz |
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz |
constant sys_conf_clksys_vcomultiply : positive := 12; -- vco 1200 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 120 MHz |
constant sys_conf_clksys_gentype : string := "MMCM"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
/trunk/rtl/sys_gen/tst_rlink/basys3/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,7 → 16,7
-- Description: Definitions for sys_tst_rlink_b3 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 |
-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-12 741 1.1 add sysmon_rbus |
/trunk/rtl/sys_gen/tst_rlink/basys3/tb/Makefile
1,7 → 1,9
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ |
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 776 1.1.1 add xsim_clean |
# 2016-04-22 763 1.1 add include dep_vsim |
# 2015-02-18 648 1.0 Initial version |
# |
EXE_all = tb_tst_rlink_b3 |
8,17 → 10,25
# |
include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk |
# |
.PHONY : all all_ssim clean |
.PHONY : all all_ssim all_osim clean |
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
all_osim : $(EXE_all:=_osim) |
# |
clean : viv_clean ghdl_clean |
all_XSim : $(EXE_all:=_XSim) |
all_XSim_ssim : $(EXE_all:=_XSim_ssim) |
all_XSim_osim : $(EXE_all:=_XSim_osim) |
all_XSim_tsim : $(EXE_all:=_XSim_tsim) |
# |
clean : viv_clean ghdl_clean xsim_clean |
# |
#----- |
# |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
25,6 → 35,7
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_vsyn) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_vsim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
/trunk/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_b3.vhd 745 2016-03-18 22:10:34Z mueller $ |
-- $Id: sys_tst_rlink_b3.vhd 758 2016-04-02 18:01:39Z mueller $ |
-- |
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
22,7 → 22,8
-- vlib/rlink/rlink_sp1c |
-- rbd_tst_rlink |
-- bplib/sysmon/sysmonx_rbus_base |
-- vlib/rbus/rb_sres_or_3 |
-- vlib/rbus/rbd_usracc |
-- vlib/rbus/rb_sres_or_4 |
-- |
-- Test bench: tb/tb_tst_rlink_b3 |
-- |
31,11 → 32,14
-- |
-- Synthesized (xst): |
-- Date Rev viv Target flop lutl lutm bram slic |
-- 2016-03-27 753 2015.4 xc7a35t-1 986 1352 36 3.0 473 meminf |
-- 2016-03-13 743 2015.4 xc7a35t-1 988 1372 64 4.5 503 +XADC |
-- 2015-01-30 636 2014.4 xc7a35t-1 946 1319 64 4.5 476 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-04-02 758 1.1.3 add rbd_usracc (bitfile+jtag timestamp access) |
-- 2016-03-19 748 1.1.2 define rlink SYSID |
-- 2016-03-18 745 1.1.1 hardwire XON=1 |
-- 2016-03-12 741 1.1 add sysmon_rbus |
-- 2016-02-26 735 1.0.2 use s7_cmt_sfs |
68,6 → 72,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.bpgenrbuslib.all; |
112,6 → 117,7
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal RB_SRES_TST : rb_sres_type := rb_sres_init; |
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; |
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
122,6 → 128,10
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx |
|
constant sysid_proj : slv16 := x"0101"; -- tst_rlink |
constant sysid_board : slv8 := x"06"; -- basys3 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
194,12 → 204,12
generic map ( |
BTOWIDTH => 6, |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, |
OFAWIDTH => 5, |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDWIDTH => 12, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink |
RBMON_RBADDR => (others=>'0')) |
254,11 → 264,19
); |
end generate SMRB; |
|
RB_SRES_OR1 : rb_sres_or_3 |
UARB : rbd_usracc |
port map ( |
CLK => CLK, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_USRACC |
); |
|
RB_SRES_OR1 : rb_sres_or_4 |
port map ( |
RB_SRES_1 => RB_SRES_HIO, |
RB_SRES_2 => RB_SRES_TST, |
RB_SRES_3 => RB_SRES_SYSMON, |
RB_SRES_4 => RB_SRES_USRACC, |
RB_SRES_OR => RB_SRES |
); |
|
/trunk/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/bpgen/bpgenrbuslib.vbom |
18,7 → 19,8
../../../vlib/rlink/rlink_sp1c.vbom |
../rbd_tst_rlink.vbom |
../../../bplib/sysmon/sysmonx_rbus_base.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
../../../vlib/rbus/rbd_usracc.vbom |
../../../vlib/rbus/rb_sres_or_4.vbom |
# design |
sys_tst_rlink_b3.vhd |
@xdc:../../../bplib/basys3/basys3_pclk.xdc |
/trunk/rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset
0,0 → 1,26
# $Id: sys_tst_rlink_b3.vmfset 773 2016-06-05 20:03:15Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# unconnected ports -------------------------------------------- |
I [Synth 8-3331] RB_MREQ # generic |
# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 |
i [Synth 8-3331] rlink_sp1c.*CE_USEC |
|
# unused sequential element ------------------------------------ |
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic |
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 |
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] |
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] |
# --> LED(6:2) currently not driven # OK 2016-06-05 |
i [Synth 8-3332] R_REGS_reg[ledin][\d] |
# ENAESC=0, therefore esc logic inactive # OK 2016-06-05 |
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] |
i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] |
# --> SER_MONI.rxovr indeed unused # OK 2016-06-05 |
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.mfset
File deleted
\ No newline at end of file
/trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_n2.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_tst_rlink_n2.vhd 748 2016-03-20 15:18:50Z mueller $ |
-- |
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
41,6 → 41,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-19 748 1.4.2 define rlink SYSID |
-- 2015-04-11 666 1.4.1 rearrange XON handling |
-- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit |
150,6 → 151,10
|
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
|
constant sysid_proj : slv16 := x"0101"; -- tst_rlink |
constant sysid_board : slv8 := x"02"; -- nexys2 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
223,7 → 228,7
generic map ( |
BTOWIDTH => 6, |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, |
OFAWIDTH => 5, |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
/trunk/rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.imfset
0,0 → 1,60
# $Id: sys_tst_rlink_n2.imfset 779 2016-06-26 15:37:16Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Mux is complete : default of case is discarded |
|
Node <HIO/R_REGS.swieff_[1-7]> of sequential type is unconnected |
Node <HIO/R_REGS.swi_[1-7]> of sequential type is unconnected |
Node <HIO/R_REGS.btneff_[0-5]> of sequential type is unconnected |
Node <HIO/R_REGS.btn_[0-5]> of sequential type is unconnected |
|
Unconnected output port 'SIZE' of component 'fifo_1c_dram' |
Unconnected output port 'LOCKED' of component 'dcm_sfs' |
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' |
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen' |
Unconnected output port 'RL_MONI' of component 'rlink_sp1c' |
|
Input <I_MEM_WAIT> is never used |
Input <RB_MREQ.din<\d+:\d+>> is never used |
Input <RB_MREQ.init> is never used |
Input <CE_USEC> is never used |
|
Signal <L_DO<17:16>> is assigned but never used |
Signal <FIFO_SIZE> is assigned but never used |
Signal <RXFIFO_SIZE<2:0>> is assigned but never used |
Signal <RB_LAM_TEST<1:0>> is assigned but never used |
Signal <SWI<7:2>> is assigned but never used |
Signal <SER_MONI.rxovr> is assigned but never used |
Signal <SER_MONI.rxerr> is assigned but never used |
Signal <SER_MONI.abdone> is assigned but never used |
Signal <STAT<7:2>> is assigned but never used |
Signal <BTN> is assigned but never used |
|
FF/Latch <R_REGS.ledin_2> in Unit <sn_humanio_rbus> is equivalent |
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent |
|
FF/Latch <R_REGS.ledin_2> has a constant value of 0 |
FF/Latch <R_REGS.ucnt_6> has a constant value of 0 |
|
# |
# ---------------------------------------------------------------------------- |
[tra] |
|
# |
# ---------------------------------------------------------------------------- |
[map] |
The signal <I_MEM_WAIT_IBUF> is incomplete |
Logical network I_MEM_WAIT_IBUF has no load |
INFO:.* |
|
# |
# ---------------------------------------------------------------------------- |
[par] |
The signal I_MEM_WAIT_IBUF has no load |
There are 1 loadless signals in this design |
# |
# ---------------------------------------------------------------------------- |
[bgn] |
Spartan-3 1200E and 1600E devices do not support bitstream |
The signal <I_MEM_WAIT_IBUF> is incomplete |
/trunk/rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_n3.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_tst_rlink_n3.vhd 748 2016-03-20 15:18:50Z mueller $ |
-- |
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
38,6 → 38,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-19 748 1.4.2 define rlink SYSID |
-- 2015-04-11 666 1.4.1 rearrange XON handling |
-- 2014-11-09 603 1.4 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 1.3 rb_mreq addr now 16 bit |
143,6 → 144,10
|
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
|
constant sysid_proj : slv16 := x"0101"; -- tst_rlink |
constant sysid_board : slv8 := x"03"; -- nexys3 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
221,7 → 226,7
generic map ( |
BTOWIDTH => 6, |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, |
OFAWIDTH => 5, |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,7 → 16,7
-- Description: Definitions for sys_tst_rlink_n4 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: ise 14.5-14.7; viv 2014.42015.4; ghdl 0.29-0.33 |
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-12 741 1.1 add sysmon_rbus |
/trunk/rtl/sys_gen/tst_rlink/nexys4/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,7 → 16,7
-- Description: Definitions for sys_tst_rlink_n4 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: xst 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 |
-- Tool versions: xst 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-12 741 1.1 add sysmon_rbus |
/trunk/rtl/sys_gen/tst_rlink/nexys4/tb/Makefile
1,7 → 1,9
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ |
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 776 1.1.1 add xsim_clean |
# 2016-04-22 763 1.1 add include dep_vsim |
# 2016-02-07 729 1.0.1 add generic_xsim.mk |
# 2015-02-18 648 1.0 Initial version |
# |
9,7 → 11,8
# |
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk |
# |
.PHONY : all all_ssim clean |
.PHONY : all all_ssim all_osim clean |
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
20,13 → 23,13
all_XSim_osim : $(EXE_all:=_XSim_osim) |
all_XSim_tsim : $(EXE_all:=_XSim_tsim) |
# |
clean : viv_clean ghdl_clean |
clean : viv_clean ghdl_clean xsim_clean |
# |
#----- |
# |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
33,6 → 36,7
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_vsyn) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_vsim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_n4.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_tst_rlink_n4.vhd 772 2016-06-05 12:55:11Z mueller $ |
-- |
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
24,8 → 24,9
-- bplib/bpgen/rgbdrv_master |
-- bplib/bpgen/rgbdrv_analog_rbus |
-- bplib/sysmon/sysmonx_rbus_base |
-- vlib/rbus/rbd_usracc |
-- vlib/rbus/rb_sres_or_2 |
-- vlib/rbus/rb_sres_or_4 |
-- vlib/rbus/rb_sres_or_6 |
-- |
-- Test bench: tb/tb_tst_rlink_n4 |
-- |
34,6 → 35,8
-- |
-- Synthesized: |
-- Date Rev viv Target flop lutl lutm bram slic |
-- 2016-04-02 758 2015.4 xc7a100t-1 1113 1461 36 3.0 528 usracc |
-- 2016-03-27 753 2015.4 xc7a100t-1 1124 1461 36 3.0 522 meminf |
-- 2016-03-13 743 2015.4 xc7a100t-1 1124 1463 64 4.5 567 +XADC |
-- 2016-02-20 734 2015.4 xc7a100t-1 1080 1424 64 4.5 502 +RGB |
-- 2015-01-31 640 2014.4 xc7a100t-1 990 1360 64 4.5 495 |
40,6 → 43,9
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-06-05 772 1.5.3 use CDUWIDTH=7, 120 MHz clock is natural choice |
-- 2016-04-02 758 1.5.2 add rbd_usracc_e2 (bitfile+jtag timestamp access) |
-- 2016-03-19 748 1.5.1 define rlink SYSID |
-- 2016-03-12 741 1.5 add sysmon_rbus |
-- 2016-02-20 734 1.4.2 add rgbdrv_analog_rbus for two rgb leds |
-- 2015-04-11 666 1.4.1 rearrange XON handling |
76,6 → 82,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.bpgenrbuslib.all; |
130,6 → 137,7
signal RB_SRES_RGB1 : rb_sres_type := rb_sres_init; |
signal RB_SRES_RGB : rb_sres_type := rb_sres_init; |
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; |
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
145,6 → 153,10
constant rbaddr_rgb1 : slv16 := x"fc04"; -- fe04/0004: 1111 1100 0000 01xx |
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx |
|
constant sysid_proj : slv16 := x"0101"; -- tst_rlink |
constant sysid_board : slv8 := x"05"; -- nexys4 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
170,7 → 182,7
|
CLKDIV : clkdivce |
generic map ( |
CDUWIDTH => 8, -- good up to 254 MHz |
CDUWIDTH => 7, -- good up to 127 MHz |
USECDIV => sys_conf_clksys_mhz, |
MSECDIV => 1000) |
port map ( |
222,12 → 234,12
generic map ( |
BTOWIDTH => 6, |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, |
OFAWIDTH => 5, |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 15, |
CDWIDTH => 12, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink |
RBMON_RBADDR => (others=>'0')) |
322,6 → 334,13
); |
end generate SMRB; |
|
UARB : rbd_usracc |
port map ( |
CLK => CLK, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_USRACC |
); |
|
RB_SRES_ORRGB : rb_sres_or_2 |
port map ( |
RB_SRES_1 => RB_SRES_RGB0, |
329,12 → 348,13
RB_SRES_OR => RB_SRES_RGB |
); |
|
RB_SRES_OR1 : rb_sres_or_4 |
RB_SRES_OR1 : rb_sres_or_6 |
port map ( |
RB_SRES_1 => RB_SRES_HIO, |
RB_SRES_2 => RB_SRES_TST, |
RB_SRES_3 => RB_SRES_RGB, |
RB_SRES_4 => RB_SRES_SYSMON, |
RB_SRES_5 => RB_SRES_USRACC, |
RB_SRES_OR => RB_SRES |
); |
|
/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/bpgen/bpgenrbuslib.vbom |
20,8 → 21,9
../../../bplib/bpgen/rgbdrv_master.vbom |
../../../bplib/bpgen/rgbdrv_analog_rbus.vbom |
../../../bplib/sysmon/sysmonx_rbus_base.vbom |
../../../vlib/rbus/rbd_usracc.vbom |
../../../vlib/rbus/rb_sres_or_2.vbom |
../../../vlib/rbus/rb_sres_or_4.vbom |
../../../vlib/rbus/rb_sres_or_6.vbom |
# design |
sys_tst_rlink_n4.vhd |
@ucf_cpp: sys_tst_rlink_n4.ucf |
/trunk/rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset
0,0 → 1,28
# $Id: sys_tst_rlink_n4.vmfset 773 2016-06-05 20:03:15Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# unconnected ports -------------------------------------------- |
I [Synth 8-3331] RB_MREQ # generic |
# --> I_BTNRST_N unused in design # OK 2016-06-05 |
I [Synth 8-3331] I_BTNRST_N |
# --> rlink_sp1c doesn't use CE_USEC # OK 2016-06-05 |
i [Synth 8-3331] rlink_sp1c.*CE_USEC |
|
# unused sequential element ------------------------------------ |
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic |
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 |
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop] |
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn] |
# --> LED(6:2) currently not driven # OK 2016-06-05 |
i [Synth 8-3332] R_REGS_reg[ledin][\d].*sn_humanio_rbus |
# ENAESC=0, therefore esc logic inactive # OK 2016-06-05 |
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen] |
i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend] |
# --> SER_MONI.rxovr indeed unused # OK 2016-06-05 |
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr] |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/tst_rlink/nexys4/Makefile
1,4 → 1,4
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ |
# $Id: Makefile 763 2016-04-22 17:48:24Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
21,6 → 21,5
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_vsyn) |
##include $(VBOM_all:.vbom=.dep_ghdl) |
endif |
# |
/trunk/rtl/sys_gen/tst_rlink/Makefile.ise
0,0 → 1,27
# -*- makefile-gmake -*- |
# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-12-11 438 1.0 Initial version |
# |
VBOM_all = $(wildcard *.vbom) |
NGC_all = $(VBOM_all:.vbom=.ngc) |
# |
include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk |
# |
.PHONY : all clean |
# |
all : $(NGC_all) |
# |
clean : ise_clean |
# |
# |
#---- |
# |
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
endif |
# |
/trunk/rtl/sys_gen/tst_rlink/s3board/sys_tst_rlink_s3.vhd
1,4 → 1,4
-- $Id: sys_tst_rlink_s3.vhd 743 2016-03-13 16:42:31Z mueller $ |
-- $Id: sys_tst_rlink_s3.vhd 748 2016-03-20 15:18:50Z mueller $ |
-- |
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
36,6 → 36,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-19 748 1.2.2 define rlink SYSID |
-- 2015-04-11 666 1.2.1 rearrange XON handling |
-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT |
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit |
131,6 → 132,10
|
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
|
constant sysid_proj : slv16 := x"0101"; -- tst_rlink |
constant sysid_board : slv8 := x"01"; -- s3board |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
194,7 → 199,7
generic map ( |
BTOWIDTH => 6, |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, |
OFAWIDTH => 5, |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
/trunk/rtl/sys_gen/w11a/arty_bram/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,9 → 16,14
-- Description: Definitions for sys_w11a_br_arty (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: viv 2015.4; ghdl 0.33 |
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype |
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural |
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) (@ 80 MHz) |
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser (@75 MHz) |
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth |
-- 2016-03-13 742 1.1 add sysmon_bus |
-- 2016-02-27 736 1.0 Initial version (derived from _b3 version) |
------------------------------------------------------------------------------ |
35,11 → 40,11
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
constant sys_conf_clksys_gentype : string := "MMCM"; |
-- single clock design, clkser = clksys |
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; |
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; |
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
-- dual clock design, clkser = 120 MHz |
constant sys_conf_clkser_vcodivide : positive := 1; |
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz |
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz |
constant sys_conf_clkser_gentype : string := "PLL"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
52,7 → 57,7
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs |
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs |
constant sys_conf_dmscnt : boolean := true; |
constant sys_conf_dmscnt : boolean := false; |
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs |
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) |
60,9 → 65,10
-- configure w11 cpu core -------------------------------------------------- |
-- sys_conf_mem_losize is highest 64 byte MMU block number |
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks |
constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; |
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/arty_bram/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,9 → 16,14
-- Description: Definitions for sys_w11a_br_arty (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: viv 2015.4; ghdl 0.33 |
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype |
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural |
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) |
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser |
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth |
-- 2016-03-13 742 1.1 add sysmon_bus |
-- 2016-02-27 736 1.0 Initial version |
------------------------------------------------------------------------------ |
32,14 → 37,14
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz |
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz |
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
constant sys_conf_clksys_gentype : string := "MMCM"; |
-- single clock design, clkser = clksys |
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; |
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; |
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
-- dual clock design, clkser = 120 MHz |
constant sys_conf_clkser_vcodivide : positive := 1; |
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz |
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz |
constant sys_conf_clkser_gentype : string := "PLL"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
52,7 → 57,7
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs |
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs |
constant sys_conf_dmscnt : boolean := true; |
constant sys_conf_dmscnt : boolean := false; |
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs |
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) |
60,9 → 65,10
-- configure w11 cpu core -------------------------------------------------- |
-- sys_conf_mem_losize is highest 64 byte MMU block number |
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks |
constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; |
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/arty_bram/tb/Makefile
1,7 → 1,9
# $Id: Makefile 736 2016-02-27 12:33:40Z mueller $ |
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 776 1.1.1 add xsim_clean |
# 2016-04-22 763 1.1 add include dep_vsim |
# 2016-02-27 736 1.0 Initial version |
# |
EXE_all = tb_w11a_br_arty |
8,17 → 10,25
# |
include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk |
# |
.PHONY : all all_ssim clean |
.PHONY : all all_ssim all_osim clean |
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
all_osim : $(EXE_all:=_osim) |
# |
clean : viv_clean ghdl_clean |
all_XSim : $(EXE_all:=_XSim) |
all_XSim_ssim : $(EXE_all:=_XSim_ssim) |
all_XSim_osim : $(EXE_all:=_XSim_osim) |
all_XSim_tsim : $(EXE_all:=_XSim_tsim) |
# |
clean : viv_clean ghdl_clean xsim_clean |
# |
#----- |
# |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
25,6 → 35,7
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_vsyn) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_vsim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
/trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
1,4 → 1,4
-- $Id: sys_w11a_br_arty.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_w11a_br_arty.vhd 768 2016-05-26 16:47:00Z mueller $ |
-- |
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,7 → 18,7
-- Dependencies: vlib/xlib/s7_cmt_sfs |
-- vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_2line_iob |
-- vlib/rlink/rlink_sp1c |
-- vlib/rlink/rlink_sp2c |
-- w11a/pdp11_sys70 |
-- ibus/ibdr_maxisys |
-- w11a/pdp11_bram_memctl |
27,20 → 27,27
-- bplib/bpgen/bp_swibtnled |
-- bplib/bpgen/rgbdrv_3x4mux |
-- bplib/sysmon/sysmonx_rbus_arty |
-- vlib/rbus/rb_sres_or_2 |
-- vlib/rbus/rbd_usracc |
-- vlib/rbus/rb_sres_or_3 |
-- |
-- Test bench: tb/tb_sys_w11a_br_arty |
-- |
-- Target Devices: generic |
-- Tool versions: viv 2015.4; ghdl 0.33 |
-- Tool versions: viv 2015.4-2016.1; ghdl 0.33 |
-- |
-- Synthesized: |
-- Date Rev viv Target flop lutl lutm bram slic |
-- 2016-05-26 768 2016.1 xc7a35t-1 2226 5080 138 47.5 1569 fsm+dsm=0 |
-- 2016-03-29 756 2015.4 xc7a35t-1 2106 4428 138 48.5 1397 serport2 |
-- 2016-03-27 753 2015.4 xc7a35t-1 1995 4298 138 48.5 1349 meminf |
-- 2016-03-13 742 2015.4 xc7a35t-1 1996 4309 162 48.5 1333 +XADC |
-- 2016-02-27 737 2015.4 xc7a35t-1 1952 4246 162 48.5 1316 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access) |
-- 2016-03-28 755 1.2 use serport_2clock2 |
-- 2016-03-19 748 1.1.2 define rlink SYSID |
-- 2016-03-13 742 1.1.1 add sysmon_rbus |
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config |
-- 2016-02-27 736 1.0 Initial version (derived from sys_w11a_b3) |
98,6 → 105,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.sysmonrbuslib.all; |
134,6 → 142,9
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CLKS : slbit := '0'; |
signal CES_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
|
142,6 → 153,7
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; |
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
187,6 → 199,10
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx |
|
constant sysid_proj : slv16 := x"0201"; -- w11a |
constant sysid_board : slv8 := x"07"; -- arty |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
193,7 → 209,7
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- |
GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ |
generic map ( |
VCO_DIVIDE => sys_conf_clksys_vcodivide, |
VCO_MULTIPLY => sys_conf_clksys_vcomultiply, |
208,7 → 224,7
LOCKED => open |
); |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clksys_mhz, |
219,9 → 235,35
CE_MSEC => CE_MSEC |
); |
|
GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ |
generic map ( |
VCO_DIVIDE => sys_conf_clkser_vcodivide, |
VCO_MULTIPLY => sys_conf_clkser_vcomultiply, |
OUT_DIVIDE => sys_conf_clkser_outdivide, |
CLKIN_PERIOD => 10.0, |
CLKIN_JITTER => 0.01, |
STARTUP_WAIT => false, |
GEN_TYPE => sys_conf_clkser_gentype) |
port map ( |
CLKIN => I_CLK100, |
CLKFX => CLKS, |
LOCKED => open |
); |
|
CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clkser_mhz, |
MSECDIV => 1000) |
port map ( |
CLK => CLKS, |
CE_USEC => open, |
CE_MSEC => CES_MSEC |
); |
|
IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- |
port map ( |
CLK => CLK, |
CLK => CLKS, |
RXD => RXD, |
TXD => TXD, |
I_RXD => I_RXD, |
228,16 → 270,16
O_TXD => O_TXD |
); |
|
RLINK : rlink_sp1c -- rlink for serport ----------------- |
RLINK : rlink_sp2c -- rlink for serport ----------------- |
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, -- 32 word input fifo |
OFAWIDTH => 5, -- 32 word output fifo |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDWIDTH => 12, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
247,6 → 289,8
CE_MSEC => CE_MSEC, |
CE_INT => CE_MSEC, |
RESET => RESET, |
CLKS => CLKS, |
CES_MSEC => CES_MSEC, |
ENAXON => '1', -- XON statically enabled ! |
ESCFILL => '0', |
RXSD => RXD, |
404,10 → 448,18
); |
end generate SMRB; |
|
RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- |
UARB : rbd_usracc |
port map ( |
CLK => CLK, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_USRACC |
); |
|
RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_SYSMON, |
RB_SRES_3 => RB_SRES_USRACC, |
RB_SRES_OR => RB_SRES |
); |
|
/trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/sysmon/sysmonrbuslib.vbom |
16,7 → 17,7
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_2line_iob.vbom |
../../../vlib/rlink/rlink_sp1c.vbom |
../../../vlib/rlink/rlink_sp2c.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../w11a/pdp11_bram_memctl.vbom |
25,7 → 26,8
../../../bplib/bpgen/bp_swibtnled.vbom |
../../../bplib/bpgen/rgbdrv_3x4mux.vbom |
../../../bplib/sysmon/sysmonx_rbus_arty.vbom |
../../../vlib/rbus/rb_sres_or_2.vbom |
../../../vlib/rbus/rbd_usracc.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
# design |
sys_w11a_br_arty.vhd |
@xdc:../../../bplib/arty/arty_pclk.xdc |
/trunk/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
0,0 → 1,50
# $Id: sys_w11a_br_arty.vmfset 773 2016-06-05 20:03:15Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# false_path -hold ignored by synth ---------------------------- |
I [Designutils 20-1567] # generic |
|
# net without driver ------------------------------------------- |
i [Synth 8-3848] DM_STAT_SE[snum].*pdp11_sequencer # OK 2016-06-05 |
|
# unconnected ports -------------------------------------------- |
I [Synth 8-3331] RB_MREQ # generic |
I [Synth 8-3331] DM_STAT_DP # generic |
# --> pdp11_hio70_arty uses only subset of CP_STAT info # OK 2016-06-05 |
I [Synth 8-3331] pdp11_hio70_arty.*CP_STAT[.*] |
|
# unused sequential element ------------------------------------ |
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic |
# --> many HIO pins not used # OK 2016-06-05 |
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] |
i [Synth 8-3332] HIO/IOB_BTN/R_DI_reg[\d*] |
i [Synth 8-3332] HIO/DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*] |
# --> usec not used for serport clock domain # OK 2016-06-05 |
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] |
# --> inst_compl logic disabled in pdp11_mmu # OK 2016-06-05 |
i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl] |
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2016-06-05 |
i [Synth 8-3332] VMBOX/R_REGS_reg[ibcacc] |
# --> not yet used # OK 2016-06-05 |
i [Synth 8-3332] SEQ/R_STATUS_reg[suspext] |
# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05 |
i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d] |
# --> indeed no types with [3] set # OK 2016-06-05 |
i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp |
# --> not yet used # OK 2016-06-05 |
i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist |
i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist |
# --> [8] is for DZ11TX, not yet available # OK 2016-06-05 |
# --> [9] is for DZ11RX, unclear why this one isn't removed too !! |
i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8] |
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-06-05 |
i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2] |
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05 |
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] |
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/w11a/basys3/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,9 → 16,14
-- Description: Definitions for sys_w11a_b3 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 |
-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype |
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural |
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) (@80 MHz) |
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser (@75 MHz) |
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth |
-- 2016-03-13 742 1.1.2 add sysmon_bus; use 72 MHz, no tc otherwise |
-- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions |
33,15 → 38,15
package sys_conf is |
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz |
constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
constant sys_conf_clksys_gentype : string := "MMCM"; |
-- single clock design, clkser = clksys |
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; |
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; |
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
-- dual clock design, clkser = 120 MHz |
constant sys_conf_clkser_vcodivide : positive := 1; |
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz |
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz |
constant sys_conf_clkser_gentype : string := "PLL"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
54,7 → 59,7
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs |
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs |
constant sys_conf_dmscnt : boolean := true; |
constant sys_conf_dmscnt : boolean := false; |
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs |
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) |
62,9 → 67,10
-- configure w11 cpu core -------------------------------------------------- |
-- sys_conf_mem_losize is highest 64 byte MMU block number |
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks |
constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; |
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/basys3/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,9 → 16,14
-- Description: Definitions for sys_w11a_b3 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 |
-- Tool versions: viv 2014.4-2016.2; ghdl 0.31-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype |
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural |
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) |
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser |
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth |
-- 2016-03-13 742 1.1.2 add sysmon_bus (but disabled like for fpga) |
-- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions |
34,14 → 39,14
|
-- configure clocks -------------------------------------------------------- |
constant sys_conf_clksys_vcodivide : positive := 1; |
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz |
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz |
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
constant sys_conf_clksys_gentype : string := "MMCM"; |
-- single clock design, clkser = clksys |
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; |
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; |
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
-- dual clock design, clkser = 120 MHz |
constant sys_conf_clkser_vcodivide : positive := 1; |
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz |
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz |
constant sys_conf_clkser_gentype : string := "PLL"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
54,7 → 59,7
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs |
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs |
constant sys_conf_dmscnt : boolean := true; |
constant sys_conf_dmscnt : boolean := false; |
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs |
constant sys_conf_rbd_sysmon : boolean := false; -- SYSMON(XADC) |
62,9 → 67,10
-- configure w11 cpu core -------------------------------------------------- |
-- sys_conf_mem_losize is highest 64 byte MMU block number |
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks |
constant sys_conf_mem_losize : integer := 256*sys_conf_memctl_nblock-1; |
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1; |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/basys3/tb/Makefile
1,7 → 1,9
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ |
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 776 1.1.1 add xsim_clean |
# 2016-04-22 763 1.1 add include dep_vsim |
# 2015-02-21 649 1.0 Initial version |
# |
EXE_all = tb_w11a_b3 |
8,17 → 10,25
# |
include ${RETROBASE}/rtl/make_viv/viv_default_basys3.mk |
# |
.PHONY : all all_ssim clean |
.PHONY : all all_ssim all_osim clean |
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
all_osim : $(EXE_all:=_osim) |
# |
clean : viv_clean ghdl_clean |
all_XSim : $(EXE_all:=_XSim) |
all_XSim_ssim : $(EXE_all:=_XSim_ssim) |
all_XSim_osim : $(EXE_all:=_XSim_osim) |
all_XSim_tsim : $(EXE_all:=_XSim_tsim) |
# |
clean : viv_clean ghdl_clean xsim_clean |
# |
#----- |
# |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
25,6 → 35,7
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_vsyn) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_vsim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
/trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd
1,4 → 1,4
-- $Id: sys_w11a_b3.vhd 745 2016-03-18 22:10:34Z mueller $ |
-- $Id: sys_w11a_b3.vhd 768 2016-05-26 16:47:00Z mueller $ |
-- |
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,7 → 18,7
-- Dependencies: vlib/xlib/s7_cmt_sfs |
-- vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_2line_iob |
-- vlib/rlink/rlink_sp1c |
-- vlib/rlink/rlink_sp2c |
-- w11a/pdp11_sys70 |
-- ibus/ibdr_maxisys |
-- w11a/pdp11_bram_memctl |
26,15 → 26,20
-- w11a/pdp11_hio70 |
-- bplib/bpgen/sn_humanio_rbus |
-- bplib/sysmon/sysmonx_rbus_base |
-- vlib/rbus/rb_sres_or_3 |
-- vlib/rbus/rbd_usracc |
-- vlib/rbus/rb_sres_or_4 |
-- |
-- Test bench: tb/tb_sys_w11a_b3 |
-- |
-- Target Devices: generic |
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31-0.33 |
-- Tool versions: viv 2014.4-2016.1; ghdl 0.31-0.33 |
-- |
-- Synthesized: |
-- Date Rev viv Target flop lutl lutm bram slic |
-- 2016-05-26 768 2016.1 xc7a35t-1 2361 5203 138 47.5 1600 fsm+dsm=0 |
-- 2016-05-22 767 2016.1 xc7a35t-1 2362 5340 138 48.5 1660 fsm |
-- 2016-03-29 756 2015.4 xc7a35t-1 2240 4518 138 48.5 1430 serport2 |
-- 2016-03-27 753 2015.4 xc7a35t-1 2131 4398 138 48.5 1362 meminf |
-- 2016-03-13 742 2015.4 xc7a35t-1 2135 4420 162 48.5 1396 +XADC |
-- 2015-06-04 686 2014.4 xc7a35t-1 1919 4372 162 47.5 1408 +TM11 17% |
-- 2015-05-14 680 2014.4 xc7a35t-1 1837 4304 162 47.5 1354 +RHRP 17% |
42,6 → 47,9
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access) |
-- 2016-03-28 755 2.3 use serport_2clock2 |
-- 2016-03-19 748 2.2.2 define rlink SYSID |
-- 2016-03-18 745 2.2.1 hardwire XON=1 |
-- 2016-03-13 742 2.2 add sysmon_rbus |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
104,6 → 112,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.bpgenrbuslib.all; |
137,6 → 146,9
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CLKS : slbit := '0'; |
signal CES_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
|
145,6 → 157,7
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; |
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
190,6 → 203,10
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx |
|
constant sysid_proj : slv16 := x"0201"; -- w11a |
constant sysid_board : slv8 := x"06"; -- basys3 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
196,7 → 213,7
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- |
GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ |
generic map ( |
VCO_DIVIDE => sys_conf_clksys_vcodivide, |
VCO_MULTIPLY => sys_conf_clksys_vcomultiply, |
211,7 → 228,7
LOCKED => open |
); |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clksys_mhz, |
222,9 → 239,35
CE_MSEC => CE_MSEC |
); |
|
GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ |
generic map ( |
VCO_DIVIDE => sys_conf_clkser_vcodivide, |
VCO_MULTIPLY => sys_conf_clkser_vcomultiply, |
OUT_DIVIDE => sys_conf_clkser_outdivide, |
CLKIN_PERIOD => 10.0, |
CLKIN_JITTER => 0.01, |
STARTUP_WAIT => false, |
GEN_TYPE => sys_conf_clkser_gentype) |
port map ( |
CLKIN => I_CLK100, |
CLKFX => CLKS, |
LOCKED => open |
); |
|
CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clkser_mhz, |
MSECDIV => 1000) |
port map ( |
CLK => CLKS, |
CE_USEC => open, |
CE_MSEC => CES_MSEC |
); |
|
IOB_RS232 : bp_rs232_2line_iob -- serport iob ---------------------- |
port map ( |
CLK => CLK, |
CLK => CLKS, |
RXD => RXD, |
TXD => TXD, |
I_RXD => I_RXD, |
231,16 → 274,16
O_TXD => O_TXD |
); |
|
RLINK : rlink_sp1c -- rlink for serport ----------------- |
RLINK : rlink_sp2c -- rlink for serport ----------------- |
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, -- 32 word input fifo |
OFAWIDTH => 5, -- 32 word output fifo |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDWIDTH => 12, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
250,6 → 293,8
CE_MSEC => CE_MSEC, |
CE_INT => CE_MSEC, |
RESET => RESET, |
CLKS => CLKS, |
CES_MSEC => CES_MSEC, |
ENAXON => '1', |
ESCFILL => '0', |
RXSD => RXD, |
399,11 → 444,19
); |
end generate SMRB; |
|
RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- |
UARB : rbd_usracc |
port map ( |
CLK => CLK, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_USRACC |
); |
|
RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_HIO, |
RB_SRES_3 => RB_SRES_SYSMON, |
RB_SRES_4 => RB_SRES_USRACC, |
RB_SRES_OR => RB_SRES |
); |
|
/trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/bpgen/bpgenrbuslib.vbom |
17,7 → 18,7
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_2line_iob.vbom |
../../../vlib/rlink/rlink_sp1c.vbom |
../../../vlib/rlink/rlink_sp2c.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../w11a/pdp11_bram_memctl.vbom |
25,7 → 26,8
../../../w11a/pdp11_hio70.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../bplib/sysmon/sysmonx_rbus_base.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
../../../vlib/rbus/rbd_usracc.vbom |
../../../vlib/rbus/rb_sres_or_4.vbom |
# design |
sys_w11a_b3.vhd |
@xdc:../../../bplib/basys3/basys3_pclk.xdc |
/trunk/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
0,0 → 1,46
# $Id: sys_w11a_b3.vmfset 773 2016-06-05 20:03:15Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# false_path -hold ignored by synth ---------------------------- |
I [Designutils 20-1567] # generic |
|
# net without driver ------------------------------------------- |
# --> snum currently disabled # OK 2016-06-04 |
i [Synth 8-3848] DM_STAT_SE[snum].*pdp11_sequencer |
|
# unconnected ports -------------------------------------------- |
I [Synth 8-3331] RB_MREQ # generic |
I [Synth 8-3331] DM_STAT_DP # generic |
|
# unused sequential element ------------------------------------ |
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic |
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic |
# --> usec not used for serport clock domain # OK 2016-06-04 |
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] |
# --> inst_compl logic disabled in pdp11_mmu # OK 2016-06-04 |
i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl] |
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2016-06-05 |
i [Synth 8-3332] VMBOX/R_REGS_reg[ibcacc] |
# --> not yet used # OK 2016-06-04 |
i [Synth 8-3332] SEQ/R_STATUS_reg[suspext] |
# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05 |
i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d] |
# --> indeed no types with [3] set # OK 2016-06-04 |
i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp |
# --> not yet used # OK 2016-06-04 |
i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist |
i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist |
# --> [8] is for DZ11TX, not yet available # OK 2016-06-04 |
# --> [9] is for DZ11RX, unclear why this one isn't removed too !! |
i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8] |
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-06-04 |
i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2] |
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-04 |
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] |
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.mfset
File deleted
\ No newline at end of file
/trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vhd
1,6 → 1,6
-- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ |
-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
16,9 → 16,11
-- Description: Definitions for sys_w11a_n2 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 |
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural |
-- 2016-03-22 750 1.5 add sys_conf_cache_twidth |
-- 2015-06-26 695 1.4.2 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-06-21 692 1.4.1 use clksys=52 (no closure after rhrp fixes) |
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions |
69,9 → 71,10
constant sys_conf_memctl_writedelay : positive := 4; |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd
1,6 → 1,6
-- $Id: sys_conf_sim.vhd 698 2015-07-05 21:20:18Z mueller $ |
-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
16,9 → 16,11
-- Description: Definitions for sys_w11a_n2 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31 |
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural |
-- 2016-03-22 750 1.5 add sys_conf_cache_twidth |
-- 2015-06-26 695 1.4.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions |
-- 2015-02-07 643 1.3 drop bram and minisys options |
63,9 → 65,10
constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
1,6 → 1,6
-- $Id: sys_w11a_n2.vhd 734 2016-02-20 22:43:20Z mueller $ |
-- $Id: sys_w11a_n2.vhd 748 2016-03-20 15:18:50Z mueller $ |
-- |
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
30,7 → 30,7
-- Test bench: tb/tb_sys_w11a_n2 |
-- |
-- Target Devices: generic |
-- Tool versions: xst 8.2-14.7; ghdl 0.26-0.31 |
-- Tool versions: xst 8.2-14.7; ghdl 0.26-0.33 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
67,6 → 67,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-19 748 2.1.1 define rlink SYSID |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 |
-- 2015-04-11 666 1.7.2 rearrange XON handling |
279,6 → 280,10
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
|
constant sysid_proj : slv16 := x"0201"; -- w11a |
constant sysid_board : slv8 := x"02"; -- nexys2 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
328,7 → 333,7
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, -- 32 word input fifo |
OFAWIDTH => 5, -- 32 word output fifo |
PETOWIDTH => sys_conf_fx2_petowidth, |
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.imfset
0,0 → 1,148
# $Id: sys_w11a_n2.imfset 779 2016-06-26 15:37:16Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Mux is complete : default of case is discarded |
INFO:.*You can improve the performance of the multiplier |
|
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected |
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected |
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected |
Node <HIO/R_REGS.swieff_\d*> of sequential type is unconnected |
Node <HIO/R_REGS.btneff_\d*> of sequential type is unconnected |
Node <HIO/R_REGS.swi_\d*> of sequential type is unconnected |
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected |
Node <MEM_SRAM.SRAM_CTL/R_REGS.addr0> of sequential type is unconnected |
|
Unconnected output port 'LOCKED' of component 'dcm_sfs' |
Unconnected output port 'RL_MONI' of component 'rlink_base_serport' |
Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport' |
Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as' |
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base' |
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' |
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen' |
|
Input <CP_STAT.cpuwait> is never used |
Input <CP_STAT.cmdbusy> is never used |
Input <IB_MREQ.cacc> is never used |
Input <IB_MREQ.rmw> is never used |
Input <IB_MREQ.din<\d*:\d*>> is never used |
Input <IB_MREQ.din<\d*>> is never used |
Input <IB_MREQ.racc> is never used |
Input <IB_MREQ.be0> is never used |
Input <IB_MREQ.be1> is never used |
Input <IB_MREQ.din> is never used |
Input <IB_MREQ.re> is never used |
Input <IB_MREQ.we> is never used |
Input <IB_MREQ.addr<\d*:\d*>> is never used |
Input <CCIN<2:1>> is never used |
Input <EI_ACK> is never used |
Input <IREG<\d*:\d*>> is never used |
Input <MONI.idone> is never used |
Input <MONI.trace_prev> is never used |
Input <DIN<\d*:\d*>> is never used |
Input <I_MEM_WAIT> is never used |
Input <RB_MREQ.init> is never used |
Input <RB_MREQ.din<\d*:\d*>> is never used |
Input <RB_MREQ.aval> is never used |
Input <RB_MREQ.re> is never used |
Input <CNTL.trap_done> is never used |
Input <VADDR<\d*:\d*>> is never used |
|
Signal <R_VMSTAT.trap_ysv> is assigned but never used |
Signal <R_VMSTAT.trap_mmu> is assigned but never used |
Signal <R_VMSTAT.ack> is assigned but never used |
Signal <R_IDSTAT.is_res> is assigned but never used |
Signal <R_IDSTAT.fork_srcr> is assigned but never used |
Signal <R_IDSTAT.fork_op> is assigned but never used |
Signal <R_IDSTAT.force_srcsp> is assigned but never used |
Signal <R_IDSTAT.do_pref_dec> is assigned but never used |
Signal <R_IDSTAT.do_fork_srcr> is assigned but never used |
Signal <R_IDSTAT.do_fork_opg> is assigned but never used |
Signal <R_IDSTAT.do_fork_op> is assigned but never used |
Signal <R_IDSTAT.do_fork_dsta> is assigned but never used |
|
Signal <DM_STAT_VM.ibsres.dout> is assigned but never used |
Signal <DM_STAT_VM.ibsres.busy> is assigned but never used |
Signal <DM_STAT_VM.ibsres.ack> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.we> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.rmw> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.re> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.racc> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.din> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.cacc> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.be1> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.be0> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.aval> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.addr> is assigned but never used |
Signal <DM_STAT_DP.psw.tflag> is assigned but never used |
Signal <DM_STAT_DP.psw.rset> is assigned but never used |
Signal <DM_STAT_DP.psw.pmode> is assigned but never used |
Signal <DM_STAT_DP.psw.cc> is assigned but never used |
Signal <DM_STAT_DP.pc> is assigned but never used |
Signal <DM_STAT_DP.ireg_we> is assigned but never used |
Signal <DM_STAT_DP.ireg> is assigned but never used |
Signal <DM_STAT_DP.gpr_we> is assigned but never used |
Signal <DM_STAT_DP.gpr_mode> is assigned but never used |
Signal <DM_STAT_DP.gpr_bytop> is assigned but never used |
Signal <DM_STAT_DP.gpr_adst> is assigned but never used |
Signal <DM_STAT_DP.dtmp> is assigned but never used |
Signal <DM_STAT_DP.dsrc> is assigned but never used |
Signal <DM_STAT_DP.dres> is assigned but never used |
Signal <DM_STAT_DP.ddst> is assigned but never used |
Signal <DM_STAT_CO.cpuhalt> is assigned but never used |
Signal <DM_STAT_CO.cpugo> is assigned but never used |
|
Signal <IIST_MREQ.lock> is assigned but never used |
Signal <IIST_MREQ.boot> is assigned but never used |
|
Signal <EI_ACK_RL11> is assigned but never used |
Signal <EI_ACK_KW11P> is assigned but never used |
Signal <EI_ACK_DZ11TX> is assigned but never used |
Signal <EI_ACK_DZ11RX> is assigned but never used |
Signal <EI_ACK<\d*>> is assigned but never used |
|
Signal <SIZE<\d*:\d*>> is assigned but never used |
Signal <SWI<\d*:\d*>> is assigned but never used |
Signal <BTN> is assigned but never used |
|
FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent |
FF/Latch <R_REGS.paddr_iopage_\d*> in Unit <pdp11_vmbox> is equivalent |
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent |
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.memdi_\d*> in Unit <sys_w11a_n2> is equivalent |
FF/Latch <CORE/SEQ/R_IDSTAT.aunit_srcmod_\d*> in Unit <sys_w11a_n2> is equivalent |
FF/Latch <CORE/SEQ/R_IDSTAT.fork_dsta_\d*> in Unit <sys_w11a_n2> is equivalent |
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_n2> is equivalent |
|
FF/Latch <R_SSR0.inst_compl> has a constant value of 0 |
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.cntdly_\d*> has a constant value of 0 |
FF/Latch <RLINK/BASE/RL/R_REGS.attn_\d*> has a constant value |
FF/Latch <MEM_SRAM.SRAM_CTL/IOB_MEM_ADDRH/R_DO_\d*> has a constant value of 0 |
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0 |
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0 |
|
# |
# ---------------------------------------------------------------------------- |
[tra] |
INFO:.*TNM.*used in period specification.*was traced into DCM_SP |
|
# |
# ---------------------------------------------------------------------------- |
[map] |
The signal <I_MEM_WAIT_IBUF> is incomplete |
Logical network I_MEM_WAIT_IBUF has no load |
There is a dangling output parity pin |
INFO:.* |
|
# |
# ---------------------------------------------------------------------------- |
[par] |
The signal I_MEM_WAIT_IBUF has no load |
There are 1 loadless signals in this design |
# |
# ---------------------------------------------------------------------------- |
[bgn] |
Spartan-3 1200E and 1600E devices do not support bitstream |
The signal <I_MEM_WAIT_IBUF> is incomplete |
There is a dangling output parity pin |
INFO:.*To achieve optimal frequency synthesis performance |
/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.mfset
File deleted
/trunk/rtl/sys_gen/w11a/nexys3/sys_conf.vhd
1,6 → 1,6
-- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ |
-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
16,9 → 16,11
-- Description: Definitions for sys_w11a_n3 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 |
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-28 770 1.5.1 sys_conf_mem_losize now type natural |
-- 2016-03-22 750 1.5 add sys_conf_cache_twidth |
-- 2015-06-26 695 1.4.2 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-06-21 692 1.4.1 use clksys=64 (no closure after rhrp fixes) |
-- 2015-03-14 658 1.4 add sys_conf_ibd_* definitions |
75,9 → 77,10
constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd
1,6 → 1,6
-- $Id: sys_conf_sim.vhd 718 2015-12-26 15:59:48Z mueller $ |
-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
16,9 → 16,11
-- Description: Definitions for sys_w11a_n3 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 |
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-28 770 1.6.1 sys_conf_mem_losize now type natural |
-- 2016-03-22 750 1.6 add sys_conf_cache_twidth |
-- 2015-12-26 718 1.5.2 use clksys=64 (as since r692 in sys_conf.vhd) |
-- 2015-06-26 695 1.5.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.5 add sys_conf_ibd_* definitions |
63,9 → 65,10
constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
1,6 → 1,6
-- $Id: sys_w11a_n3.vhd 734 2016-02-20 22:43:20Z mueller $ |
-- $Id: sys_w11a_n3.vhd 748 2016-03-20 15:18:50Z mueller $ |
-- |
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
30,7 → 30,7
-- Test bench: tb/tb_sys_w11a_n3 |
-- |
-- Target Devices: generic |
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31 |
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33 |
-- |
-- Synthesized (xst): |
-- Date Rev ise Target flop lutl lutm slic t peri |
52,6 → 52,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-19 748 2.1.1 define rlink SYSID |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 |
-- 2015-04-24 668 1.8.3 added ibd_ibmon |
247,6 → 248,10
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
|
constant sysid_proj : slv16 := x"0201"; -- w11a |
constant sysid_board : slv8 := x"03"; -- nexys3 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.imfset
0,0 → 1,45
# $Id: sys_w11a_n3.imfset 776 2016-06-18 17:22:51Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Case statement is complete. others clause is never selected |
INFO:.*The small RAM <.*> will be implemented on LUTs |
|
Output port <LOCKED> of the instance <GEN_CLKSYS> is unconnected |
Output port <FX2_MONI_.*> of the instance <RLINK> is unconnected |
Output port <BTN> of the instance <HIO> is unconnected |
Output port <RL_MONI_.*> of the instance <RLINK> is unconnected |
# |
Input <CP_STAT_.*> is never used |
Input <MONI_.*> is never used |
Input <SER_MONI_.*> is never used |
Input <IB_MREQ_.*> is never used |
Input <RB_MREQ_.*> is never used |
Input <RB_SRES_.*> is never used |
Input <DM_STAT_(DP|VM|CO|SE)_.*> is never used |
# |
INFO:.*Instance.*has been replaced by RAMB16BWER |
# |
# ---------------------------------------------------------------------------- |
[tra] |
INFO:.*TNM 'I_CLK100'.*was traced into DCM_SP |
INFO:.*Setting CLKIN_PERIOD attribute associated with DCM instance |
# |
# ---------------------------------------------------------------------------- |
[map] |
WARNING:.*has the attribute CLK_FEEDBACK set to NONE |
WARNING:.*The signal <I_MEM_WAIT_IBUF> is incomplete |
WARNING:.*to use input parity pin.*dangling output for parity pin |
INFO:.* |
# |
# ---------------------------------------------------------------------------- |
[par] |
WARNING:.*has the attribute CLK_FEEDBACK set to NONE |
WARNING:.*The signal I_MEM_WAIT_IBUF has no load |
WARNING:.*There are 1 loadless signals in this design |
# |
# ---------------------------------------------------------------------------- |
[bgn] |
WARNING:.*The signal <I_MEM_WAIT_IBUF> is incomplete |
WARNING:.*to use input parity pin.*dangling output for parity pin |
INFO:.*To achieve optimal frequency synthesis performance |
/trunk/rtl/sys_gen/w11a/nexys4/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_conf.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,9 → 16,16
-- Description: Definitions for sys_w11a_n4 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 |
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype |
-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise |
-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt |
-- 2016-05-28 770 1.4.2 sys_conf_mem_losize now type natural |
-- 2016-05-26 768 1.4.1 set dmscnt=0 (vivado fsm issue); TW=8 (@90 MHz) |
-- 2016-03-28 755 1.4 use serport_2clock2 -> define clkser (@75 MHz) |
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth, use TW=8 (16 kByte) |
-- 2016-03-13 742 1.2.2 add sysmon_bus |
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
47,11 → 54,11
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
constant sys_conf_clksys_gentype : string := "MMCM"; |
-- single clock design, clkser = clksys |
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; |
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; |
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
-- dual clock design, clkser = 120 MHz |
constant sys_conf_clkser_vcodivide : positive := 1; |
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz |
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz |
constant sys_conf_clkser_gentype : string := "PLL"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud |
65,16 → 72,17
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable |
constant sys_conf_dmscnt : boolean := true; |
constant sys_conf_dmscnt : boolean := false; |
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 0; -- use 0 to disable, 9 to use |
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
|
constant sys_conf_cache_twidth : integer := 6; -- 64kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11 |
/trunk/rtl/sys_gen/w11a/nexys4/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_conf_sim.vhd 775 2016-06-18 13:42:00Z mueller $ |
-- |
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
16,9 → 16,16
-- Description: Definitions for sys_w11a_n4 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: xst 14.5-14.7; ghdl 0.29-0.33 |
-- Tool versions: xst 14.5-14.7; viv 2016.1-2016.2; ghdl 0.29-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-06-18 775 1.4.5 use PLL for clkser_gentype |
-- 2016-06-04 772 1.4.4 go for 80 MHz and 64 kB cache, best compromise |
-- 2016-05-28 771 1.4.3 set dmcmon_awidth=0, useless without dmscnt |
-- 2016-05-28 770 1.4.2 sys_conf_mem_losize now type natural |
-- 2016-05-26 768 1.4.1 set dmscnt=0 (vivado fsm issue); TW=8 (@90 MHz) |
-- 2016-03-28 755 1.4 use serport_2clock2 -> define clkser |
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth |
-- 2016-03-13 742 1.2.2 add sysmon_bus |
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
38,11 → 45,11
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz |
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz |
constant sys_conf_clksys_gentype : string := "MMCM"; |
-- single clock design, clkser = clksys |
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide; |
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply; |
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide; |
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype; |
-- dual clock design, clkser = 120 MHz |
constant sys_conf_clkser_vcodivide : positive := 1; |
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz |
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz |
constant sys_conf_clkser_gentype : string := "PLL"; |
|
-- configure rlink and hio interfaces -------------------------------------- |
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim |
56,15 → 63,16
-- configure debug and monitoring units ------------------------------------ |
constant sys_conf_rbmon_awidth : integer := 9; -- use 0 to disable |
constant sys_conf_ibmon_awidth : integer := 9; -- use 0 to disable |
constant sys_conf_dmscnt : boolean := true; |
constant sys_conf_dmscnt : boolean := false; |
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable |
constant sys_conf_dmcmon_awidth : integer := 0; -- use 0 to disable, 9 to use |
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC) |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte |
constant sys_conf_mem_losize : natural := 8#167777#; -- 4 MByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 6; -- 64kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/nexys4/tb/Makefile
1,7 → 1,9
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $ |
# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2016-06-18 776 1.1.1 add xsim_clean |
# 2016-04-22 763 1.1 add include dep_vsim |
# 2016-02-07 729 1.0.1 add generic_xsim.mk |
# 2015-02-14 646 1.0 Initial version |
# 2015-02-01 640 0.1 First draft |
10,7 → 12,8
# |
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk |
# |
.PHONY : all all_ssim clean |
.PHONY : all all_ssim all_osim clean |
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim |
# |
all : $(EXE_all) |
all_ssim : $(EXE_all:=_ssim) |
21,13 → 24,13
all_XSim_osim : $(EXE_all:=_XSim_osim) |
all_XSim_tsim : $(EXE_all:=_XSim_tsim) |
# |
clean : viv_clean ghdl_clean |
clean : viv_clean ghdl_clean xsim_clean |
# |
#----- |
# |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk |
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk |
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk |
# |
VBOM_all = $(wildcard *.vbom) |
# |
34,6 → 37,7
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_vsyn) |
include $(VBOM_all:.vbom=.dep_ghdl) |
include $(VBOM_all:.vbom=.dep_vsim) |
include $(wildcard *.o.dep_ghdl) |
endif |
# |
/trunk/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
1,4 → 1,4
-- $Id: sys_w11a_n4.vhd 742 2016-03-13 14:40:19Z mueller $ |
-- $Id: sys_w11a_n4.vhd 768 2016-05-26 16:47:00Z mueller $ |
-- |
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
18,7 → 18,7
-- Dependencies: vlib/xlib/s7_cmt_sfs |
-- vlib/genlib/clkdivce |
-- bplib/bpgen/bp_rs232_4line_iob |
-- vlib/rlink/rlink_sp1c |
-- vlib/rlink/rlink_sp2c |
-- w11a/pdp11_sys70 |
-- ibus/ibdr_maxisys |
-- bplib/nxcramlib/nx_cram_memctl_as |
26,25 → 26,34
-- w11a/pdp11_hio70 |
-- bplib/bpgen/sn_humanio_rbus |
-- bplib/sysmon/sysmonx_rbus_base |
-- vlib/rbus/rb_sres_or_3 |
-- vlib/rbus/rbd_usracc |
-- vlib/rbus/rb_sres_or_4 |
-- |
-- Test bench: tb/tb_sys_w11a_n4 |
-- |
-- Target Devices: generic |
-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33 |
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.1; ghdl 0.29-0.33 |
-- |
-- Synthesized: |
-- Date Rev viv Target flop lutl lutm bram slic MHz |
-- 2016-05-26 768 2016.1 xc7a100t-1 2777 5672 150 10.0 1763 90 dms=0 |
-- 2016-05-22 767 2016.1 xc7a100t-1 2790 5774 150 11.0 1812 75 fsm |
-- 2016-03-29 756 2015.4 xc7a100t-1 2651 4955 150 11.0 1608 75 2clock |
-- 2016-03-27 753 2015.4 xc7a100t-1 2545 4850 150 11.0 1576 80 meminf |
-- 2016-03-27 752 2015.4 xc7a100t-1 2544 4875 178 13.0 1569 80 +TW=8 |
-- 2016-03-13 742 2015.4 xc7a100t-1 2536 4868 178 10.5 1542 80 +XADC |
-- 2015-06-04 686 2014.4 xc7a100t-1 2111 4541 162 7.5 1469 80 +TM11 |
-- 2015-05-14 680 2014.4 xc7a100t-1 2030 4459 162 7.5 1427 80 |
-- 2015-02-22 650 2014.4 xc7a100t-1 1606 3652 146 3.5 1158 80 |
-- 2015-02-22 650 i 17.7 xc7a100t-1 1670 3564 124 1508 80 |
-- 2015-02-22 650 i 14.7 xc7a100t-1 1670 3564 124 1508 80 |
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access) |
-- 2016-03-28 755 2.3 use serport_2clock2 |
-- 2016-03-19 748 2.2.1 define rlink SYSID |
-- 2016-03-13 742 2.2 add sysmon_rbus |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; ; reset overhaul |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 |
-- 2015-04-11 666 1.4.2 rearrange XON handling |
-- 2015-02-21 649 1.4.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) |
113,6 → 122,7
use work.genlib.all; |
use work.serportlib.all; |
use work.rblib.all; |
use work.rbdlib.all; |
use work.rlinklib.all; |
use work.bpgenlib.all; |
use work.bpgenrbuslib.all; |
162,6 → 172,9
signal CE_USEC : slbit := '0'; |
signal CE_MSEC : slbit := '0'; |
|
signal CLKS : slbit := '0'; |
signal CES_MSEC : slbit := '0'; |
|
signal RXD : slbit := '1'; |
signal TXD : slbit := '0'; |
signal RTS_N : slbit := '0'; |
172,6 → 185,7
signal RB_SRES_CPU : rb_sres_type := rb_sres_init; |
signal RB_SRES_HIO : rb_sres_type := rb_sres_init; |
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init; |
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init; |
|
signal RB_LAM : slv16 := (others=>'0'); |
signal RB_STAT : slv4 := (others=>'0'); |
220,6 → 234,10
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx |
|
constant sysid_proj : slv16 := x"0201"; -- w11a |
constant sysid_board : slv8 := x"05"; -- nexys4 |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
assert (sys_conf_clksys mod 1000000) = 0 |
226,7 → 244,7
report "assert sys_conf_clksys on MHz grid" |
severity failure; |
|
GEN_CLKSYS : s7_cmt_sfs -- clock generator ------------------- |
GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------ |
generic map ( |
VCO_DIVIDE => sys_conf_clksys_vcodivide, |
VCO_MULTIPLY => sys_conf_clksys_vcomultiply, |
241,7 → 259,7
LOCKED => open |
); |
|
CLKDIV : clkdivce -- usec/msec clock divider ----------- |
CLKDIV_CLK : clkdivce -- usec/msec clock divider system ---- |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clksys_mhz, |
252,9 → 270,35
CE_MSEC => CE_MSEC |
); |
|
GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------ |
generic map ( |
VCO_DIVIDE => sys_conf_clkser_vcodivide, |
VCO_MULTIPLY => sys_conf_clkser_vcomultiply, |
OUT_DIVIDE => sys_conf_clkser_outdivide, |
CLKIN_PERIOD => 10.0, |
CLKIN_JITTER => 0.01, |
STARTUP_WAIT => false, |
GEN_TYPE => sys_conf_clkser_gentype) |
port map ( |
CLKIN => I_CLK100, |
CLKFX => CLKS, |
LOCKED => open |
); |
|
CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport --- |
generic map ( |
CDUWIDTH => 7, |
USECDIV => sys_conf_clkser_mhz, |
MSECDIV => 1000) |
port map ( |
CLK => CLKS, |
CE_USEC => open, |
CE_MSEC => CES_MSEC |
); |
|
IOB_RS232 : bp_rs232_4line_iob -- serport iob ---------------------- |
port map ( |
CLK => CLK, |
CLK => CLKS, |
RXD => RXD, |
TXD => TXD, |
CTS_N => CTS_N, |
265,16 → 309,16
O_RTS_N => O_RTS_N |
); |
|
RLINK : rlink_sp1c -- rlink for serport ----------------- |
RLINK : rlink_sp2c -- rlink for serport ----------------- |
generic map ( |
BTOWIDTH => 7, -- 128 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, -- 32 word input fifo |
OFAWIDTH => 5, -- 32 word output fifo |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
ENAPIN_RBMON => sbcntl_sbf_rbmon, |
CDWIDTH => 13, |
CDWIDTH => 12, |
CDINIT => sys_conf_ser2rri_cdinit, |
RBMON_AWIDTH => sys_conf_rbmon_awidth, |
RBMON_RBADDR => rbaddr_rbmon) |
284,6 → 328,8
CE_MSEC => CE_MSEC, |
CE_INT => CE_MSEC, |
RESET => RESET, |
CLKS => CLKS, |
CES_MSEC => CES_MSEC, |
ENAXON => SWI(1), |
ESCFILL => '0', |
RXSD => RXD, |
445,11 → 491,19
); |
end generate SMRB; |
|
RB_SRES_OR : rb_sres_or_3 -- rbus or --------------------------- |
UARB : rbd_usracc |
port map ( |
CLK => CLK, |
RB_MREQ => RB_MREQ, |
RB_SRES => RB_SRES_USRACC |
); |
|
RB_SRES_OR : rb_sres_or_4 -- rbus or --------------------------- |
port map ( |
RB_SRES_1 => RB_SRES_CPU, |
RB_SRES_2 => RB_SRES_HIO, |
RB_SRES_3 => RB_SRES_SYSMON, |
RB_SRES_4 => RB_SRES_USRACC, |
RB_SRES_OR => RB_SRES |
); |
|
/trunk/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom
4,6 → 4,7
../../../vlib/genlib/genlib.vhd |
../../../vlib/serport/serportlib.vbom |
../../../vlib/rbus/rblib.vhd |
../../../vlib/rbus/rbdlib.vhd |
../../../vlib/rlink/rlinklib.vbom |
../../../bplib/bpgen/bpgenlib.vbom |
../../../bplib/bpgen/bpgenrbuslib.vbom |
18,7 → 19,7
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom |
../../../vlib/genlib/clkdivce.vbom |
../../../bplib/bpgen/bp_rs232_4line_iob.vbom |
../../../vlib/rlink/rlink_sp1c.vbom |
../../../vlib/rlink/rlink_sp2c.vbom |
../../../w11a/pdp11_sys70.vbom |
../../../ibus/ibdr_maxisys.vbom |
../../../bplib/nxcramlib/nx_cram_memctl_as.vbom |
26,7 → 27,8
../../../w11a/pdp11_hio70.vbom |
../../../bplib/bpgen/sn_humanio_rbus.vbom |
../../../bplib/sysmon/sysmonx_rbus_base.vbom |
../../../vlib/rbus/rb_sres_or_3.vbom |
../../../vlib/rbus/rbd_usracc.vbom |
../../../vlib/rbus/rb_sres_or_4.vbom |
# design |
sys_w11a_n4.vhd |
# constraints |
34,3 → 36,4
@xdc:../../../bplib/nexys4/nexys4_pclk.xdc |
@xdc:../../../bplib/nexys4/nexys4_pins.xdc |
@xdc:../../../bplib/nexys4/nexys4_pins_cram.xdc |
#@xdc:sys_w11a_n4.xdc |
/trunk/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
0,0 → 1,64
# $Id: sys_w11a_n4.vmfset 774 2016-06-12 17:08:47Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# false_path -hold ignored by synth ---------------------------- |
I [Designutils 20-1567] |
|
# net without driver ------------------------------------------- |
# --> snum currently disabled # OK 2016-05-28 |
i [Synth 8-3848] DM_STAT_SE[snum].*pdp11_sequencer |
|
# port driven by constant -------------------------------------- |
# --> RGBLED0 currently unused # OK 2016-05-28 |
i [Synth 8-3917] O_RGBLED0[\d] |
|
# unconnected ports -------------------------------------------- |
I [Synth 8-3331] RB_MREQ # generic |
I [Synth 8-3331] DM_STAT_DP # generic |
|
# unused sequential element ------------------------------------ |
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic |
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic |
# --> only 4 MB out of 16 MB used # OK 2016-05-28 |
i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[20] |
i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[21] |
# --> usec not used for serport clock domain # OK 2016-05-28 |
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec] |
# --> inst_compl logic disabled in pdp11_mmu # OK 2016-05-28 |
i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl] |
# --> not yet used # OK 2016-05-28 |
i [Synth 8-3332] SEQ/R_STATUS_reg[suspext] |
# --> indeed no types with [3] set # OK 2016-05-28 |
i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp |
# --> not yet used # OK 2016-05-28 |
i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist |
i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist |
# --> [8] is for DZ11TX, not yet available # OK 2016-05-28 |
# --> [9] is for DZ11RX, unclear why this one isn't removed too !! |
i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8] |
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-05-28 |
i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2] |
# --> monitor outputs moneop,monattn currently not used # OK 2016-05-28 |
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop] |
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn] |
|
# INFO: encoded FSM with state register as -------------------- |
# test for sys_w11a_n4 that all FSMs are one_hot |
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core' |
r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox' |
r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'nx_cram_memctl_as' |
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core' |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.mfset
File deleted
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.imfset
0,0 → 1,120
# $Id: sys_w11a_s3.imfset 769 2016-05-28 11:36:22Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Mux is complete : default of case is discarded |
|
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected |
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected |
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected |
|
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen' |
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen' |
Unconnected output port 'ACK_W' of component 's3_sram_memctl' |
|
Input <CP_STAT.cpuwait> is never used |
Input <CP_STAT.cmdbusy> is never used |
Input <IB_MREQ.cacc> is never used |
Input <IB_MREQ.rmw> is never used |
Input <IB_MREQ.din<\d*:\d*>> is never used |
Input <IB_MREQ.din<\d*>> is never used |
Input <IB_MREQ.racc> is never used |
Input <IB_MREQ.be0> is never used |
Input <IB_MREQ.be1> is never used |
Input <IB_MREQ.din> is never used |
Input <IB_MREQ.re> is never used |
Input <IB_MREQ.we> is never used |
Input <IB_MREQ.addr<\d*:\d*>> is never used |
Input <CCIN<2:1>> is never used |
Input <EI_ACK> is never used |
Input <IREG<\d*:\d*>> is never used |
Input <MONI.idone> is never used |
Input <MONI.trace_prev> is never used |
Input <DIN<\d*:\d*>> is never used |
Input <CNTL.trap_done> is never used |
Input <VADDR<\d*:\d*>> is never used |
|
Signal <R_VMSTAT.trap_ysv> is assigned but never used |
Signal <R_VMSTAT.trap_mmu> is assigned but never used |
Signal <R_VMSTAT.ack> is assigned but never used |
Signal <R_IDSTAT.is_res> is assigned but never used |
Signal <R_IDSTAT.fork_srcr> is assigned but never used |
Signal <R_IDSTAT.fork_op> is assigned but never used |
Signal <R_IDSTAT.force_srcsp> is assigned but never used |
Signal <R_IDSTAT.do_pref_dec> is assigned but never used |
Signal <R_IDSTAT.do_fork_srcr> is assigned but never used |
Signal <R_IDSTAT.do_fork_opg> is assigned but never used |
Signal <R_IDSTAT.do_fork_op> is assigned but never used |
Signal <R_IDSTAT.do_fork_dsta> is assigned but never used |
|
Signal <DM_STAT_VM.ibsres.dout> is assigned but never used |
Signal <DM_STAT_VM.ibsres.busy> is assigned but never used |
Signal <DM_STAT_VM.ibsres.ack> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.we> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.rmw> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.re> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.racc> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.din> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.cacc> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.be1> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.be0> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.aval> is assigned but never used |
Signal <DM_STAT_VM.ibmreq.addr> is assigned but never used |
Signal <DM_STAT_DP.psw.tflag> is assigned but never used |
Signal <DM_STAT_DP.psw.rset> is assigned but never used |
Signal <DM_STAT_DP.psw.pmode> is assigned but never used |
Signal <DM_STAT_DP.psw.cc> is assigned but never used |
Signal <DM_STAT_DP.pc> is assigned but never used |
Signal <DM_STAT_DP.ireg_we> is assigned but never used |
Signal <DM_STAT_DP.ireg> is assigned but never used |
Signal <DM_STAT_DP.gpr_we> is assigned but never used |
Signal <DM_STAT_DP.gpr_mode> is assigned but never used |
Signal <DM_STAT_DP.gpr_bytop> is assigned but never used |
Signal <DM_STAT_DP.gpr_adst> is assigned but never used |
Signal <DM_STAT_DP.dtmp> is assigned but never used |
Signal <DM_STAT_DP.dsrc> is assigned but never used |
Signal <DM_STAT_DP.dres> is assigned but never used |
Signal <DM_STAT_DP.ddst> is assigned but never used |
Signal <DM_STAT_CO.cpuhalt> is assigned but never used |
Signal <DM_STAT_CO.cpugo> is assigned but never used |
|
Signal <IIST_MREQ.lock> is assigned but never used |
Signal <IIST_MREQ.boot> is assigned but never used |
|
Signal <EI_ACK_RL11> is assigned but never used |
Signal <EI_ACK_KW11P> is assigned but never used |
Signal <EI_ACK_DZ11TX> is assigned but never used |
Signal <EI_ACK_DZ11RX> is assigned but never used |
Signal <EI_ACK<\d*>> is assigned but never used |
|
Signal <MEM_ADDR<\d*:\d*>> is assigned but never used |
|
FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent |
FF/Latch <R_REGS.paddr_iopage_\d*> in Unit <pdp11_vmbox> is equivalent |
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent |
FF/Latch <CORE/SEQ/R_IDSTAT.fork_dsta_\d*> in Unit <sys_w11a_s3> is equivalent |
FF/Latch <CORE/SEQ/R_IDSTAT.aunit_srcmod_\d*> in Unit <sys_w11a_s3> is equivalent |
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_s3> is equivalent |
|
FF/Latch <R_SSR0.inst_compl> has a constant value of 0 |
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0 |
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0 |
|
# |
# ---------------------------------------------------------------------------- |
[tra] |
|
# |
# ---------------------------------------------------------------------------- |
[map] |
There is a dangling output parity pin |
INFO:.* |
|
# |
# ---------------------------------------------------------------------------- |
[par] |
|
# |
# ---------------------------------------------------------------------------- |
[bgn] |
There is a dangling output parity pin |
/trunk/rtl/sys_gen/w11a/s3board/sys_conf.vhd
1,6 → 1,6
-- $Id: sys_conf.vhd 698 2015-07-05 21:20:18Z mueller $ |
-- $Id: sys_conf.vhd 770 2016-05-28 14:15:00Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
16,9 → 16,11
-- Description: Definitions for sys_w11a_s3 (for synthesis) |
-- |
-- Dependencies: - |
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 |
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-27 770 1.3.1 sys_conf_mem_losize now type natural |
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth |
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
-- 2014-12-22 619 1.1.2 add _rbmon_awidth |
46,9 → 48,10
constant sys_conf_dmcmon_awidth : integer := 9; -- use 0 to disable |
|
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte |
constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/s3board/tb/sys_conf_sim.vhd
1,6 → 1,6
-- $Id: sys_conf_sim.vhd 698 2015-07-05 21:20:18Z mueller $ |
-- $Id: sys_conf_sim.vhd 770 2016-05-28 14:15:00Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
16,9 → 16,11
-- Description: Definitions for sys_w11a_s3 (for simulation) |
-- |
-- Dependencies: - |
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31 |
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.33 |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-05-28 770 1.3.1 sys_conf_mem_losize now type natural |
-- 2016-03-22 750 1.3 add sys_conf_cache_twidth |
-- 2015-06-26 695 1.2.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*) |
-- 2015-03-14 658 1.2 add sys_conf_ibd_* definitions |
-- 2014-12-22 619 1.1.2 add _rbmon_awidth |
48,14 → 50,15
-- configure w11 cpu core -------------------------------------------------- |
constant sys_conf_bram : integer := 0; -- no bram, use cache |
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB) |
constant sys_conf_mem_losize : integer := 8#037777#; -- 1 MByte |
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug) |
constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte |
--constant sys_conf_mem_losize : natural := 8#003777#; -- 128 kByte (debug) |
|
-- constant sys_conf_bram : integer := 1; -- bram only |
-- constant sys_conf_bram_awidth : integer := 16; -- bram size (64 kB) |
-- constant sys_conf_mem_losize : integer := 8#001777#; -- 64 kByte |
-- constant sys_conf_mem_losize : natural := 8#001777#; -- 64 kByte |
|
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled |
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache |
|
-- configure w11 system devices -------------------------------------------- |
-- configure character and communication devices |
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
1,6 → 1,6
-- $Id: sys_w11a_s3.vhd 734 2016-02-20 22:43:20Z mueller $ |
-- $Id: sys_w11a_s3.vhd 748 2016-03-20 15:18:50Z mueller $ |
-- |
-- Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> |
-- |
-- This program is free software; you may redistribute and/or modify it under |
-- the terms of the GNU General Public License as published by the Free |
74,6 → 74,7
-- |
-- Revision History: |
-- Date Rev Version Comment |
-- 2016-03-19 748 2.1.1 define rlink SYSID |
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul |
-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form |
-- 2015-04-11 666 1.7.1 rearrange XON handling |
277,6 → 278,10
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx |
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx |
|
constant sysid_proj : slv16 := x"0201"; -- w11a |
constant sysid_board : slv8 := x"01"; -- s3board |
constant sysid_vers : slv8 := x"00"; |
|
begin |
|
CLK <= I_CLK50; -- use 50MHz as system clock |
313,7 → 318,7
generic map ( |
BTOWIDTH => 6, -- 64 cycles access timeout |
RTAWIDTH => 12, |
SYSID => (others=>'0'), |
SYSID => sysid_proj & sysid_board & sysid_vers, |
IFAWIDTH => 5, -- 32 word input fifo |
OFAWIDTH => 5, -- 32 word output fifo |
ENAPIN_RLMON => sbcntl_sbf_rlmon, |
/trunk/rtl/sys_gen/tst_snhumanio/Makefile
File deleted
/trunk/rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset
0,0 → 1,10
# $Id: sys_tst_snhumanio_b3.vmfset 772 2016-06-05 12:55:11Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# --> really no messages ... ! |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.imfset
0,0 → 1,34
# $Id: sys_tst_snhumanio_n2.imfset 769 2016-05-28 11:36:22Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Mux is complete : default of case is discarded |
|
Unconnected output port 'CE_USEC' of component 'clkdivce' |
|
Input <I_MEM_WAIT> is never used |
|
FF/Latch <R_REGS.ucnt_\d*> has a constant value of 0 |
Node <CLKDIV/R_REGS.usec> of sequential type is unconnected |
|
# |
# ---------------------------------------------------------------------------- |
[tra] |
|
# |
# ---------------------------------------------------------------------------- |
[map] |
The signal <I_MEM_WAIT_IBUF> is incomplete |
INFO:.* |
|
# |
# ---------------------------------------------------------------------------- |
[par] |
The signal I_MEM_WAIT_IBUF has no load |
There are 1 loadless signals in this design |
|
# |
# ---------------------------------------------------------------------------- |
[bgn] |
Spartan-3 1200E and 1600E devices do not support bitstream |
The signal <I_MEM_WAIT_IBUF> is incomplete |
/trunk/rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset
0,0 → 1,16
# $Id: sys_tst_snhumanio_n4.vmfset 772 2016-06-05 12:55:11Z mueller $ |
# |
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[syn] |
# port driven by constant -------------------------------------- |
# --> RGBLED0 and upper 4 DSP digits unused # OK 2016-06-05 |
i [Synth 8-3917] O_RGBLED0[\d] |
i [Synth 8-3917] O_ANO_N[4] |
i [Synth 8-3917] O_ANO_N[5] |
i [Synth 8-3917] O_ANO_N[6] |
i [Synth 8-3917] O_ANO_N[7] |
|
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
[imp] |
I [Vivado 12-2489] # multiple of 1 ps |
I [Physopt 32-742] # BRAM Flop Optimization |
/trunk/rtl/sys_gen/tst_snhumanio/atlys/sys_tst_snhumanio_atlys.imfset
0,0 → 1,29
# $Id: sys_tst_snhumanio_atlys.imfset 769 2016-05-28 11:36:22Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Case statement is complete. others clause is never selected |
|
sys_tst_snhumanio_atlys\..*Output port <CE_USEC> of the instance <CLKDIV> is unconnected |
|
Node <CLKDIV/R_REGS_usec> of sequential type is unconnected |
|
The FF/Latch <HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[0-1]> in Unit <.*> is equivalent |
The small RAM <.*> will be implemented on LUTs |
|
# |
# ---------------------------------------------------------------------------- |
[tra] |
|
# |
# ---------------------------------------------------------------------------- |
[map] |
INFO:.* |
|
# |
# ---------------------------------------------------------------------------- |
[par] |
|
# |
# ---------------------------------------------------------------------------- |
[bgn] |
/trunk/rtl/sys_gen/tst_snhumanio/Makefile.ise
0,0 → 1,26
# -*- makefile-gmake -*- |
# $Id: Makefile.ise 757 2016-04-02 11:19:06Z mueller $ |
# |
# Revision History: |
# Date Rev Version Comment |
# 2011-09-17 410 1.0 Initial version |
# |
VBOM_all = $(wildcard *.vbom) |
NGC_all = $(VBOM_all:.vbom=.ngc) |
# |
include ${RETROBASE}/rtl/make_ise/xflow_default_s3board.mk |
# |
.PHONY : all clean |
# |
all : $(NGC_all) |
# |
clean : ise_clean |
# |
#---- |
# |
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk |
# |
ifndef DONTINCDEP |
include $(VBOM_all:.vbom=.dep_xst) |
endif |
# |
/trunk/rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.imfset
0,0 → 1,27
# $Id: sys_tst_snhumanio_s3.imfset 769 2016-05-28 11:36:22Z mueller $ |
# |
# ---------------------------------------------------------------------------- |
[xst] |
INFO:.*Mux is complete : default of case is discarded |
|
Unconnected output port 'CE_USEC' of component 'clkdivce' |
|
FF/Latch <R_REGS.ucnt_\d*> has a constant value of 0 |
Node <CLKDIV/R_REGS.usec> of sequential type is unconnected |
|
# |
# ---------------------------------------------------------------------------- |
[tra] |
|
# |
# ---------------------------------------------------------------------------- |
[map] |
INFO:.* |
|
# |
# ---------------------------------------------------------------------------- |
[par] |
|
# |
# ---------------------------------------------------------------------------- |
[bgn] |
trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
Property changes :
Deleted: svn:ignore
## -1,43 +0,0 ##
-*.gz
-*.tar
-*.tgz
-*.dep_*
-work-obj93.cf
-*.vcd
-*.ghw
-*.sav
-*.tmp
-*.exe
-ise
-xflow.his
-*.ngc
-*.ncd
-*.pcf
-*.bit
-*.msk
-*.svf
-*.log
-isim
-*_[sfot]sim.vhd
-*_tsim.sdf
-rlink_cext_fifo_[rt]x
-rlink_cext_conf
-tmu_ofile
-*.dsk
-*.tap
-*.lst
-*.cof
-.Xil
-project_mflow
-xsim.dir
-webtalk_*
-*_[sfot]sim
-*_[IX]Sim
-*_[IX]Sim_[sfot]sim
-*.dcp
-*.jou
-*.pb
-*.prj
-*.rpt
-*.wdb
-sys_tst_rlink_cuff_ic3_n2.ucf
Index: trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset
===================================================================
--- trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset (revision 35)
+++ trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.mfset (nonexistent)
@@ -1,104 +0,0 @@
-# $Id: sys_tst_rlink_cuff_ic_n2.mfset 466 2012-12-30 13:26:55Z mueller $
-#
-# ----------------------------------------------------------------------------
-[xst]
-INFO:.*Mux is complete : default of case is discarded
-
-Register in unit has a constant value
-Register in unit has a constant value
-Register in unit has a constant value
-Register in unit has a constant value
-Register in unit has a constant value
-Register in unit has a constant value
-
-Unconnected output port 'SIZE' of component 'fifo_1c_dram'
-Unconnected output port 'LOCKED' of component 'dcm_sfs'
-Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
-Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
-Unconnected output port 'RL_MONI' of component 'rlink_core8'
-
-Input is never used
-Input > is never used
-Input is never used
-Input is never used
-Input > is never used
-Input > is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-
-Output is never assigned
-
-Signal > is assigned but never used
-Signal is assigned but never used
-Signal > is assigned but never used
-Signal > is assigned but never used
-Signal is assigned but never used
-Signal is assigned but never used
-Signal is assigned but never used
-Signal > is assigned but never used
-Signal > is assigned but never used
-Signal is assigned but never used
-Signal is assigned but never used
-Signal is assigned but never used
-Signal is assigned but never used
-Signal is assigned but never used
-
-Signal is used but never assigned
-Signal is used but never assigned
-Signal is used but never assigned
-
-Signal is never used or assigned
-
-FF/Latch in Unit is equivalent
-
-FF/Latch has a constant value of 0
-FF/Latch has a constant value of 0
-FF/Latch has a constant value of 0
-FF/Latch has a constant value of 0
-FF/Latch has a constant value of 0
-
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-
-Node of sequential type is unconnected
-#
-# ----------------------------------------------------------------------------
-[tra]
-
-#
-# ----------------------------------------------------------------------------
-[map]
-The signal is incomplete
-Signal I_FX2_FLAG<3> connected to top level port I_FX2_FLAG<3> has been removed
-INFO:.*
-
-#
-# ----------------------------------------------------------------------------
-[par]
-The signal I_MEM_WAIT_IBUF has no load
-There are 1 loadless signals in this design
-This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied
-#
-# ----------------------------------------------------------------------------
-[bgn]
-Spartan-3 1200E and 1600E devices do not support bitstream
-The signal is incomplete
Index: trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset
===================================================================
--- trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset (nonexistent)
+++ trunk/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset (revision 36)
@@ -0,0 +1,104 @@
+# $Id: sys_tst_rlink_cuff_ic_n2.imfset 769 2016-05-28 11:36:22Z mueller $
+#
+# ----------------------------------------------------------------------------
+[xst]
+INFO:.*Mux is complete : default of case is discarded
+
+Register in unit has a constant value
+Register in unit has a constant value
+Register in unit has a constant value
+Register in unit has a constant value
+Register in unit has a constant value
+Register in unit has a constant value
+
+Unconnected output port 'SIZE' of component 'fifo_1c_dram'
+Unconnected output port 'LOCKED' of component 'dcm_sfs'
+Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
+Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
+Unconnected output port 'RL_MONI' of component 'rlink_core8'
+
+Input is never used
+Input > is never used
+Input is never used
+Input is never used
+Input > is never used
+Input > is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+Input is never used
+
+Output is never assigned
+
+Signal > is assigned but never used
+Signal is assigned but never used
+Signal > is assigned but never used
+Signal > is assigned but never used
+Signal is assigned but never used
+Signal is assigned but never used
+Signal is assigned but never used
+Signal > is assigned but never used
+Signal > is assigned but never used
+Signal is assigned but never used
+Signal is assigned but never used
+Signal is assigned but never used
+Signal is assigned but never used
+Signal is assigned but never used
+
+Signal is used but never assigned
+Signal is used but never assigned
+Signal is used but never assigned
+
+Signal is never used or assigned
+
+FF/Latch in Unit is equivalent
+
+FF/Latch has a constant value of 0
+FF/Latch has a constant value of 0
+FF/Latch has a constant value of 0
+FF/Latch has a constant value of 0
+FF/Latch has a constant value of 0
+
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+Node of sequential type is unconnected
+
+Node of sequential type is unconnected
+#
+# ----------------------------------------------------------------------------
+[tra]
+
+#
+# ----------------------------------------------------------------------------
+[map]
+The signal is incomplete
+Signal I_FX2_FLAG<3> connected to top level port I_FX2_FLAG<3> has been removed
+INFO:.*
+
+#
+# ----------------------------------------------------------------------------
+[par]
+The signal I_MEM_WAIT_IBUF has no load
+There are 1 loadless signals in this design
+This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied
+#
+# ----------------------------------------------------------------------------
+[bgn]
+Spartan-3 1200E and 1600E devices do not support bitstream
+The signal is incomplete
Index: trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset
===================================================================
--- trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset (revision 35)
+++ trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset (nonexistent)
@@ -1,100 +0,0 @@
-# $Id: sys_tst_rlink_cuff_ic_n3.mfset 472 2013-01-06 14:39:10Z mueller $
-#
-# ----------------------------------------------------------------------------
-[xst]
-Case statement is complete. others clause is never selected
-Using initial value '0' for reset since it is never assigned
-Using initial value '0' for fx2_tx2ena_l since it is never assigned
-
-Net does not have a driver.
-
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected
-Output port of the instance is unconnected or connected
-Output port of the instance is unconnected or connected
-Output port of the instance is unconnected
-
-Signal is used but never assigned
-
-Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_n3'
-
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-ode of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-Node of sequential type is unconnected
-
-Input is never used
-Input > is never used
-Input is never used
-Input > is never used
-Input > is never used
-Input > is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-Input is never used
-
-FF/Latch has a constant value of 0
-FF/Latch has a constant value
-FF/Latch has a constant value
-
-of type RAMB16_S18 has been replaced by RAMB16BWER
-of type RAMB16_S36 has been replaced by RAMB16BWER
-of type RAMB16_S36_S36 has been replaced by RAMB16BWER
-
-FF/Latch has a constant value of 0
-FF/Latch has a constant value
-
-The FF/Latch .* is equivalent
-The FF/Latch .* is equivalent
-The FF/Latch .* is the opposite
-
-#
-# ----------------------------------------------------------------------------
-[tra]
-
-#
-# ----------------------------------------------------------------------------
-[map]
-INFO:.*
-
-#
-# ----------------------------------------------------------------------------
-[par]
-The signal I_MEM_WAIT_IBUF has no load
-The signal I_FX2_FLAG<3>_IBUF has no load
-There are 2 loadless signals in this design
-
-#
-# ----------------------------------------------------------------------------
-[bgn]
Index: trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset
===================================================================
--- trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset (nonexistent)
+++ trunk/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset (revision 36)
@@ -0,0 +1,100 @@
+# $Id: sys_tst_rlink_cuff_ic_n3.imfset 769 2016-05-28 11:36:22Z mueller $
+#
+# ----------------------------------------------------------------------------
+[xst]
+Case statement is complete. others clause is never selected
+Using initial value '0' for reset since it is never assigned
+Using initial value '0' for fx2_tx2ena_l since it is never assigned
+
+Net does not have a driver.
+
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected
+Output port of the instance is unconnected or connected
+Output port of the instance is unconnected or connected
+Output port of the instance is unconnected
+
+Signal is used but never assigned
+
+Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_n3'
+
+Node