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URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

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  • This comparison shows the changes necessary to convert path 
    /wb2axip/trunk/bench
    from Rev 2 to Rev 8
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Rev 2 → Rev 8

/cpp/Makefile
0,0 → 1,73
################################################################################
##
## Filename: Makefile
##
## Project: Pipelined Wishbone to AXI converter
##
## Purpose:
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
CXX := g++
FLAGS := -Wall -Og -g
OBJDIR := obj-pc
RTLD := ../verilog
VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT| head -1 | sed -e " s/^.*=\s*//"')
INCS := -I$(RTLD)/obj_dir/ -I$(VROOT)/include
SOURCES := # testset.cpp
VOBJDR := $(RTLD)/obj_dir
VLIB := $(VROOT)/include/verilated.cpp
SIMSRCS := aximemsim.cpp # testset.cpp
SIMOBJ := $(subst .cpp,.o,$(SIMSRCS))
SIMOBJS:= $(addprefix $(OBJDIR)/,$(SIMOBJ))
all: $(OBJDIR)/ testset
 
$(OBJDIR)/:
@bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
 
$(OBJDIR)/aximemsim.o: aximemsim.cpp aximemsim.h
 
$(OBJDIR)/%.o: %.cpp
$(CXX) $(FLAGS) $(INCS) -c $< -o $@
 
# testset: $(OBJDIR)/testset.o $(OBJDIR)/aximemsim.o $(VOBJDR)/Vtestset__ALL.a
# $(CXX) $(FLAGS) $(INCS) $^ $(VLIB) -o $@
.PHONY: testset
testset:
@echo
@echo "I seem to have lost the testset.cpp file that this test suite"
@echo "was based off of. Hence, the suite is incomplete."
@echo
 
.PHONY: clean
clean:
rm -rf $(OBJDIR)/
# rm -f ./testset
 
/cpp/aximemsim.cpp
0,0 → 1,204
////////////////////////////////////////////////////////////////////////////////
//
// Filename: aximemsim.cpp
//
// Project: Pipelined Wishbone to AXI converter
//
// Purpose:
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include <stdio.h>
 
#include "aximemsim.h"
 
class ADRFIFO {
typedef {
int id; unsigned addr;
} ADRFIFOELEMENT;
int m_head, m_tail, m_len;
int *m_mem;
public:
ADRFIFO(int ln) {
m_mem = new ADRFIFOELEMENT[ln];
m_head = m_tail = 0;
m_len = ln;
}
 
void push(int id, unsigned addr) {
int nhead = m_head + 1;
if (nhead >= m_len)
nhead = 0;
assert(nhead != m_tail);
m_mem[m_head].id = id;
m_mem[m_head].addr = addr;
m_head = nhead;
}
 
bool full(void) {
int nhead = m_head + 1;
if (nhead >= m_len)
nhead = 0;
return (nhead == m_tail);
}
 
bool valid(void) {
return (m_head != m_tail);
}
 
int id(void) { return m_mem[m_tail].id; }
int addr(void) { return m_mem[m_tail].addr; }
int pop(void) {
if (m_tail == m_head)
return;
m_tail++;
if (m_tail >= m_len)
m_tail = 0;
}
};
 
class DATFIFO {
typedef {
unsigned data[4];
int strb;
} DATAFIFOELEMENT;
int m_head, m_tail, m_len;
int *m_mem;
public:
DATAFIFO(int ln) {
m_mem = new DATAFIFOELEMENT[ln];
m_head = m_tail = 0;
m_len = ln;
}
 
void push(int strb, unsigned dat0, unsigned dat1,
unsigned dat, unsigned dat3) {
int nhead = m_head + 1;
if (nhead >= m_len)
nhead = 0;
assert(nhead != m_tail);
m_mem[m_head].strb = id;
m_mem[m_head].data[0] = dat0;
m_mem[m_head].data[1] = dat1;
m_mem[m_head].data[2] = dat2;
m_mem[m_head].data[3] = dat3;
m_head = nhead;
}
 
bool full(void) {
int nhead = m_head + 1;
if (nhead >= m_len)
nhead = 0;
return (nhead == m_tail);
}
 
bool valid(void) {
return (m_head != m_tail);
}
 
int strb(void) { return m_mem[m_tail].strb; }
unsigned *data(void) { return &m_mem[m_tail].data[0]; }
int pop(void) {
if (m_tail == m_head)
return;
m_tail++;
if (m_tail >= m_len)
m_tail = 0;
}
};
 
AXIMEMSIM::AXIMEMSIM(unsigned abits) {
// abits is the number of bits in a memory address, referencing 8-bit
// bytes, therefore we can size our memory properly.
assert(abits>2);
m_len = (1<<(abits-2));
m_mask= m_len-1;
m_mem = new unsigned[(1<<(abits-2))];
 
memset(m_mem, 0, sizeof(unsigned)<<(abits-2));
}
 
void AXIMEMSIM::apply(AXIBUS &bus) {
// First, let's validate our inputs ..., and queue up our outputs
bus.ar.ready = (!m_readfifo.full());
bus.aw.ready = (!m_writefifo.full());
bus.w.ready = (!m_wdata.full());
if (bus.r.ready)
bus.r.valid = false;
if (bus.b.ready)
bus.b.valid = false;
 
if ((bus.ar.ready)&&(!m_readfifo.full())) {
assert(bus.ar.len == 0);
assert(bus.ar.size == 5);
assert(bus.ar.burst == 1);
assert(bus.ar.lock == 0);
assert(bus.ar.cache == 2);
assert(bus.ar.prot == 2);
assert(bus.ar.qos == 0);
 
m_readfifo.push(bus.ar.id, bus.ar.addr);
}
 
if ((bus.aw.ready)&&(!m_writefifo.full())) {
assert(bus.aw.len == 0);
assert(bus.aw.size == 5);
assert(bus.aw.burst == 1);
assert(bus.aw.lock == 0);
assert(bus.aw.cache == 2);
assert(bus.aw.prot == 2);
assert(bus.aw.qos == 0);
 
m_awfifo.push(bus.aw.id, bus.aw.addr);
}
 
if ((bus.w.ready)&&(!m_writedata.full())) {
m_writefifo.push(bus.aw.strb, bus.aw.data[0], bus.aw.data[1],
bus.aw.data[2], bus.aw.data[3]);
 
if (m_respfifo[m_now].valid) {
if (m_respfifo[m_now].read) {
if ((!bus.r.valid)||(bus.r.ready)) {
bus.r.data[0] = m_respfifo[m_now].data[0];
bus.r.data[1] = m_respfifo[m_now].data[1];
bus.r.data[2] = m_respfifo[m_now].data[2];
bus.r.data[3] = m_respfifo[m_now].data[3];
bus.r.valid = true;
m_now++;
}
} else if ((!bus.b.valid)||(bus.b.ready)) {
bus.b.resp = m_respfifo[m_now].resp;
bus.b.id = m_respfifo[m_now].id;
bus.b.valid = true;
m_now++;
}
}
}
 
/cpp/aximemsim.h
0,0 → 1,88
////////////////////////////////////////////////////////////////////////////////
//
// Filename: aximemsim.h
//
// Project: Pipelined Wishbone to AXI converter
//
// Purpose: To attempt to emulate how the MIG responds to AXI requests.
// Of course, this is written with no knowledge of how MIG actually
// responds, just a touch of knowledge regarding how a DDR3 memory works,
// so ... your mileage might vary.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef AXIMEMSIM_H
#define AXIMEMSIM_H
 
typedef struct {
unsigned addr;
int id, len, size, burst, lock, cache, prot, qos;
bool ready, valid;
} AXI_AWBUS;
 
typedef struct {
unsigned addr;
int id, len, size, burst, lock, cache, prot, qos;
bool ready, valid;
} AXI_ARBUS;
 
typedef struct {
int strb;
unsigned data[4]; // 128 bits
int ready, valid, last;
} AXI_WBUS;
 
typedef struct {
int id, resp;
int ready, valid;
} AXI_WRESP;
 
typedef struct {
int id, resp;
unsigned data[4]; // 128 bits
int ready, valid, last;
} AXI_RDATA;
 
typedef struct {
AXI_AWBUS aw;
AXI_ARBUS ar;
AXI_WBUS w;
AXI_WRESP b;
AXI_RDATA r;
} AXIBUS;
 
class AXIMEMSIM {
unsigned *m_mem;
public:
AXIMEMSIM(unsigned abits);
void apply(AXIBUS &bus);
};
 
#endif

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